1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMSubtarget.h"
15 #include "ARMFrameLowering.h"
16 #include "ARMISelLowering.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSelectionDAGInfo.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "Thumb1FrameLowering.h"
23 #include "Thumb1InstrInfo.h"
24 #include "Thumb2InstrInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Attributes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetOptions.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 #include "llvm/Support/TargetParser.h"
35 
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "arm-subtarget"
39 
40 #define GET_SUBTARGETINFO_TARGET_DESC
41 #define GET_SUBTARGETINFO_CTOR
42 #include "ARMGenSubtargetInfo.inc"
43 
44 static cl::opt<bool>
45 UseFusedMulOps("arm-use-mulops",
46                cl::init(true), cl::Hidden);
47 
48 enum ITMode {
49   DefaultIT,
50   RestrictedIT,
51   NoRestrictedIT
52 };
53 
54 static cl::opt<ITMode>
55 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
56    cl::ZeroOrMore,
57    cl::values(clEnumValN(DefaultIT, "arm-default-it",
58                          "Generate IT block based on arch"),
59               clEnumValN(RestrictedIT, "arm-restrict-it",
60                          "Disallow deprecated IT based on ARMv8"),
61               clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
62                          "Allow IT blocks based on ARMv7")));
63 
64 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
65 /// currently supported (for testing only).
66 static cl::opt<bool>
67 ForceFastISel("arm-force-fast-isel",
68                cl::init(false), cl::Hidden);
69 
70 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
71 /// so that we can use initializer lists for subtarget initialization.
72 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
73                                                             StringRef FS) {
74   initializeEnvironment();
75   initSubtargetFeatures(CPU, FS);
76   return *this;
77 }
78 
79 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
80                                                         StringRef FS) {
81   ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
82   if (STI.isThumb1Only())
83     return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
84 
85   return new ARMFrameLowering(STI);
86 }
87 
88 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
89                            const std::string &FS,
90                            const ARMBaseTargetMachine &TM, bool IsLittle)
91     : ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
92       CPUString(CPU), IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options),
93       TM(TM), FrameLowering(initializeFrameLowering(CPU, FS)),
94       // At this point initializeSubtargetDependencies has been called so
95       // we can query directly.
96       InstrInfo(isThumb1Only()
97                     ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
98                     : !isThumb()
99                           ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
100                           : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
101       TLInfo(TM, *this), GISel() {}
102 
103 const CallLowering *ARMSubtarget::getCallLowering() const {
104   assert(GISel && "Access to GlobalISel APIs not set");
105   return GISel->getCallLowering();
106 }
107 
108 const InstructionSelector *ARMSubtarget::getInstructionSelector() const {
109   assert(GISel && "Access to GlobalISel APIs not set");
110   return GISel->getInstructionSelector();
111 }
112 
113 const LegalizerInfo *ARMSubtarget::getLegalizerInfo() const {
114   assert(GISel && "Access to GlobalISel APIs not set");
115   return GISel->getLegalizerInfo();
116 }
117 
118 const RegisterBankInfo *ARMSubtarget::getRegBankInfo() const {
119   assert(GISel && "Access to GlobalISel APIs not set");
120   return GISel->getRegBankInfo();
121 }
122 
123 bool ARMSubtarget::isXRaySupported() const {
124   // We don't currently suppport Thumb, but Windows requires Thumb.
125   return hasV6Ops() && hasARMOps() && !isTargetWindows();
126 }
127 
128 void ARMSubtarget::initializeEnvironment() {
129   // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
130   // directly from it, but we can try to make sure they're consistent when both
131   // available.
132   UseSjLjEH = isTargetDarwin() && !isTargetWatchABI();
133   assert((!TM.getMCAsmInfo() ||
134           (TM.getMCAsmInfo()->getExceptionHandlingType() ==
135            ExceptionHandling::SjLj) == UseSjLjEH) &&
136          "inconsistent sjlj choice between CodeGen and MC");
137 }
138 
139 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
140   if (CPUString.empty()) {
141     CPUString = "generic";
142 
143     if (isTargetDarwin()) {
144       StringRef ArchName = TargetTriple.getArchName();
145       unsigned ArchKind = llvm::ARM::parseArch(ArchName);
146       if (ArchKind == llvm::ARM::AK_ARMV7S)
147         // Default to the Swift CPU when targeting armv7s/thumbv7s.
148         CPUString = "swift";
149       else if (ArchKind == llvm::ARM::AK_ARMV7K)
150         // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
151         // ARMv7k does not use SjLj exception handling.
152         CPUString = "cortex-a7";
153     }
154   }
155 
156   // Insert the architecture feature derived from the target triple into the
157   // feature string. This is important for setting features that are implied
158   // based on the architecture version.
159   std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
160   if (!FS.empty()) {
161     if (!ArchFS.empty())
162       ArchFS = (Twine(ArchFS) + "," + FS).str();
163     else
164       ArchFS = FS;
165   }
166   ParseSubtargetFeatures(CPUString, ArchFS);
167 
168   // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
169   // Assert this for now to make the change obvious.
170   assert(hasV6T2Ops() || !hasThumb2());
171 
172   // Keep a pointer to static instruction cost data for the specified CPU.
173   SchedModel = getSchedModelForCPU(CPUString);
174 
175   // Initialize scheduling itinerary for the specified CPU.
176   InstrItins = getInstrItineraryForCPU(CPUString);
177 
178   // FIXME: this is invalid for WindowsCE
179   if (isTargetWindows())
180     NoARM = true;
181 
182   if (isAAPCS_ABI())
183     stackAlignment = 8;
184   if (isTargetNaCl() || isAAPCS16_ABI())
185     stackAlignment = 16;
186 
187   // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
188   // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
189   // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
190   // support in the assembler and linker to be used. This would need to be
191   // fixed to fully support tail calls in Thumb1.
192   //
193   // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
194   // LR.  This means if we need to reload LR, it takes an extra instructions,
195   // which outweighs the value of the tail call; but here we don't know yet
196   // whether LR is going to be used.  Probably the right approach is to
197   // generate the tail call here and turn it back into CALL/RET in
198   // emitEpilogue if LR is used.
199 
200   // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
201   // but we need to make sure there are enough registers; the only valid
202   // registers are the 4 used for parameters.  We don't currently do this
203   // case.
204 
205   SupportsTailCall = !isThumb() || hasV8MBaselineOps();
206 
207   if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
208     SupportsTailCall = false;
209 
210   switch (IT) {
211   case DefaultIT:
212     RestrictIT = hasV8Ops();
213     break;
214   case RestrictedIT:
215     RestrictIT = true;
216     break;
217   case NoRestrictedIT:
218     RestrictIT = false;
219     break;
220   }
221 
222   // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
223   const FeatureBitset &Bits = getFeatureBits();
224   if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
225       (Options.UnsafeFPMath || isTargetDarwin()))
226     UseNEONForSinglePrecisionFP = true;
227 
228   if (isRWPI())
229     ReserveR9 = true;
230 
231   // FIXME: Teach TableGen to deal with these instead of doing it manually here.
232   switch (ARMProcFamily) {
233   case Others:
234   case CortexA5:
235     break;
236   case CortexA7:
237     LdStMultipleTiming = DoubleIssue;
238     break;
239   case CortexA8:
240     LdStMultipleTiming = DoubleIssue;
241     break;
242   case CortexA9:
243     LdStMultipleTiming = DoubleIssueCheckUnalignedAccess;
244     PreISelOperandLatencyAdjustment = 1;
245     break;
246   case CortexA12:
247     break;
248   case CortexA15:
249     MaxInterleaveFactor = 2;
250     PreISelOperandLatencyAdjustment = 1;
251     PartialUpdateClearance = 12;
252     break;
253   case CortexA17:
254   case CortexA32:
255   case CortexA35:
256   case CortexA53:
257   case CortexA57:
258   case CortexA72:
259   case CortexA73:
260   case CortexR4:
261   case CortexR4F:
262   case CortexR5:
263   case CortexR7:
264   case CortexM3:
265   case ExynosM1:
266   case CortexR52:
267     break;
268   case Krait:
269     PreISelOperandLatencyAdjustment = 1;
270     break;
271   case Swift:
272     MaxInterleaveFactor = 2;
273     LdStMultipleTiming = SingleIssuePlusExtras;
274     PreISelOperandLatencyAdjustment = 1;
275     PartialUpdateClearance = 12;
276     break;
277   }
278 }
279 
280 bool ARMSubtarget::isAPCS_ABI() const {
281   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
282   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
283 }
284 bool ARMSubtarget::isAAPCS_ABI() const {
285   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
286   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
287          TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
288 }
289 bool ARMSubtarget::isAAPCS16_ABI() const {
290   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
291   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
292 }
293 
294 bool ARMSubtarget::isROPI() const {
295   return TM.getRelocationModel() == Reloc::ROPI ||
296          TM.getRelocationModel() == Reloc::ROPI_RWPI;
297 }
298 bool ARMSubtarget::isRWPI() const {
299   return TM.getRelocationModel() == Reloc::RWPI ||
300          TM.getRelocationModel() == Reloc::ROPI_RWPI;
301 }
302 
303 bool ARMSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
304   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
305     return true;
306 
307   // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
308   // the section that is being relocated. This means we have to use o load even
309   // for GVs that are known to be local to the dso.
310   if (isTargetMachO() && TM.isPositionIndependent() &&
311       (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
312     return true;
313 
314   return false;
315 }
316 
317 unsigned ARMSubtarget::getMispredictionPenalty() const {
318   return SchedModel.MispredictPenalty;
319 }
320 
321 bool ARMSubtarget::hasSinCos() const {
322   return isTargetWatchOS() ||
323     (isTargetIOS() && !getTargetTriple().isOSVersionLT(7, 0));
324 }
325 
326 bool ARMSubtarget::enableMachineScheduler() const {
327   // Enable the MachineScheduler before register allocation for out-of-order
328   // architectures where we do not use the PostRA scheduler anymore (for now
329   // restricted to swift).
330   return getSchedModel().isOutOfOrder() && isSwift();
331 }
332 
333 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
334 bool ARMSubtarget::enablePostRAScheduler() const {
335   // No need for PostRA scheduling on out of order CPUs (for now restricted to
336   // swift).
337   if (getSchedModel().isOutOfOrder() && isSwift())
338     return false;
339   return (!isThumb() || hasThumb2());
340 }
341 
342 bool ARMSubtarget::enableAtomicExpand() const { return hasAnyDataBarrier(); }
343 
344 bool ARMSubtarget::useStride4VFPs(const MachineFunction &MF) const {
345   // For general targets, the prologue can grow when VFPs are allocated with
346   // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
347   // format which it's more important to get right.
348   return isTargetWatchABI() || (isSwift() && !MF.getFunction()->optForMinSize());
349 }
350 
351 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
352   // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
353   // immediates as it is inherently position independent, and may be out of
354   // range otherwise.
355   return !NoMovt && hasV8MBaselineOps() &&
356          (isTargetWindows() || !MF.getFunction()->optForMinSize());
357 }
358 
359 bool ARMSubtarget::useFastISel() const {
360   // Enable fast-isel for any target, for testing only.
361   if (ForceFastISel)
362     return true;
363 
364   // Limit fast-isel to the targets that are or have been tested.
365   if (!hasV6Ops())
366     return false;
367 
368   // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
369   return TM.Options.EnableFastISel &&
370          ((isTargetMachO() && !isThumb1Only()) ||
371           (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
372 }
373