1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMSubtarget.h"
15 #include "ARMFrameLowering.h"
16 #include "ARMISelLowering.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSelectionDAGInfo.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "Thumb1FrameLowering.h"
23 #include "Thumb1InstrInfo.h"
24 #include "Thumb2InstrInfo.h"
25 #include "llvm/CodeGen/Analysis.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Attributes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/GlobalValue.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "arm-subtarget"
39 
40 #define GET_SUBTARGETINFO_TARGET_DESC
41 #define GET_SUBTARGETINFO_CTOR
42 #include "ARMGenSubtargetInfo.inc"
43 
44 static cl::opt<bool>
45 UseFusedMulOps("arm-use-mulops",
46                cl::init(true), cl::Hidden);
47 
48 enum ITMode {
49   DefaultIT,
50   RestrictedIT,
51   NoRestrictedIT
52 };
53 
54 static cl::opt<ITMode>
55 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
56    cl::ZeroOrMore,
57    cl::values(clEnumValN(DefaultIT, "arm-default-it",
58                          "Generate IT block based on arch"),
59               clEnumValN(RestrictedIT, "arm-restrict-it",
60                          "Disallow deprecated IT based on ARMv8"),
61               clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
62                          "Allow IT blocks based on ARMv7"),
63               clEnumValEnd));
64 
65 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
66 /// currently supported (for testing only).
67 static cl::opt<bool>
68 ForceFastISel("arm-force-fast-isel",
69                cl::init(false), cl::Hidden);
70 
71 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
72 /// so that we can use initializer lists for subtarget initialization.
73 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
74                                                             StringRef FS) {
75   initializeEnvironment();
76   initSubtargetFeatures(CPU, FS);
77   return *this;
78 }
79 
80 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
81                                                         StringRef FS) {
82   ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
83   if (STI.isThumb1Only())
84     return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
85 
86   return new ARMFrameLowering(STI);
87 }
88 
89 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
90                            const std::string &FS,
91                            const ARMBaseTargetMachine &TM, bool IsLittle)
92     : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
93       ARMProcClass(None), ARMArch(ARMv4t), stackAlignment(4), CPUString(CPU),
94       IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options), TM(TM),
95       FrameLowering(initializeFrameLowering(CPU, FS)),
96       // At this point initializeSubtargetDependencies has been called so
97       // we can query directly.
98       InstrInfo(isThumb1Only()
99                     ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
100                     : !isThumb()
101                           ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
102                           : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
103       TLInfo(TM, *this) {}
104 
105 void ARMSubtarget::initializeEnvironment() {
106   HasV4TOps = false;
107   HasV5TOps = false;
108   HasV5TEOps = false;
109   HasV6Ops = false;
110   HasV6MOps = false;
111   HasV6KOps = false;
112   HasV6T2Ops = false;
113   HasV7Ops = false;
114   HasV8Ops = false;
115   HasV8_1aOps = false;
116   HasV8_2aOps = false;
117   HasV8MBaselineOps = false;
118   HasV8MMainlineOps = false;
119   HasVFPv2 = false;
120   HasVFPv3 = false;
121   HasVFPv4 = false;
122   HasFPARMv8 = false;
123   HasNEON = false;
124   UseNEONForSinglePrecisionFP = false;
125   UseMulOps = UseFusedMulOps;
126   SlowFPVMLx = false;
127   HasVMLxForwarding = false;
128   SlowFPBrcc = false;
129   InThumbMode = false;
130   UseSoftFloat = false;
131   HasThumb2 = false;
132   NoARM = false;
133   ReserveR9 = false;
134   NoMovt = false;
135   SupportsTailCall = false;
136   HasFP16 = false;
137   HasFullFP16 = false;
138   HasD16 = false;
139   HasHardwareDivide = false;
140   HasHardwareDivideInARM = false;
141   HasT2ExtractPack = false;
142   HasDataBarrier = false;
143   Pref32BitThumb = false;
144   AvoidCPSRPartialUpdate = false;
145   AvoidMOVsShifterOperand = false;
146   HasRAS = false;
147   HasMPExtension = false;
148   HasVirtualization = false;
149   FPOnlySP = false;
150   HasPerfMon = false;
151   HasTrustZone = false;
152   Has8MSecExt = false;
153   HasCrypto = false;
154   HasCRC = false;
155   HasZeroCycleZeroing = false;
156   StrictAlign = false;
157   HasDSP = false;
158   UseNaClTrap = false;
159   GenLongCalls = false;
160   UnsafeFPMath = false;
161   HasV7Clrex = false;
162   HasAcquireRelease = false;
163 
164   // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
165   // directly from it, but we can try to make sure they're consistent when both
166   // available.
167   UseSjLjEH = isTargetDarwin() && !isTargetWatchABI();
168   assert((!TM.getMCAsmInfo() ||
169           (TM.getMCAsmInfo()->getExceptionHandlingType() ==
170            ExceptionHandling::SjLj) == UseSjLjEH) &&
171          "inconsistent sjlj choice between CodeGen and MC");
172 }
173 
174 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
175   if (CPUString.empty()) {
176     CPUString = "generic";
177 
178     if (isTargetDarwin()) {
179       StringRef ArchName = TargetTriple.getArchName();
180       if (ArchName.endswith("v7s"))
181         // Default to the Swift CPU when targeting armv7s/thumbv7s.
182         CPUString = "swift";
183       else if (ArchName.endswith("v7k"))
184         // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
185         // ARMv7k does not use SjLj exception handling.
186         CPUString = "cortex-a7";
187     }
188   }
189 
190   // Insert the architecture feature derived from the target triple into the
191   // feature string. This is important for setting features that are implied
192   // based on the architecture version.
193   std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
194   if (!FS.empty()) {
195     if (!ArchFS.empty())
196       ArchFS = (Twine(ArchFS) + "," + FS).str();
197     else
198       ArchFS = FS;
199   }
200   ParseSubtargetFeatures(CPUString, ArchFS);
201 
202   // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
203   // Assert this for now to make the change obvious.
204   assert(hasV6T2Ops() || !hasThumb2());
205 
206   // Keep a pointer to static instruction cost data for the specified CPU.
207   SchedModel = getSchedModelForCPU(CPUString);
208 
209   // Initialize scheduling itinerary for the specified CPU.
210   InstrItins = getInstrItineraryForCPU(CPUString);
211 
212   // FIXME: this is invalid for WindowsCE
213   if (isTargetWindows())
214     NoARM = true;
215 
216   if (isAAPCS_ABI())
217     stackAlignment = 8;
218   if (isTargetNaCl() || isAAPCS16_ABI())
219     stackAlignment = 16;
220 
221   // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
222   // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
223   // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
224   // support in the assembler and linker to be used. This would need to be
225   // fixed to fully support tail calls in Thumb1.
226   //
227   // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
228   // LR.  This means if we need to reload LR, it takes an extra instructions,
229   // which outweighs the value of the tail call; but here we don't know yet
230   // whether LR is going to be used.  Probably the right approach is to
231   // generate the tail call here and turn it back into CALL/RET in
232   // emitEpilogue if LR is used.
233 
234   // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
235   // but we need to make sure there are enough registers; the only valid
236   // registers are the 4 used for parameters.  We don't currently do this
237   // case.
238 
239   SupportsTailCall = !isThumb() || hasV8MBaselineOps();
240 
241   if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
242     SupportsTailCall = false;
243 
244   switch (IT) {
245   case DefaultIT:
246     RestrictIT = hasV8Ops();
247     break;
248   case RestrictedIT:
249     RestrictIT = true;
250     break;
251   case NoRestrictedIT:
252     RestrictIT = false;
253     break;
254   }
255 
256   // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
257   const FeatureBitset &Bits = getFeatureBits();
258   if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
259       (Options.UnsafeFPMath || isTargetDarwin()))
260     UseNEONForSinglePrecisionFP = true;
261 }
262 
263 bool ARMSubtarget::isAPCS_ABI() const {
264   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
265   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
266 }
267 bool ARMSubtarget::isAAPCS_ABI() const {
268   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
269   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
270          TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
271 }
272 bool ARMSubtarget::isAAPCS16_ABI() const {
273   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
274   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
275 }
276 
277 /// true if the GV will be accessed via an indirect symbol.
278 bool
279 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
280                                  Reloc::Model RelocM) const {
281   if (!shouldAssumeDSOLocal(RelocM, TargetTriple, *GV->getParent(), GV))
282     return true;
283 
284   // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
285   // the section that is being relocated. This means we have to use o load even
286   // for GVs that are known to be local to the dso.
287   if (isTargetDarwin() && RelocM == Reloc::PIC_ &&
288       (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
289     return true;
290 
291   return false;
292 }
293 
294 unsigned ARMSubtarget::getMispredictionPenalty() const {
295   return SchedModel.MispredictPenalty;
296 }
297 
298 bool ARMSubtarget::hasSinCos() const {
299   return isTargetWatchOS() ||
300     (isTargetIOS() && !getTargetTriple().isOSVersionLT(7, 0));
301 }
302 
303 bool ARMSubtarget::enableMachineScheduler() const {
304   // Enable the MachineScheduler before register allocation for out-of-order
305   // architectures where we do not use the PostRA scheduler anymore (for now
306   // restricted to swift).
307   return getSchedModel().isOutOfOrder() && isSwift();
308 }
309 
310 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
311 bool ARMSubtarget::enablePostRAScheduler() const {
312   // No need for PostRA scheduling on out of order CPUs (for now restricted to
313   // swift).
314   if (getSchedModel().isOutOfOrder() && isSwift())
315     return false;
316   return (!isThumb() || hasThumb2());
317 }
318 
319 bool ARMSubtarget::enableAtomicExpand() const {
320   return hasAnyDataBarrier() && (!isThumb() || hasV8MBaselineOps());
321 }
322 
323 bool ARMSubtarget::useStride4VFPs(const MachineFunction &MF) const {
324   // For general targets, the prologue can grow when VFPs are allocated with
325   // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
326   // format which it's more important to get right.
327   return isTargetWatchABI() || (isSwift() && !MF.getFunction()->optForMinSize());
328 }
329 
330 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
331   // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
332   // immediates as it is inherently position independent, and may be out of
333   // range otherwise.
334   return !NoMovt && hasV8MBaselineOps() &&
335          (isTargetWindows() || !MF.getFunction()->optForMinSize());
336 }
337 
338 bool ARMSubtarget::useFastISel() const {
339   // Enable fast-isel for any target, for testing only.
340   if (ForceFastISel)
341     return true;
342 
343   // Limit fast-isel to the targets that are or have been tested.
344   if (!hasV6Ops())
345     return false;
346 
347   // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
348   return TM.Options.EnableFastISel &&
349          ((isTargetMachO() && !isThumb1Only()) ||
350           (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
351 }
352