1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARM.h"
15 
16 #include "ARMCallLowering.h"
17 #include "ARMLegalizerInfo.h"
18 #include "ARMRegisterBankInfo.h"
19 #include "ARMSubtarget.h"
20 #include "ARMFrameLowering.h"
21 #include "ARMInstrInfo.h"
22 #include "ARMSubtarget.h"
23 #include "ARMTargetMachine.h"
24 #include "MCTargetDesc/ARMMCTargetDesc.h"
25 #include "Thumb1FrameLowering.h"
26 #include "Thumb1InstrInfo.h"
27 #include "Thumb2InstrInfo.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/ADT/Triple.h"
30 #include "llvm/ADT/Twine.h"
31 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
32 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
33 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/MachineFunction.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/GlobalValue.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCTargetOptions.h"
40 #include "llvm/Support/CodeGen.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/TargetParser.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include <cassert>
45 #include <string>
46 
47 using namespace llvm;
48 
49 #define DEBUG_TYPE "arm-subtarget"
50 
51 #define GET_SUBTARGETINFO_TARGET_DESC
52 #define GET_SUBTARGETINFO_CTOR
53 #include "ARMGenSubtargetInfo.inc"
54 
55 static cl::opt<bool>
56 UseFusedMulOps("arm-use-mulops",
57                cl::init(true), cl::Hidden);
58 
59 enum ITMode {
60   DefaultIT,
61   RestrictedIT,
62   NoRestrictedIT
63 };
64 
65 static cl::opt<ITMode>
66 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
67    cl::ZeroOrMore,
68    cl::values(clEnumValN(DefaultIT, "arm-default-it",
69                          "Generate IT block based on arch"),
70               clEnumValN(RestrictedIT, "arm-restrict-it",
71                          "Disallow deprecated IT based on ARMv8"),
72               clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
73                          "Allow IT blocks based on ARMv7")));
74 
75 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
76 /// currently supported (for testing only).
77 static cl::opt<bool>
78 ForceFastISel("arm-force-fast-isel",
79                cl::init(false), cl::Hidden);
80 
81 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
82 /// so that we can use initializer lists for subtarget initialization.
83 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
84                                                             StringRef FS) {
85   initializeEnvironment();
86   initSubtargetFeatures(CPU, FS);
87   return *this;
88 }
89 
90 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
91                                                         StringRef FS) {
92   ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
93   if (STI.isThumb1Only())
94     return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
95 
96   return new ARMFrameLowering(STI);
97 }
98 
99 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
100                            const std::string &FS,
101                            const ARMBaseTargetMachine &TM, bool IsLittle)
102     : ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
103       CPUString(CPU), IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options),
104       TM(TM), FrameLowering(initializeFrameLowering(CPU, FS)),
105       // At this point initializeSubtargetDependencies has been called so
106       // we can query directly.
107       InstrInfo(isThumb1Only()
108                     ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
109                     : !isThumb()
110                           ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
111                           : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
112       TLInfo(TM, *this) {
113 
114   CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering()));
115   Legalizer.reset(new ARMLegalizerInfo(*this));
116 
117   auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo());
118 
119   // FIXME: At this point, we can't rely on Subtarget having RBI.
120   // It's awkward to mix passing RBI and the Subtarget; should we pass
121   // TII/TRI as well?
122   InstSelector.reset(createARMInstructionSelector(
123       *static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI));
124 
125   RegBankInfo.reset(RBI);
126 }
127 
128 const CallLowering *ARMSubtarget::getCallLowering() const {
129   return CallLoweringInfo.get();
130 }
131 
132 const InstructionSelector *ARMSubtarget::getInstructionSelector() const {
133   return InstSelector.get();
134 }
135 
136 const LegalizerInfo *ARMSubtarget::getLegalizerInfo() const {
137   return Legalizer.get();
138 }
139 
140 const RegisterBankInfo *ARMSubtarget::getRegBankInfo() const {
141   return RegBankInfo.get();
142 }
143 
144 bool ARMSubtarget::isXRaySupported() const {
145   // We don't currently suppport Thumb, but Windows requires Thumb.
146   return hasV6Ops() && hasARMOps() && !isTargetWindows();
147 }
148 
149 void ARMSubtarget::initializeEnvironment() {
150   // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
151   // directly from it, but we can try to make sure they're consistent when both
152   // available.
153   UseSjLjEH = (isTargetDarwin() && !isTargetWatchABI() &&
154                Options.ExceptionModel == ExceptionHandling::None) ||
155               Options.ExceptionModel == ExceptionHandling::SjLj;
156   assert((!TM.getMCAsmInfo() ||
157           (TM.getMCAsmInfo()->getExceptionHandlingType() ==
158            ExceptionHandling::SjLj) == UseSjLjEH) &&
159          "inconsistent sjlj choice between CodeGen and MC");
160 }
161 
162 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
163   if (CPUString.empty()) {
164     CPUString = "generic";
165 
166     if (isTargetDarwin()) {
167       StringRef ArchName = TargetTriple.getArchName();
168       ARM::ArchKind AK = ARM::parseArch(ArchName);
169       if (AK == ARM::ArchKind::ARMV7S)
170         // Default to the Swift CPU when targeting armv7s/thumbv7s.
171         CPUString = "swift";
172       else if (AK == ARM::ArchKind::ARMV7K)
173         // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
174         // ARMv7k does not use SjLj exception handling.
175         CPUString = "cortex-a7";
176     }
177   }
178 
179   // Insert the architecture feature derived from the target triple into the
180   // feature string. This is important for setting features that are implied
181   // based on the architecture version.
182   std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
183   if (!FS.empty()) {
184     if (!ArchFS.empty())
185       ArchFS = (Twine(ArchFS) + "," + FS).str();
186     else
187       ArchFS = FS;
188   }
189   ParseSubtargetFeatures(CPUString, ArchFS);
190 
191   // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
192   // Assert this for now to make the change obvious.
193   assert(hasV6T2Ops() || !hasThumb2());
194 
195   // Execute only support requires movt support
196   if (genExecuteOnly())
197     assert(hasV8MBaselineOps() && !NoMovt && "Cannot generate execute-only code for this target");
198 
199   // Keep a pointer to static instruction cost data for the specified CPU.
200   SchedModel = getSchedModelForCPU(CPUString);
201 
202   // Initialize scheduling itinerary for the specified CPU.
203   InstrItins = getInstrItineraryForCPU(CPUString);
204 
205   // FIXME: this is invalid for WindowsCE
206   if (isTargetWindows())
207     NoARM = true;
208 
209   if (isAAPCS_ABI())
210     stackAlignment = 8;
211   if (isTargetNaCl() || isAAPCS16_ABI())
212     stackAlignment = 16;
213 
214   // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
215   // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
216   // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
217   // support in the assembler and linker to be used. This would need to be
218   // fixed to fully support tail calls in Thumb1.
219   //
220   // For ARMv8-M, we /do/ implement tail calls.  Doing this is tricky for v8-M
221   // baseline, since the LDM/POP instruction on Thumb doesn't take LR.  This
222   // means if we need to reload LR, it takes extra instructions, which outweighs
223   // the value of the tail call; but here we don't know yet whether LR is going
224   // to be used. We take the optimistic approach of generating the tail call and
225   // perhaps taking a hit if we need to restore the LR.
226 
227   // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
228   // but we need to make sure there are enough registers; the only valid
229   // registers are the 4 used for parameters.  We don't currently do this
230   // case.
231 
232   SupportsTailCall = !isThumb() || hasV8MBaselineOps();
233 
234   if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
235     SupportsTailCall = false;
236 
237   switch (IT) {
238   case DefaultIT:
239     RestrictIT = hasV8Ops();
240     break;
241   case RestrictedIT:
242     RestrictIT = true;
243     break;
244   case NoRestrictedIT:
245     RestrictIT = false;
246     break;
247   }
248 
249   // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
250   const FeatureBitset &Bits = getFeatureBits();
251   if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
252       (Options.UnsafeFPMath || isTargetDarwin()))
253     UseNEONForSinglePrecisionFP = true;
254 
255   if (isRWPI())
256     ReserveR9 = true;
257 
258   // FIXME: Teach TableGen to deal with these instead of doing it manually here.
259   switch (ARMProcFamily) {
260   case Others:
261   case CortexA5:
262     break;
263   case CortexA7:
264     LdStMultipleTiming = DoubleIssue;
265     break;
266   case CortexA8:
267     LdStMultipleTiming = DoubleIssue;
268     break;
269   case CortexA9:
270     LdStMultipleTiming = DoubleIssueCheckUnalignedAccess;
271     PreISelOperandLatencyAdjustment = 1;
272     break;
273   case CortexA12:
274     break;
275   case CortexA15:
276     MaxInterleaveFactor = 2;
277     PreISelOperandLatencyAdjustment = 1;
278     PartialUpdateClearance = 12;
279     break;
280   case CortexA17:
281   case CortexA32:
282   case CortexA35:
283   case CortexA53:
284   case CortexA55:
285   case CortexA57:
286   case CortexA72:
287   case CortexA73:
288   case CortexA75:
289   case CortexR4:
290   case CortexR4F:
291   case CortexR5:
292   case CortexR7:
293   case CortexM3:
294   case CortexR52:
295   case ExynosM1:
296   case Kryo:
297     break;
298   case Krait:
299     PreISelOperandLatencyAdjustment = 1;
300     break;
301   case Swift:
302     MaxInterleaveFactor = 2;
303     LdStMultipleTiming = SingleIssuePlusExtras;
304     PreISelOperandLatencyAdjustment = 1;
305     PartialUpdateClearance = 12;
306     break;
307   }
308 }
309 
310 bool ARMSubtarget::isAPCS_ABI() const {
311   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
312   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
313 }
314 bool ARMSubtarget::isAAPCS_ABI() const {
315   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
316   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
317          TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
318 }
319 bool ARMSubtarget::isAAPCS16_ABI() const {
320   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
321   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
322 }
323 
324 bool ARMSubtarget::isROPI() const {
325   return TM.getRelocationModel() == Reloc::ROPI ||
326          TM.getRelocationModel() == Reloc::ROPI_RWPI;
327 }
328 bool ARMSubtarget::isRWPI() const {
329   return TM.getRelocationModel() == Reloc::RWPI ||
330          TM.getRelocationModel() == Reloc::ROPI_RWPI;
331 }
332 
333 bool ARMSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
334   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
335     return true;
336 
337   // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
338   // the section that is being relocated. This means we have to use o load even
339   // for GVs that are known to be local to the dso.
340   if (isTargetMachO() && TM.isPositionIndependent() &&
341       (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
342     return true;
343 
344   return false;
345 }
346 
347 bool ARMSubtarget::isGVInGOT(const GlobalValue *GV) const {
348   return isTargetELF() && TM.isPositionIndependent() &&
349          !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
350 }
351 
352 unsigned ARMSubtarget::getMispredictionPenalty() const {
353   return SchedModel.MispredictPenalty;
354 }
355 
356 bool ARMSubtarget::hasSinCos() const {
357   return isTargetWatchOS() ||
358     (isTargetIOS() && !getTargetTriple().isOSVersionLT(7, 0));
359 }
360 
361 bool ARMSubtarget::enableMachineScheduler() const {
362   // Enable the MachineScheduler before register allocation for subtargets
363   // with the use-misched feature.
364   return useMachineScheduler();
365 }
366 
367 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
368 bool ARMSubtarget::enablePostRAScheduler() const {
369   if (disablePostRAScheduler())
370     return false;
371   // Don't reschedule potential IT blocks.
372   return !isThumb1Only();
373 }
374 
375 bool ARMSubtarget::enableAtomicExpand() const { return hasAnyDataBarrier(); }
376 
377 bool ARMSubtarget::useStride4VFPs(const MachineFunction &MF) const {
378   // For general targets, the prologue can grow when VFPs are allocated with
379   // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
380   // format which it's more important to get right.
381   return isTargetWatchABI() || (isSwift() && !MF.getFunction()->optForMinSize());
382 }
383 
384 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
385   // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
386   // immediates as it is inherently position independent, and may be out of
387   // range otherwise.
388   return !NoMovt && hasV8MBaselineOps() &&
389          (isTargetWindows() || !MF.getFunction()->optForMinSize() || genExecuteOnly());
390 }
391 
392 bool ARMSubtarget::useFastISel() const {
393   // Enable fast-isel for any target, for testing only.
394   if (ForceFastISel)
395     return true;
396 
397   // Limit fast-isel to the targets that are or have been tested.
398   if (!hasV6Ops())
399     return false;
400 
401   // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
402   return TM.Options.EnableFastISel &&
403          ((isTargetMachO() && !isThumb1Only()) ||
404           (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
405 }
406