1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the ARM specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "ARMSubtarget.h" 15 #include "ARMBaseRegisterInfo.h" 16 #include "llvm/GlobalValue.h" 17 #include "llvm/Target/TargetSubtargetInfo.h" 18 #include "llvm/Support/CommandLine.h" 19 #include "llvm/ADT/SmallVector.h" 20 21 #define GET_SUBTARGETINFO_TARGET_DESC 22 #define GET_SUBTARGETINFO_CTOR 23 #include "ARMGenSubtargetInfo.inc" 24 25 using namespace llvm; 26 27 static cl::opt<bool> 28 ReserveR9("arm-reserve-r9", cl::Hidden, 29 cl::desc("Reserve R9, making it unavailable as GPR")); 30 31 static cl::opt<bool> 32 DarwinUseMOVT("arm-darwin-use-movt", cl::init(true), cl::Hidden); 33 34 static cl::opt<bool> 35 StrictAlign("arm-strict-align", cl::Hidden, 36 cl::desc("Disallow all unaligned memory accesses")); 37 38 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, 39 const std::string &FS) 40 : ARMGenSubtargetInfo(TT, CPU, FS) 41 , ARMProcFamily(Others) 42 , HasV4TOps(false) 43 , HasV5TOps(false) 44 , HasV5TEOps(false) 45 , HasV6Ops(false) 46 , HasV6T2Ops(false) 47 , HasV7Ops(false) 48 , HasVFPv2(false) 49 , HasVFPv3(false) 50 , HasNEON(false) 51 , UseNEONForSinglePrecisionFP(false) 52 , SlowFPVMLx(false) 53 , HasVMLxForwarding(false) 54 , SlowFPBrcc(false) 55 , InThumbMode(false) 56 , InNaClMode(false) 57 , HasThumb2(false) 58 , NoARM(false) 59 , PostRAScheduler(false) 60 , IsR9Reserved(ReserveR9) 61 , UseMovt(false) 62 , HasFP16(false) 63 , HasD16(false) 64 , HasHardwareDivide(false) 65 , HasT2ExtractPack(false) 66 , HasDataBarrier(false) 67 , Pref32BitThumb(false) 68 , AvoidCPSRPartialUpdate(false) 69 , HasMPExtension(false) 70 , FPOnlySP(false) 71 , AllowsUnalignedMem(false) 72 , Thumb2DSP(false) 73 , stackAlignment(4) 74 , CPUString(CPU) 75 , TargetTriple(TT) 76 , TargetABI(ARM_ABI_APCS) { 77 // Determine default and user specified characteristics 78 if (CPUString.empty()) 79 CPUString = "generic"; 80 81 // Insert the architecture feature derived from the target triple into the 82 // feature string. This is important for setting features that are implied 83 // based on the architecture version. 84 std::string ArchFS = ARM_MC::ParseARMTriple(TT); 85 if (!FS.empty()) { 86 if (!ArchFS.empty()) 87 ArchFS = ArchFS + "," + FS; 88 else 89 ArchFS = FS; 90 } 91 ParseSubtargetFeatures(CPUString, ArchFS); 92 93 // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a 94 // ARM version or CPU and then remove this. 95 if (!HasV6T2Ops && hasThumb2()) 96 HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true; 97 98 // Initialize scheduling itinerary for the specified CPU. 99 InstrItins = getInstrItineraryForCPU(CPUString); 100 101 // After parsing Itineraries, set ItinData.IssueWidth. 102 computeIssueWidth(); 103 104 if (TT.find("eabi") != std::string::npos) 105 TargetABI = ARM_ABI_AAPCS; 106 107 if (isAAPCS_ABI()) 108 stackAlignment = 8; 109 110 if (!isTargetDarwin()) 111 UseMovt = hasV6T2Ops(); 112 else { 113 IsR9Reserved = ReserveR9 | !HasV6Ops; 114 UseMovt = DarwinUseMOVT && hasV6T2Ops(); 115 } 116 117 if (!isThumb() || hasThumb2()) 118 PostRAScheduler = true; 119 120 // v6+ may or may not support unaligned mem access depending on the system 121 // configuration. 122 if (!StrictAlign && hasV6Ops() && isTargetDarwin()) 123 AllowsUnalignedMem = true; 124 } 125 126 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol. 127 bool 128 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV, 129 Reloc::Model RelocM) const { 130 if (RelocM == Reloc::Static) 131 return false; 132 133 // Materializable GVs (in JIT lazy compilation mode) do not require an extra 134 // load from stub. 135 bool isDecl = GV->hasAvailableExternallyLinkage(); 136 if (GV->isDeclaration() && !GV->isMaterializable()) 137 isDecl = true; 138 139 if (!isTargetDarwin()) { 140 // Extra load is needed for all externally visible. 141 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility()) 142 return false; 143 return true; 144 } else { 145 if (RelocM == Reloc::PIC_) { 146 // If this is a strong reference to a definition, it is definitely not 147 // through a stub. 148 if (!isDecl && !GV->isWeakForLinker()) 149 return false; 150 151 // Unless we have a symbol with hidden visibility, we have to go through a 152 // normal $non_lazy_ptr stub because this symbol might be resolved late. 153 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference. 154 return true; 155 156 // If symbol visibility is hidden, we have a stub for common symbol 157 // references and external declarations. 158 if (isDecl || GV->hasCommonLinkage()) 159 // Hidden $non_lazy_ptr reference. 160 return true; 161 162 return false; 163 } else { 164 // If this is a strong reference to a definition, it is definitely not 165 // through a stub. 166 if (!isDecl && !GV->isWeakForLinker()) 167 return false; 168 169 // Unless we have a symbol with hidden visibility, we have to go through a 170 // normal $non_lazy_ptr stub because this symbol might be resolved late. 171 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference. 172 return true; 173 } 174 } 175 176 return false; 177 } 178 179 unsigned ARMSubtarget::getMispredictionPenalty() const { 180 // If we have a reasonable estimate of the pipeline depth, then we can 181 // estimate the penalty of a misprediction based on that. 182 if (isCortexA8()) 183 return 13; 184 else if (isCortexA9()) 185 return 8; 186 187 // Otherwise, just return a sensible default. 188 return 10; 189 } 190 191 void ARMSubtarget::computeIssueWidth() { 192 unsigned allStage1Units = 0; 193 for (const InstrItinerary *itin = InstrItins.Itineraries; 194 itin->FirstStage != ~0U; ++itin) { 195 const InstrStage *IS = InstrItins.Stages + itin->FirstStage; 196 allStage1Units |= IS->getUnits(); 197 } 198 InstrItins.IssueWidth = 0; 199 while (allStage1Units) { 200 ++InstrItins.IssueWidth; 201 // clear the lowest bit 202 allStage1Units ^= allStage1Units & ~(allStage1Units - 1); 203 } 204 assert(InstrItins.IssueWidth <= 2 && "itinerary bug, too many stage 1 units"); 205 } 206 207 bool ARMSubtarget::enablePostRAScheduler( 208 CodeGenOpt::Level OptLevel, 209 TargetSubtargetInfo::AntiDepBreakMode& Mode, 210 RegClassVector& CriticalPathRCs) const { 211 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL; 212 CriticalPathRCs.clear(); 213 CriticalPathRCs.push_back(&ARM::GPRRegClass); 214 return PostRAScheduler && OptLevel >= CodeGenOpt::Default; 215 } 216