1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMSubtarget.h"
15 #include "ARMFrameLowering.h"
16 #include "ARMISelLowering.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSelectionDAGInfo.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "Thumb1FrameLowering.h"
23 #include "Thumb1InstrInfo.h"
24 #include "Thumb2InstrInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Attributes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetOptions.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 #include "llvm/Support/TargetParser.h"
35 
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "arm-subtarget"
39 
40 #define GET_SUBTARGETINFO_TARGET_DESC
41 #define GET_SUBTARGETINFO_CTOR
42 #include "ARMGenSubtargetInfo.inc"
43 
44 static cl::opt<bool>
45 UseFusedMulOps("arm-use-mulops",
46                cl::init(true), cl::Hidden);
47 
48 enum ITMode {
49   DefaultIT,
50   RestrictedIT,
51   NoRestrictedIT
52 };
53 
54 static cl::opt<ITMode>
55 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
56    cl::ZeroOrMore,
57    cl::values(clEnumValN(DefaultIT, "arm-default-it",
58                          "Generate IT block based on arch"),
59               clEnumValN(RestrictedIT, "arm-restrict-it",
60                          "Disallow deprecated IT based on ARMv8"),
61               clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
62                          "Allow IT blocks based on ARMv7"),
63               clEnumValEnd));
64 
65 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
66 /// currently supported (for testing only).
67 static cl::opt<bool>
68 ForceFastISel("arm-force-fast-isel",
69                cl::init(false), cl::Hidden);
70 
71 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
72 /// so that we can use initializer lists for subtarget initialization.
73 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
74                                                             StringRef FS) {
75   initializeEnvironment();
76   initSubtargetFeatures(CPU, FS);
77   return *this;
78 }
79 
80 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
81                                                         StringRef FS) {
82   ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
83   if (STI.isThumb1Only())
84     return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
85 
86   return new ARMFrameLowering(STI);
87 }
88 
89 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
90                            const std::string &FS,
91                            const ARMBaseTargetMachine &TM, bool IsLittle)
92     : ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
93       CPUString(CPU), IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options),
94       TM(TM), FrameLowering(initializeFrameLowering(CPU, FS)),
95       // At this point initializeSubtargetDependencies has been called so
96       // we can query directly.
97       InstrInfo(isThumb1Only()
98                     ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
99                     : !isThumb()
100                           ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
101                           : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
102       TLInfo(TM, *this) {}
103 
104 bool ARMSubtarget::isXRaySupported() const {
105   // We don't currently suppport Thumb, but Windows requires Thumb.
106   return hasV6Ops() && hasARMOps() && !isTargetWindows();
107 }
108 
109 void ARMSubtarget::initializeEnvironment() {
110   // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
111   // directly from it, but we can try to make sure they're consistent when both
112   // available.
113   UseSjLjEH = isTargetDarwin() && !isTargetWatchABI();
114   assert((!TM.getMCAsmInfo() ||
115           (TM.getMCAsmInfo()->getExceptionHandlingType() ==
116            ExceptionHandling::SjLj) == UseSjLjEH) &&
117          "inconsistent sjlj choice between CodeGen and MC");
118 }
119 
120 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
121   if (CPUString.empty()) {
122     CPUString = "generic";
123 
124     if (isTargetDarwin()) {
125       StringRef ArchName = TargetTriple.getArchName();
126       unsigned ArchKind = llvm::ARM::parseArch(ArchName);
127       if (ArchKind == llvm::ARM::AK_ARMV7S)
128         // Default to the Swift CPU when targeting armv7s/thumbv7s.
129         CPUString = "swift";
130       else if (ArchKind == llvm::ARM::AK_ARMV7K)
131         // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
132         // ARMv7k does not use SjLj exception handling.
133         CPUString = "cortex-a7";
134     }
135   }
136 
137   // Insert the architecture feature derived from the target triple into the
138   // feature string. This is important for setting features that are implied
139   // based on the architecture version.
140   std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
141   if (!FS.empty()) {
142     if (!ArchFS.empty())
143       ArchFS = (Twine(ArchFS) + "," + FS).str();
144     else
145       ArchFS = FS;
146   }
147   ParseSubtargetFeatures(CPUString, ArchFS);
148 
149   // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
150   // Assert this for now to make the change obvious.
151   assert(hasV6T2Ops() || !hasThumb2());
152 
153   // Keep a pointer to static instruction cost data for the specified CPU.
154   SchedModel = getSchedModelForCPU(CPUString);
155 
156   // Initialize scheduling itinerary for the specified CPU.
157   InstrItins = getInstrItineraryForCPU(CPUString);
158 
159   // FIXME: this is invalid for WindowsCE
160   if (isTargetWindows())
161     NoARM = true;
162 
163   if (isAAPCS_ABI())
164     stackAlignment = 8;
165   if (isTargetNaCl() || isAAPCS16_ABI())
166     stackAlignment = 16;
167 
168   // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
169   // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
170   // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
171   // support in the assembler and linker to be used. This would need to be
172   // fixed to fully support tail calls in Thumb1.
173   //
174   // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
175   // LR.  This means if we need to reload LR, it takes an extra instructions,
176   // which outweighs the value of the tail call; but here we don't know yet
177   // whether LR is going to be used.  Probably the right approach is to
178   // generate the tail call here and turn it back into CALL/RET in
179   // emitEpilogue if LR is used.
180 
181   // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
182   // but we need to make sure there are enough registers; the only valid
183   // registers are the 4 used for parameters.  We don't currently do this
184   // case.
185 
186   SupportsTailCall = !isThumb() || hasV8MBaselineOps();
187 
188   if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
189     SupportsTailCall = false;
190 
191   switch (IT) {
192   case DefaultIT:
193     RestrictIT = hasV8Ops();
194     break;
195   case RestrictedIT:
196     RestrictIT = true;
197     break;
198   case NoRestrictedIT:
199     RestrictIT = false;
200     break;
201   }
202 
203   // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
204   const FeatureBitset &Bits = getFeatureBits();
205   if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
206       (Options.UnsafeFPMath || isTargetDarwin()))
207     UseNEONForSinglePrecisionFP = true;
208 
209   if (isRWPI())
210     ReserveR9 = true;
211 
212   // FIXME: Teach TableGen to deal with these instead of doing it manually here.
213   switch (ARMProcFamily) {
214   case Others:
215   case CortexA5:
216     break;
217   case CortexA7:
218     LdStMultipleTiming = DoubleIssue;
219     break;
220   case CortexA8:
221     LdStMultipleTiming = DoubleIssue;
222     break;
223   case CortexA9:
224     LdStMultipleTiming = DoubleIssueCheckUnalignedAccess;
225     PreISelOperandLatencyAdjustment = 1;
226     break;
227   case CortexA12:
228     break;
229   case CortexA15:
230     MaxInterleaveFactor = 2;
231     PreISelOperandLatencyAdjustment = 1;
232     PartialUpdateClearance = 12;
233     break;
234   case CortexA17:
235   case CortexA32:
236   case CortexA35:
237   case CortexA53:
238   case CortexA57:
239   case CortexA72:
240   case CortexA73:
241   case CortexR4:
242   case CortexR4F:
243   case CortexR5:
244   case CortexR7:
245   case CortexM3:
246   case ExynosM1:
247     break;
248   case Krait:
249     PreISelOperandLatencyAdjustment = 1;
250     break;
251   case Swift:
252     MaxInterleaveFactor = 2;
253     LdStMultipleTiming = SingleIssuePlusExtras;
254     PreISelOperandLatencyAdjustment = 1;
255     PartialUpdateClearance = 12;
256     break;
257   }
258 }
259 
260 bool ARMSubtarget::isAPCS_ABI() const {
261   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
262   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
263 }
264 bool ARMSubtarget::isAAPCS_ABI() const {
265   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
266   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
267          TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
268 }
269 bool ARMSubtarget::isAAPCS16_ABI() const {
270   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
271   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
272 }
273 
274 bool ARMSubtarget::isROPI() const {
275   return TM.getRelocationModel() == Reloc::ROPI ||
276          TM.getRelocationModel() == Reloc::ROPI_RWPI;
277 }
278 bool ARMSubtarget::isRWPI() const {
279   return TM.getRelocationModel() == Reloc::RWPI ||
280          TM.getRelocationModel() == Reloc::ROPI_RWPI;
281 }
282 
283 bool ARMSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
284   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
285     return true;
286 
287   // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
288   // the section that is being relocated. This means we have to use o load even
289   // for GVs that are known to be local to the dso.
290   if (isTargetMachO() && TM.isPositionIndependent() &&
291       (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
292     return true;
293 
294   return false;
295 }
296 
297 unsigned ARMSubtarget::getMispredictionPenalty() const {
298   return SchedModel.MispredictPenalty;
299 }
300 
301 bool ARMSubtarget::hasSinCos() const {
302   return isTargetWatchOS() ||
303     (isTargetIOS() && !getTargetTriple().isOSVersionLT(7, 0));
304 }
305 
306 bool ARMSubtarget::enableMachineScheduler() const {
307   // Enable the MachineScheduler before register allocation for out-of-order
308   // architectures where we do not use the PostRA scheduler anymore (for now
309   // restricted to swift).
310   return getSchedModel().isOutOfOrder() && isSwift();
311 }
312 
313 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
314 bool ARMSubtarget::enablePostRAScheduler() const {
315   // No need for PostRA scheduling on out of order CPUs (for now restricted to
316   // swift).
317   if (getSchedModel().isOutOfOrder() && isSwift())
318     return false;
319   return (!isThumb() || hasThumb2());
320 }
321 
322 bool ARMSubtarget::enableAtomicExpand() const {
323   return hasAnyDataBarrier() && (!isThumb() || hasV8MBaselineOps());
324 }
325 
326 bool ARMSubtarget::useStride4VFPs(const MachineFunction &MF) const {
327   // For general targets, the prologue can grow when VFPs are allocated with
328   // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
329   // format which it's more important to get right.
330   return isTargetWatchABI() || (isSwift() && !MF.getFunction()->optForMinSize());
331 }
332 
333 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
334   // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
335   // immediates as it is inherently position independent, and may be out of
336   // range otherwise.
337   return !NoMovt && hasV8MBaselineOps() &&
338          (isTargetWindows() || !MF.getFunction()->optForMinSize());
339 }
340 
341 bool ARMSubtarget::useFastISel() const {
342   // Enable fast-isel for any target, for testing only.
343   if (ForceFastISel)
344     return true;
345 
346   // Limit fast-isel to the targets that are or have been tested.
347   if (!hasV6Ops())
348     return false;
349 
350   // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
351   return TM.Options.EnableFastISel &&
352          ((isTargetMachO() && !isThumb1Only()) ||
353           (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
354 }
355