1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the ARM specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "ARMSubtarget.h" 15 #include "ARMBaseRegisterInfo.h" 16 #include "ARMBaseInstrInfo.h" 17 #include "llvm/GlobalValue.h" 18 #include "llvm/Target/TargetInstrInfo.h" 19 #include "llvm/Support/CommandLine.h" 20 21 #define GET_SUBTARGETINFO_TARGET_DESC 22 #define GET_SUBTARGETINFO_CTOR 23 #include "ARMGenSubtargetInfo.inc" 24 25 using namespace llvm; 26 27 static cl::opt<bool> 28 ReserveR9("arm-reserve-r9", cl::Hidden, 29 cl::desc("Reserve R9, making it unavailable as GPR")); 30 31 static cl::opt<bool> 32 DarwinUseMOVT("arm-darwin-use-movt", cl::init(true), cl::Hidden); 33 34 static cl::opt<bool> 35 UseFusedMulOps("arm-use-mulops", 36 cl::init(true), cl::Hidden); 37 38 static cl::opt<bool> 39 StrictAlign("arm-strict-align", cl::Hidden, 40 cl::desc("Disallow all unaligned memory accesses")); 41 42 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, 43 const std::string &FS) 44 : ARMGenSubtargetInfo(TT, CPU, FS) 45 , ARMProcFamily(Others) 46 , HasV4TOps(false) 47 , HasV5TOps(false) 48 , HasV5TEOps(false) 49 , HasV6Ops(false) 50 , HasV6T2Ops(false) 51 , HasV7Ops(false) 52 , HasVFPv2(false) 53 , HasVFPv3(false) 54 , HasVFPv4(false) 55 , HasNEON(false) 56 , UseNEONForSinglePrecisionFP(false) 57 , UseMulOps(UseFusedMulOps) 58 , SlowFPVMLx(false) 59 , HasVMLxForwarding(false) 60 , SlowFPBrcc(false) 61 , InThumbMode(false) 62 , HasThumb2(false) 63 , IsMClass(false) 64 , NoARM(false) 65 , PostRAScheduler(false) 66 , IsR9Reserved(ReserveR9) 67 , UseMovt(false) 68 , SupportsTailCall(false) 69 , HasFP16(false) 70 , HasD16(false) 71 , HasHardwareDivide(false) 72 , HasHardwareDivideInARM(false) 73 , HasT2ExtractPack(false) 74 , HasDataBarrier(false) 75 , Pref32BitThumb(false) 76 , AvoidCPSRPartialUpdate(false) 77 , HasRAS(false) 78 , HasMPExtension(false) 79 , FPOnlySP(false) 80 , AllowsUnalignedMem(false) 81 , Thumb2DSP(false) 82 , stackAlignment(4) 83 , CPUString(CPU) 84 , TargetTriple(TT) 85 , TargetABI(ARM_ABI_APCS) { 86 // Determine default and user specified characteristics 87 if (CPUString.empty()) 88 CPUString = "generic"; 89 90 // Insert the architecture feature derived from the target triple into the 91 // feature string. This is important for setting features that are implied 92 // based on the architecture version. 93 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPUString); 94 if (!FS.empty()) { 95 if (!ArchFS.empty()) 96 ArchFS = ArchFS + "," + FS; 97 else 98 ArchFS = FS; 99 } 100 ParseSubtargetFeatures(CPUString, ArchFS); 101 102 // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a 103 // ARM version or CPU and then remove this. 104 if (!HasV6T2Ops && hasThumb2()) 105 HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true; 106 107 // Keep a pointer to static instruction cost data for the specified CPU. 108 SchedModel = getSchedModelForCPU(CPUString); 109 110 // Initialize scheduling itinerary for the specified CPU. 111 InstrItins = getInstrItineraryForCPU(CPUString); 112 113 if ((TT.find("eabi") != std::string::npos) || (isTargetIOS() && isMClass())) 114 // FIXME: We might want to separate AAPCS and EABI. Some systems, e.g. 115 // Darwin-EABI conforms to AACPS but not the rest of EABI. 116 TargetABI = ARM_ABI_AAPCS; 117 118 if (isAAPCS_ABI()) 119 stackAlignment = 8; 120 121 if (!isTargetIOS()) 122 UseMovt = hasV6T2Ops(); 123 else { 124 IsR9Reserved = ReserveR9 | !HasV6Ops; 125 UseMovt = DarwinUseMOVT && hasV6T2Ops(); 126 SupportsTailCall = !getTargetTriple().isOSVersionLT(5, 0); 127 } 128 129 if (!isThumb() || hasThumb2()) 130 PostRAScheduler = true; 131 132 // v6+ may or may not support unaligned mem access depending on the system 133 // configuration. 134 if (!StrictAlign && hasV6Ops() && isTargetDarwin()) 135 AllowsUnalignedMem = true; 136 } 137 138 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol. 139 bool 140 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV, 141 Reloc::Model RelocM) const { 142 if (RelocM == Reloc::Static) 143 return false; 144 145 // Materializable GVs (in JIT lazy compilation mode) do not require an extra 146 // load from stub. 147 bool isDecl = GV->hasAvailableExternallyLinkage(); 148 if (GV->isDeclaration() && !GV->isMaterializable()) 149 isDecl = true; 150 151 if (!isTargetDarwin()) { 152 // Extra load is needed for all externally visible. 153 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility()) 154 return false; 155 return true; 156 } else { 157 if (RelocM == Reloc::PIC_) { 158 // If this is a strong reference to a definition, it is definitely not 159 // through a stub. 160 if (!isDecl && !GV->isWeakForLinker()) 161 return false; 162 163 // Unless we have a symbol with hidden visibility, we have to go through a 164 // normal $non_lazy_ptr stub because this symbol might be resolved late. 165 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference. 166 return true; 167 168 // If symbol visibility is hidden, we have a stub for common symbol 169 // references and external declarations. 170 if (isDecl || GV->hasCommonLinkage()) 171 // Hidden $non_lazy_ptr reference. 172 return true; 173 174 return false; 175 } else { 176 // If this is a strong reference to a definition, it is definitely not 177 // through a stub. 178 if (!isDecl && !GV->isWeakForLinker()) 179 return false; 180 181 // Unless we have a symbol with hidden visibility, we have to go through a 182 // normal $non_lazy_ptr stub because this symbol might be resolved late. 183 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference. 184 return true; 185 } 186 } 187 188 return false; 189 } 190 191 unsigned ARMSubtarget::getMispredictionPenalty() const { 192 return SchedModel->MispredictPenalty; 193 } 194 195 bool ARMSubtarget::enablePostRAScheduler( 196 CodeGenOpt::Level OptLevel, 197 TargetSubtargetInfo::AntiDepBreakMode& Mode, 198 RegClassVector& CriticalPathRCs) const { 199 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL; 200 CriticalPathRCs.clear(); 201 CriticalPathRCs.push_back(&ARM::GPRRegClass); 202 return PostRAScheduler && OptLevel >= CodeGenOpt::Default; 203 } 204