1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the ARM specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "ARMSubtarget.h" 15 #include "ARMBaseRegisterInfo.h" 16 #include "llvm/GlobalValue.h" 17 #include "llvm/Target/TargetSubtargetInfo.h" 18 #include "llvm/Support/CommandLine.h" 19 20 #define GET_SUBTARGETINFO_TARGET_DESC 21 #define GET_SUBTARGETINFO_CTOR 22 #include "ARMGenSubtargetInfo.inc" 23 24 using namespace llvm; 25 26 static cl::opt<bool> 27 ReserveR9("arm-reserve-r9", cl::Hidden, 28 cl::desc("Reserve R9, making it unavailable as GPR")); 29 30 static cl::opt<bool> 31 DarwinUseMOVT("arm-darwin-use-movt", cl::init(true), cl::Hidden); 32 33 static cl::opt<bool> 34 StrictAlign("arm-strict-align", cl::Hidden, 35 cl::desc("Disallow all unaligned memory accesses")); 36 37 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, 38 const std::string &FS) 39 : ARMGenSubtargetInfo(TT, CPU, FS) 40 , ARMProcFamily(Others) 41 , HasV4TOps(false) 42 , HasV5TOps(false) 43 , HasV5TEOps(false) 44 , HasV6Ops(false) 45 , HasV6T2Ops(false) 46 , HasV7Ops(false) 47 , HasVFPv2(false) 48 , HasVFPv3(false) 49 , HasVFPv4(false) 50 , HasNEON(false) 51 , UseNEONForSinglePrecisionFP(false) 52 , SlowFPVMLx(false) 53 , HasVMLxForwarding(false) 54 , SlowFPBrcc(false) 55 , InThumbMode(false) 56 , HasThumb2(false) 57 , IsMClass(false) 58 , NoARM(false) 59 , PostRAScheduler(false) 60 , IsR9Reserved(ReserveR9) 61 , UseMovt(false) 62 , SupportsTailCall(false) 63 , HasFP16(false) 64 , HasD16(false) 65 , HasHardwareDivide(false) 66 , HasT2ExtractPack(false) 67 , HasDataBarrier(false) 68 , Pref32BitThumb(false) 69 , AvoidCPSRPartialUpdate(false) 70 , HasRAS(false) 71 , HasMPExtension(false) 72 , FPOnlySP(false) 73 , AllowsUnalignedMem(false) 74 , Thumb2DSP(false) 75 , stackAlignment(4) 76 , CPUString(CPU) 77 , TargetTriple(TT) 78 , TargetABI(ARM_ABI_APCS) { 79 // Determine default and user specified characteristics 80 if (CPUString.empty()) 81 CPUString = "generic"; 82 83 // Insert the architecture feature derived from the target triple into the 84 // feature string. This is important for setting features that are implied 85 // based on the architecture version. 86 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPUString); 87 if (!FS.empty()) { 88 if (!ArchFS.empty()) 89 ArchFS = ArchFS + "," + FS; 90 else 91 ArchFS = FS; 92 } 93 ParseSubtargetFeatures(CPUString, ArchFS); 94 95 // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a 96 // ARM version or CPU and then remove this. 97 if (!HasV6T2Ops && hasThumb2()) 98 HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true; 99 100 // Initialize scheduling itinerary for the specified CPU. 101 InstrItins = getInstrItineraryForCPU(CPUString); 102 103 if ((TT.find("eabi") != std::string::npos) || (isTargetIOS() && isMClass())) 104 // FIXME: We might want to separate AAPCS and EABI. Some systems, e.g. 105 // Darwin-EABI conforms to AACPS but not the rest of EABI. 106 TargetABI = ARM_ABI_AAPCS; 107 108 if (isAAPCS_ABI()) 109 stackAlignment = 8; 110 111 if (!isTargetIOS()) 112 UseMovt = hasV6T2Ops(); 113 else { 114 IsR9Reserved = ReserveR9 | !HasV6Ops; 115 UseMovt = DarwinUseMOVT && hasV6T2Ops(); 116 SupportsTailCall = !getTargetTriple().isOSVersionLT(5, 0); 117 } 118 119 if (!isThumb() || hasThumb2()) 120 PostRAScheduler = true; 121 122 // v6+ may or may not support unaligned mem access depending on the system 123 // configuration. 124 if (!StrictAlign && hasV6Ops() && isTargetDarwin()) 125 AllowsUnalignedMem = true; 126 } 127 128 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol. 129 bool 130 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV, 131 Reloc::Model RelocM) const { 132 if (RelocM == Reloc::Static) 133 return false; 134 135 // Materializable GVs (in JIT lazy compilation mode) do not require an extra 136 // load from stub. 137 bool isDecl = GV->hasAvailableExternallyLinkage(); 138 if (GV->isDeclaration() && !GV->isMaterializable()) 139 isDecl = true; 140 141 if (!isTargetDarwin()) { 142 // Extra load is needed for all externally visible. 143 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility()) 144 return false; 145 return true; 146 } else { 147 if (RelocM == Reloc::PIC_) { 148 // If this is a strong reference to a definition, it is definitely not 149 // through a stub. 150 if (!isDecl && !GV->isWeakForLinker()) 151 return false; 152 153 // Unless we have a symbol with hidden visibility, we have to go through a 154 // normal $non_lazy_ptr stub because this symbol might be resolved late. 155 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference. 156 return true; 157 158 // If symbol visibility is hidden, we have a stub for common symbol 159 // references and external declarations. 160 if (isDecl || GV->hasCommonLinkage()) 161 // Hidden $non_lazy_ptr reference. 162 return true; 163 164 return false; 165 } else { 166 // If this is a strong reference to a definition, it is definitely not 167 // through a stub. 168 if (!isDecl && !GV->isWeakForLinker()) 169 return false; 170 171 // Unless we have a symbol with hidden visibility, we have to go through a 172 // normal $non_lazy_ptr stub because this symbol might be resolved late. 173 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference. 174 return true; 175 } 176 } 177 178 return false; 179 } 180 181 unsigned ARMSubtarget::getMispredictionPenalty() const { 182 // If we have a reasonable estimate of the pipeline depth, then we can 183 // estimate the penalty of a misprediction based on that. 184 if (isCortexA8()) 185 return 13; 186 else if (isCortexA9()) 187 return 8; 188 189 // Otherwise, just return a sensible default. 190 return 10; 191 } 192 193 bool ARMSubtarget::enablePostRAScheduler( 194 CodeGenOpt::Level OptLevel, 195 TargetSubtargetInfo::AntiDepBreakMode& Mode, 196 RegClassVector& CriticalPathRCs) const { 197 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL; 198 CriticalPathRCs.clear(); 199 CriticalPathRCs.push_back(&ARM::GPRRegClass); 200 return PostRAScheduler && OptLevel >= CodeGenOpt::Default; 201 } 202