1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ------------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARM specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMSubtarget.h"
15 #include "ARMGenSubtarget.inc"
16 #include "ARMBaseRegisterInfo.h"
17 #include "llvm/GlobalValue.h"
18 #include "llvm/Target/TargetOptions.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/ADT/SmallVector.h"
21 using namespace llvm;
22 
23 static cl::opt<bool>
24 ReserveR9("arm-reserve-r9", cl::Hidden,
25           cl::desc("Reserve R9, making it unavailable as GPR"));
26 
27 static cl::opt<bool>
28 DarwinUseMOVT("arm-darwin-use-movt", cl::init(true), cl::Hidden);
29 
30 static cl::opt<bool>
31 StrictAlign("arm-strict-align", cl::Hidden,
32             cl::desc("Disallow all unaligned memory accesses"));
33 
34 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
35                            bool isT)
36   : ARMArchVersion(V4)
37   , ARMProcFamily(Others)
38   , ARMFPUType(None)
39   , UseNEONForSinglePrecisionFP(false)
40   , SlowFPVMLx(false)
41   , HasVMLxForwarding(false)
42   , SlowFPBrcc(false)
43   , IsThumb(isT)
44   , ThumbMode(Thumb1)
45   , NoARM(false)
46   , PostRAScheduler(false)
47   , IsR9Reserved(ReserveR9)
48   , UseMovt(false)
49   , HasFP16(false)
50   , HasD16(false)
51   , HasHardwareDivide(false)
52   , HasT2ExtractPack(false)
53   , HasDataBarrier(false)
54   , Pref32BitThumb(false)
55   , HasMPExtension(false)
56   , FPOnlySP(false)
57   , AllowsUnalignedMem(false)
58   , stackAlignment(4)
59   , CPUString("generic")
60   , TargetTriple(TT)
61   , TargetABI(ARM_ABI_APCS) {
62   // Default to soft float ABI
63   if (FloatABIType == FloatABI::Default)
64     FloatABIType = FloatABI::Soft;
65 
66   // Determine default and user specified characteristics
67 
68   // When no arch is specified either by CPU or by attributes, make the default
69   // ARMv4T.
70   const char *ARMArchFeature = "";
71   if (CPUString == "generic" && (FS.empty() || FS == "generic")) {
72     ARMArchVersion = V4T;
73     ARMArchFeature = ",+v4t";
74   }
75 
76   // Set the boolean corresponding to the current target triple, or the default
77   // if one cannot be determined, to true.
78   unsigned Len = TT.length();
79   unsigned Idx = 0;
80 
81   if (Len >= 5 && TT.substr(0, 4) == "armv")
82     Idx = 4;
83   else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
84     IsThumb = true;
85     if (Len >= 7 && TT[5] == 'v')
86       Idx = 6;
87   }
88   if (Idx) {
89     unsigned SubVer = TT[Idx];
90     if (SubVer >= '7' && SubVer <= '9') {
91       ARMArchVersion = V7A;
92       ARMArchFeature = ",+v7a";
93       if (Len >= Idx+2 && TT[Idx+1] == 'm') {
94         ARMArchVersion = V7M;
95         ARMArchFeature = ",+v7m";
96       }
97     } else if (SubVer == '6') {
98       ARMArchVersion = V6;
99       ARMArchFeature = ",+v6";
100       if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') {
101         ARMArchVersion = V6T2;
102         ARMArchFeature = ",+v6t2";
103       }
104     } else if (SubVer == '5') {
105       ARMArchVersion = V5T;
106       ARMArchFeature = ",+v5t";
107       if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') {
108         ARMArchVersion = V5TE;
109         ARMArchFeature = ",+v5te";
110       }
111     } else if (SubVer == '4') {
112       if (Len >= Idx+2 && TT[Idx+1] == 't') {
113         ARMArchVersion = V4T;
114         ARMArchFeature = ",+v4t";
115       } else {
116         ARMArchVersion = V4;
117         ARMArchFeature = "";
118       }
119     }
120   }
121 
122   if (TT.find("eabi") != std::string::npos)
123     TargetABI = ARM_ABI_AAPCS;
124 
125   // Parse features string.  If the first entry in FS (the CPU) is missing,
126   // insert the architecture feature derived from the target triple.  This is
127   // important for setting features that are implied based on the architecture
128   // version.
129   std::string FSWithArch;
130   if (FS.empty())
131     FSWithArch = std::string(ARMArchFeature);
132   else if (FS.find(',') == 0)
133     FSWithArch = std::string(ARMArchFeature) + FS;
134   else
135     FSWithArch = FS;
136   CPUString = ParseSubtargetFeatures(FSWithArch, CPUString);
137 
138   // After parsing Itineraries, set ItinData.IssueWidth.
139   computeIssueWidth();
140 
141   // Thumb2 implies at least V6T2.
142   if (ARMArchVersion >= V6T2)
143     ThumbMode = Thumb2;
144   else if (ThumbMode >= Thumb2)
145     ARMArchVersion = V6T2;
146 
147   if (isAAPCS_ABI())
148     stackAlignment = 8;
149 
150   if (!isTargetDarwin())
151     UseMovt = hasV6T2Ops();
152   else {
153     IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
154     UseMovt = DarwinUseMOVT && hasV6T2Ops();
155   }
156 
157   if (!isThumb() || hasThumb2())
158     PostRAScheduler = true;
159 
160   // v6+ may or may not support unaligned mem access depending on the system
161   // configuration.
162   if (!StrictAlign && hasV6Ops() && isTargetDarwin())
163     AllowsUnalignedMem = true;
164 }
165 
166 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
167 bool
168 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
169                                  Reloc::Model RelocM) const {
170   if (RelocM == Reloc::Static)
171     return false;
172 
173   // Materializable GVs (in JIT lazy compilation mode) do not require an extra
174   // load from stub.
175   bool isDecl = GV->hasAvailableExternallyLinkage();
176   if (GV->isDeclaration() && !GV->isMaterializable())
177     isDecl = true;
178 
179   if (!isTargetDarwin()) {
180     // Extra load is needed for all externally visible.
181     if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
182       return false;
183     return true;
184   } else {
185     if (RelocM == Reloc::PIC_) {
186       // If this is a strong reference to a definition, it is definitely not
187       // through a stub.
188       if (!isDecl && !GV->isWeakForLinker())
189         return false;
190 
191       // Unless we have a symbol with hidden visibility, we have to go through a
192       // normal $non_lazy_ptr stub because this symbol might be resolved late.
193       if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
194         return true;
195 
196       // If symbol visibility is hidden, we have a stub for common symbol
197       // references and external declarations.
198       if (isDecl || GV->hasCommonLinkage())
199         // Hidden $non_lazy_ptr reference.
200         return true;
201 
202       return false;
203     } else {
204       // If this is a strong reference to a definition, it is definitely not
205       // through a stub.
206       if (!isDecl && !GV->isWeakForLinker())
207         return false;
208 
209       // Unless we have a symbol with hidden visibility, we have to go through a
210       // normal $non_lazy_ptr stub because this symbol might be resolved late.
211       if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
212         return true;
213     }
214   }
215 
216   return false;
217 }
218 
219 unsigned ARMSubtarget::getMispredictionPenalty() const {
220   // If we have a reasonable estimate of the pipeline depth, then we can
221   // estimate the penalty of a misprediction based on that.
222   if (isCortexA8())
223     return 13;
224   else if (isCortexA9())
225     return 8;
226 
227   // Otherwise, just return a sensible default.
228   return 10;
229 }
230 
231 void ARMSubtarget::computeIssueWidth() {
232   unsigned allStage1Units = 0;
233   for (const InstrItinerary *itin = InstrItins.Itineraries;
234        itin->FirstStage != ~0U; ++itin) {
235     const InstrStage *IS = InstrItins.Stages + itin->FirstStage;
236     allStage1Units |= IS->getUnits();
237   }
238   InstrItins.IssueWidth = 0;
239   while (allStage1Units) {
240     ++InstrItins.IssueWidth;
241     // clear the lowest bit
242     allStage1Units ^= allStage1Units & ~(allStage1Units - 1);
243   }
244   assert(InstrItins.IssueWidth <= 2 && "itinerary bug, too many stage 1 units");
245 }
246 
247 bool ARMSubtarget::enablePostRAScheduler(
248            CodeGenOpt::Level OptLevel,
249            TargetSubtarget::AntiDepBreakMode& Mode,
250            RegClassVector& CriticalPathRCs) const {
251   Mode = TargetSubtarget::ANTIDEP_CRITICAL;
252   CriticalPathRCs.clear();
253   CriticalPathRCs.push_back(&ARM::GPRRegClass);
254   return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
255 }
256