1//===- ARMRegisterInfo.td - ARM Register defs -------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the ARM register file 12//===----------------------------------------------------------------------===// 13 14// Registers are identified with 4-bit ID numbers. 15class ARMReg<bits<4> num, string n, list<Register> subregs = []> : Register<n> { 16 field bits<4> Num; 17 let Namespace = "ARM"; 18 let SubRegs = subregs; 19} 20 21class ARMFReg<bits<5> num, string n> : Register<n> { 22 field bits<5> Num; 23 let Namespace = "ARM"; 24} 25 26// Integer registers 27def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>; 28def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>; 29def R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>; 30def R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>; 31def R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>; 32def R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>; 33def R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>; 34def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>; 35def R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>; 36def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>; 37def R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>; 38def R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>; 39def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>; 40def SP : ARMReg<13, "sp">, DwarfRegNum<[13]>; 41def LR : ARMReg<14, "lr">, DwarfRegNum<[14]>; 42def PC : ARMReg<15, "pc">, DwarfRegNum<[15]>; 43 44// Float registers 45def S0 : ARMFReg< 0, "s0">; def S1 : ARMFReg< 1, "s1">; 46def S2 : ARMFReg< 2, "s2">; def S3 : ARMFReg< 3, "s3">; 47def S4 : ARMFReg< 4, "s4">; def S5 : ARMFReg< 5, "s5">; 48def S6 : ARMFReg< 6, "s6">; def S7 : ARMFReg< 7, "s7">; 49def S8 : ARMFReg< 8, "s8">; def S9 : ARMFReg< 9, "s9">; 50def S10 : ARMFReg<10, "s10">; def S11 : ARMFReg<11, "s11">; 51def S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">; 52def S14 : ARMFReg<14, "s14">; def S15 : ARMFReg<15, "s15">; 53def S16 : ARMFReg<16, "s16">; def S17 : ARMFReg<17, "s17">; 54def S18 : ARMFReg<18, "s18">; def S19 : ARMFReg<19, "s19">; 55def S20 : ARMFReg<20, "s20">; def S21 : ARMFReg<21, "s21">; 56def S22 : ARMFReg<22, "s22">; def S23 : ARMFReg<23, "s23">; 57def S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">; 58def S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">; 59def S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">; 60def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">; 61 62// Aliases of the F* registers used to hold 64-bit fp values (doubles) 63def D0 : ARMReg< 0, "d0", [S0, S1]>; 64def D1 : ARMReg< 1, "d1", [S2, S3]>; 65def D2 : ARMReg< 2, "d2", [S4, S5]>; 66def D3 : ARMReg< 3, "d3", [S6, S7]>; 67def D4 : ARMReg< 4, "d4", [S8, S9]>; 68def D5 : ARMReg< 5, "d5", [S10, S11]>; 69def D6 : ARMReg< 6, "d6", [S12, S13]>; 70def D7 : ARMReg< 7, "d7", [S14, S15]>; 71def D8 : ARMReg< 8, "d8", [S16, S17]>; 72def D9 : ARMReg< 9, "d9", [S18, S19]>; 73def D10 : ARMReg<10, "d10", [S20, S21]>; 74def D11 : ARMReg<11, "d11", [S22, S23]>; 75def D12 : ARMReg<12, "d12", [S24, S25]>; 76def D13 : ARMReg<13, "d13", [S26, S27]>; 77def D14 : ARMReg<14, "d14", [S28, S29]>; 78def D15 : ARMReg<15, "d15", [S30, S31]>; 79 80// VFP3 defines 16 additional double registers 81def D16 : ARMFReg<16, "d16">; def D17 : ARMFReg<17, "d17">; 82def D18 : ARMFReg<18, "d18">; def D19 : ARMFReg<19, "d19">; 83def D20 : ARMFReg<20, "d20">; def D21 : ARMFReg<21, "d21">; 84def D22 : ARMFReg<22, "d22">; def D23 : ARMFReg<23, "d23">; 85def D24 : ARMFReg<24, "d24">; def D25 : ARMFReg<25, "d25">; 86def D26 : ARMFReg<26, "d26">; def D27 : ARMFReg<27, "d27">; 87def D28 : ARMFReg<28, "d28">; def D29 : ARMFReg<29, "d29">; 88def D30 : ARMFReg<30, "d30">; def D31 : ARMFReg<31, "d31">; 89 90// Advanced SIMD (NEON) defines 16 quad-word aliases 91def Q0 : ARMReg< 0, "q0", [D0, D1]>; 92def Q1 : ARMReg< 1, "q1", [D2, D3]>; 93def Q2 : ARMReg< 2, "q2", [D4, D5]>; 94def Q3 : ARMReg< 3, "q3", [D6, D7]>; 95def Q4 : ARMReg< 4, "q4", [D8, D9]>; 96def Q5 : ARMReg< 5, "q5", [D10, D11]>; 97def Q6 : ARMReg< 6, "q6", [D12, D13]>; 98def Q7 : ARMReg< 7, "q7", [D14, D15]>; 99def Q8 : ARMReg< 8, "q8", [D16, D17]>; 100def Q9 : ARMReg< 9, "q9", [D18, D19]>; 101def Q10 : ARMReg<10, "q10", [D20, D21]>; 102def Q11 : ARMReg<11, "q11", [D22, D23]>; 103def Q12 : ARMReg<12, "q12", [D24, D25]>; 104def Q13 : ARMReg<13, "q13", [D26, D27]>; 105def Q14 : ARMReg<14, "q14", [D28, D29]>; 106def Q15 : ARMReg<15, "q15", [D30, D31]>; 107 108// Current Program Status Register. 109def CPSR : ARMReg<0, "cpsr">; 110 111def FPSCR : ARMReg<1, "fpscr">; 112 113// Register classes. 114// 115// pc == Program Counter 116// lr == Link Register 117// sp == Stack Pointer 118// r12 == ip (scratch) 119// r7 == Frame Pointer (thumb-style backtraces) 120// r9 == May be reserved as Thread Register 121// r11 == Frame Pointer (arm-style backtraces) 122// r10 == Stack Limit 123// 124def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, 125 R7, R8, R9, R10, R12, R11, 126 LR, SP, PC]> { 127 let MethodProtos = [{ 128 iterator allocation_order_begin(const MachineFunction &MF) const; 129 iterator allocation_order_end(const MachineFunction &MF) const; 130 }]; 131 // FIXME: We are reserving r12 in case the PEI needs to use it to 132 // generate large stack offset. Make it available once we have register 133 // scavenging. Similarly r3 is reserved in Thumb mode for now. 134 let MethodBodies = [{ 135 // FP is R11, R9 is available. 136 static const unsigned ARM_GPR_AO_1[] = { 137 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 138 ARM::R12,ARM::LR, 139 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 140 ARM::R8, ARM::R9, ARM::R10, 141 ARM::R11 }; 142 // FP is R11, R9 is not available. 143 static const unsigned ARM_GPR_AO_2[] = { 144 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 145 ARM::R12,ARM::LR, 146 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 147 ARM::R8, ARM::R10, 148 ARM::R11 }; 149 // FP is R7, R9 is available as non-callee-saved register. 150 // This is used by Darwin. 151 static const unsigned ARM_GPR_AO_3[] = { 152 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 153 ARM::R9, ARM::R12,ARM::LR, 154 ARM::R4, ARM::R5, ARM::R6, 155 ARM::R8, ARM::R10,ARM::R11,ARM::R7 }; 156 // FP is R7, R9 is not available. 157 static const unsigned ARM_GPR_AO_4[] = { 158 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 159 ARM::R12,ARM::LR, 160 ARM::R4, ARM::R5, ARM::R6, 161 ARM::R8, ARM::R10,ARM::R11, 162 ARM::R7 }; 163 164 GPRClass::iterator 165 GPRClass::allocation_order_begin(const MachineFunction &MF) const { 166 const TargetMachine &TM = MF.getTarget(); 167 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>(); 168 if (Subtarget.isTargetDarwin()) { 169 if (Subtarget.isR9Reserved()) 170 return ARM_GPR_AO_4; 171 else 172 return ARM_GPR_AO_3; 173 } else { 174 if (Subtarget.isR9Reserved()) 175 return ARM_GPR_AO_2; 176 else 177 return ARM_GPR_AO_1; 178 } 179 } 180 181 GPRClass::iterator 182 GPRClass::allocation_order_end(const MachineFunction &MF) const { 183 const TargetMachine &TM = MF.getTarget(); 184 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 185 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>(); 186 GPRClass::iterator I; 187 188 if (Subtarget.isTargetDarwin()) { 189 if (Subtarget.isR9Reserved()) 190 I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned)); 191 else 192 I = ARM_GPR_AO_3 + (sizeof(ARM_GPR_AO_3)/sizeof(unsigned)); 193 } else { 194 if (Subtarget.isR9Reserved()) 195 I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned)); 196 else 197 I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned)); 198 } 199 200 // Mac OS X requires FP not to be clobbered for backtracing purpose. 201 return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I; 202 } 203 }]; 204} 205 206// Thumb registers are R0-R7 normally. Some instructions can still use 207// the general GPR register class above (MOV, e.g.) 208def tGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7]> { 209 let MethodProtos = [{ 210 iterator allocation_order_begin(const MachineFunction &MF) const; 211 iterator allocation_order_end(const MachineFunction &MF) const; 212 }]; 213 // FIXME: We are reserving r3 in Thumb mode in case the PEI needs to use it 214 // to generate large stack offset. Make it available once we have register 215 // scavenging. 216 let MethodBodies = [{ 217 static const unsigned THUMB_tGPR_AO[] = { 218 ARM::R0, ARM::R1, ARM::R2, 219 ARM::R4, ARM::R5, ARM::R6, ARM::R7 }; 220 221 // FP is R7, only low registers available. 222 tGPRClass::iterator 223 tGPRClass::allocation_order_begin(const MachineFunction &MF) const { 224 return THUMB_tGPR_AO; 225 } 226 227 tGPRClass::iterator 228 tGPRClass::allocation_order_end(const MachineFunction &MF) const { 229 const TargetMachine &TM = MF.getTarget(); 230 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 231 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>(); 232 tGPRClass::iterator I = 233 THUMB_tGPR_AO + (sizeof(THUMB_tGPR_AO)/sizeof(unsigned)); 234 // Mac OS X requires FP not to be clobbered for backtracing purpose. 235 return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I; 236 } 237 }]; 238} 239 240// Scalar single precision floating point register class.. 241def SPR : RegisterClass<"ARM", [f32], 32, [S0, S1, S2, S3, S4, S5, S6, S7, S8, 242 S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, 243 S23, S24, S25, S26, S27, S28, S29, S30, S31]>; 244 245// Scalar double precision floating point / generic 64-bit vector register 246// class. 247// ARM requires only word alignment for double. It's more performant if it 248// is double-word alignment though. 249def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64, 250 [D0, D1, D2, D3, D4, D5, D6, D7, 251 D8, D9, D10, D11, D12, D13, D14, D15, 252 D16, D17, D18, D19, D20, D21, D22, D23, 253 D24, D25, D26, D27, D28, D29, D30, D31]> { 254 let SubRegClassList = [SPR, SPR]; 255 let MethodProtos = [{ 256 iterator allocation_order_begin(const MachineFunction &MF) const; 257 iterator allocation_order_end(const MachineFunction &MF) const; 258 }]; 259 let MethodBodies = [{ 260 // VFP2 261 static const unsigned ARM_DPR_VFP2[] = { 262 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 263 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 264 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 265 ARM::D12, ARM::D13, ARM::D14, ARM::D15 }; 266 // VFP3 267 static const unsigned ARM_DPR_VFP3[] = { 268 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 269 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 270 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 271 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 272 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 273 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 274 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 275 ARM::D28, ARM::D29, ARM::D30, ARM::D31 }; 276 DPRClass::iterator 277 DPRClass::allocation_order_begin(const MachineFunction &MF) const { 278 const TargetMachine &TM = MF.getTarget(); 279 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>(); 280 if (Subtarget.hasVFP3()) 281 return ARM_DPR_VFP3; 282 return ARM_DPR_VFP2; 283 } 284 285 DPRClass::iterator 286 DPRClass::allocation_order_end(const MachineFunction &MF) const { 287 const TargetMachine &TM = MF.getTarget(); 288 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>(); 289 if (Subtarget.hasVFP3()) 290 return ARM_DPR_VFP3 + (sizeof(ARM_DPR_VFP3)/sizeof(unsigned)); 291 else 292 return ARM_DPR_VFP2 + (sizeof(ARM_DPR_VFP2)/sizeof(unsigned)); 293 } 294 }]; 295} 296 297// Generic 128-bit vector register class. 298def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128, 299 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, 300 Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15]> { 301 let SubRegClassList = [SPR, SPR, SPR, SPR, DPR, DPR]; 302} 303 304// Condition code registers. 305def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>; 306 307//===----------------------------------------------------------------------===// 308// Subregister Set Definitions... now that we have all of the pieces, define the 309// sub registers for each register. 310// 311 312def arm_ssubreg_0 : PatLeaf<(i32 1)>; 313def arm_ssubreg_1 : PatLeaf<(i32 2)>; 314def arm_ssubreg_2 : PatLeaf<(i32 3)>; 315def arm_ssubreg_3 : PatLeaf<(i32 4)>; 316def arm_dsubreg_0 : PatLeaf<(i32 5)>; 317def arm_dsubreg_1 : PatLeaf<(i32 6)>; 318 319// S sub-registers of D registers. 320def : SubRegSet<1, [D0, D1, D2, D3, D4, D5, D6, D7, 321 D8, D9, D10, D11, D12, D13, D14, D15], 322 [S0, S2, S4, S6, S8, S10, S12, S14, 323 S16, S18, S20, S22, S24, S26, S28, S30]>; 324def : SubRegSet<2, [D0, D1, D2, D3, D4, D5, D6, D7, 325 D8, D9, D10, D11, D12, D13, D14, D15], 326 [S1, S3, S5, S7, S9, S11, S13, S15, 327 S17, S19, S21, S23, S25, S27, S29, S31]>; 328 329// S sub-registers of Q registers. 330def : SubRegSet<1, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7], 331 [S0, S4, S8, S12, S16, S20, S24, S28]>; 332def : SubRegSet<2, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7], 333 [S1, S5, S9, S13, S17, S21, S25, S29]>; 334def : SubRegSet<3, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7], 335 [S2, S6, S10, S14, S18, S22, S26, S30]>; 336def : SubRegSet<4, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7], 337 [S3, S7, S11, S15, S19, S23, S27, S31]>; 338 339// D sub-registers of Q registers. 340def : SubRegSet<5, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, 341 Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15], 342 [D0, D2, D4, D6, D8, D10, D12, D14, 343 D16, D18, D20, D22, D24, D26, D28, D30]>; 344def : SubRegSet<6, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, 345 Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15], 346 [D1, D3, D5, D7, D9, D11, D13, D15, 347 D17, D19, D21, D23, D25, D27, D29, D31]>; 348 349