1 //===- ARMRegisterBankInfo ---------------------------------------*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file declares the targeting of the RegisterBankInfo class for ARM.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H
15 #define LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H
16 
17 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
18 
19 namespace llvm {
20 
21 class TargetRegisterInfo;
22 
23 namespace ARM {
24 enum {
25   GPRRegBankID = 0, // General purpose registers
26   NumRegisterBanks,
27 };
28 } // end namespace ARM
29 
30 /// This class provides the information for the target register banks.
31 class ARMRegisterBankInfo final : public RegisterBankInfo {
32 public:
33   ARMRegisterBankInfo(const TargetRegisterInfo &TRI);
34 
35   const RegisterBank &
36   getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
37 
38   InstructionMapping getInstrMapping(const MachineInstr &MI) const override;
39 };
40 } // End llvm namespace.
41 #endif
42