1 //===- ARMRegisterBankInfo.cpp -----------------------------------*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the targeting of the RegisterBankInfo class for ARM.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMRegisterBankInfo.h"
15 #include "ARMInstrInfo.h" // For the register classes
16 #include "ARMSubtarget.h"
17 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
18 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetRegisterInfo.h"
21 
22 #define GET_TARGET_REGBANK_IMPL
23 #include "ARMGenRegisterBank.inc"
24 
25 using namespace llvm;
26 
27 // FIXME: TableGen this.
28 // If it grows too much and TableGen still isn't ready to do the job, extract it
29 // into an ARMGenRegisterBankInfo.def (similar to AArch64).
30 namespace llvm {
31 namespace ARM {
32 enum PartialMappingIdx {
33   PMI_GPR,
34   PMI_SPR,
35   PMI_DPR,
36   PMI_Min = PMI_GPR,
37 };
38 
39 RegisterBankInfo::PartialMapping PartMappings[]{
40     // GPR Partial Mapping
41     {0, 32, GPRRegBank},
42     // SPR Partial Mapping
43     {0, 32, FPRRegBank},
44     // DPR Partial Mapping
45     {0, 64, FPRRegBank},
46 };
47 
48 #ifndef NDEBUG
49 static bool checkPartMapping(const RegisterBankInfo::PartialMapping &PM,
50                              unsigned Start, unsigned Length,
51                              unsigned RegBankID) {
52   return PM.StartIdx == Start && PM.Length == Length &&
53          PM.RegBank->getID() == RegBankID;
54 }
55 
56 static void checkPartialMappings() {
57   assert(
58       checkPartMapping(PartMappings[PMI_GPR - PMI_Min], 0, 32, GPRRegBankID) &&
59       "Wrong mapping for GPR");
60   assert(
61       checkPartMapping(PartMappings[PMI_SPR - PMI_Min], 0, 32, FPRRegBankID) &&
62       "Wrong mapping for SPR");
63   assert(
64       checkPartMapping(PartMappings[PMI_DPR - PMI_Min], 0, 64, FPRRegBankID) &&
65       "Wrong mapping for DPR");
66 }
67 #endif
68 
69 enum ValueMappingIdx {
70   InvalidIdx = 0,
71   GPR3OpsIdx = 1,
72   SPR3OpsIdx = 4,
73   DPR3OpsIdx = 7,
74 };
75 
76 RegisterBankInfo::ValueMapping ValueMappings[] = {
77     // invalid
78     {nullptr, 0},
79     // 3 ops in GPRs
80     {&PartMappings[PMI_GPR - PMI_Min], 1},
81     {&PartMappings[PMI_GPR - PMI_Min], 1},
82     {&PartMappings[PMI_GPR - PMI_Min], 1},
83     // 3 ops in SPRs
84     {&PartMappings[PMI_SPR - PMI_Min], 1},
85     {&PartMappings[PMI_SPR - PMI_Min], 1},
86     {&PartMappings[PMI_SPR - PMI_Min], 1},
87     // 3 ops in DPRs
88     {&PartMappings[PMI_DPR - PMI_Min], 1},
89     {&PartMappings[PMI_DPR - PMI_Min], 1},
90     {&PartMappings[PMI_DPR - PMI_Min], 1}};
91 
92 #ifndef NDEBUG
93 static bool checkValueMapping(const RegisterBankInfo::ValueMapping &VM,
94                               RegisterBankInfo::PartialMapping *BreakDown) {
95   return VM.NumBreakDowns == 1 && VM.BreakDown == BreakDown;
96 }
97 
98 static void checkValueMappings() {
99   assert(checkValueMapping(ValueMappings[GPR3OpsIdx],
100                            &PartMappings[PMI_GPR - PMI_Min]) &&
101          "Wrong value mapping for 3 GPR ops instruction");
102   assert(checkValueMapping(ValueMappings[GPR3OpsIdx + 1],
103                            &PartMappings[PMI_GPR - PMI_Min]) &&
104          "Wrong value mapping for 3 GPR ops instruction");
105   assert(checkValueMapping(ValueMappings[GPR3OpsIdx + 2],
106                            &PartMappings[PMI_GPR - PMI_Min]) &&
107          "Wrong value mapping for 3 GPR ops instruction");
108 
109   assert(checkValueMapping(ValueMappings[SPR3OpsIdx],
110                            &PartMappings[PMI_SPR - PMI_Min]) &&
111          "Wrong value mapping for 3 SPR ops instruction");
112   assert(checkValueMapping(ValueMappings[SPR3OpsIdx + 1],
113                            &PartMappings[PMI_SPR - PMI_Min]) &&
114          "Wrong value mapping for 3 SPR ops instruction");
115   assert(checkValueMapping(ValueMappings[SPR3OpsIdx + 2],
116                            &PartMappings[PMI_SPR - PMI_Min]) &&
117          "Wrong value mapping for 3 SPR ops instruction");
118 
119   assert(checkValueMapping(ValueMappings[DPR3OpsIdx],
120                            &PartMappings[PMI_DPR - PMI_Min]) &&
121          "Wrong value mapping for 3 DPR ops instruction");
122   assert(checkValueMapping(ValueMappings[DPR3OpsIdx + 1],
123                            &PartMappings[PMI_DPR - PMI_Min]) &&
124          "Wrong value mapping for 3 DPR ops instruction");
125   assert(checkValueMapping(ValueMappings[DPR3OpsIdx + 2],
126                            &PartMappings[PMI_DPR - PMI_Min]) &&
127          "Wrong value mapping for 3 DPR ops instruction");
128 }
129 #endif
130 } // end namespace arm
131 } // end namespace llvm
132 
133 ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI)
134     : ARMGenRegisterBankInfo() {
135   static bool AlreadyInit = false;
136   // We have only one set of register banks, whatever the subtarget
137   // is. Therefore, the initialization of the RegBanks table should be
138   // done only once. Indeed the table of all register banks
139   // (ARM::RegBanks) is unique in the compiler. At some point, it
140   // will get tablegen'ed and the whole constructor becomes empty.
141   if (AlreadyInit)
142     return;
143   AlreadyInit = true;
144 
145   const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);
146   (void)RBGPR;
147   assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");
148 
149   // Initialize the GPR bank.
150   assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&
151          "Subclass not added?");
152   assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&
153          "Subclass not added?");
154   assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) &&
155          "Subclass not added?");
156   assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) &&
157          "Subclass not added?");
158   assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) &&
159          "Subclass not added?");
160   assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) &&
161          "Subclass not added?");
162   assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) &&
163          "Subclass not added?");
164   assert(RBGPR.getSize() == 32 && "GPRs should hold up to 32-bit");
165 
166 #ifndef NDEBUG
167   ARM::checkPartialMappings();
168   ARM::checkValueMappings();
169 #endif
170 }
171 
172 const RegisterBank &ARMRegisterBankInfo::getRegBankFromRegClass(
173     const TargetRegisterClass &RC) const {
174   using namespace ARM;
175 
176   switch (RC.getID()) {
177   case GPRRegClassID:
178   case GPRnopcRegClassID:
179   case GPRspRegClassID:
180   case tGPR_and_tcGPRRegClassID:
181   case tGPRRegClassID:
182     return getRegBank(ARM::GPRRegBankID);
183   case SPR_8RegClassID:
184   case SPRRegClassID:
185   case DPR_8RegClassID:
186   case DPRRegClassID:
187     return getRegBank(ARM::FPRRegBankID);
188   default:
189     llvm_unreachable("Unsupported register kind");
190   }
191 
192   llvm_unreachable("Switch should handle all register classes");
193 }
194 
195 const RegisterBankInfo::InstructionMapping &
196 ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
197   auto Opc = MI.getOpcode();
198 
199   // Try the default logic for non-generic instructions that are either copies
200   // or already have some operands assigned to banks.
201   if (!isPreISelGenericOpcode(Opc) || Opc == TargetOpcode::G_PHI) {
202     const InstructionMapping &Mapping = getInstrMappingImpl(MI);
203     if (Mapping.isValid())
204       return Mapping;
205   }
206 
207   using namespace TargetOpcode;
208 
209   const MachineFunction &MF = *MI.getParent()->getParent();
210   const MachineRegisterInfo &MRI = MF.getRegInfo();
211   unsigned NumOperands = MI.getNumOperands();
212   const ValueMapping *OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx];
213 
214   switch (Opc) {
215   case G_ADD:
216   case G_SUB:
217   case G_MUL:
218   case G_AND:
219   case G_OR:
220   case G_XOR:
221   case G_LSHR:
222   case G_ASHR:
223   case G_SHL:
224   case G_SDIV:
225   case G_UDIV:
226   case G_SEXT:
227   case G_ZEXT:
228   case G_ANYEXT:
229   case G_TRUNC:
230   case G_GEP:
231     // FIXME: We're abusing the fact that everything lives in a GPR for now; in
232     // the real world we would use different mappings.
233     OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx];
234     break;
235   case G_LOAD:
236   case G_STORE: {
237     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
238     OperandsMapping =
239         Ty.getSizeInBits() == 64
240             ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
241                                   &ARM::ValueMappings[ARM::GPR3OpsIdx]})
242             : &ARM::ValueMappings[ARM::GPR3OpsIdx];
243     break;
244   }
245   case G_FADD:
246   case G_FSUB:
247   case G_FMUL:
248   case G_FDIV: {
249     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
250     OperandsMapping =Ty.getSizeInBits() == 64
251                           ? &ARM::ValueMappings[ARM::DPR3OpsIdx]
252                           : &ARM::ValueMappings[ARM::SPR3OpsIdx];
253     break;
254   }
255   case G_CONSTANT:
256   case G_FRAME_INDEX:
257   case G_GLOBAL_VALUE:
258     OperandsMapping =
259         getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr});
260     break;
261   case G_SELECT: {
262     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
263     (void)Ty;
264     LLT Ty2 = MRI.getType(MI.getOperand(1).getReg());
265     (void)Ty2;
266     assert(Ty.getSizeInBits() == 32 && "Unsupported size for G_SELECT");
267     assert(Ty2.getSizeInBits() == 1 && "Unsupported size for G_SELECT");
268     OperandsMapping =
269         getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
270                             &ARM::ValueMappings[ARM::GPR3OpsIdx],
271                             &ARM::ValueMappings[ARM::GPR3OpsIdx],
272                             &ARM::ValueMappings[ARM::GPR3OpsIdx]});
273     break;
274   }
275   case G_ICMP: {
276     LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
277     (void)Ty2;
278     assert(Ty2.getSizeInBits() == 32 && "Unsupported size for G_ICMP");
279     OperandsMapping =
280         getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr,
281                             &ARM::ValueMappings[ARM::GPR3OpsIdx],
282                             &ARM::ValueMappings[ARM::GPR3OpsIdx]});
283     break;
284   }
285   case G_FCMP: {
286     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
287     (void)Ty;
288     LLT Ty1 = MRI.getType(MI.getOperand(2).getReg());
289     LLT Ty2 = MRI.getType(MI.getOperand(3).getReg());
290     (void)Ty2;
291     assert(Ty.getSizeInBits() == 1 && "Unsupported size for G_FCMP");
292     assert(Ty1.getSizeInBits() == Ty2.getSizeInBits() &&
293            "Mismatched operand sizes for G_FCMP");
294 
295     unsigned Size = Ty1.getSizeInBits();
296     assert((Size == 32 || Size == 64) && "Unsupported size for G_FCMP");
297 
298     auto FPRValueMapping = Size == 32 ? &ARM::ValueMappings[ARM::SPR3OpsIdx]
299                                       : &ARM::ValueMappings[ARM::DPR3OpsIdx];
300     OperandsMapping =
301         getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr,
302                             FPRValueMapping, FPRValueMapping});
303     break;
304   }
305   case G_MERGE_VALUES: {
306     // We only support G_MERGE_VALUES for creating a double precision floating
307     // point value out of two GPRs.
308     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
309     LLT Ty1 = MRI.getType(MI.getOperand(1).getReg());
310     LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
311     if (Ty.getSizeInBits() != 64 || Ty1.getSizeInBits() != 32 ||
312         Ty2.getSizeInBits() != 32)
313       return getInvalidInstructionMapping();
314     OperandsMapping =
315         getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
316                             &ARM::ValueMappings[ARM::GPR3OpsIdx],
317                             &ARM::ValueMappings[ARM::GPR3OpsIdx]});
318     break;
319   }
320   case G_UNMERGE_VALUES: {
321     // We only support G_UNMERGE_VALUES for splitting a double precision
322     // floating point value into two GPRs.
323     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
324     LLT Ty1 = MRI.getType(MI.getOperand(1).getReg());
325     LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
326     if (Ty.getSizeInBits() != 32 || Ty1.getSizeInBits() != 32 ||
327         Ty2.getSizeInBits() != 64)
328       return getInvalidInstructionMapping();
329     OperandsMapping =
330         getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
331                             &ARM::ValueMappings[ARM::GPR3OpsIdx],
332                             &ARM::ValueMappings[ARM::DPR3OpsIdx]});
333     break;
334   }
335   case G_BR:
336     OperandsMapping = getOperandsMapping({nullptr});
337     break;
338   case G_BRCOND:
339     OperandsMapping =
340         getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr});
341     break;
342   default:
343     return getInvalidInstructionMapping();
344   }
345 
346 #ifndef NDEBUG
347   for (unsigned i = 0; i < NumOperands; i++) {
348     for (const auto &Mapping : OperandsMapping[i]) {
349       assert(
350           (Mapping.RegBank->getID() != ARM::FPRRegBankID ||
351            MF.getSubtarget<ARMSubtarget>().hasVFP2()) &&
352           "Trying to use floating point register bank on target without vfp");
353     }
354   }
355 #endif
356 
357   return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping,
358                                NumOperands);
359 }
360