1 //===-- ARMMCInstLower.cpp - Convert ARM MachineInstr to an MCInst --------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains code to lower ARM MachineInstrs to their corresponding 11 // MCInst records. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "ARM.h" 16 #include "ARMAsmPrinter.h" 17 #include "MCTargetDesc/ARMBaseInfo.h" 18 #include "MCTargetDesc/ARMMCExpr.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/IR/Constants.h" 21 #include "llvm/IR/Mangler.h" 22 #include "llvm/MC/MCExpr.h" 23 #include "llvm/MC/MCInst.h" 24 #include "llvm/MC/MCContext.h" 25 #include "llvm/MC/MCSymbolELF.h" 26 #include "llvm/MC/MCSectionELF.h" 27 #include "llvm/MC/MCInstBuilder.h" 28 #include "llvm/MC/MCStreamer.h" 29 using namespace llvm; 30 31 32 MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO, 33 const MCSymbol *Symbol) { 34 const MCExpr *Expr = 35 MCSymbolRefExpr::create(Symbol, MCSymbolRefExpr::VK_None, OutContext); 36 switch (MO.getTargetFlags() & ARMII::MO_OPTION_MASK) { 37 default: 38 llvm_unreachable("Unknown target flag on symbol operand"); 39 case ARMII::MO_NO_FLAG: 40 break; 41 case ARMII::MO_LO16: 42 Expr = 43 MCSymbolRefExpr::create(Symbol, MCSymbolRefExpr::VK_None, OutContext); 44 Expr = ARMMCExpr::createLower16(Expr, OutContext); 45 break; 46 case ARMII::MO_HI16: 47 Expr = 48 MCSymbolRefExpr::create(Symbol, MCSymbolRefExpr::VK_None, OutContext); 49 Expr = ARMMCExpr::createUpper16(Expr, OutContext); 50 break; 51 } 52 53 if (!MO.isJTI() && MO.getOffset()) 54 Expr = MCBinaryExpr::createAdd(Expr, 55 MCConstantExpr::create(MO.getOffset(), 56 OutContext), 57 OutContext); 58 return MCOperand::createExpr(Expr); 59 60 } 61 62 bool ARMAsmPrinter::lowerOperand(const MachineOperand &MO, 63 MCOperand &MCOp) { 64 switch (MO.getType()) { 65 default: llvm_unreachable("unknown operand type"); 66 case MachineOperand::MO_Register: 67 // Ignore all non-CPSR implicit register operands. 68 if (MO.isImplicit() && MO.getReg() != ARM::CPSR) 69 return false; 70 assert(!MO.getSubReg() && "Subregs should be eliminated!"); 71 MCOp = MCOperand::createReg(MO.getReg()); 72 break; 73 case MachineOperand::MO_Immediate: 74 MCOp = MCOperand::createImm(MO.getImm()); 75 break; 76 case MachineOperand::MO_MachineBasicBlock: 77 MCOp = MCOperand::createExpr(MCSymbolRefExpr::create( 78 MO.getMBB()->getSymbol(), OutContext)); 79 break; 80 case MachineOperand::MO_GlobalAddress: { 81 MCOp = GetSymbolRef(MO, 82 GetARMGVSymbol(MO.getGlobal(), MO.getTargetFlags())); 83 break; 84 } 85 case MachineOperand::MO_ExternalSymbol: 86 MCOp = GetSymbolRef(MO, 87 GetExternalSymbolSymbol(MO.getSymbolName())); 88 break; 89 case MachineOperand::MO_JumpTableIndex: 90 MCOp = GetSymbolRef(MO, GetJTISymbol(MO.getIndex())); 91 break; 92 case MachineOperand::MO_ConstantPoolIndex: 93 MCOp = GetSymbolRef(MO, GetCPISymbol(MO.getIndex())); 94 break; 95 case MachineOperand::MO_BlockAddress: 96 MCOp = GetSymbolRef(MO, GetBlockAddressSymbol(MO.getBlockAddress())); 97 break; 98 case MachineOperand::MO_FPImmediate: { 99 APFloat Val = MO.getFPImm()->getValueAPF(); 100 bool ignored; 101 Val.convert(APFloat::IEEEdouble, APFloat::rmTowardZero, &ignored); 102 MCOp = MCOperand::createFPImm(Val.convertToDouble()); 103 break; 104 } 105 case MachineOperand::MO_RegisterMask: 106 // Ignore call clobbers. 107 return false; 108 } 109 return true; 110 } 111 112 void llvm::LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, 113 ARMAsmPrinter &AP) { 114 OutMI.setOpcode(MI->getOpcode()); 115 116 // In the MC layer, we keep modified immediates in their encoded form 117 bool EncodeImms = false; 118 switch (MI->getOpcode()) { 119 default: break; 120 case ARM::MOVi: 121 case ARM::MVNi: 122 case ARM::CMPri: 123 case ARM::CMNri: 124 case ARM::TSTri: 125 case ARM::TEQri: 126 case ARM::MSRi: 127 case ARM::ADCri: 128 case ARM::ADDri: 129 case ARM::ADDSri: 130 case ARM::SBCri: 131 case ARM::SUBri: 132 case ARM::SUBSri: 133 case ARM::ANDri: 134 case ARM::ORRri: 135 case ARM::EORri: 136 case ARM::BICri: 137 case ARM::RSBri: 138 case ARM::RSBSri: 139 case ARM::RSCri: 140 EncodeImms = true; 141 break; 142 } 143 144 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 145 const MachineOperand &MO = MI->getOperand(i); 146 147 MCOperand MCOp; 148 if (AP.lowerOperand(MO, MCOp)) { 149 if (MCOp.isImm() && EncodeImms) { 150 int32_t Enc = ARM_AM::getSOImmVal(MCOp.getImm()); 151 if (Enc != -1) 152 MCOp.setImm(Enc); 153 } 154 OutMI.addOperand(MCOp); 155 } 156 } 157 } 158 159 void ARMAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind) 160 { 161 static const int8_t NoopsInSledCount = 6; 162 // We want to emit the following pattern: 163 // 164 // .Lxray_sled_N: 165 // ALIGN 166 // B #20 167 // ; 6 NOP instructions (24 bytes) 168 // .tmpN 169 // 170 // We need the 24 bytes (6 instructions) because at runtime, we'd be patching 171 // over the full 28 bytes (7 instructions) with the following pattern: 172 // 173 // PUSH{ r0, lr } 174 // MOVW r0, #<lower 16 bits of function ID> 175 // MOVT r0, #<higher 16 bits of function ID> 176 // MOVW ip, #<lower 16 bits of address of __xray_FunctionEntry/Exit> 177 // MOVT ip, #<higher 16 bits of address of __xray_FunctionEntry/Exit> 178 // BLX ip 179 // POP{ r0, lr } 180 // 181 OutStreamer->EmitCodeAlignment(4); 182 auto CurSled = OutContext.createTempSymbol("xray_sled_", true); 183 OutStreamer->EmitLabel(CurSled); 184 auto Target = OutContext.createTempSymbol(); 185 186 // Emit "B #20" instruction, which jumps over the next 24 bytes (because 187 // register pc is 8 bytes ahead of the jump instruction by the moment CPU 188 // is executing it). 189 // By analogy to ARMAsmPrinter::emitPseudoExpansionLowering() |case ARM::B|. 190 // It is not clear why |addReg(0)| is needed (the last operand). 191 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc).addImm(20) 192 .addImm(ARMCC::AL).addReg(0)); 193 194 MCInst Noop; 195 Subtarget->getInstrInfo()->getNoopForElfTarget(Noop); 196 for (int8_t I = 0; I < NoopsInSledCount; I++) 197 { 198 OutStreamer->EmitInstruction(Noop, getSubtargetInfo()); 199 } 200 201 OutStreamer->EmitLabel(Target); 202 recordSled(CurSled, MI, Kind); 203 } 204 205 void ARMAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI) 206 { 207 EmitSled(MI, SledKind::FUNCTION_ENTER); 208 } 209 210 void ARMAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI) 211 { 212 EmitSled(MI, SledKind::FUNCTION_EXIT); 213 } 214 215 void ARMAsmPrinter::EmitXRayTable() 216 { 217 if (Sleds.empty()) 218 return; 219 if (Subtarget->isTargetELF()) { 220 auto *Section = OutContext.getELFSection( 221 "xray_instr_map", ELF::SHT_PROGBITS, 222 ELF::SHF_ALLOC | ELF::SHF_GROUP | ELF::SHF_MERGE, 0, 223 CurrentFnSym->getName()); 224 auto PrevSection = OutStreamer->getCurrentSectionOnly(); 225 OutStreamer->SwitchSection(Section); 226 for (const auto &Sled : Sleds) { 227 OutStreamer->EmitSymbolValue(Sled.Sled, 4); 228 OutStreamer->EmitSymbolValue(CurrentFnSym, 4); 229 auto Kind = static_cast<uint8_t>(Sled.Kind); 230 OutStreamer->EmitBytes( 231 StringRef(reinterpret_cast<const char *>(&Kind), 1)); 232 OutStreamer->EmitBytes( 233 StringRef(reinterpret_cast<const char *>(&Sled.AlwaysInstrument), 1)); 234 OutStreamer->EmitZeros(6); 235 } 236 OutStreamer->SwitchSection(PrevSection); 237 } 238 Sleds.clear(); 239 } 240