1 //===-- ARMMCInstLower.cpp - Convert ARM MachineInstr to an MCInst --------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains code to lower ARM MachineInstrs to their corresponding 11 // MCInst records. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "ARM.h" 16 #include "ARMAsmPrinter.h" 17 #include "ARMBaseInstrInfo.h" 18 #include "ARMMachineFunctionInfo.h" 19 #include "ARMSubtarget.h" 20 #include "MCTargetDesc/ARMAddressingModes.h" 21 #include "MCTargetDesc/ARMBaseInfo.h" 22 #include "MCTargetDesc/ARMMCExpr.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/CodeGen/MachineBasicBlock.h" 25 #include "llvm/CodeGen/MachineInstr.h" 26 #include "llvm/CodeGen/MachineOperand.h" 27 #include "llvm/IR/Constants.h" 28 #include "llvm/MC/MCExpr.h" 29 #include "llvm/MC/MCInst.h" 30 #include "llvm/MC/MCContext.h" 31 #include "llvm/MC/MCInstBuilder.h" 32 #include "llvm/MC/MCStreamer.h" 33 #include "llvm/Support/ErrorHandling.h" 34 #include <cassert> 35 #include <cstdint> 36 37 using namespace llvm; 38 39 MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO, 40 const MCSymbol *Symbol) { 41 const MCExpr *Expr = 42 MCSymbolRefExpr::create(Symbol, MCSymbolRefExpr::VK_None, OutContext); 43 switch (MO.getTargetFlags() & ARMII::MO_OPTION_MASK) { 44 default: 45 llvm_unreachable("Unknown target flag on symbol operand"); 46 case ARMII::MO_NO_FLAG: 47 break; 48 case ARMII::MO_LO16: 49 Expr = 50 MCSymbolRefExpr::create(Symbol, MCSymbolRefExpr::VK_None, OutContext); 51 Expr = ARMMCExpr::createLower16(Expr, OutContext); 52 break; 53 case ARMII::MO_HI16: 54 Expr = 55 MCSymbolRefExpr::create(Symbol, MCSymbolRefExpr::VK_None, OutContext); 56 Expr = ARMMCExpr::createUpper16(Expr, OutContext); 57 break; 58 } 59 60 if (!MO.isJTI() && MO.getOffset()) 61 Expr = MCBinaryExpr::createAdd(Expr, 62 MCConstantExpr::create(MO.getOffset(), 63 OutContext), 64 OutContext); 65 return MCOperand::createExpr(Expr); 66 67 } 68 69 bool ARMAsmPrinter::lowerOperand(const MachineOperand &MO, 70 MCOperand &MCOp) { 71 switch (MO.getType()) { 72 default: llvm_unreachable("unknown operand type"); 73 case MachineOperand::MO_Register: 74 // Ignore all non-CPSR implicit register operands. 75 if (MO.isImplicit() && MO.getReg() != ARM::CPSR) 76 return false; 77 assert(!MO.getSubReg() && "Subregs should be eliminated!"); 78 MCOp = MCOperand::createReg(MO.getReg()); 79 break; 80 case MachineOperand::MO_Immediate: 81 MCOp = MCOperand::createImm(MO.getImm()); 82 break; 83 case MachineOperand::MO_MachineBasicBlock: 84 MCOp = MCOperand::createExpr(MCSymbolRefExpr::create( 85 MO.getMBB()->getSymbol(), OutContext)); 86 break; 87 case MachineOperand::MO_GlobalAddress: 88 MCOp = GetSymbolRef(MO, 89 GetARMGVSymbol(MO.getGlobal(), MO.getTargetFlags())); 90 break; 91 case MachineOperand::MO_ExternalSymbol: 92 MCOp = GetSymbolRef(MO, 93 GetExternalSymbolSymbol(MO.getSymbolName())); 94 break; 95 case MachineOperand::MO_JumpTableIndex: 96 MCOp = GetSymbolRef(MO, GetJTISymbol(MO.getIndex())); 97 break; 98 case MachineOperand::MO_ConstantPoolIndex: 99 if (Subtarget->genExecuteOnly()) 100 llvm_unreachable("execute-only should not generate constant pools"); 101 MCOp = GetSymbolRef(MO, GetCPISymbol(MO.getIndex())); 102 break; 103 case MachineOperand::MO_BlockAddress: 104 MCOp = GetSymbolRef(MO, GetBlockAddressSymbol(MO.getBlockAddress())); 105 break; 106 case MachineOperand::MO_FPImmediate: { 107 APFloat Val = MO.getFPImm()->getValueAPF(); 108 bool ignored; 109 Val.convert(APFloat::IEEEdouble(), APFloat::rmTowardZero, &ignored); 110 MCOp = MCOperand::createFPImm(Val.convertToDouble()); 111 break; 112 } 113 case MachineOperand::MO_RegisterMask: 114 // Ignore call clobbers. 115 return false; 116 } 117 return true; 118 } 119 120 void llvm::LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, 121 ARMAsmPrinter &AP) { 122 OutMI.setOpcode(MI->getOpcode()); 123 124 // In the MC layer, we keep modified immediates in their encoded form 125 bool EncodeImms = false; 126 switch (MI->getOpcode()) { 127 default: break; 128 case ARM::MOVi: 129 case ARM::MVNi: 130 case ARM::CMPri: 131 case ARM::CMNri: 132 case ARM::TSTri: 133 case ARM::TEQri: 134 case ARM::MSRi: 135 case ARM::ADCri: 136 case ARM::ADDri: 137 case ARM::ADDSri: 138 case ARM::SBCri: 139 case ARM::SUBri: 140 case ARM::SUBSri: 141 case ARM::ANDri: 142 case ARM::ORRri: 143 case ARM::EORri: 144 case ARM::BICri: 145 case ARM::RSBri: 146 case ARM::RSBSri: 147 case ARM::RSCri: 148 EncodeImms = true; 149 break; 150 } 151 152 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 153 const MachineOperand &MO = MI->getOperand(i); 154 155 MCOperand MCOp; 156 if (AP.lowerOperand(MO, MCOp)) { 157 if (MCOp.isImm() && EncodeImms) { 158 int32_t Enc = ARM_AM::getSOImmVal(MCOp.getImm()); 159 if (Enc != -1) 160 MCOp.setImm(Enc); 161 } 162 OutMI.addOperand(MCOp); 163 } 164 } 165 } 166 167 void ARMAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind) 168 { 169 if (MI.getParent()->getParent()->getInfo<ARMFunctionInfo>() 170 ->isThumbFunction()) 171 { 172 MI.emitError("An attempt to perform XRay instrumentation for a" 173 " Thumb function (not supported). Detected when emitting a sled."); 174 return; 175 } 176 static const int8_t NoopsInSledCount = 6; 177 // We want to emit the following pattern: 178 // 179 // .Lxray_sled_N: 180 // ALIGN 181 // B #20 182 // ; 6 NOP instructions (24 bytes) 183 // .tmpN 184 // 185 // We need the 24 bytes (6 instructions) because at runtime, we'd be patching 186 // over the full 28 bytes (7 instructions) with the following pattern: 187 // 188 // PUSH{ r0, lr } 189 // MOVW r0, #<lower 16 bits of function ID> 190 // MOVT r0, #<higher 16 bits of function ID> 191 // MOVW ip, #<lower 16 bits of address of __xray_FunctionEntry/Exit> 192 // MOVT ip, #<higher 16 bits of address of __xray_FunctionEntry/Exit> 193 // BLX ip 194 // POP{ r0, lr } 195 // 196 OutStreamer->EmitCodeAlignment(4); 197 auto CurSled = OutContext.createTempSymbol("xray_sled_", true); 198 OutStreamer->EmitLabel(CurSled); 199 auto Target = OutContext.createTempSymbol(); 200 201 // Emit "B #20" instruction, which jumps over the next 24 bytes (because 202 // register pc is 8 bytes ahead of the jump instruction by the moment CPU 203 // is executing it). 204 // By analogy to ARMAsmPrinter::emitPseudoExpansionLowering() |case ARM::B|. 205 // It is not clear why |addReg(0)| is needed (the last operand). 206 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc).addImm(20) 207 .addImm(ARMCC::AL).addReg(0)); 208 209 MCInst Noop; 210 Subtarget->getInstrInfo()->getNoopForElfTarget(Noop); 211 for (int8_t I = 0; I < NoopsInSledCount; I++) 212 { 213 OutStreamer->EmitInstruction(Noop, getSubtargetInfo()); 214 } 215 216 OutStreamer->EmitLabel(Target); 217 recordSled(CurSled, MI, Kind); 218 } 219 220 void ARMAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI) 221 { 222 EmitSled(MI, SledKind::FUNCTION_ENTER); 223 } 224 225 void ARMAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI) 226 { 227 EmitSled(MI, SledKind::FUNCTION_EXIT); 228 } 229 230 void ARMAsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI) 231 { 232 EmitSled(MI, SledKind::TAIL_CALL); 233 } 234