1 //===-- ARMMCInstLower.cpp - Convert ARM MachineInstr to an MCInst --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains code to lower ARM MachineInstrs to their corresponding
11 // MCInst records.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "ARM.h"
16 #include "ARMAsmPrinter.h"
17 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "MCTargetDesc/ARMMCExpr.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/IR/Constants.h"
21 #include "llvm/IR/Mangler.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCContext.h"
25 #include "llvm/MC/MCInstBuilder.h"
26 #include "llvm/MC/MCStreamer.h"
27 using namespace llvm;
28 
29 
30 MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO,
31                                       const MCSymbol *Symbol) {
32   const MCExpr *Expr =
33       MCSymbolRefExpr::create(Symbol, MCSymbolRefExpr::VK_None, OutContext);
34   switch (MO.getTargetFlags() & ARMII::MO_OPTION_MASK) {
35   default:
36     llvm_unreachable("Unknown target flag on symbol operand");
37   case ARMII::MO_NO_FLAG:
38     break;
39   case ARMII::MO_LO16:
40     Expr =
41         MCSymbolRefExpr::create(Symbol, MCSymbolRefExpr::VK_None, OutContext);
42     Expr = ARMMCExpr::createLower16(Expr, OutContext);
43     break;
44   case ARMII::MO_HI16:
45     Expr =
46         MCSymbolRefExpr::create(Symbol, MCSymbolRefExpr::VK_None, OutContext);
47     Expr = ARMMCExpr::createUpper16(Expr, OutContext);
48     break;
49   }
50 
51   if (!MO.isJTI() && MO.getOffset())
52     Expr = MCBinaryExpr::createAdd(Expr,
53                                    MCConstantExpr::create(MO.getOffset(),
54                                                           OutContext),
55                                    OutContext);
56   return MCOperand::createExpr(Expr);
57 
58 }
59 
60 bool ARMAsmPrinter::lowerOperand(const MachineOperand &MO,
61                                  MCOperand &MCOp) {
62   switch (MO.getType()) {
63   default: llvm_unreachable("unknown operand type");
64   case MachineOperand::MO_Register:
65     // Ignore all non-CPSR implicit register operands.
66     if (MO.isImplicit() && MO.getReg() != ARM::CPSR)
67       return false;
68     assert(!MO.getSubReg() && "Subregs should be eliminated!");
69     MCOp = MCOperand::createReg(MO.getReg());
70     break;
71   case MachineOperand::MO_Immediate:
72     MCOp = MCOperand::createImm(MO.getImm());
73     break;
74   case MachineOperand::MO_MachineBasicBlock:
75     MCOp = MCOperand::createExpr(MCSymbolRefExpr::create(
76         MO.getMBB()->getSymbol(), OutContext));
77     break;
78   case MachineOperand::MO_GlobalAddress: {
79     MCOp = GetSymbolRef(MO,
80                         GetARMGVSymbol(MO.getGlobal(), MO.getTargetFlags()));
81     break;
82   }
83   case MachineOperand::MO_ExternalSymbol:
84     MCOp = GetSymbolRef(MO,
85                         GetExternalSymbolSymbol(MO.getSymbolName()));
86     break;
87   case MachineOperand::MO_JumpTableIndex:
88     MCOp = GetSymbolRef(MO, GetJTISymbol(MO.getIndex()));
89     break;
90   case MachineOperand::MO_ConstantPoolIndex:
91     if (Subtarget->genExecuteOnly())
92       llvm_unreachable("execute-only should not generate constant pools");
93     MCOp = GetSymbolRef(MO, GetCPISymbol(MO.getIndex()));
94     break;
95   case MachineOperand::MO_BlockAddress:
96     MCOp = GetSymbolRef(MO, GetBlockAddressSymbol(MO.getBlockAddress()));
97     break;
98   case MachineOperand::MO_FPImmediate: {
99     APFloat Val = MO.getFPImm()->getValueAPF();
100     bool ignored;
101     Val.convert(APFloat::IEEEdouble(), APFloat::rmTowardZero, &ignored);
102     MCOp = MCOperand::createFPImm(Val.convertToDouble());
103     break;
104   }
105   case MachineOperand::MO_RegisterMask:
106     // Ignore call clobbers.
107     return false;
108   }
109   return true;
110 }
111 
112 void llvm::LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
113                                         ARMAsmPrinter &AP) {
114   OutMI.setOpcode(MI->getOpcode());
115 
116   // In the MC layer, we keep modified immediates in their encoded form
117   bool EncodeImms = false;
118   switch (MI->getOpcode()) {
119   default: break;
120   case ARM::MOVi:
121   case ARM::MVNi:
122   case ARM::CMPri:
123   case ARM::CMNri:
124   case ARM::TSTri:
125   case ARM::TEQri:
126   case ARM::MSRi:
127   case ARM::ADCri:
128   case ARM::ADDri:
129   case ARM::ADDSri:
130   case ARM::SBCri:
131   case ARM::SUBri:
132   case ARM::SUBSri:
133   case ARM::ANDri:
134   case ARM::ORRri:
135   case ARM::EORri:
136   case ARM::BICri:
137   case ARM::RSBri:
138   case ARM::RSBSri:
139   case ARM::RSCri:
140     EncodeImms = true;
141     break;
142   }
143 
144   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
145     const MachineOperand &MO = MI->getOperand(i);
146 
147     MCOperand MCOp;
148     if (AP.lowerOperand(MO, MCOp)) {
149       if (MCOp.isImm() && EncodeImms) {
150         int32_t Enc = ARM_AM::getSOImmVal(MCOp.getImm());
151         if (Enc != -1)
152           MCOp.setImm(Enc);
153       }
154       OutMI.addOperand(MCOp);
155     }
156   }
157 }
158 
159 void ARMAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind)
160 {
161   if (MI.getParent()->getParent()->getInfo<ARMFunctionInfo>()
162     ->isThumbFunction())
163   {
164     MI.emitError("An attempt to perform XRay instrumentation for a"
165       " Thumb function (not supported). Detected when emitting a sled.");
166     return;
167   }
168   static const int8_t NoopsInSledCount = 6;
169   // We want to emit the following pattern:
170   //
171   // .Lxray_sled_N:
172   //   ALIGN
173   //   B #20
174   //   ; 6 NOP instructions (24 bytes)
175   // .tmpN
176   //
177   // We need the 24 bytes (6 instructions) because at runtime, we'd be patching
178   // over the full 28 bytes (7 instructions) with the following pattern:
179   //
180   //   PUSH{ r0, lr }
181   //   MOVW r0, #<lower 16 bits of function ID>
182   //   MOVT r0, #<higher 16 bits of function ID>
183   //   MOVW ip, #<lower 16 bits of address of __xray_FunctionEntry/Exit>
184   //   MOVT ip, #<higher 16 bits of address of __xray_FunctionEntry/Exit>
185   //   BLX ip
186   //   POP{ r0, lr }
187   //
188   OutStreamer->EmitCodeAlignment(4);
189   auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
190   OutStreamer->EmitLabel(CurSled);
191   auto Target = OutContext.createTempSymbol();
192 
193   // Emit "B #20" instruction, which jumps over the next 24 bytes (because
194   // register pc is 8 bytes ahead of the jump instruction by the moment CPU
195   // is executing it).
196   // By analogy to ARMAsmPrinter::emitPseudoExpansionLowering() |case ARM::B|.
197   // It is not clear why |addReg(0)| is needed (the last operand).
198   EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc).addImm(20)
199     .addImm(ARMCC::AL).addReg(0));
200 
201   MCInst Noop;
202   Subtarget->getInstrInfo()->getNoopForElfTarget(Noop);
203   for (int8_t I = 0; I < NoopsInSledCount; I++)
204   {
205     OutStreamer->EmitInstruction(Noop, getSubtargetInfo());
206   }
207 
208   OutStreamer->EmitLabel(Target);
209   recordSled(CurSled, MI, Kind);
210 }
211 
212 void ARMAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
213 {
214   EmitSled(MI, SledKind::FUNCTION_ENTER);
215 }
216 
217 void ARMAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
218 {
219   EmitSled(MI, SledKind::FUNCTION_EXIT);
220 }
221 
222 void ARMAsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
223 {
224   EmitSled(MI, SledKind::TAIL_CALL);
225 }
226