1 //===-- ARMMCInstLower.cpp - Convert ARM MachineInstr to an MCInst --------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains code to lower ARM MachineInstrs to their corresponding 11 // MCInst records. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "ARM.h" 16 #include "ARMAsmPrinter.h" 17 #include "ARMMCExpr.h" 18 #include "llvm/Constants.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/MC/MCExpr.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/Target/Mangler.h" 23 using namespace llvm; 24 25 26 static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol, 27 ARMAsmPrinter &Printer) { 28 MCContext &Ctx = Printer.OutContext; 29 const MCExpr *Expr; 30 switch (MO.getTargetFlags()) { 31 default: { 32 Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, Ctx); 33 switch (MO.getTargetFlags()) { 34 default: 35 assert(0 && "Unknown target flag on symbol operand"); 36 case 0: 37 break; 38 case ARMII::MO_LO16: 39 Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, Ctx); 40 Expr = ARMMCExpr::CreateLower16(Expr, Ctx); 41 break; 42 case ARMII::MO_HI16: 43 Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, Ctx); 44 Expr = ARMMCExpr::CreateUpper16(Expr, Ctx); 45 break; 46 } 47 break; 48 } 49 50 case ARMII::MO_PLT: 51 Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_ARM_PLT, Ctx); 52 break; 53 } 54 55 if (!MO.isJTI() && MO.getOffset()) 56 Expr = MCBinaryExpr::CreateAdd(Expr, 57 MCConstantExpr::Create(MO.getOffset(), Ctx), 58 Ctx); 59 return MCOperand::CreateExpr(Expr); 60 61 } 62 63 void llvm::LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, 64 ARMAsmPrinter &AP) { 65 OutMI.setOpcode(MI->getOpcode()); 66 67 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 68 const MachineOperand &MO = MI->getOperand(i); 69 70 MCOperand MCOp; 71 switch (MO.getType()) { 72 default: 73 MI->dump(); 74 assert(0 && "unknown operand type"); 75 case MachineOperand::MO_Register: 76 // Ignore all non-CPSR implicit register operands. 77 if (MO.isImplicit() && MO.getReg() != ARM::CPSR) continue; 78 assert(!MO.getSubReg() && "Subregs should be eliminated!"); 79 MCOp = MCOperand::CreateReg(MO.getReg()); 80 break; 81 case MachineOperand::MO_Immediate: 82 MCOp = MCOperand::CreateImm(MO.getImm()); 83 break; 84 case MachineOperand::MO_MachineBasicBlock: 85 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create( 86 MO.getMBB()->getSymbol(), AP.OutContext)); 87 break; 88 case MachineOperand::MO_GlobalAddress: 89 MCOp = GetSymbolRef(MO, AP.Mang->getSymbol(MO.getGlobal()), AP); 90 break; 91 case MachineOperand::MO_ExternalSymbol: 92 MCOp = GetSymbolRef(MO, 93 AP.GetExternalSymbolSymbol(MO.getSymbolName()), AP); 94 break; 95 case MachineOperand::MO_JumpTableIndex: 96 MCOp = GetSymbolRef(MO, AP.GetJTISymbol(MO.getIndex()), AP); 97 break; 98 case MachineOperand::MO_ConstantPoolIndex: 99 MCOp = GetSymbolRef(MO, AP.GetCPISymbol(MO.getIndex()), AP); 100 break; 101 case MachineOperand::MO_BlockAddress: 102 MCOp = GetSymbolRef(MO,AP.GetBlockAddressSymbol(MO.getBlockAddress()),AP); 103 break; 104 case MachineOperand::MO_FPImmediate: { 105 APFloat Val = MO.getFPImm()->getValueAPF(); 106 bool ignored; 107 Val.convert(APFloat::IEEEdouble, APFloat::rmTowardZero, &ignored); 108 MCOp = MCOperand::CreateFPImm(Val.convertToDouble()); 109 break; 110 } 111 } 112 113 OutMI.addOperand(MCOp); 114 } 115 } 116