1 //===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the targeting of the Machinelegalizer class for ARM.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMLegalizerInfo.h"
15 #include "ARMCallLowering.h"
16 #include "ARMSubtarget.h"
17 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
18 #include "llvm/CodeGen/LowLevelType.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/IR/DerivedTypes.h"
22 #include "llvm/IR/Type.h"
23 #include "llvm/Target/TargetOpcodes.h"
24 
25 using namespace llvm;
26 
27 static bool AEABI(const ARMSubtarget &ST) {
28   return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI();
29 }
30 
31 ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
32   using namespace TargetOpcode;
33 
34   const LLT p0 = LLT::pointer(0, 32);
35 
36   const LLT s1 = LLT::scalar(1);
37   const LLT s8 = LLT::scalar(8);
38   const LLT s16 = LLT::scalar(16);
39   const LLT s32 = LLT::scalar(32);
40   const LLT s64 = LLT::scalar(64);
41 
42   setAction({G_GLOBAL_VALUE, p0}, Legal);
43   setAction({G_FRAME_INDEX, p0}, Legal);
44 
45   for (unsigned Op : {G_LOAD, G_STORE}) {
46     for (auto Ty : {s1, s8, s16, s32, p0})
47       setAction({Op, Ty}, Legal);
48     setAction({Op, 1, p0}, Legal);
49   }
50 
51   for (unsigned Op : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) {
52     for (auto Ty : {s1, s8, s16})
53       setAction({Op, Ty}, WidenScalar);
54     setAction({Op, s32}, Legal);
55   }
56 
57   for (unsigned Op : {G_SDIV, G_UDIV}) {
58     for (auto Ty : {s8, s16})
59       setAction({Op, Ty}, WidenScalar);
60     if (ST.hasDivideInARMMode())
61       setAction({Op, s32}, Legal);
62     else
63       setAction({Op, s32}, Libcall);
64   }
65 
66   for (unsigned Op : {G_SREM, G_UREM}) {
67     for (auto Ty : {s8, s16})
68       setAction({Op, Ty}, WidenScalar);
69     if (ST.hasDivideInARMMode())
70       setAction({Op, s32}, Lower);
71     else if (AEABI(ST))
72       setAction({Op, s32}, Custom);
73     else
74       setAction({Op, s32}, Libcall);
75   }
76 
77   for (unsigned Op : {G_SEXT, G_ZEXT}) {
78     setAction({Op, s32}, Legal);
79     for (auto Ty : {s1, s8, s16})
80       setAction({Op, 1, Ty}, Legal);
81   }
82 
83   setAction({G_GEP, p0}, Legal);
84   setAction({G_GEP, 1, s32}, Legal);
85 
86   setAction({G_SELECT, s32}, Legal);
87   setAction({G_SELECT, p0}, Legal);
88   setAction({G_SELECT, 1, s1}, Legal);
89 
90   setAction({G_BRCOND, s1}, Legal);
91 
92   setAction({G_CONSTANT, s32}, Legal);
93   for (auto Ty : {s1, s8, s16})
94     setAction({G_CONSTANT, Ty}, WidenScalar);
95 
96   setAction({G_ICMP, s1}, Legal);
97   for (auto Ty : {s8, s16})
98     setAction({G_ICMP, 1, Ty}, WidenScalar);
99   for (auto Ty : {s32, p0})
100     setAction({G_ICMP, 1, Ty}, Legal);
101 
102   if (!ST.useSoftFloat() && ST.hasVFP2()) {
103     setAction({G_FADD, s32}, Legal);
104     setAction({G_FADD, s64}, Legal);
105 
106     setAction({G_LOAD, s64}, Legal);
107     setAction({G_STORE, s64}, Legal);
108 
109     setAction({G_FCMP, s1}, Legal);
110     setAction({G_FCMP, 1, s32}, Legal);
111     setAction({G_FCMP, 1, s64}, Legal);
112   } else {
113     for (auto Ty : {s32, s64})
114       setAction({G_FADD, Ty}, Libcall);
115 
116     setAction({G_FCMP, s1}, Legal);
117     setAction({G_FCMP, 1, s32}, Custom);
118     setAction({G_FCMP, 1, s64}, Custom);
119 
120     if (AEABI(ST))
121       setFCmpLibcallsAEABI();
122     else
123       setFCmpLibcallsGNU();
124   }
125 
126   for (unsigned Op : {G_FREM, G_FPOW})
127     for (auto Ty : {s32, s64})
128       setAction({Op, Ty}, Libcall);
129 
130   computeTables();
131 }
132 
133 void ARMLegalizerInfo::setFCmpLibcallsAEABI() {
134   // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
135   // default-initialized.
136   FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
137   FCmp32Libcalls[CmpInst::FCMP_OEQ] = {
138       {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}};
139   FCmp32Libcalls[CmpInst::FCMP_OGE] = {
140       {RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}};
141   FCmp32Libcalls[CmpInst::FCMP_OGT] = {
142       {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}};
143   FCmp32Libcalls[CmpInst::FCMP_OLE] = {
144       {RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}};
145   FCmp32Libcalls[CmpInst::FCMP_OLT] = {
146       {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
147   FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
148   FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}};
149   FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}};
150   FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}};
151   FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}};
152   FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}};
153   FCmp32Libcalls[CmpInst::FCMP_UNO] = {
154       {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
155   FCmp32Libcalls[CmpInst::FCMP_ONE] = {
156       {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE},
157       {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
158   FCmp32Libcalls[CmpInst::FCMP_UEQ] = {
159       {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE},
160       {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
161 
162   FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
163   FCmp64Libcalls[CmpInst::FCMP_OEQ] = {
164       {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}};
165   FCmp64Libcalls[CmpInst::FCMP_OGE] = {
166       {RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}};
167   FCmp64Libcalls[CmpInst::FCMP_OGT] = {
168       {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}};
169   FCmp64Libcalls[CmpInst::FCMP_OLE] = {
170       {RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}};
171   FCmp64Libcalls[CmpInst::FCMP_OLT] = {
172       {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
173   FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
174   FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}};
175   FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}};
176   FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}};
177   FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}};
178   FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}};
179   FCmp64Libcalls[CmpInst::FCMP_UNO] = {
180       {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
181   FCmp64Libcalls[CmpInst::FCMP_ONE] = {
182       {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE},
183       {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
184   FCmp64Libcalls[CmpInst::FCMP_UEQ] = {
185       {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE},
186       {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
187 }
188 
189 void ARMLegalizerInfo::setFCmpLibcallsGNU() {
190   // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
191   // default-initialized.
192   FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
193   FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}};
194   FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}};
195   FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}};
196   FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}};
197   FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
198   FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
199   FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}};
200   FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}};
201   FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}};
202   FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}};
203   FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}};
204   FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}};
205   FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT},
206                                        {RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
207   FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ},
208                                        {RTLIB::UO_F32, CmpInst::ICMP_NE}};
209 
210   FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
211   FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}};
212   FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}};
213   FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}};
214   FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}};
215   FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
216   FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
217   FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}};
218   FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}};
219   FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}};
220   FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}};
221   FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}};
222   FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}};
223   FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT},
224                                        {RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
225   FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ},
226                                        {RTLIB::UO_F64, CmpInst::ICMP_NE}};
227 }
228 
229 ARMLegalizerInfo::FCmpLibcallsList
230 ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate,
231                                   unsigned Size) const {
232   assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate");
233   if (Size == 32)
234     return FCmp32Libcalls[Predicate];
235   if (Size == 64)
236     return FCmp64Libcalls[Predicate];
237   llvm_unreachable("Unsupported size for FCmp predicate");
238 }
239 
240 bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI,
241                                       MachineRegisterInfo &MRI,
242                                       MachineIRBuilder &MIRBuilder) const {
243   using namespace TargetOpcode;
244 
245   MIRBuilder.setInstr(MI);
246 
247   switch (MI.getOpcode()) {
248   default:
249     return false;
250   case G_SREM:
251   case G_UREM: {
252     unsigned OriginalResult = MI.getOperand(0).getReg();
253     auto Size = MRI.getType(OriginalResult).getSizeInBits();
254     if (Size != 32)
255       return false;
256 
257     auto Libcall =
258         MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
259 
260     // Our divmod libcalls return a struct containing the quotient and the
261     // remainder. We need to create a virtual register for it.
262     auto &Ctx = MIRBuilder.getMF().getFunction()->getContext();
263     Type *ArgTy = Type::getInt32Ty(Ctx);
264     StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true);
265     auto RetVal = MRI.createGenericVirtualRegister(
266         getLLTForType(*RetTy, MIRBuilder.getMF().getDataLayout()));
267 
268     auto Status = createLibcall(MIRBuilder, Libcall, {RetVal, RetTy},
269                                 {{MI.getOperand(1).getReg(), ArgTy},
270                                  {MI.getOperand(2).getReg(), ArgTy}});
271     if (Status != LegalizerHelper::Legalized)
272       return false;
273 
274     // The remainder is the second result of divmod. Split the return value into
275     // a new, unused register for the quotient and the destination of the
276     // original instruction for the remainder.
277     MIRBuilder.buildUnmerge(
278         {MRI.createGenericVirtualRegister(LLT::scalar(32)), OriginalResult},
279         RetVal);
280     break;
281   }
282   case G_FCMP: {
283     assert(MRI.getType(MI.getOperand(2).getReg()) ==
284                MRI.getType(MI.getOperand(3).getReg()) &&
285            "Mismatched operands for G_FCMP");
286     auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
287 
288     auto OriginalResult = MI.getOperand(0).getReg();
289     auto Predicate =
290         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
291     auto Libcalls = getFCmpLibcalls(Predicate, OpSize);
292 
293     if (Libcalls.empty()) {
294       assert((Predicate == CmpInst::FCMP_TRUE ||
295               Predicate == CmpInst::FCMP_FALSE) &&
296              "Predicate needs libcalls, but none specified");
297       MIRBuilder.buildConstant(OriginalResult,
298                                Predicate == CmpInst::FCMP_TRUE ? 1 : 0);
299       MI.eraseFromParent();
300       return true;
301     }
302 
303     auto &Ctx = MIRBuilder.getMF().getFunction()->getContext();
304     assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size");
305     auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx);
306     auto *RetTy = Type::getInt32Ty(Ctx);
307 
308     SmallVector<unsigned, 2> Results;
309     for (auto Libcall : Libcalls) {
310       auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32));
311       auto Status =
312           createLibcall(MIRBuilder, Libcall.LibcallID, {LibcallResult, RetTy},
313                         {{MI.getOperand(2).getReg(), ArgTy},
314                          {MI.getOperand(3).getReg(), ArgTy}});
315 
316       if (Status != LegalizerHelper::Legalized)
317         return false;
318 
319       auto ProcessedResult =
320           Libcalls.size() == 1
321               ? OriginalResult
322               : MRI.createGenericVirtualRegister(MRI.getType(OriginalResult));
323 
324       // We have a result, but we need to transform it into a proper 1-bit 0 or
325       // 1, taking into account the different peculiarities of the values
326       // returned by the comparison functions.
327       CmpInst::Predicate ResultPred = Libcall.Predicate;
328       if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) {
329         // We have a nice 0 or 1, and we just need to truncate it back to 1 bit
330         // to keep the types consistent.
331         MIRBuilder.buildTrunc(ProcessedResult, LibcallResult);
332       } else {
333         // We need to compare against 0.
334         assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate");
335         auto Zero = MRI.createGenericVirtualRegister(LLT::scalar(32));
336         MIRBuilder.buildConstant(Zero, 0);
337         MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero);
338       }
339       Results.push_back(ProcessedResult);
340     }
341 
342     if (Results.size() != 1) {
343       assert(Results.size() == 2 && "Unexpected number of results");
344       MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]);
345     }
346     break;
347   }
348   }
349 
350   MI.eraseFromParent();
351   return true;
352 }
353