1 //===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements the targeting of the Machinelegalizer class for ARM. 10 /// \todo This should be generated by TableGen. 11 //===----------------------------------------------------------------------===// 12 13 #include "ARMLegalizerInfo.h" 14 #include "ARMCallLowering.h" 15 #include "ARMSubtarget.h" 16 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" 17 #include "llvm/CodeGen/LowLevelType.h" 18 #include "llvm/CodeGen/MachineRegisterInfo.h" 19 #include "llvm/CodeGen/TargetOpcodes.h" 20 #include "llvm/CodeGen/ValueTypes.h" 21 #include "llvm/IR/DerivedTypes.h" 22 #include "llvm/IR/Type.h" 23 24 using namespace llvm; 25 using namespace LegalizeActions; 26 27 /// FIXME: The following static functions are SizeChangeStrategy functions 28 /// that are meant to temporarily mimic the behaviour of the old legalization 29 /// based on doubling/halving non-legal types as closely as possible. This is 30 /// not entirly possible as only legalizing the types that are exactly a power 31 /// of 2 times the size of the legal types would require specifying all those 32 /// sizes explicitly. 33 /// In practice, not specifying those isn't a problem, and the below functions 34 /// should disappear quickly as we add support for legalizing non-power-of-2 35 /// sized types further. 36 static void 37 addAndInterleaveWithUnsupported(LegalizerInfo::SizeAndActionsVec &result, 38 const LegalizerInfo::SizeAndActionsVec &v) { 39 for (unsigned i = 0; i < v.size(); ++i) { 40 result.push_back(v[i]); 41 if (i + 1 < v[i].first && i + 1 < v.size() && 42 v[i + 1].first != v[i].first + 1) 43 result.push_back({v[i].first + 1, Unsupported}); 44 } 45 } 46 47 static LegalizerInfo::SizeAndActionsVec 48 widen_8_16(const LegalizerInfo::SizeAndActionsVec &v) { 49 assert(v.size() >= 1); 50 assert(v[0].first > 17); 51 LegalizerInfo::SizeAndActionsVec result = {{1, Unsupported}, 52 {8, WidenScalar}, 53 {9, Unsupported}, 54 {16, WidenScalar}, 55 {17, Unsupported}}; 56 addAndInterleaveWithUnsupported(result, v); 57 auto Largest = result.back().first; 58 result.push_back({Largest + 1, Unsupported}); 59 return result; 60 } 61 62 static bool AEABI(const ARMSubtarget &ST) { 63 return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI(); 64 } 65 66 ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { 67 using namespace TargetOpcode; 68 69 const LLT p0 = LLT::pointer(0, 32); 70 71 const LLT s1 = LLT::scalar(1); 72 const LLT s8 = LLT::scalar(8); 73 const LLT s16 = LLT::scalar(16); 74 const LLT s32 = LLT::scalar(32); 75 const LLT s64 = LLT::scalar(64); 76 77 if (ST.isThumb1Only()) { 78 // Thumb1 is not supported yet. 79 computeTables(); 80 verify(*ST.getInstrInfo()); 81 return; 82 } 83 84 getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT}) 85 .legalForCartesianProduct({s32}, {s1, s8, s16}); 86 87 getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) 88 .legalFor({s32}) 89 .minScalar(0, s32); 90 91 getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL}) 92 .legalFor({{s32, s32}}) 93 .minScalar(0, s32) 94 .clampScalar(1, s32, s32); 95 96 bool HasHWDivide = (!ST.isThumb() && ST.hasDivideInARMMode()) || 97 (ST.isThumb() && ST.hasDivideInThumbMode()); 98 if (HasHWDivide) 99 getActionDefinitionsBuilder({G_SDIV, G_UDIV}) 100 .legalFor({s32}) 101 .clampScalar(0, s32, s32); 102 else 103 getActionDefinitionsBuilder({G_SDIV, G_UDIV}) 104 .libcallFor({s32}) 105 .clampScalar(0, s32, s32); 106 107 for (unsigned Op : {G_SREM, G_UREM}) { 108 setLegalizeScalarToDifferentSizeStrategy(Op, 0, widen_8_16); 109 if (HasHWDivide) 110 setAction({Op, s32}, Lower); 111 else if (AEABI(ST)) 112 setAction({Op, s32}, Custom); 113 else 114 setAction({Op, s32}, Libcall); 115 } 116 117 getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}}); 118 getActionDefinitionsBuilder(G_PTRTOINT).legalFor({{s32, p0}}); 119 120 getActionDefinitionsBuilder(G_CONSTANT) 121 .legalFor({s32, p0}) 122 .clampScalar(0, s32, s32); 123 124 getActionDefinitionsBuilder(G_ICMP) 125 .legalForCartesianProduct({s1}, {s32, p0}) 126 .minScalar(1, s32); 127 128 getActionDefinitionsBuilder(G_SELECT).legalForCartesianProduct({s32, p0}, 129 {s1}); 130 131 // We're keeping these builders around because we'll want to add support for 132 // floating point to them. 133 auto &LoadStoreBuilder = getActionDefinitionsBuilder({G_LOAD, G_STORE}) 134 .legalForTypesWithMemDesc({{s1, p0, 8, 8}, 135 {s8, p0, 8, 8}, 136 {s16, p0, 16, 8}, 137 {s32, p0, 32, 8}, 138 {p0, p0, 32, 8}}) 139 .unsupportedIfMemSizeNotPow2(); 140 141 getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0}); 142 getActionDefinitionsBuilder(G_GLOBAL_VALUE).legalFor({p0}); 143 144 auto &PhiBuilder = 145 getActionDefinitionsBuilder(G_PHI) 146 .legalFor({s32, p0}) 147 .minScalar(0, s32); 148 149 getActionDefinitionsBuilder(G_GEP).legalFor({{p0, s32}}); 150 151 getActionDefinitionsBuilder(G_BRCOND).legalFor({s1}); 152 153 if (!ST.useSoftFloat() && ST.hasVFP2()) { 154 getActionDefinitionsBuilder( 155 {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG}) 156 .legalFor({s32, s64}); 157 158 LoadStoreBuilder 159 .legalForTypesWithMemDesc({{s64, p0, 64, 32}}) 160 .maxScalar(0, s32); 161 PhiBuilder.legalFor({s64}); 162 163 getActionDefinitionsBuilder(G_FCMP).legalForCartesianProduct({s1}, 164 {s32, s64}); 165 166 getActionDefinitionsBuilder(G_MERGE_VALUES).legalFor({{s64, s32}}); 167 getActionDefinitionsBuilder(G_UNMERGE_VALUES).legalFor({{s32, s64}}); 168 169 getActionDefinitionsBuilder(G_FPEXT).legalFor({{s64, s32}}); 170 getActionDefinitionsBuilder(G_FPTRUNC).legalFor({{s32, s64}}); 171 172 getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI}) 173 .legalForCartesianProduct({s32}, {s32, s64}); 174 getActionDefinitionsBuilder({G_SITOFP, G_UITOFP}) 175 .legalForCartesianProduct({s32, s64}, {s32}); 176 } else { 177 getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV}) 178 .libcallFor({s32, s64}); 179 180 LoadStoreBuilder.maxScalar(0, s32); 181 182 for (auto Ty : {s32, s64}) 183 setAction({G_FNEG, Ty}, Lower); 184 185 getActionDefinitionsBuilder(G_FCONSTANT).customFor({s32, s64}); 186 187 getActionDefinitionsBuilder(G_FCMP).customForCartesianProduct({s1}, 188 {s32, s64}); 189 190 if (AEABI(ST)) 191 setFCmpLibcallsAEABI(); 192 else 193 setFCmpLibcallsGNU(); 194 195 getActionDefinitionsBuilder(G_FPEXT).libcallFor({{s64, s32}}); 196 getActionDefinitionsBuilder(G_FPTRUNC).libcallFor({{s32, s64}}); 197 198 getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI}) 199 .libcallForCartesianProduct({s32}, {s32, s64}); 200 getActionDefinitionsBuilder({G_SITOFP, G_UITOFP}) 201 .libcallForCartesianProduct({s32, s64}, {s32}); 202 } 203 204 if (!ST.useSoftFloat() && ST.hasVFP4()) 205 getActionDefinitionsBuilder(G_FMA).legalFor({s32, s64}); 206 else 207 getActionDefinitionsBuilder(G_FMA).libcallFor({s32, s64}); 208 209 getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64}); 210 211 if (ST.hasV5TOps()) { 212 getActionDefinitionsBuilder(G_CTLZ) 213 .legalFor({s32, s32}) 214 .clampScalar(1, s32, s32) 215 .clampScalar(0, s32, s32); 216 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF) 217 .lowerFor({s32, s32}) 218 .clampScalar(1, s32, s32) 219 .clampScalar(0, s32, s32); 220 } else { 221 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF) 222 .libcallFor({s32, s32}) 223 .clampScalar(1, s32, s32) 224 .clampScalar(0, s32, s32); 225 getActionDefinitionsBuilder(G_CTLZ) 226 .lowerFor({s32, s32}) 227 .clampScalar(1, s32, s32) 228 .clampScalar(0, s32, s32); 229 } 230 231 computeTables(); 232 verify(*ST.getInstrInfo()); 233 } 234 235 void ARMLegalizerInfo::setFCmpLibcallsAEABI() { 236 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be 237 // default-initialized. 238 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 239 FCmp32Libcalls[CmpInst::FCMP_OEQ] = { 240 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}}; 241 FCmp32Libcalls[CmpInst::FCMP_OGE] = { 242 {RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}}; 243 FCmp32Libcalls[CmpInst::FCMP_OGT] = { 244 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 245 FCmp32Libcalls[CmpInst::FCMP_OLE] = { 246 {RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}}; 247 FCmp32Libcalls[CmpInst::FCMP_OLT] = { 248 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 249 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}}; 250 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}}; 251 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}}; 252 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}}; 253 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}}; 254 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}}; 255 FCmp32Libcalls[CmpInst::FCMP_UNO] = { 256 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}}; 257 FCmp32Libcalls[CmpInst::FCMP_ONE] = { 258 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}, 259 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 260 FCmp32Libcalls[CmpInst::FCMP_UEQ] = { 261 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}, 262 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}}; 263 264 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 265 FCmp64Libcalls[CmpInst::FCMP_OEQ] = { 266 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}}; 267 FCmp64Libcalls[CmpInst::FCMP_OGE] = { 268 {RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}}; 269 FCmp64Libcalls[CmpInst::FCMP_OGT] = { 270 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 271 FCmp64Libcalls[CmpInst::FCMP_OLE] = { 272 {RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}}; 273 FCmp64Libcalls[CmpInst::FCMP_OLT] = { 274 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 275 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}}; 276 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}}; 277 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}}; 278 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}}; 279 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}}; 280 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}}; 281 FCmp64Libcalls[CmpInst::FCMP_UNO] = { 282 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}}; 283 FCmp64Libcalls[CmpInst::FCMP_ONE] = { 284 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}, 285 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 286 FCmp64Libcalls[CmpInst::FCMP_UEQ] = { 287 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}, 288 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}}; 289 } 290 291 void ARMLegalizerInfo::setFCmpLibcallsGNU() { 292 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be 293 // default-initialized. 294 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 295 FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}}; 296 FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}}; 297 FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}}; 298 FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}}; 299 FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}}; 300 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}}; 301 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}}; 302 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}}; 303 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}}; 304 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}}; 305 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}}; 306 FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}}; 307 FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}, 308 {RTLIB::OLT_F32, CmpInst::ICMP_SLT}}; 309 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}, 310 {RTLIB::UO_F32, CmpInst::ICMP_NE}}; 311 312 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 313 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}}; 314 FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}}; 315 FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}}; 316 FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}}; 317 FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}}; 318 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}}; 319 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}}; 320 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}}; 321 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}}; 322 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}}; 323 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}}; 324 FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}}; 325 FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}, 326 {RTLIB::OLT_F64, CmpInst::ICMP_SLT}}; 327 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}, 328 {RTLIB::UO_F64, CmpInst::ICMP_NE}}; 329 } 330 331 ARMLegalizerInfo::FCmpLibcallsList 332 ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate, 333 unsigned Size) const { 334 assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate"); 335 if (Size == 32) 336 return FCmp32Libcalls[Predicate]; 337 if (Size == 64) 338 return FCmp64Libcalls[Predicate]; 339 llvm_unreachable("Unsupported size for FCmp predicate"); 340 } 341 342 bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI, 343 MachineRegisterInfo &MRI, 344 MachineIRBuilder &MIRBuilder, 345 GISelChangeObserver &Observer) const { 346 using namespace TargetOpcode; 347 348 MIRBuilder.setInstr(MI); 349 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 350 351 switch (MI.getOpcode()) { 352 default: 353 return false; 354 case G_SREM: 355 case G_UREM: { 356 unsigned OriginalResult = MI.getOperand(0).getReg(); 357 auto Size = MRI.getType(OriginalResult).getSizeInBits(); 358 if (Size != 32) 359 return false; 360 361 auto Libcall = 362 MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; 363 364 // Our divmod libcalls return a struct containing the quotient and the 365 // remainder. We need to create a virtual register for it. 366 Type *ArgTy = Type::getInt32Ty(Ctx); 367 StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true); 368 auto RetVal = MRI.createGenericVirtualRegister( 369 getLLTForType(*RetTy, MIRBuilder.getMF().getDataLayout())); 370 371 auto Status = createLibcall(MIRBuilder, Libcall, {RetVal, RetTy}, 372 {{MI.getOperand(1).getReg(), ArgTy}, 373 {MI.getOperand(2).getReg(), ArgTy}}); 374 if (Status != LegalizerHelper::Legalized) 375 return false; 376 377 // The remainder is the second result of divmod. Split the return value into 378 // a new, unused register for the quotient and the destination of the 379 // original instruction for the remainder. 380 MIRBuilder.buildUnmerge( 381 {MRI.createGenericVirtualRegister(LLT::scalar(32)), OriginalResult}, 382 RetVal); 383 break; 384 } 385 case G_FCMP: { 386 assert(MRI.getType(MI.getOperand(2).getReg()) == 387 MRI.getType(MI.getOperand(3).getReg()) && 388 "Mismatched operands for G_FCMP"); 389 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); 390 391 auto OriginalResult = MI.getOperand(0).getReg(); 392 auto Predicate = 393 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 394 auto Libcalls = getFCmpLibcalls(Predicate, OpSize); 395 396 if (Libcalls.empty()) { 397 assert((Predicate == CmpInst::FCMP_TRUE || 398 Predicate == CmpInst::FCMP_FALSE) && 399 "Predicate needs libcalls, but none specified"); 400 MIRBuilder.buildConstant(OriginalResult, 401 Predicate == CmpInst::FCMP_TRUE ? 1 : 0); 402 MI.eraseFromParent(); 403 return true; 404 } 405 406 assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size"); 407 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx); 408 auto *RetTy = Type::getInt32Ty(Ctx); 409 410 SmallVector<unsigned, 2> Results; 411 for (auto Libcall : Libcalls) { 412 auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32)); 413 auto Status = 414 createLibcall(MIRBuilder, Libcall.LibcallID, {LibcallResult, RetTy}, 415 {{MI.getOperand(2).getReg(), ArgTy}, 416 {MI.getOperand(3).getReg(), ArgTy}}); 417 418 if (Status != LegalizerHelper::Legalized) 419 return false; 420 421 auto ProcessedResult = 422 Libcalls.size() == 1 423 ? OriginalResult 424 : MRI.createGenericVirtualRegister(MRI.getType(OriginalResult)); 425 426 // We have a result, but we need to transform it into a proper 1-bit 0 or 427 // 1, taking into account the different peculiarities of the values 428 // returned by the comparison functions. 429 CmpInst::Predicate ResultPred = Libcall.Predicate; 430 if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) { 431 // We have a nice 0 or 1, and we just need to truncate it back to 1 bit 432 // to keep the types consistent. 433 MIRBuilder.buildTrunc(ProcessedResult, LibcallResult); 434 } else { 435 // We need to compare against 0. 436 assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate"); 437 auto Zero = MRI.createGenericVirtualRegister(LLT::scalar(32)); 438 MIRBuilder.buildConstant(Zero, 0); 439 MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero); 440 } 441 Results.push_back(ProcessedResult); 442 } 443 444 if (Results.size() != 1) { 445 assert(Results.size() == 2 && "Unexpected number of results"); 446 MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]); 447 } 448 break; 449 } 450 case G_FCONSTANT: { 451 // Convert to integer constants, while preserving the binary representation. 452 auto AsInteger = 453 MI.getOperand(1).getFPImm()->getValueAPF().bitcastToAPInt(); 454 MIRBuilder.buildConstant(MI.getOperand(0).getReg(), 455 *ConstantInt::get(Ctx, AsInteger)); 456 break; 457 } 458 } 459 460 MI.eraseFromParent(); 461 return true; 462 } 463