1 //===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the targeting of the Machinelegalizer class for ARM.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMLegalizerInfo.h"
15 #include "ARMCallLowering.h"
16 #include "ARMSubtarget.h"
17 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
18 #include "llvm/CodeGen/LowLevelType.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetOpcodes.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/IR/DerivedTypes.h"
23 #include "llvm/IR/Type.h"
24 
25 using namespace llvm;
26 
27 /// FIXME: The following static functions are SizeChangeStrategy functions
28 /// that are meant to temporarily mimic the behaviour of the old legalization
29 /// based on doubling/halving non-legal types as closely as possible. This is
30 /// not entirly possible as only legalizing the types that are exactly a power
31 /// of 2 times the size of the legal types would require specifying all those
32 /// sizes explicitly.
33 /// In practice, not specifying those isn't a problem, and the below functions
34 /// should disappear quickly as we add support for legalizing non-power-of-2
35 /// sized types further.
36 static void
37 addAndInterleaveWithUnsupported(LegalizerInfo::SizeAndActionsVec &result,
38                                 const LegalizerInfo::SizeAndActionsVec &v) {
39   for (unsigned i = 0; i < v.size(); ++i) {
40     result.push_back(v[i]);
41     if (i + 1 < v[i].first && i + 1 < v.size() &&
42         v[i + 1].first != v[i].first + 1)
43       result.push_back({v[i].first + 1, LegalizerInfo::Unsupported});
44   }
45 }
46 
47 static LegalizerInfo::SizeAndActionsVec
48 widen_8_16(const LegalizerInfo::SizeAndActionsVec &v) {
49   assert(v.size() >= 1);
50   assert(v[0].first > 17);
51   LegalizerInfo::SizeAndActionsVec result = {
52       {1, LegalizerInfo::Unsupported},
53       {8, LegalizerInfo::WidenScalar},  {9, LegalizerInfo::Unsupported},
54       {16, LegalizerInfo::WidenScalar}, {17, LegalizerInfo::Unsupported}};
55   addAndInterleaveWithUnsupported(result, v);
56   auto Largest = result.back().first;
57   result.push_back({Largest + 1, LegalizerInfo::Unsupported});
58   return result;
59 }
60 
61 static LegalizerInfo::SizeAndActionsVec
62 widen_1_8_16_narrowToLargest(const LegalizerInfo::SizeAndActionsVec &v) {
63   assert(v.size() >= 1);
64   assert(v[0].first > 17);
65   LegalizerInfo::SizeAndActionsVec result = {
66       {1, LegalizerInfo::WidenScalar},  {2, LegalizerInfo::Unsupported},
67       {8, LegalizerInfo::WidenScalar},  {9, LegalizerInfo::Unsupported},
68       {16, LegalizerInfo::WidenScalar}, {17, LegalizerInfo::Unsupported}};
69   addAndInterleaveWithUnsupported(result, v);
70   auto Largest = result.back().first;
71   result.push_back({Largest + 1, LegalizerInfo::NarrowScalar});
72   return result;
73 }
74 
75 static bool AEABI(const ARMSubtarget &ST) {
76   return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI();
77 }
78 
79 ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
80   using namespace TargetOpcode;
81 
82   const LLT p0 = LLT::pointer(0, 32);
83 
84   const LLT s1 = LLT::scalar(1);
85   const LLT s8 = LLT::scalar(8);
86   const LLT s16 = LLT::scalar(16);
87   const LLT s32 = LLT::scalar(32);
88   const LLT s64 = LLT::scalar(64);
89 
90   setAction({G_GLOBAL_VALUE, p0}, Legal);
91   setAction({G_FRAME_INDEX, p0}, Legal);
92 
93   for (unsigned Op : {G_LOAD, G_STORE}) {
94     for (auto Ty : {s1, s8, s16, s32, p0})
95       setAction({Op, Ty}, Legal);
96     setAction({Op, 1, p0}, Legal);
97   }
98 
99   for (unsigned Op : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) {
100     if (Op != G_ADD)
101       setLegalizeScalarToDifferentSizeStrategy(
102           Op, 0, widenToLargerTypesUnsupportedOtherwise);
103     setAction({Op, s32}, Legal);
104   }
105 
106   for (unsigned Op : {G_SDIV, G_UDIV}) {
107     setLegalizeScalarToDifferentSizeStrategy(Op, 0,
108         widenToLargerTypesUnsupportedOtherwise);
109     if (ST.hasDivideInARMMode())
110       setAction({Op, s32}, Legal);
111     else
112       setAction({Op, s32}, Libcall);
113   }
114 
115   for (unsigned Op : {G_SREM, G_UREM}) {
116     setLegalizeScalarToDifferentSizeStrategy(Op, 0, widen_8_16);
117     if (ST.hasDivideInARMMode())
118       setAction({Op, s32}, Lower);
119     else if (AEABI(ST))
120       setAction({Op, s32}, Custom);
121     else
122       setAction({Op, s32}, Libcall);
123   }
124 
125   for (unsigned Op : {G_SEXT, G_ZEXT, G_ANYEXT}) {
126     setAction({Op, s32}, Legal);
127   }
128 
129   setAction({G_INTTOPTR, p0}, Legal);
130   setAction({G_INTTOPTR, 1, s32}, Legal);
131 
132   setAction({G_PTRTOINT, s32}, Legal);
133   setAction({G_PTRTOINT, 1, p0}, Legal);
134 
135   for (unsigned Op : {G_ASHR, G_LSHR, G_SHL})
136     setAction({Op, s32}, Legal);
137 
138   setAction({G_GEP, p0}, Legal);
139   setAction({G_GEP, 1, s32}, Legal);
140 
141   setAction({G_SELECT, s32}, Legal);
142   setAction({G_SELECT, p0}, Legal);
143   setAction({G_SELECT, 1, s1}, Legal);
144 
145   setAction({G_BRCOND, s1}, Legal);
146 
147   for (auto Ty : {s32, p0})
148     setAction({G_PHI, Ty}, Legal);
149   setLegalizeScalarToDifferentSizeStrategy(
150       G_PHI, 0, widenToLargerTypesUnsupportedOtherwise);
151 
152   setAction({G_CONSTANT, s32}, Legal);
153   setAction({G_CONSTANT, p0}, Legal);
154   setLegalizeScalarToDifferentSizeStrategy(G_CONSTANT, 0,
155                                            widen_1_8_16_narrowToLargest);
156 
157   setAction({G_ICMP, s1}, Legal);
158   setLegalizeScalarToDifferentSizeStrategy(G_ICMP, 1,
159       widenToLargerTypesUnsupportedOtherwise);
160   for (auto Ty : {s32, p0})
161     setAction({G_ICMP, 1, Ty}, Legal);
162 
163   if (!ST.useSoftFloat() && ST.hasVFP2()) {
164     for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG})
165       for (auto Ty : {s32, s64})
166         setAction({BinOp, Ty}, Legal);
167 
168     setAction({G_LOAD, s64}, Legal);
169     setAction({G_STORE, s64}, Legal);
170 
171     setAction({G_PHI, s64}, Legal);
172 
173     setAction({G_FCMP, s1}, Legal);
174     setAction({G_FCMP, 1, s32}, Legal);
175     setAction({G_FCMP, 1, s64}, Legal);
176 
177     setAction({G_MERGE_VALUES, s64}, Legal);
178     setAction({G_MERGE_VALUES, 1, s32}, Legal);
179     setAction({G_UNMERGE_VALUES, s32}, Legal);
180     setAction({G_UNMERGE_VALUES, 1, s64}, Legal);
181   } else {
182     for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
183       for (auto Ty : {s32, s64})
184         setAction({BinOp, Ty}, Libcall);
185 
186     for (auto Ty : {s32, s64}) {
187       setAction({G_FNEG, Ty}, Lower);
188       setAction({G_FCONSTANT, Ty}, Custom);
189     }
190 
191     setAction({G_FCMP, s1}, Legal);
192     setAction({G_FCMP, 1, s32}, Custom);
193     setAction({G_FCMP, 1, s64}, Custom);
194 
195     if (AEABI(ST))
196       setFCmpLibcallsAEABI();
197     else
198       setFCmpLibcallsGNU();
199   }
200 
201   if (!ST.useSoftFloat() && ST.hasVFP4())
202     for (auto Ty : {s32, s64})
203       setAction({G_FMA, Ty}, Legal);
204   else
205     for (auto Ty : {s32, s64})
206       setAction({G_FMA, Ty}, Libcall);
207 
208   for (unsigned Op : {G_FREM, G_FPOW})
209     for (auto Ty : {s32, s64})
210       setAction({Op, Ty}, Libcall);
211 
212   computeTables();
213 }
214 
215 void ARMLegalizerInfo::setFCmpLibcallsAEABI() {
216   // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
217   // default-initialized.
218   FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
219   FCmp32Libcalls[CmpInst::FCMP_OEQ] = {
220       {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}};
221   FCmp32Libcalls[CmpInst::FCMP_OGE] = {
222       {RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}};
223   FCmp32Libcalls[CmpInst::FCMP_OGT] = {
224       {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}};
225   FCmp32Libcalls[CmpInst::FCMP_OLE] = {
226       {RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}};
227   FCmp32Libcalls[CmpInst::FCMP_OLT] = {
228       {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
229   FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
230   FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}};
231   FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}};
232   FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}};
233   FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}};
234   FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}};
235   FCmp32Libcalls[CmpInst::FCMP_UNO] = {
236       {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
237   FCmp32Libcalls[CmpInst::FCMP_ONE] = {
238       {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE},
239       {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
240   FCmp32Libcalls[CmpInst::FCMP_UEQ] = {
241       {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE},
242       {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
243 
244   FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
245   FCmp64Libcalls[CmpInst::FCMP_OEQ] = {
246       {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}};
247   FCmp64Libcalls[CmpInst::FCMP_OGE] = {
248       {RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}};
249   FCmp64Libcalls[CmpInst::FCMP_OGT] = {
250       {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}};
251   FCmp64Libcalls[CmpInst::FCMP_OLE] = {
252       {RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}};
253   FCmp64Libcalls[CmpInst::FCMP_OLT] = {
254       {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
255   FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
256   FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}};
257   FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}};
258   FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}};
259   FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}};
260   FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}};
261   FCmp64Libcalls[CmpInst::FCMP_UNO] = {
262       {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
263   FCmp64Libcalls[CmpInst::FCMP_ONE] = {
264       {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE},
265       {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
266   FCmp64Libcalls[CmpInst::FCMP_UEQ] = {
267       {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE},
268       {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
269 }
270 
271 void ARMLegalizerInfo::setFCmpLibcallsGNU() {
272   // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
273   // default-initialized.
274   FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
275   FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}};
276   FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}};
277   FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}};
278   FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}};
279   FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
280   FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
281   FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}};
282   FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}};
283   FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}};
284   FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}};
285   FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}};
286   FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}};
287   FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT},
288                                        {RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
289   FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ},
290                                        {RTLIB::UO_F32, CmpInst::ICMP_NE}};
291 
292   FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
293   FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}};
294   FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}};
295   FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}};
296   FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}};
297   FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
298   FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
299   FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}};
300   FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}};
301   FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}};
302   FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}};
303   FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}};
304   FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}};
305   FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT},
306                                        {RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
307   FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ},
308                                        {RTLIB::UO_F64, CmpInst::ICMP_NE}};
309 }
310 
311 ARMLegalizerInfo::FCmpLibcallsList
312 ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate,
313                                   unsigned Size) const {
314   assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate");
315   if (Size == 32)
316     return FCmp32Libcalls[Predicate];
317   if (Size == 64)
318     return FCmp64Libcalls[Predicate];
319   llvm_unreachable("Unsupported size for FCmp predicate");
320 }
321 
322 bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI,
323                                       MachineRegisterInfo &MRI,
324                                       MachineIRBuilder &MIRBuilder) const {
325   using namespace TargetOpcode;
326 
327   MIRBuilder.setInstr(MI);
328   LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
329 
330   switch (MI.getOpcode()) {
331   default:
332     return false;
333   case G_SREM:
334   case G_UREM: {
335     unsigned OriginalResult = MI.getOperand(0).getReg();
336     auto Size = MRI.getType(OriginalResult).getSizeInBits();
337     if (Size != 32)
338       return false;
339 
340     auto Libcall =
341         MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
342 
343     // Our divmod libcalls return a struct containing the quotient and the
344     // remainder. We need to create a virtual register for it.
345     Type *ArgTy = Type::getInt32Ty(Ctx);
346     StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true);
347     auto RetVal = MRI.createGenericVirtualRegister(
348         getLLTForType(*RetTy, MIRBuilder.getMF().getDataLayout()));
349 
350     auto Status = createLibcall(MIRBuilder, Libcall, {RetVal, RetTy},
351                                 {{MI.getOperand(1).getReg(), ArgTy},
352                                  {MI.getOperand(2).getReg(), ArgTy}});
353     if (Status != LegalizerHelper::Legalized)
354       return false;
355 
356     // The remainder is the second result of divmod. Split the return value into
357     // a new, unused register for the quotient and the destination of the
358     // original instruction for the remainder.
359     MIRBuilder.buildUnmerge(
360         {MRI.createGenericVirtualRegister(LLT::scalar(32)), OriginalResult},
361         RetVal);
362     break;
363   }
364   case G_FCMP: {
365     assert(MRI.getType(MI.getOperand(2).getReg()) ==
366                MRI.getType(MI.getOperand(3).getReg()) &&
367            "Mismatched operands for G_FCMP");
368     auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
369 
370     auto OriginalResult = MI.getOperand(0).getReg();
371     auto Predicate =
372         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
373     auto Libcalls = getFCmpLibcalls(Predicate, OpSize);
374 
375     if (Libcalls.empty()) {
376       assert((Predicate == CmpInst::FCMP_TRUE ||
377               Predicate == CmpInst::FCMP_FALSE) &&
378              "Predicate needs libcalls, but none specified");
379       MIRBuilder.buildConstant(OriginalResult,
380                                Predicate == CmpInst::FCMP_TRUE ? 1 : 0);
381       MI.eraseFromParent();
382       return true;
383     }
384 
385     assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size");
386     auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx);
387     auto *RetTy = Type::getInt32Ty(Ctx);
388 
389     SmallVector<unsigned, 2> Results;
390     for (auto Libcall : Libcalls) {
391       auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32));
392       auto Status =
393           createLibcall(MIRBuilder, Libcall.LibcallID, {LibcallResult, RetTy},
394                         {{MI.getOperand(2).getReg(), ArgTy},
395                          {MI.getOperand(3).getReg(), ArgTy}});
396 
397       if (Status != LegalizerHelper::Legalized)
398         return false;
399 
400       auto ProcessedResult =
401           Libcalls.size() == 1
402               ? OriginalResult
403               : MRI.createGenericVirtualRegister(MRI.getType(OriginalResult));
404 
405       // We have a result, but we need to transform it into a proper 1-bit 0 or
406       // 1, taking into account the different peculiarities of the values
407       // returned by the comparison functions.
408       CmpInst::Predicate ResultPred = Libcall.Predicate;
409       if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) {
410         // We have a nice 0 or 1, and we just need to truncate it back to 1 bit
411         // to keep the types consistent.
412         MIRBuilder.buildTrunc(ProcessedResult, LibcallResult);
413       } else {
414         // We need to compare against 0.
415         assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate");
416         auto Zero = MRI.createGenericVirtualRegister(LLT::scalar(32));
417         MIRBuilder.buildConstant(Zero, 0);
418         MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero);
419       }
420       Results.push_back(ProcessedResult);
421     }
422 
423     if (Results.size() != 1) {
424       assert(Results.size() == 2 && "Unexpected number of results");
425       MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]);
426     }
427     break;
428   }
429   case G_FCONSTANT: {
430     // Convert to integer constants, while preserving the binary representation.
431     auto AsInteger =
432         MI.getOperand(1).getFPImm()->getValueAPF().bitcastToAPInt();
433     MIRBuilder.buildConstant(MI.getOperand(0).getReg(),
434                              *ConstantInt::get(Ctx, AsInteger));
435     break;
436   }
437   }
438 
439   MI.eraseFromParent();
440   return true;
441 }
442