1 //===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the targeting of the Machinelegalizer class for ARM.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMLegalizerInfo.h"
15 #include "ARMCallLowering.h"
16 #include "ARMSubtarget.h"
17 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
18 #include "llvm/CodeGen/LowLevelType.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetOpcodes.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/IR/DerivedTypes.h"
23 #include "llvm/IR/Type.h"
24 
25 using namespace llvm;
26 using namespace LegalizeActions;
27 
28 /// FIXME: The following static functions are SizeChangeStrategy functions
29 /// that are meant to temporarily mimic the behaviour of the old legalization
30 /// based on doubling/halving non-legal types as closely as possible. This is
31 /// not entirly possible as only legalizing the types that are exactly a power
32 /// of 2 times the size of the legal types would require specifying all those
33 /// sizes explicitly.
34 /// In practice, not specifying those isn't a problem, and the below functions
35 /// should disappear quickly as we add support for legalizing non-power-of-2
36 /// sized types further.
37 static void
38 addAndInterleaveWithUnsupported(LegalizerInfo::SizeAndActionsVec &result,
39                                 const LegalizerInfo::SizeAndActionsVec &v) {
40   for (unsigned i = 0; i < v.size(); ++i) {
41     result.push_back(v[i]);
42     if (i + 1 < v[i].first && i + 1 < v.size() &&
43         v[i + 1].first != v[i].first + 1)
44       result.push_back({v[i].first + 1, Unsupported});
45   }
46 }
47 
48 static LegalizerInfo::SizeAndActionsVec
49 widen_8_16(const LegalizerInfo::SizeAndActionsVec &v) {
50   assert(v.size() >= 1);
51   assert(v[0].first > 17);
52   LegalizerInfo::SizeAndActionsVec result = {{1, Unsupported},
53                                              {8, WidenScalar},
54                                              {9, Unsupported},
55                                              {16, WidenScalar},
56                                              {17, Unsupported}};
57   addAndInterleaveWithUnsupported(result, v);
58   auto Largest = result.back().first;
59   result.push_back({Largest + 1, Unsupported});
60   return result;
61 }
62 
63 static bool AEABI(const ARMSubtarget &ST) {
64   return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI();
65 }
66 
67 ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
68   using namespace TargetOpcode;
69 
70   const LLT p0 = LLT::pointer(0, 32);
71 
72   const LLT s1 = LLT::scalar(1);
73   const LLT s8 = LLT::scalar(8);
74   const LLT s16 = LLT::scalar(16);
75   const LLT s32 = LLT::scalar(32);
76   const LLT s64 = LLT::scalar(64);
77 
78   getActionDefinitionsBuilder(G_GLOBAL_VALUE).legalFor({p0});
79   getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0});
80 
81   getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
82       .legalFor({s32})
83       .minScalar(0, s32);
84 
85   if (ST.hasDivideInARMMode())
86     getActionDefinitionsBuilder({G_SDIV, G_UDIV})
87         .legalFor({s32})
88         .clampScalar(0, s32, s32);
89   else
90     getActionDefinitionsBuilder({G_SDIV, G_UDIV})
91         .libcallFor({s32})
92         .clampScalar(0, s32, s32);
93 
94   for (unsigned Op : {G_SREM, G_UREM}) {
95     setLegalizeScalarToDifferentSizeStrategy(Op, 0, widen_8_16);
96     if (ST.hasDivideInARMMode())
97       setAction({Op, s32}, Lower);
98     else if (AEABI(ST))
99       setAction({Op, s32}, Custom);
100     else
101       setAction({Op, s32}, Libcall);
102   }
103 
104   getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
105       .legalForCartesianProduct({s32}, {s1, s8, s16});
106 
107   getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}});
108   getActionDefinitionsBuilder(G_PTRTOINT).legalFor({{s32, p0}});
109 
110   getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL}).legalFor({s32});
111 
112   if (ST.hasV5TOps()) {
113     getActionDefinitionsBuilder(G_CTLZ)
114         .legalFor({s32})
115         .clampScalar(0, s32, s32);
116     getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
117         .lowerFor({s32})
118         .clampScalar(0, s32, s32);
119   } else {
120     getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
121         .libcallFor({s32})
122         .clampScalar(0, s32, s32);
123     getActionDefinitionsBuilder(G_CTLZ)
124         .lowerFor({s32})
125         .clampScalar(0, s32, s32);
126   }
127 
128   getActionDefinitionsBuilder(G_GEP).legalFor({{p0, s32}});
129 
130   getActionDefinitionsBuilder(G_SELECT).legalForCartesianProduct({s32, p0},
131                                                                  {s1});
132 
133   getActionDefinitionsBuilder(G_BRCOND).legalFor({s1});
134 
135   getActionDefinitionsBuilder(G_CONSTANT)
136       .legalFor({s32, p0})
137       .clampScalar(0, s32, s32);
138 
139   getActionDefinitionsBuilder(G_ICMP)
140       .legalForCartesianProduct({s1}, {s32, p0})
141       .minScalar(1, s32);
142 
143   // We're keeping these builders around because we'll want to add support for
144   // floating point to them.
145   auto &LoadStoreBuilder =
146       getActionDefinitionsBuilder({G_LOAD, G_STORE})
147           .legalForCartesianProduct({s1, s8, s16, s32, p0}, {p0});
148 
149   auto &PhiBuilder =
150       getActionDefinitionsBuilder(G_PHI).legalFor({s32, p0}).minScalar(0, s32);
151 
152   if (!ST.useSoftFloat() && ST.hasVFP2()) {
153     getActionDefinitionsBuilder(
154         {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG})
155         .legalFor({s32, s64});
156 
157     LoadStoreBuilder.legalFor({{s64, p0}});
158     PhiBuilder.legalFor({s64});
159 
160     getActionDefinitionsBuilder(G_FCMP).legalForCartesianProduct({s1},
161                                                                  {s32, s64});
162 
163     getActionDefinitionsBuilder(G_MERGE_VALUES).legalFor({{s64, s32}});
164     getActionDefinitionsBuilder(G_UNMERGE_VALUES).legalFor({{s32, s64}});
165 
166     getActionDefinitionsBuilder(G_FPEXT).legalFor({{s64, s32}});
167     getActionDefinitionsBuilder(G_FPTRUNC).legalFor({{s32, s64}});
168 
169     getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
170         .legalForCartesianProduct({s32}, {s32, s64});
171     getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
172         .legalForCartesianProduct({s32, s64}, {s32});
173   } else {
174     getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV})
175         .libcallFor({s32, s64});
176 
177     LoadStoreBuilder.maxScalar(0, s32);
178 
179     for (auto Ty : {s32, s64})
180       setAction({G_FNEG, Ty}, Lower);
181 
182     getActionDefinitionsBuilder(G_FCONSTANT).customFor({s32, s64});
183 
184     getActionDefinitionsBuilder(G_FCMP).customForCartesianProduct({s1},
185                                                                   {s32, s64});
186 
187     if (AEABI(ST))
188       setFCmpLibcallsAEABI();
189     else
190       setFCmpLibcallsGNU();
191 
192     getActionDefinitionsBuilder(G_FPEXT).libcallFor({{s64, s32}});
193     getActionDefinitionsBuilder(G_FPTRUNC).libcallFor({{s32, s64}});
194 
195     getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
196         .libcallForCartesianProduct({s32}, {s32, s64});
197     getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
198         .libcallForCartesianProduct({s32, s64}, {s32});
199   }
200 
201   if (!ST.useSoftFloat() && ST.hasVFP4())
202     getActionDefinitionsBuilder(G_FMA).legalFor({s32, s64});
203   else
204     getActionDefinitionsBuilder(G_FMA).libcallFor({s32, s64});
205 
206   getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64});
207 
208   computeTables();
209   verify(*ST.getInstrInfo());
210 }
211 
212 void ARMLegalizerInfo::setFCmpLibcallsAEABI() {
213   // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
214   // default-initialized.
215   FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
216   FCmp32Libcalls[CmpInst::FCMP_OEQ] = {
217       {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}};
218   FCmp32Libcalls[CmpInst::FCMP_OGE] = {
219       {RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}};
220   FCmp32Libcalls[CmpInst::FCMP_OGT] = {
221       {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}};
222   FCmp32Libcalls[CmpInst::FCMP_OLE] = {
223       {RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}};
224   FCmp32Libcalls[CmpInst::FCMP_OLT] = {
225       {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
226   FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
227   FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}};
228   FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}};
229   FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}};
230   FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}};
231   FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}};
232   FCmp32Libcalls[CmpInst::FCMP_UNO] = {
233       {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
234   FCmp32Libcalls[CmpInst::FCMP_ONE] = {
235       {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE},
236       {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
237   FCmp32Libcalls[CmpInst::FCMP_UEQ] = {
238       {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE},
239       {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
240 
241   FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
242   FCmp64Libcalls[CmpInst::FCMP_OEQ] = {
243       {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}};
244   FCmp64Libcalls[CmpInst::FCMP_OGE] = {
245       {RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}};
246   FCmp64Libcalls[CmpInst::FCMP_OGT] = {
247       {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}};
248   FCmp64Libcalls[CmpInst::FCMP_OLE] = {
249       {RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}};
250   FCmp64Libcalls[CmpInst::FCMP_OLT] = {
251       {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
252   FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
253   FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}};
254   FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}};
255   FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}};
256   FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}};
257   FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}};
258   FCmp64Libcalls[CmpInst::FCMP_UNO] = {
259       {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
260   FCmp64Libcalls[CmpInst::FCMP_ONE] = {
261       {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE},
262       {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
263   FCmp64Libcalls[CmpInst::FCMP_UEQ] = {
264       {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE},
265       {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
266 }
267 
268 void ARMLegalizerInfo::setFCmpLibcallsGNU() {
269   // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
270   // default-initialized.
271   FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
272   FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}};
273   FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}};
274   FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}};
275   FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}};
276   FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
277   FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
278   FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}};
279   FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}};
280   FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}};
281   FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}};
282   FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}};
283   FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}};
284   FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT},
285                                        {RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
286   FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ},
287                                        {RTLIB::UO_F32, CmpInst::ICMP_NE}};
288 
289   FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
290   FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}};
291   FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}};
292   FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}};
293   FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}};
294   FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
295   FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
296   FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}};
297   FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}};
298   FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}};
299   FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}};
300   FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}};
301   FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}};
302   FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT},
303                                        {RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
304   FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ},
305                                        {RTLIB::UO_F64, CmpInst::ICMP_NE}};
306 }
307 
308 ARMLegalizerInfo::FCmpLibcallsList
309 ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate,
310                                   unsigned Size) const {
311   assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate");
312   if (Size == 32)
313     return FCmp32Libcalls[Predicate];
314   if (Size == 64)
315     return FCmp64Libcalls[Predicate];
316   llvm_unreachable("Unsupported size for FCmp predicate");
317 }
318 
319 bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI,
320                                       MachineRegisterInfo &MRI,
321                                       MachineIRBuilder &MIRBuilder) const {
322   using namespace TargetOpcode;
323 
324   MIRBuilder.setInstr(MI);
325   LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
326 
327   switch (MI.getOpcode()) {
328   default:
329     return false;
330   case G_SREM:
331   case G_UREM: {
332     unsigned OriginalResult = MI.getOperand(0).getReg();
333     auto Size = MRI.getType(OriginalResult).getSizeInBits();
334     if (Size != 32)
335       return false;
336 
337     auto Libcall =
338         MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
339 
340     // Our divmod libcalls return a struct containing the quotient and the
341     // remainder. We need to create a virtual register for it.
342     Type *ArgTy = Type::getInt32Ty(Ctx);
343     StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true);
344     auto RetVal = MRI.createGenericVirtualRegister(
345         getLLTForType(*RetTy, MIRBuilder.getMF().getDataLayout()));
346 
347     auto Status = createLibcall(MIRBuilder, Libcall, {RetVal, RetTy},
348                                 {{MI.getOperand(1).getReg(), ArgTy},
349                                  {MI.getOperand(2).getReg(), ArgTy}});
350     if (Status != LegalizerHelper::Legalized)
351       return false;
352 
353     // The remainder is the second result of divmod. Split the return value into
354     // a new, unused register for the quotient and the destination of the
355     // original instruction for the remainder.
356     MIRBuilder.buildUnmerge(
357         {MRI.createGenericVirtualRegister(LLT::scalar(32)), OriginalResult},
358         RetVal);
359     break;
360   }
361   case G_FCMP: {
362     assert(MRI.getType(MI.getOperand(2).getReg()) ==
363                MRI.getType(MI.getOperand(3).getReg()) &&
364            "Mismatched operands for G_FCMP");
365     auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
366 
367     auto OriginalResult = MI.getOperand(0).getReg();
368     auto Predicate =
369         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
370     auto Libcalls = getFCmpLibcalls(Predicate, OpSize);
371 
372     if (Libcalls.empty()) {
373       assert((Predicate == CmpInst::FCMP_TRUE ||
374               Predicate == CmpInst::FCMP_FALSE) &&
375              "Predicate needs libcalls, but none specified");
376       MIRBuilder.buildConstant(OriginalResult,
377                                Predicate == CmpInst::FCMP_TRUE ? 1 : 0);
378       MI.eraseFromParent();
379       return true;
380     }
381 
382     assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size");
383     auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx);
384     auto *RetTy = Type::getInt32Ty(Ctx);
385 
386     SmallVector<unsigned, 2> Results;
387     for (auto Libcall : Libcalls) {
388       auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32));
389       auto Status =
390           createLibcall(MIRBuilder, Libcall.LibcallID, {LibcallResult, RetTy},
391                         {{MI.getOperand(2).getReg(), ArgTy},
392                          {MI.getOperand(3).getReg(), ArgTy}});
393 
394       if (Status != LegalizerHelper::Legalized)
395         return false;
396 
397       auto ProcessedResult =
398           Libcalls.size() == 1
399               ? OriginalResult
400               : MRI.createGenericVirtualRegister(MRI.getType(OriginalResult));
401 
402       // We have a result, but we need to transform it into a proper 1-bit 0 or
403       // 1, taking into account the different peculiarities of the values
404       // returned by the comparison functions.
405       CmpInst::Predicate ResultPred = Libcall.Predicate;
406       if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) {
407         // We have a nice 0 or 1, and we just need to truncate it back to 1 bit
408         // to keep the types consistent.
409         MIRBuilder.buildTrunc(ProcessedResult, LibcallResult);
410       } else {
411         // We need to compare against 0.
412         assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate");
413         auto Zero = MRI.createGenericVirtualRegister(LLT::scalar(32));
414         MIRBuilder.buildConstant(Zero, 0);
415         MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero);
416       }
417       Results.push_back(ProcessedResult);
418     }
419 
420     if (Results.size() != 1) {
421       assert(Results.size() == 2 && "Unexpected number of results");
422       MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]);
423     }
424     break;
425   }
426   case G_FCONSTANT: {
427     // Convert to integer constants, while preserving the binary representation.
428     auto AsInteger =
429         MI.getOperand(1).getFPImm()->getValueAPF().bitcastToAPInt();
430     MIRBuilder.buildConstant(MI.getOperand(0).getReg(),
431                              *ConstantInt::get(Ctx, AsInteger));
432     break;
433   }
434   }
435 
436   MI.eraseFromParent();
437   return true;
438 }
439