1 //===- ARMInstructionSelector.cpp ----------------------------*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the targeting of the InstructionSelector class for ARM.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMInstructionSelector.h"
15 #include "ARMRegisterBankInfo.h"
16 #include "ARMSubtarget.h"
17 #include "ARMTargetMachine.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/Support/Debug.h"
20 
21 #define DEBUG_TYPE "arm-isel"
22 
23 using namespace llvm;
24 
25 #ifndef LLVM_BUILD_GLOBAL_ISEL
26 #error "You shouldn't build this"
27 #endif
28 
29 ARMInstructionSelector::ARMInstructionSelector(const ARMSubtarget &STI,
30                                                const ARMRegisterBankInfo &RBI)
31     : InstructionSelector(), TII(*STI.getInstrInfo()),
32       TRI(*STI.getRegisterInfo()), RBI(RBI) {}
33 
34 static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
35                        MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
36                        const RegisterBankInfo &RBI) {
37   unsigned DstReg = I.getOperand(0).getReg();
38   if (TargetRegisterInfo::isPhysicalRegister(DstReg))
39     return true;
40 
41   const RegisterBank *RegBank = RBI.getRegBank(DstReg, MRI, TRI);
42   (void)RegBank;
43   assert(RegBank && "Can't get reg bank for virtual register");
44 
45   const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
46   (void)DstSize;
47   unsigned SrcReg = I.getOperand(1).getReg();
48   const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
49   (void)SrcSize;
50   assert((DstSize == SrcSize ||
51           // Copies are a means to setup initial types, the number of
52           // bits may not exactly match.
53           (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
54            DstSize <= SrcSize)) &&
55          "Copy with different width?!");
56 
57   assert((RegBank->getID() == ARM::GPRRegBankID ||
58           RegBank->getID() == ARM::FPRRegBankID) &&
59          "Unsupported reg bank");
60 
61   const TargetRegisterClass *RC = &ARM::GPRRegClass;
62 
63   if (RegBank->getID() == ARM::FPRRegBankID) {
64     if (DstSize == 32)
65       RC = &ARM::SPRRegClass;
66     else if (DstSize == 64)
67       RC = &ARM::DPRRegClass;
68     else
69       llvm_unreachable("Unsupported destination size");
70   }
71 
72   // No need to constrain SrcReg. It will get constrained when
73   // we hit another of its uses or its defs.
74   // Copies do not have constraints.
75   if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
76     DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
77                  << " operand\n");
78     return false;
79   }
80   return true;
81 }
82 
83 static bool selectFAdd(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII,
84                        MachineRegisterInfo &MRI) {
85   assert(TII.getSubtarget().hasVFP2() && "Can't select fp add without vfp");
86 
87   LLT Ty = MRI.getType(MIB->getOperand(0).getReg());
88   unsigned ValSize = Ty.getSizeInBits();
89 
90   if (ValSize == 32) {
91     if (TII.getSubtarget().useNEONForSinglePrecisionFP())
92       return false;
93     MIB->setDesc(TII.get(ARM::VADDS));
94   } else {
95     assert(ValSize == 64 && "Unsupported size for floating point value");
96     if (TII.getSubtarget().isFPOnlySP())
97       return false;
98     MIB->setDesc(TII.get(ARM::VADDD));
99   }
100   MIB.add(predOps(ARMCC::AL));
101 
102   return true;
103 }
104 
105 static bool selectSequence(MachineInstrBuilder &MIB,
106                            const ARMBaseInstrInfo &TII,
107                            MachineRegisterInfo &MRI,
108                            const TargetRegisterInfo &TRI,
109                            const RegisterBankInfo &RBI) {
110   assert(TII.getSubtarget().hasVFP2() && "Can't select sequence without VFP");
111 
112   // We only support G_SEQUENCE as a way to stick together two scalar GPRs
113   // into one DPR.
114   unsigned VReg0 = MIB->getOperand(0).getReg();
115   (void)VReg0;
116   assert(MRI.getType(VReg0).getSizeInBits() == 64 &&
117          RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID &&
118          "Unsupported operand for G_SEQUENCE");
119   unsigned VReg1 = MIB->getOperand(1).getReg();
120   (void)VReg1;
121   assert(MRI.getType(VReg1).getSizeInBits() == 32 &&
122          RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
123          "Unsupported operand for G_SEQUENCE");
124   unsigned VReg2 = MIB->getOperand(3).getReg();
125   (void)VReg2;
126   assert(MRI.getType(VReg2).getSizeInBits() == 32 &&
127          RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID &&
128          "Unsupported operand for G_SEQUENCE");
129 
130   // Remove the operands corresponding to the offsets.
131   MIB->RemoveOperand(4);
132   MIB->RemoveOperand(2);
133 
134   MIB->setDesc(TII.get(ARM::VMOVDRR));
135   MIB.add(predOps(ARMCC::AL));
136 
137   return true;
138 }
139 
140 static bool selectExtract(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII,
141                           MachineRegisterInfo &MRI,
142                           const TargetRegisterInfo &TRI,
143                           const RegisterBankInfo &RBI) {
144   assert(TII.getSubtarget().hasVFP2() && "Can't select extract without VFP");
145 
146   // We only support G_EXTRACT as a way to break up one DPR into two GPRs.
147   unsigned VReg0 = MIB->getOperand(0).getReg();
148   (void)VReg0;
149   assert(MRI.getType(VReg0).getSizeInBits() == 32 &&
150          RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID &&
151          "Unsupported operand for G_SEQUENCE");
152   unsigned VReg1 = MIB->getOperand(1).getReg();
153   (void)VReg1;
154   assert(MRI.getType(VReg1).getSizeInBits() == 32 &&
155          RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
156          "Unsupported operand for G_SEQUENCE");
157   unsigned VReg2 = MIB->getOperand(2).getReg();
158   (void)VReg2;
159   assert(MRI.getType(VReg2).getSizeInBits() == 64 &&
160          RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID &&
161          "Unsupported operand for G_SEQUENCE");
162 
163   // Remove the operands corresponding to the offsets.
164   MIB->RemoveOperand(4);
165   MIB->RemoveOperand(3);
166 
167   MIB->setDesc(TII.get(ARM::VMOVRRD));
168   MIB.add(predOps(ARMCC::AL));
169 
170   return true;
171 }
172 
173 /// Select the opcode for simple extensions (that translate to a single SXT/UXT
174 /// instruction). Extension operations more complicated than that should not
175 /// invoke this. Returns the original opcode if it doesn't know how to select a
176 /// better one.
177 static unsigned selectSimpleExtOpc(unsigned Opc, unsigned Size) {
178   using namespace TargetOpcode;
179 
180   if (Size != 8 && Size != 16)
181     return Opc;
182 
183   if (Opc == G_SEXT)
184     return Size == 8 ? ARM::SXTB : ARM::SXTH;
185 
186   if (Opc == G_ZEXT)
187     return Size == 8 ? ARM::UXTB : ARM::UXTH;
188 
189   return Opc;
190 }
191 
192 /// Select the opcode for simple loads. For types smaller than 32 bits, the
193 /// value will be zero extended. Returns G_LOAD if it doesn't know how to select
194 /// an opcode.
195 static unsigned selectLoadOpCode(unsigned RegBank, unsigned Size) {
196   if (RegBank == ARM::GPRRegBankID) {
197     switch (Size) {
198     case 1:
199     case 8:
200       return ARM::LDRBi12;
201     case 16:
202       return ARM::LDRH;
203     case 32:
204       return ARM::LDRi12;
205     default:
206       return TargetOpcode::G_LOAD;
207     }
208   }
209 
210   if (RegBank == ARM::FPRRegBankID) {
211     switch (Size) {
212     case 32:
213       return ARM::VLDRS;
214     case 64:
215       return ARM::VLDRD;
216     default:
217       return TargetOpcode::G_LOAD;
218     }
219   }
220 
221   return TargetOpcode::G_LOAD;
222 }
223 
224 bool ARMInstructionSelector::select(MachineInstr &I) const {
225   assert(I.getParent() && "Instruction should be in a basic block!");
226   assert(I.getParent()->getParent() && "Instruction should be in a function!");
227 
228   auto &MBB = *I.getParent();
229   auto &MF = *MBB.getParent();
230   auto &MRI = MF.getRegInfo();
231 
232   if (!isPreISelGenericOpcode(I.getOpcode())) {
233     if (I.isCopy())
234       return selectCopy(I, TII, MRI, TRI, RBI);
235 
236     return true;
237   }
238 
239   MachineInstrBuilder MIB{MF, I};
240   bool isSExt = false;
241 
242   using namespace TargetOpcode;
243   switch (I.getOpcode()) {
244   case G_SEXT:
245     isSExt = true;
246     LLVM_FALLTHROUGH;
247   case G_ZEXT: {
248     LLT DstTy = MRI.getType(I.getOperand(0).getReg());
249     // FIXME: Smaller destination sizes coming soon!
250     if (DstTy.getSizeInBits() != 32) {
251       DEBUG(dbgs() << "Unsupported destination size for extension");
252       return false;
253     }
254 
255     LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
256     unsigned SrcSize = SrcTy.getSizeInBits();
257     switch (SrcSize) {
258     case 1: {
259       // ZExt boils down to & 0x1; for SExt we also subtract that from 0
260       I.setDesc(TII.get(ARM::ANDri));
261       MIB.addImm(1).add(predOps(ARMCC::AL)).add(condCodeOp());
262 
263       if (isSExt) {
264         unsigned SExtResult = I.getOperand(0).getReg();
265 
266         // Use a new virtual register for the result of the AND
267         unsigned AndResult = MRI.createVirtualRegister(&ARM::GPRRegClass);
268         I.getOperand(0).setReg(AndResult);
269 
270         auto InsertBefore = std::next(I.getIterator());
271         auto SubI =
272             BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(ARM::RSBri))
273                 .addDef(SExtResult)
274                 .addUse(AndResult)
275                 .addImm(0)
276                 .add(predOps(ARMCC::AL))
277                 .add(condCodeOp());
278         if (!constrainSelectedInstRegOperands(*SubI, TII, TRI, RBI))
279           return false;
280       }
281       break;
282     }
283     case 8:
284     case 16: {
285       unsigned NewOpc = selectSimpleExtOpc(I.getOpcode(), SrcSize);
286       if (NewOpc == I.getOpcode())
287         return false;
288       I.setDesc(TII.get(NewOpc));
289       MIB.addImm(0).add(predOps(ARMCC::AL));
290       break;
291     }
292     default:
293       DEBUG(dbgs() << "Unsupported source size for extension");
294       return false;
295     }
296     break;
297   }
298   case G_ADD:
299     I.setDesc(TII.get(ARM::ADDrr));
300     MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
301     break;
302   case G_FADD:
303     if (!selectFAdd(MIB, TII, MRI))
304       return false;
305     break;
306   case G_FRAME_INDEX:
307     // Add 0 to the given frame index and hope it will eventually be folded into
308     // the user(s).
309     I.setDesc(TII.get(ARM::ADDri));
310     MIB.addImm(0).add(predOps(ARMCC::AL)).add(condCodeOp());
311     break;
312   case G_LOAD: {
313     const auto &MemOp = **I.memoperands_begin();
314     if (MemOp.getOrdering() != AtomicOrdering::NotAtomic) {
315       DEBUG(dbgs() << "Atomic load/store not supported yet\n");
316       return false;
317     }
318 
319     unsigned Reg = I.getOperand(0).getReg();
320     unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID();
321 
322     LLT ValTy = MRI.getType(Reg);
323     const auto ValSize = ValTy.getSizeInBits();
324 
325     assert((ValSize != 64 || TII.getSubtarget().hasVFP2()) &&
326            "Don't know how to load 64-bit value without VFP");
327 
328     const auto NewOpc = selectLoadOpCode(RegBank, ValSize);
329     if (NewOpc == G_LOAD)
330       return false;
331 
332     I.setDesc(TII.get(NewOpc));
333 
334     if (NewOpc == ARM::LDRH)
335       // LDRH has a funny addressing mode (there's already a FIXME for it).
336       MIB.addReg(0);
337     MIB.addImm(0).add(predOps(ARMCC::AL));
338     break;
339   }
340   case G_SEQUENCE: {
341     if (!selectSequence(MIB, TII, MRI, TRI, RBI))
342       return false;
343     break;
344   }
345   case G_EXTRACT: {
346     if (!selectExtract(MIB, TII, MRI, TRI, RBI))
347       return false;
348     break;
349   }
350   default:
351     return false;
352   }
353 
354   return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
355 }
356