1 //===- ARMInstructionSelector.cpp ----------------------------*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the targeting of the InstructionSelector class for ARM.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMRegisterBankInfo.h"
15 #include "ARMSubtarget.h"
16 #include "ARMTargetMachine.h"
17 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/Support/Debug.h"
20 
21 #define DEBUG_TYPE "arm-isel"
22 
23 using namespace llvm;
24 
25 #ifndef LLVM_BUILD_GLOBAL_ISEL
26 #error "You shouldn't build this"
27 #endif
28 
29 namespace {
30 
31 #define GET_GLOBALISEL_PREDICATE_BITSET
32 #include "ARMGenGlobalISel.inc"
33 #undef GET_GLOBALISEL_PREDICATE_BITSET
34 
35 class ARMInstructionSelector : public InstructionSelector {
36 public:
37   ARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI,
38                          const ARMRegisterBankInfo &RBI);
39 
40   bool select(MachineInstr &I) const override;
41 
42 private:
43   bool selectImpl(MachineInstr &I) const;
44 
45   const ARMBaseInstrInfo &TII;
46   const ARMBaseRegisterInfo &TRI;
47   const ARMBaseTargetMachine &TM;
48   const ARMRegisterBankInfo &RBI;
49   const ARMSubtarget &STI;
50 
51 #define GET_GLOBALISEL_PREDICATES_DECL
52 #include "ARMGenGlobalISel.inc"
53 #undef GET_GLOBALISEL_PREDICATES_DECL
54 
55 // We declare the temporaries used by selectImpl() in the class to minimize the
56 // cost of constructing placeholder values.
57 #define GET_GLOBALISEL_TEMPORARIES_DECL
58 #include "ARMGenGlobalISel.inc"
59 #undef GET_GLOBALISEL_TEMPORARIES_DECL
60 };
61 } // end anonymous namespace
62 
63 namespace llvm {
64 InstructionSelector *
65 createARMInstructionSelector(const ARMBaseTargetMachine &TM,
66                              const ARMSubtarget &STI,
67                              const ARMRegisterBankInfo &RBI) {
68   return new ARMInstructionSelector(TM, STI, RBI);
69 }
70 }
71 
72 unsigned zero_reg = 0;
73 
74 #define GET_GLOBALISEL_IMPL
75 #include "ARMGenGlobalISel.inc"
76 #undef GET_GLOBALISEL_IMPL
77 
78 ARMInstructionSelector::ARMInstructionSelector(const ARMBaseTargetMachine &TM,
79                                                const ARMSubtarget &STI,
80                                                const ARMRegisterBankInfo &RBI)
81     : InstructionSelector(), TII(*STI.getInstrInfo()),
82       TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI),
83 #define GET_GLOBALISEL_PREDICATES_INIT
84 #include "ARMGenGlobalISel.inc"
85 #undef GET_GLOBALISEL_PREDICATES_INIT
86 #define GET_GLOBALISEL_TEMPORARIES_INIT
87 #include "ARMGenGlobalISel.inc"
88 #undef GET_GLOBALISEL_TEMPORARIES_INIT
89 {
90 }
91 
92 static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
93                        MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
94                        const RegisterBankInfo &RBI) {
95   unsigned DstReg = I.getOperand(0).getReg();
96   if (TargetRegisterInfo::isPhysicalRegister(DstReg))
97     return true;
98 
99   const RegisterBank *RegBank = RBI.getRegBank(DstReg, MRI, TRI);
100   (void)RegBank;
101   assert(RegBank && "Can't get reg bank for virtual register");
102 
103   const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
104   assert((RegBank->getID() == ARM::GPRRegBankID ||
105           RegBank->getID() == ARM::FPRRegBankID) &&
106          "Unsupported reg bank");
107 
108   const TargetRegisterClass *RC = &ARM::GPRRegClass;
109 
110   if (RegBank->getID() == ARM::FPRRegBankID) {
111     if (DstSize == 32)
112       RC = &ARM::SPRRegClass;
113     else if (DstSize == 64)
114       RC = &ARM::DPRRegClass;
115     else
116       llvm_unreachable("Unsupported destination size");
117   }
118 
119   // No need to constrain SrcReg. It will get constrained when
120   // we hit another of its uses or its defs.
121   // Copies do not have constraints.
122   if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
123     DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
124                  << " operand\n");
125     return false;
126   }
127   return true;
128 }
129 
130 static bool selectSequence(MachineInstrBuilder &MIB,
131                            const ARMBaseInstrInfo &TII,
132                            MachineRegisterInfo &MRI,
133                            const TargetRegisterInfo &TRI,
134                            const RegisterBankInfo &RBI) {
135   assert(TII.getSubtarget().hasVFP2() && "Can't select sequence without VFP");
136 
137   // We only support G_SEQUENCE as a way to stick together two scalar GPRs
138   // into one DPR.
139   unsigned VReg0 = MIB->getOperand(0).getReg();
140   (void)VReg0;
141   assert(MRI.getType(VReg0).getSizeInBits() == 64 &&
142          RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID &&
143          "Unsupported operand for G_SEQUENCE");
144   unsigned VReg1 = MIB->getOperand(1).getReg();
145   (void)VReg1;
146   assert(MRI.getType(VReg1).getSizeInBits() == 32 &&
147          RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
148          "Unsupported operand for G_SEQUENCE");
149   unsigned VReg2 = MIB->getOperand(3).getReg();
150   (void)VReg2;
151   assert(MRI.getType(VReg2).getSizeInBits() == 32 &&
152          RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID &&
153          "Unsupported operand for G_SEQUENCE");
154 
155   // Remove the operands corresponding to the offsets.
156   MIB->RemoveOperand(4);
157   MIB->RemoveOperand(2);
158 
159   MIB->setDesc(TII.get(ARM::VMOVDRR));
160   MIB.add(predOps(ARMCC::AL));
161 
162   return true;
163 }
164 
165 static bool selectExtract(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII,
166                           MachineRegisterInfo &MRI,
167                           const TargetRegisterInfo &TRI,
168                           const RegisterBankInfo &RBI) {
169   assert(TII.getSubtarget().hasVFP2() && "Can't select extract without VFP");
170 
171   // We only support G_EXTRACT as a way to break up one DPR into two GPRs.
172   unsigned VReg0 = MIB->getOperand(0).getReg();
173   (void)VReg0;
174   assert(MRI.getType(VReg0).getSizeInBits() == 32 &&
175          RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID &&
176          "Unsupported operand for G_EXTRACT");
177   unsigned VReg1 = MIB->getOperand(1).getReg();
178   (void)VReg1;
179   assert(MRI.getType(VReg1).getSizeInBits() == 64 &&
180          RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::FPRRegBankID &&
181          "Unsupported operand for G_EXTRACT");
182   assert(MIB->getOperand(2).getImm() % 32 == 0 &&
183          "Unsupported operand for G_EXTRACT");
184 
185   // Remove the operands corresponding to the offsets.
186   MIB->getOperand(2).setImm(MIB->getOperand(2).getImm() / 32);
187 
188   MIB->setDesc(TII.get(ARM::VGETLNi32));
189   MIB.add(predOps(ARMCC::AL));
190 
191   return true;
192 }
193 
194 /// Select the opcode for simple extensions (that translate to a single SXT/UXT
195 /// instruction). Extension operations more complicated than that should not
196 /// invoke this. Returns the original opcode if it doesn't know how to select a
197 /// better one.
198 static unsigned selectSimpleExtOpc(unsigned Opc, unsigned Size) {
199   using namespace TargetOpcode;
200 
201   if (Size != 8 && Size != 16)
202     return Opc;
203 
204   if (Opc == G_SEXT)
205     return Size == 8 ? ARM::SXTB : ARM::SXTH;
206 
207   if (Opc == G_ZEXT)
208     return Size == 8 ? ARM::UXTB : ARM::UXTH;
209 
210   return Opc;
211 }
212 
213 /// Select the opcode for simple loads and stores. For types smaller than 32
214 /// bits, the value will be zero extended. Returns the original opcode if it
215 /// doesn't know how to select a better one.
216 static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank,
217                                       unsigned Size) {
218   bool isStore = Opc == TargetOpcode::G_STORE;
219 
220   if (RegBank == ARM::GPRRegBankID) {
221     switch (Size) {
222     case 1:
223     case 8:
224       return isStore ? ARM::STRBi12 : ARM::LDRBi12;
225     case 16:
226       return isStore ? ARM::STRH : ARM::LDRH;
227     case 32:
228       return isStore ? ARM::STRi12 : ARM::LDRi12;
229     default:
230       return Opc;
231     }
232   }
233 
234   if (RegBank == ARM::FPRRegBankID) {
235     switch (Size) {
236     case 32:
237       return isStore ? ARM::VSTRS : ARM::VLDRS;
238     case 64:
239       return isStore ? ARM::VSTRD : ARM::VLDRD;
240     default:
241       return Opc;
242     }
243   }
244 
245   return Opc;
246 }
247 
248 bool ARMInstructionSelector::select(MachineInstr &I) const {
249   assert(I.getParent() && "Instruction should be in a basic block!");
250   assert(I.getParent()->getParent() && "Instruction should be in a function!");
251 
252   auto &MBB = *I.getParent();
253   auto &MF = *MBB.getParent();
254   auto &MRI = MF.getRegInfo();
255 
256   if (!isPreISelGenericOpcode(I.getOpcode())) {
257     if (I.isCopy())
258       return selectCopy(I, TII, MRI, TRI, RBI);
259 
260     return true;
261   }
262 
263   if (selectImpl(I))
264     return true;
265 
266   MachineInstrBuilder MIB{MF, I};
267   bool isSExt = false;
268 
269   using namespace TargetOpcode;
270   switch (I.getOpcode()) {
271   case G_SEXT:
272     isSExt = true;
273     LLVM_FALLTHROUGH;
274   case G_ZEXT: {
275     LLT DstTy = MRI.getType(I.getOperand(0).getReg());
276     // FIXME: Smaller destination sizes coming soon!
277     if (DstTy.getSizeInBits() != 32) {
278       DEBUG(dbgs() << "Unsupported destination size for extension");
279       return false;
280     }
281 
282     LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
283     unsigned SrcSize = SrcTy.getSizeInBits();
284     switch (SrcSize) {
285     case 1: {
286       // ZExt boils down to & 0x1; for SExt we also subtract that from 0
287       I.setDesc(TII.get(ARM::ANDri));
288       MIB.addImm(1).add(predOps(ARMCC::AL)).add(condCodeOp());
289 
290       if (isSExt) {
291         unsigned SExtResult = I.getOperand(0).getReg();
292 
293         // Use a new virtual register for the result of the AND
294         unsigned AndResult = MRI.createVirtualRegister(&ARM::GPRRegClass);
295         I.getOperand(0).setReg(AndResult);
296 
297         auto InsertBefore = std::next(I.getIterator());
298         auto SubI =
299             BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(ARM::RSBri))
300                 .addDef(SExtResult)
301                 .addUse(AndResult)
302                 .addImm(0)
303                 .add(predOps(ARMCC::AL))
304                 .add(condCodeOp());
305         if (!constrainSelectedInstRegOperands(*SubI, TII, TRI, RBI))
306           return false;
307       }
308       break;
309     }
310     case 8:
311     case 16: {
312       unsigned NewOpc = selectSimpleExtOpc(I.getOpcode(), SrcSize);
313       if (NewOpc == I.getOpcode())
314         return false;
315       I.setDesc(TII.get(NewOpc));
316       MIB.addImm(0).add(predOps(ARMCC::AL));
317       break;
318     }
319     default:
320       DEBUG(dbgs() << "Unsupported source size for extension");
321       return false;
322     }
323     break;
324   }
325   case G_ANYEXT:
326   case G_TRUNC: {
327     // The high bits are undefined, so there's nothing special to do, just
328     // treat it as a copy.
329     auto SrcReg = I.getOperand(1).getReg();
330     auto DstReg = I.getOperand(0).getReg();
331 
332     const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
333     const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
334 
335     if (SrcRegBank.getID() != DstRegBank.getID()) {
336       DEBUG(dbgs() << "G_TRUNC/G_ANYEXT operands on different register banks\n");
337       return false;
338     }
339 
340     if (SrcRegBank.getID() != ARM::GPRRegBankID) {
341       DEBUG(dbgs() << "G_TRUNC/G_ANYEXT on non-GPR not supported yet\n");
342       return false;
343     }
344 
345     I.setDesc(TII.get(COPY));
346     return selectCopy(I, TII, MRI, TRI, RBI);
347   }
348   case G_GEP:
349     I.setDesc(TII.get(ARM::ADDrr));
350     MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
351     break;
352   case G_FRAME_INDEX:
353     // Add 0 to the given frame index and hope it will eventually be folded into
354     // the user(s).
355     I.setDesc(TII.get(ARM::ADDri));
356     MIB.addImm(0).add(predOps(ARMCC::AL)).add(condCodeOp());
357     break;
358   case G_CONSTANT: {
359     unsigned Reg = I.getOperand(0).getReg();
360     if (MRI.getType(Reg).getSizeInBits() != 32)
361       return false;
362 
363     assert(RBI.getRegBank(Reg, MRI, TRI)->getID() == ARM::GPRRegBankID &&
364            "Expected constant to live in a GPR");
365     I.setDesc(TII.get(ARM::MOVi));
366     MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
367 
368     auto &Val = I.getOperand(1);
369     if (Val.isCImm()) {
370       if (Val.getCImm()->getBitWidth() > 32)
371         return false;
372       Val.ChangeToImmediate(Val.getCImm()->getZExtValue());
373     }
374 
375     if (!Val.isImm()) {
376       return false;
377     }
378 
379     break;
380   }
381   case G_STORE:
382   case G_LOAD: {
383     const auto &MemOp = **I.memoperands_begin();
384     if (MemOp.getOrdering() != AtomicOrdering::NotAtomic) {
385       DEBUG(dbgs() << "Atomic load/store not supported yet\n");
386       return false;
387     }
388 
389     unsigned Reg = I.getOperand(0).getReg();
390     unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID();
391 
392     LLT ValTy = MRI.getType(Reg);
393     const auto ValSize = ValTy.getSizeInBits();
394 
395     assert((ValSize != 64 || TII.getSubtarget().hasVFP2()) &&
396            "Don't know how to load/store 64-bit value without VFP");
397 
398     const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize);
399     if (NewOpc == G_LOAD || NewOpc == G_STORE)
400       return false;
401 
402     I.setDesc(TII.get(NewOpc));
403 
404     if (NewOpc == ARM::LDRH || NewOpc == ARM::STRH)
405       // LDRH has a funny addressing mode (there's already a FIXME for it).
406       MIB.addReg(0);
407     MIB.addImm(0).add(predOps(ARMCC::AL));
408     break;
409   }
410   case G_SEQUENCE: {
411     if (!selectSequence(MIB, TII, MRI, TRI, RBI))
412       return false;
413     break;
414   }
415   case G_EXTRACT: {
416     if (!selectExtract(MIB, TII, MRI, TRI, RBI))
417       return false;
418     break;
419   }
420   default:
421     return false;
422   }
423 
424   return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
425 }
426