1//===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Thumb specific DAG Nodes. 16// 17 18def imm_sr_XFORM: SDNodeXForm<imm, [{ 19 unsigned Imm = N->getZExtValue(); 20 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), SDLoc(N), MVT::i32); 21}]>; 22def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; } 23def imm_sr : Operand<i32>, PatLeaf<(imm), [{ 24 uint64_t Imm = N->getZExtValue(); 25 return Imm > 0 && Imm <= 32; 26}], imm_sr_XFORM> { 27 let PrintMethod = "printThumbSRImm"; 28 let ParserMatchClass = ThumbSRImmAsmOperand; 29} 30 31def imm_comp_XFORM : SDNodeXForm<imm, [{ 32 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N), 33 MVT::i32); 34}]>; 35 36def imm0_7_neg : PatLeaf<(i32 imm), [{ 37 return (uint32_t)-N->getZExtValue() < 8; 38}], imm_neg_XFORM>; 39 40def imm0_255_comp : PatLeaf<(i32 imm), [{ 41 return ~((uint32_t)N->getZExtValue()) < 256; 42}]>; 43 44def imm8_255 : ImmLeaf<i32, [{ 45 return Imm >= 8 && Imm < 256; 46}]>; 47def imm8_255_neg : PatLeaf<(i32 imm), [{ 48 unsigned Val = -N->getZExtValue(); 49 return Val >= 8 && Val < 256; 50}], imm_neg_XFORM>; 51 52// Break imm's up into two pieces: an immediate + a left shift. This uses 53// thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt 54// to get the val/shift pieces. 55def thumb_immshifted : PatLeaf<(imm), [{ 56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue()); 57}]>; 58 59def thumb_immshifted_val : SDNodeXForm<imm, [{ 60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue()); 61 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32); 62}]>; 63 64def thumb_immshifted_shamt : SDNodeXForm<imm, [{ 65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue()); 66 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32); 67}]>; 68 69def imm256_510 : ImmLeaf<i32, [{ 70 return Imm >= 256 && Imm < 511; 71}]>; 72 73def thumb_imm256_510_addend : SDNodeXForm<imm, [{ 74 return CurDAG->getTargetConstant(N->getZExtValue() - 255, SDLoc(N), MVT::i32); 75}]>; 76 77// Scaled 4 immediate. 78def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; } 79def t_imm0_1020s4 : Operand<i32> { 80 let PrintMethod = "printThumbS4ImmOperand"; 81 let ParserMatchClass = t_imm0_1020s4_asmoperand; 82 let OperandType = "OPERAND_IMMEDIATE"; 83} 84 85def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; } 86def t_imm0_508s4 : Operand<i32> { 87 let PrintMethod = "printThumbS4ImmOperand"; 88 let ParserMatchClass = t_imm0_508s4_asmoperand; 89 let OperandType = "OPERAND_IMMEDIATE"; 90} 91// Alias use only, so no printer is necessary. 92def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; } 93def t_imm0_508s4_neg : Operand<i32> { 94 let ParserMatchClass = t_imm0_508s4_neg_asmoperand; 95 let OperandType = "OPERAND_IMMEDIATE"; 96} 97 98// Define Thumb specific addressing modes. 99 100// unsigned 8-bit, 2-scaled memory offset 101class OperandUnsignedOffset_b8s2 : AsmOperandClass { 102 let Name = "UnsignedOffset_b8s2"; 103 let PredicateMethod = "isUnsignedOffset<8, 2>"; 104} 105 106def UnsignedOffset_b8s2 : OperandUnsignedOffset_b8s2; 107 108// thumb style PC relative operand. signed, 8 bits magnitude, 109// two bits shift. can be represented as either [pc, #imm], #imm, 110// or relocatable expression... 111def ThumbMemPC : AsmOperandClass { 112 let Name = "ThumbMemPC"; 113} 114 115let OperandType = "OPERAND_PCREL" in { 116def t_brtarget : Operand<OtherVT> { 117 let EncoderMethod = "getThumbBRTargetOpValue"; 118 let DecoderMethod = "DecodeThumbBROperand"; 119} 120 121// ADR instruction labels. 122def t_adrlabel : Operand<i32> { 123 let EncoderMethod = "getThumbAdrLabelOpValue"; 124 let PrintMethod = "printAdrLabelOperand<2>"; 125 let ParserMatchClass = UnsignedOffset_b8s2; 126} 127 128def t_bcctarget : Operand<i32> { 129 let EncoderMethod = "getThumbBCCTargetOpValue"; 130 let DecoderMethod = "DecodeThumbBCCTargetOperand"; 131} 132 133def t_cbtarget : Operand<i32> { 134 let EncoderMethod = "getThumbCBTargetOpValue"; 135 let DecoderMethod = "DecodeThumbCmpBROperand"; 136} 137 138def t_bltarget : Operand<i32> { 139 let EncoderMethod = "getThumbBLTargetOpValue"; 140 let DecoderMethod = "DecodeThumbBLTargetOperand"; 141} 142 143def t_blxtarget : Operand<i32> { 144 let EncoderMethod = "getThumbBLXTargetOpValue"; 145 let DecoderMethod = "DecodeThumbBLXOffset"; 146} 147 148// t_addrmode_pc := <label> => pc + imm8 * 4 149// 150def t_addrmode_pc : MemOperand { 151 let EncoderMethod = "getAddrModePCOpValue"; 152 let DecoderMethod = "DecodeThumbAddrModePC"; 153 let PrintMethod = "printThumbLdrLabelOperand"; 154 let ParserMatchClass = ThumbMemPC; 155} 156} 157 158// t_addrmode_rr := reg + reg 159// 160def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; } 161def t_addrmode_rr : MemOperand, 162 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> { 163 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 164 let PrintMethod = "printThumbAddrModeRROperand"; 165 let DecoderMethod = "DecodeThumbAddrModeRR"; 166 let ParserMatchClass = t_addrmode_rr_asm_operand; 167 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 168} 169 170// t_addrmode_rrs := reg + reg 171// 172// We use separate scaled versions because the Select* functions need 173// to explicitly check for a matching constant and return false here so that 174// the reg+imm forms will match instead. This is a horrible way to do that, 175// as it forces tight coupling between the methods, but it's how selectiondag 176// currently works. 177def t_addrmode_rrs1 : MemOperand, 178 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> { 179 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 180 let PrintMethod = "printThumbAddrModeRROperand"; 181 let DecoderMethod = "DecodeThumbAddrModeRR"; 182 let ParserMatchClass = t_addrmode_rr_asm_operand; 183 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 184} 185def t_addrmode_rrs2 : MemOperand, 186 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> { 187 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 188 let DecoderMethod = "DecodeThumbAddrModeRR"; 189 let PrintMethod = "printThumbAddrModeRROperand"; 190 let ParserMatchClass = t_addrmode_rr_asm_operand; 191 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 192} 193def t_addrmode_rrs4 : MemOperand, 194 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> { 195 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 196 let DecoderMethod = "DecodeThumbAddrModeRR"; 197 let PrintMethod = "printThumbAddrModeRROperand"; 198 let ParserMatchClass = t_addrmode_rr_asm_operand; 199 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 200} 201 202// t_addrmode_is4 := reg + imm5 * 4 203// 204def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; } 205def t_addrmode_is4 : MemOperand, 206 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> { 207 let EncoderMethod = "getAddrModeISOpValue"; 208 let DecoderMethod = "DecodeThumbAddrModeIS"; 209 let PrintMethod = "printThumbAddrModeImm5S4Operand"; 210 let ParserMatchClass = t_addrmode_is4_asm_operand; 211 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 212} 213 214// t_addrmode_is2 := reg + imm5 * 2 215// 216def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; } 217def t_addrmode_is2 : MemOperand, 218 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> { 219 let EncoderMethod = "getAddrModeISOpValue"; 220 let DecoderMethod = "DecodeThumbAddrModeIS"; 221 let PrintMethod = "printThumbAddrModeImm5S2Operand"; 222 let ParserMatchClass = t_addrmode_is2_asm_operand; 223 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 224} 225 226// t_addrmode_is1 := reg + imm5 227// 228def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; } 229def t_addrmode_is1 : MemOperand, 230 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> { 231 let EncoderMethod = "getAddrModeISOpValue"; 232 let DecoderMethod = "DecodeThumbAddrModeIS"; 233 let PrintMethod = "printThumbAddrModeImm5S1Operand"; 234 let ParserMatchClass = t_addrmode_is1_asm_operand; 235 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 236} 237 238// t_addrmode_sp := sp + imm8 * 4 239// 240// FIXME: This really shouldn't have an explicit SP operand at all. It should 241// be implicit, just like in the instruction encoding itself. 242def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; } 243def t_addrmode_sp : MemOperand, 244 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { 245 let EncoderMethod = "getAddrModeThumbSPOpValue"; 246 let DecoderMethod = "DecodeThumbAddrModeSP"; 247 let PrintMethod = "printThumbAddrModeSPOperand"; 248 let ParserMatchClass = t_addrmode_sp_asm_operand; 249 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 250} 251 252//===----------------------------------------------------------------------===// 253// Miscellaneous Instructions. 254// 255 256// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 257// from removing one half of the matched pairs. That breaks PEI, which assumes 258// these will always be in pairs, and asserts if it finds otherwise. Better way? 259let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 260def tADJCALLSTACKUP : 261 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, 262 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, 263 Requires<[IsThumb, IsThumb1Only]>; 264 265def tADJCALLSTACKDOWN : 266 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, 267 [(ARMcallseq_start imm:$amt)]>, 268 Requires<[IsThumb, IsThumb1Only]>; 269} 270 271class T1SystemEncoding<bits<8> opc> 272 : T1Encoding<0b101111> { 273 let Inst{9-8} = 0b11; 274 let Inst{7-0} = opc; 275} 276 277def tHINT : T1pI<(outs), (ins imm0_15:$imm), NoItinerary, "hint", "\t$imm", 278 [(int_arm_hint imm0_15:$imm)]>, 279 T1SystemEncoding<0x00>, 280 Requires<[IsThumb, HasV6M]> { 281 bits<4> imm; 282 let Inst{7-4} = imm; 283} 284 285// Note: When EmitPriority == 1, the alias will be used for printing 286class tHintAlias<string Asm, dag Result, bit EmitPriority = 0> : tInstAlias<Asm, Result, EmitPriority> { 287 let Predicates = [IsThumb, HasV6M]; 288} 289 290def : tHintAlias<"nop$p", (tHINT 0, pred:$p), 1>; // A8.6.110 291def : tHintAlias<"yield$p", (tHINT 1, pred:$p), 1>; // A8.6.410 292def : tHintAlias<"wfe$p", (tHINT 2, pred:$p), 1>; // A8.6.408 293def : tHintAlias<"wfi$p", (tHINT 3, pred:$p), 1>; // A8.6.409 294def : tHintAlias<"sev$p", (tHINT 4, pred:$p), 1>; // A8.6.157 295def : tInstAlias<"sevl$p", (tHINT 5, pred:$p), 1> { 296 let Predicates = [IsThumb2, HasV8]; 297} 298 299// The imm operand $val can be used by a debugger to store more information 300// about the breakpoint. 301def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val", 302 []>, 303 T1Encoding<0b101111> { 304 let Inst{9-8} = 0b10; 305 // A8.6.22 306 bits<8> val; 307 let Inst{7-0} = val; 308} 309// default immediate for breakpoint mnemonic 310def : InstAlias<"bkpt", (tBKPT 0), 0>, Requires<[IsThumb]>; 311 312def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val", 313 []>, T1Encoding<0b101110>, Requires<[IsThumb, HasV8]> { 314 let Inst{9-6} = 0b1010; 315 bits<6> val; 316 let Inst{5-0} = val; 317} 318 319def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end", 320 []>, T1Encoding<0b101101>, Requires<[IsNotMClass]>, Deprecated<HasV8Ops> { 321 bits<1> end; 322 // A8.6.156 323 let Inst{9-5} = 0b10010; 324 let Inst{4} = 1; 325 let Inst{3} = end; 326 let Inst{2-0} = 0b000; 327} 328 329// Change Processor State is a system instruction -- for disassembly only. 330def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags), 331 NoItinerary, "cps$imod $iflags", []>, 332 T1Misc<0b0110011> { 333 // A8.6.38 & B6.1.1 334 bit imod; 335 bits<3> iflags; 336 337 let Inst{4} = imod; 338 let Inst{3} = 0; 339 let Inst{2-0} = iflags; 340 let DecoderMethod = "DecodeThumbCPS"; 341} 342 343// For both thumb1 and thumb2. 344let isNotDuplicable = 1, isCodeGenOnly = 1 in 345def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "", 346 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>, 347 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 348 // A8.6.6 349 bits<3> dst; 350 let Inst{6-3} = 0b1111; // Rm = pc 351 let Inst{2-0} = dst; 352} 353 354// ADD <Rd>, sp, #<imm8> 355// FIXME: This should not be marked as having side effects, and it should be 356// rematerializable. Clearing the side effect bit causes miscompilations, 357// probably because the instruction can be moved around. 358def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm), 359 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>, 360 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> { 361 // A6.2 & A8.6.8 362 bits<3> dst; 363 bits<8> imm; 364 let Inst{10-8} = dst; 365 let Inst{7-0} = imm; 366 let DecoderMethod = "DecodeThumbAddSpecialReg"; 367} 368 369// Thumb1 frame lowering is rather fragile, we hope to be able to use 370// tADDrSPi, but we may need to insert a sequence that clobbers CPSR. 371def tADDframe : PseudoInst<(outs tGPR:$dst), (ins i32imm:$base, i32imm:$offset), 372 NoItinerary, []>, 373 Requires<[IsThumb, IsThumb1Only]> { 374 let Defs = [CPSR]; 375} 376 377// ADD sp, sp, #<imm7> 378def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 379 IIC_iALUi, "add", "\t$Rdn, $imm", []>, 380 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> { 381 // A6.2.5 & A8.6.8 382 bits<7> imm; 383 let Inst{6-0} = imm; 384 let DecoderMethod = "DecodeThumbAddSPImm"; 385} 386 387// SUB sp, sp, #<imm7> 388// FIXME: The encoding and the ASM string don't match up. 389def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 390 IIC_iALUi, "sub", "\t$Rdn, $imm", []>, 391 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> { 392 // A6.2.5 & A8.6.214 393 bits<7> imm; 394 let Inst{6-0} = imm; 395 let DecoderMethod = "DecodeThumbAddSPImm"; 396} 397 398def : tInstAlias<"add${p} sp, $imm", 399 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 400def : tInstAlias<"add${p} sp, sp, $imm", 401 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 402 403// Can optionally specify SP as a three operand instruction. 404def : tInstAlias<"add${p} sp, sp, $imm", 405 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>; 406def : tInstAlias<"sub${p} sp, sp, $imm", 407 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>; 408 409// ADD <Rm>, sp 410def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr, 411 "add", "\t$Rdn, $sp, $Rn", []>, 412 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 413 // A8.6.9 Encoding T1 414 bits<4> Rdn; 415 let Inst{7} = Rdn{3}; 416 let Inst{6-3} = 0b1101; 417 let Inst{2-0} = Rdn{2-0}; 418 let DecoderMethod = "DecodeThumbAddSPReg"; 419} 420 421// ADD sp, <Rm> 422def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr, 423 "add", "\t$Rdn, $Rm", []>, 424 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 425 // A8.6.9 Encoding T2 426 bits<4> Rm; 427 let Inst{7} = 1; 428 let Inst{6-3} = Rm; 429 let Inst{2-0} = 0b101; 430 let DecoderMethod = "DecodeThumbAddSPReg"; 431} 432 433//===----------------------------------------------------------------------===// 434// Control Flow Instructions. 435// 436 437// Indirect branches 438let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 439 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>, 440 T1Special<{1,1,0,?}>, Sched<[WriteBr]> { 441 // A6.2.3 & A8.6.25 442 bits<4> Rm; 443 let Inst{6-3} = Rm; 444 let Inst{2-0} = 0b000; 445 let Unpredictable{2-0} = 0b111; 446 } 447 def tBXNS : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bxns${p}\t$Rm", []>, 448 Requires<[IsThumb, Has8MSecExt]>, 449 T1Special<{1,1,0,?}>, Sched<[WriteBr]> { 450 bits<4> Rm; 451 let Inst{6-3} = Rm; 452 let Inst{2-0} = 0b100; 453 let Unpredictable{1-0} = 0b11; 454 } 455} 456 457let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 458 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br, 459 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>; 460 461 // Alternative return instruction used by vararg functions. 462 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p), 463 2, IIC_Br, [], 464 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>; 465} 466 467// All calls clobber the non-callee saved registers. SP is marked as a use to 468// prevent stack-pointer assignments that appear immediately before calls from 469// potentially appearing dead. 470let isCall = 1, 471 Defs = [LR], Uses = [SP] in { 472 // Also used for Thumb2 473 def tBL : TIx2<0b11110, 0b11, 1, 474 (outs), (ins pred:$p, t_bltarget:$func), IIC_Br, 475 "bl${p}\t$func", 476 [(ARMcall tglobaladdr:$func)]>, 477 Requires<[IsThumb]>, Sched<[WriteBrL]> { 478 bits<24> func; 479 let Inst{26} = func{23}; 480 let Inst{25-16} = func{20-11}; 481 let Inst{13} = func{22}; 482 let Inst{11} = func{21}; 483 let Inst{10-0} = func{10-0}; 484 } 485 486 // ARMv5T and above, also used for Thumb2 487 def tBLXi : TIx2<0b11110, 0b11, 0, 488 (outs), (ins pred:$p, t_blxtarget:$func), IIC_Br, 489 "blx${p}\t$func", []>, 490 Requires<[IsThumb, HasV5T, IsNotMClass]>, Sched<[WriteBrL]> { 491 bits<24> func; 492 let Inst{26} = func{23}; 493 let Inst{25-16} = func{20-11}; 494 let Inst{13} = func{22}; 495 let Inst{11} = func{21}; 496 let Inst{10-1} = func{10-1}; 497 let Inst{0} = 0; // func{0} is assumed zero 498 } 499 500 // Also used for Thumb2 501 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br, 502 "blx${p}\t$func", 503 [(ARMcall GPR:$func)]>, 504 Requires<[IsThumb, HasV5T]>, 505 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24; 506 bits<4> func; 507 let Inst{6-3} = func; 508 let Inst{2-0} = 0b000; 509 } 510 511 // ARMv8-M Security Extensions 512 def tBLXNSr : TI<(outs), (ins pred:$p, GPRnopc:$func), IIC_Br, 513 "blxns${p}\t$func", []>, 514 Requires<[IsThumb, Has8MSecExt]>, 515 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { 516 bits<4> func; 517 let Inst{6-3} = func; 518 let Inst{2-0} = 0b100; 519 let Unpredictable{1-0} = 0b11; 520 } 521 522 // ARMv4T 523 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func), 524 4, IIC_Br, 525 [(ARMcall_nolink tGPR:$func)]>, 526 Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>; 527} 528 529let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 530 let isPredicable = 1 in 531 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br, 532 "b", "\t$target", [(br bb:$target)]>, 533 T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> { 534 bits<11> target; 535 let Inst{10-0} = target; 536 let AsmMatchConverter = "cvtThumbBranches"; 537 } 538 539 // Far jump 540 // Just a pseudo for a tBL instruction. Needed to let regalloc know about 541 // the clobber of LR. 542 let Defs = [LR] in 543 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p), 544 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>, 545 Sched<[WriteBrTbl]>; 546 547 def tBR_JTr : tPseudoInst<(outs), 548 (ins tGPR:$target, i32imm:$jt), 549 0, IIC_Br, 550 [(ARMbrjt tGPR:$target, tjumptable:$jt)]>, 551 Sched<[WriteBrTbl]> { 552 let Size = 2; 553 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 554 } 555} 556 557// FIXME: should be able to write a pattern for ARMBrcond, but can't use 558// a two-value operand where a dag node expects two operands. :( 559let isBranch = 1, isTerminator = 1 in 560 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br, 561 "b${p}\t$target", 562 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, 563 T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> { 564 bits<4> p; 565 bits<8> target; 566 let Inst{11-8} = p; 567 let Inst{7-0} = target; 568 let AsmMatchConverter = "cvtThumbBranches"; 569} 570 571 572// Tail calls 573let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 574 // IOS versions. 575 let Uses = [SP] in { 576 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst), 577 4, IIC_Br, [], 578 (tBX GPR:$dst, (ops 14, zero_reg))>, 579 Requires<[IsThumb]>, Sched<[WriteBr]>; 580 } 581 // tTAILJMPd: MachO version uses a Thumb2 branch (no Thumb1 tail calls 582 // on MachO), so it's in ARMInstrThumb2.td. 583 // Non-MachO version: 584 let Uses = [SP] in { 585 def tTAILJMPdND : tPseudoExpand<(outs), 586 (ins t_brtarget:$dst, pred:$p), 587 4, IIC_Br, [], 588 (tB t_brtarget:$dst, pred:$p)>, 589 Requires<[IsThumb, IsNotMachO]>, Sched<[WriteBr]>; 590 } 591} 592 593 594// A8.6.218 Supervisor Call (Software Interrupt) 595// A8.6.16 B: Encoding T1 596// If Inst{11-8} == 0b1111 then SEE SVC 597let isCall = 1, Uses = [SP] in 598def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br, 599 "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> { 600 bits<8> imm; 601 let Inst{15-12} = 0b1101; 602 let Inst{11-8} = 0b1111; 603 let Inst{7-0} = imm; 604} 605 606// The assembler uses 0xDEFE for a trap instruction. 607let isBarrier = 1, isTerminator = 1 in 608def tTRAP : TI<(outs), (ins), IIC_Br, 609 "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> { 610 let Inst = 0xdefe; 611} 612 613//===----------------------------------------------------------------------===// 614// Load Store Instructions. 615// 616 617// PC-relative loads need to be matched first as constant pool accesses need to 618// always be PC-relative. We do this using AddedComplexity, as the pattern is 619// simpler than the patterns of the other load instructions. 620let canFoldAsLoad = 1, isReMaterializable = 1, AddedComplexity = 10 in 621def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, 622 "ldr", "\t$Rt, $addr", 623 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>, 624 T1Encoding<{0,1,0,0,1,?}> { 625 // A6.2 & A8.6.59 626 bits<3> Rt; 627 bits<8> addr; 628 let Inst{10-8} = Rt; 629 let Inst{7-0} = addr; 630} 631 632// SP-relative loads should be matched before standard immediate-offset loads as 633// it means we avoid having to move SP to another register. 634let canFoldAsLoad = 1 in 635def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i, 636 "ldr", "\t$Rt, $addr", 637 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>, 638 T1LdStSP<{1,?,?}> { 639 bits<3> Rt; 640 bits<8> addr; 641 let Inst{10-8} = Rt; 642 let Inst{7-0} = addr; 643} 644 645// Loads: reg/reg and reg/imm5 646let canFoldAsLoad = 1, isReMaterializable = 1 in 647multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 648 Operand AddrMode_r, Operand AddrMode_i, 649 AddrMode am, InstrItinClass itin_r, 650 InstrItinClass itin_i, string asm, 651 PatFrag opnode> { 652 // Immediate-offset loads should be matched before register-offset loads as 653 // when the offset is a constant it's simpler to first check if it fits in the 654 // immediate offset field then fall back to register-offset if it doesn't. 655 def i : // reg/imm5 656 T1pILdStEncodeImm<imm_opc, 1 /* Load */, 657 (outs tGPR:$Rt), (ins AddrMode_i:$addr), 658 am, itin_i, asm, "\t$Rt, $addr", 659 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>; 660 // Register-offset loads are matched last. 661 def r : // reg/reg 662 T1pILdStEncode<reg_opc, 663 (outs tGPR:$Rt), (ins AddrMode_r:$addr), 664 am, itin_r, asm, "\t$Rt, $addr", 665 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>; 666} 667// Stores: reg/reg and reg/imm5 668multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 669 Operand AddrMode_r, Operand AddrMode_i, 670 AddrMode am, InstrItinClass itin_r, 671 InstrItinClass itin_i, string asm, 672 PatFrag opnode> { 673 def i : // reg/imm5 674 T1pILdStEncodeImm<imm_opc, 0 /* Store */, 675 (outs), (ins tGPR:$Rt, AddrMode_i:$addr), 676 am, itin_i, asm, "\t$Rt, $addr", 677 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>; 678 def r : // reg/reg 679 T1pILdStEncode<reg_opc, 680 (outs), (ins tGPR:$Rt, AddrMode_r:$addr), 681 am, itin_r, asm, "\t$Rt, $addr", 682 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>; 683} 684 685// A8.6.57 & A8.6.60 686defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rr, 687 t_addrmode_is4, AddrModeT1_4, 688 IIC_iLoad_r, IIC_iLoad_i, "ldr", 689 load>; 690 691// A8.6.64 & A8.6.61 692defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rr, 693 t_addrmode_is1, AddrModeT1_1, 694 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb", 695 zextloadi8>; 696 697// A8.6.76 & A8.6.73 698defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rr, 699 t_addrmode_is2, AddrModeT1_2, 700 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh", 701 zextloadi16>; 702 703let AddedComplexity = 10 in 704def tLDRSB : // A8.6.80 705 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 706 AddrModeT1_1, IIC_iLoad_bh_r, 707 "ldrsb", "\t$Rt, $addr", 708 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>; 709 710let AddedComplexity = 10 in 711def tLDRSH : // A8.6.84 712 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 713 AddrModeT1_2, IIC_iLoad_bh_r, 714 "ldrsh", "\t$Rt, $addr", 715 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>; 716 717 718def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i, 719 "str", "\t$Rt, $addr", 720 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>, 721 T1LdStSP<{0,?,?}> { 722 bits<3> Rt; 723 bits<8> addr; 724 let Inst{10-8} = Rt; 725 let Inst{7-0} = addr; 726} 727 728// A8.6.194 & A8.6.192 729defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rr, 730 t_addrmode_is4, AddrModeT1_4, 731 IIC_iStore_r, IIC_iStore_i, "str", 732 store>; 733 734// A8.6.197 & A8.6.195 735defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rr, 736 t_addrmode_is1, AddrModeT1_1, 737 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb", 738 truncstorei8>; 739 740// A8.6.207 & A8.6.205 741defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rr, 742 t_addrmode_is2, AddrModeT1_2, 743 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh", 744 truncstorei16>; 745 746 747//===----------------------------------------------------------------------===// 748// Load / store multiple Instructions. 749// 750 751// These require base address to be written back or one of the loaded regs. 752let hasSideEffects = 0 in { 753 754let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 755def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 756 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> { 757 bits<3> Rn; 758 bits<8> regs; 759 let Inst{10-8} = Rn; 760 let Inst{7-0} = regs; 761} 762 763// Writeback version is just a pseudo, as there's no encoding difference. 764// Writeback happens iff the base register is not in the destination register 765// list. 766let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 767def tLDMIA_UPD : 768 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, 769 "$Rn = $wb", IIC_iLoad_mu>, 770 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> { 771 let Size = 2; 772 let OutOperandList = (outs GPR:$wb); 773 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops); 774 let Pattern = []; 775 let isCodeGenOnly = 1; 776 let isPseudo = 1; 777 list<Predicate> Predicates = [IsThumb]; 778} 779 780// There is no non-writeback version of STM for Thumb. 781let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 782def tSTMIA_UPD : Thumb1I<(outs GPR:$wb), 783 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 784 AddrModeNone, 2, IIC_iStore_mu, 785 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>, 786 T1Encoding<{1,1,0,0,0,?}> { 787 bits<3> Rn; 788 bits<8> regs; 789 let Inst{10-8} = Rn; 790 let Inst{7-0} = regs; 791} 792 793} // hasSideEffects 794 795def : InstAlias<"ldm${p} $Rn!, $regs", 796 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs), 0>, 797 Requires<[IsThumb, IsThumb1Only]>; 798 799let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in 800def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 801 IIC_iPop, 802 "pop${p}\t$regs", []>, 803 T1Misc<{1,1,0,?,?,?,?}> { 804 bits<16> regs; 805 let Inst{8} = regs{15}; 806 let Inst{7-0} = regs{7-0}; 807} 808 809let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in 810def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 811 IIC_iStore_m, 812 "push${p}\t$regs", []>, 813 T1Misc<{0,1,0,?,?,?,?}> { 814 bits<16> regs; 815 let Inst{8} = regs{14}; 816 let Inst{7-0} = regs{7-0}; 817} 818 819//===----------------------------------------------------------------------===// 820// Arithmetic Instructions. 821// 822 823// Helper classes for encoding T1pI patterns: 824class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 825 string opc, string asm, list<dag> pattern> 826 : T1pI<oops, iops, itin, opc, asm, pattern>, 827 T1DataProcessing<opA> { 828 bits<3> Rm; 829 bits<3> Rn; 830 let Inst{5-3} = Rm; 831 let Inst{2-0} = Rn; 832} 833class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin, 834 string opc, string asm, list<dag> pattern> 835 : T1pI<oops, iops, itin, opc, asm, pattern>, 836 T1Misc<opA> { 837 bits<3> Rm; 838 bits<3> Rd; 839 let Inst{5-3} = Rm; 840 let Inst{2-0} = Rd; 841} 842 843// Helper classes for encoding T1sI patterns: 844class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 845 string opc, string asm, list<dag> pattern> 846 : T1sI<oops, iops, itin, opc, asm, pattern>, 847 T1DataProcessing<opA> { 848 bits<3> Rd; 849 bits<3> Rn; 850 let Inst{5-3} = Rn; 851 let Inst{2-0} = Rd; 852} 853class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 854 string opc, string asm, list<dag> pattern> 855 : T1sI<oops, iops, itin, opc, asm, pattern>, 856 T1General<opA> { 857 bits<3> Rm; 858 bits<3> Rn; 859 bits<3> Rd; 860 let Inst{8-6} = Rm; 861 let Inst{5-3} = Rn; 862 let Inst{2-0} = Rd; 863} 864class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 865 string opc, string asm, list<dag> pattern> 866 : T1sI<oops, iops, itin, opc, asm, pattern>, 867 T1General<opA> { 868 bits<3> Rd; 869 bits<3> Rm; 870 let Inst{5-3} = Rm; 871 let Inst{2-0} = Rd; 872} 873 874// Helper classes for encoding T1sIt patterns: 875class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 876 string opc, string asm, list<dag> pattern> 877 : T1sIt<oops, iops, itin, opc, asm, pattern>, 878 T1DataProcessing<opA> { 879 bits<3> Rdn; 880 bits<3> Rm; 881 let Inst{5-3} = Rm; 882 let Inst{2-0} = Rdn; 883} 884class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 885 string opc, string asm, list<dag> pattern> 886 : T1sIt<oops, iops, itin, opc, asm, pattern>, 887 T1General<opA> { 888 bits<3> Rdn; 889 bits<8> imm8; 890 let Inst{10-8} = Rdn; 891 let Inst{7-0} = imm8; 892} 893 894// Add with carry register 895let isCommutable = 1, Uses = [CPSR] in 896def tADC : // A8.6.2 897 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr, 898 "adc", "\t$Rdn, $Rm", 899 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 900 901// Add immediate 902def tADDi3 : // A8.6.4 T1 903 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 904 IIC_iALUi, 905 "add", "\t$Rd, $Rm, $imm3", 906 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>, 907 Sched<[WriteALU]> { 908 bits<3> imm3; 909 let Inst{8-6} = imm3; 910} 911 912def tADDi8 : // A8.6.4 T2 913 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), 914 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 915 "add", "\t$Rdn, $imm8", 916 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>, 917 Sched<[WriteALU]>; 918 919// Add register 920let isCommutable = 1 in 921def tADDrr : // A8.6.6 T1 922 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 923 IIC_iALUr, 924 "add", "\t$Rd, $Rn, $Rm", 925 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 926 927let hasSideEffects = 0 in 928def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr, 929 "add", "\t$Rdn, $Rm", []>, 930 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 931 // A8.6.6 T2 932 bits<4> Rdn; 933 bits<4> Rm; 934 let Inst{7} = Rdn{3}; 935 let Inst{6-3} = Rm; 936 let Inst{2-0} = Rdn{2-0}; 937} 938 939// AND register 940let isCommutable = 1 in 941def tAND : // A8.6.12 942 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 943 IIC_iBITr, 944 "and", "\t$Rdn, $Rm", 945 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 946 947// ASR immediate 948def tASRri : // A8.6.14 949 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 950 IIC_iMOVsi, 951 "asr", "\t$Rd, $Rm, $imm5", 952 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>, 953 Sched<[WriteALU]> { 954 bits<5> imm5; 955 let Inst{10-6} = imm5; 956} 957 958// ASR register 959def tASRrr : // A8.6.15 960 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 961 IIC_iMOVsr, 962 "asr", "\t$Rdn, $Rm", 963 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 964 965// BIC register 966def tBIC : // A8.6.20 967 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 968 IIC_iBITr, 969 "bic", "\t$Rdn, $Rm", 970 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>, 971 Sched<[WriteALU]>; 972 973// CMN register 974let isCompare = 1, Defs = [CPSR] in { 975//FIXME: Disable CMN, as CCodes are backwards from compare expectations 976// Compare-to-zero still works out, just not the relationals 977//def tCMN : // A8.6.33 978// T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs), 979// IIC_iCMPr, 980// "cmn", "\t$lhs, $rhs", 981// [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>; 982 983def tCMNz : // A8.6.33 984 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm), 985 IIC_iCMPr, 986 "cmn", "\t$Rn, $Rm", 987 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>; 988 989} // isCompare = 1, Defs = [CPSR] 990 991// CMP immediate 992let isCompare = 1, Defs = [CPSR] in { 993def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi, 994 "cmp", "\t$Rn, $imm8", 995 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>, 996 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> { 997 // A8.6.35 998 bits<3> Rn; 999 bits<8> imm8; 1000 let Inst{10-8} = Rn; 1001 let Inst{7-0} = imm8; 1002} 1003 1004// CMP register 1005def tCMPr : // A8.6.36 T1 1006 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm), 1007 IIC_iCMPr, 1008 "cmp", "\t$Rn, $Rm", 1009 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>; 1010 1011def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr, 1012 "cmp", "\t$Rn, $Rm", []>, 1013 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> { 1014 // A8.6.36 T2 1015 bits<4> Rm; 1016 bits<4> Rn; 1017 let Inst{7} = Rn{3}; 1018 let Inst{6-3} = Rm; 1019 let Inst{2-0} = Rn{2-0}; 1020} 1021} // isCompare = 1, Defs = [CPSR] 1022 1023 1024// XOR register 1025let isCommutable = 1 in 1026def tEOR : // A8.6.45 1027 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1028 IIC_iBITr, 1029 "eor", "\t$Rdn, $Rm", 1030 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1031 1032// LSL immediate 1033def tLSLri : // A8.6.88 1034 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5), 1035 IIC_iMOVsi, 1036 "lsl", "\t$Rd, $Rm, $imm5", 1037 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>, 1038 Sched<[WriteALU]> { 1039 bits<5> imm5; 1040 let Inst{10-6} = imm5; 1041} 1042 1043// LSL register 1044def tLSLrr : // A8.6.89 1045 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1046 IIC_iMOVsr, 1047 "lsl", "\t$Rdn, $Rm", 1048 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1049 1050// LSR immediate 1051def tLSRri : // A8.6.90 1052 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 1053 IIC_iMOVsi, 1054 "lsr", "\t$Rd, $Rm, $imm5", 1055 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>, 1056 Sched<[WriteALU]> { 1057 bits<5> imm5; 1058 let Inst{10-6} = imm5; 1059} 1060 1061// LSR register 1062def tLSRrr : // A8.6.91 1063 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1064 IIC_iMOVsr, 1065 "lsr", "\t$Rdn, $Rm", 1066 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1067 1068// Move register 1069let isMoveImm = 1 in 1070def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi, 1071 "mov", "\t$Rd, $imm8", 1072 [(set tGPR:$Rd, imm0_255:$imm8)]>, 1073 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> { 1074 // A8.6.96 1075 bits<3> Rd; 1076 bits<8> imm8; 1077 let Inst{10-8} = Rd; 1078 let Inst{7-0} = imm8; 1079} 1080// Because we have an explicit tMOVSr below, we need an alias to handle 1081// the immediate "movs" form here. Blech. 1082def : tInstAlias <"movs $Rdn, $imm", 1083 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>; 1084 1085// A7-73: MOV(2) - mov setting flag. 1086 1087let hasSideEffects = 0 in { 1088def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone, 1089 2, IIC_iMOVr, 1090 "mov", "\t$Rd, $Rm", "", []>, 1091 T1Special<{1,0,?,?}>, Sched<[WriteALU]> { 1092 // A8.6.97 1093 bits<4> Rd; 1094 bits<4> Rm; 1095 let Inst{7} = Rd{3}; 1096 let Inst{6-3} = Rm; 1097 let Inst{2-0} = Rd{2-0}; 1098} 1099let Defs = [CPSR] in 1100def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr, 1101 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> { 1102 // A8.6.97 1103 bits<3> Rd; 1104 bits<3> Rm; 1105 let Inst{15-6} = 0b0000000000; 1106 let Inst{5-3} = Rm; 1107 let Inst{2-0} = Rd; 1108} 1109} // hasSideEffects 1110 1111// Multiply register 1112let isCommutable = 1 in 1113def tMUL : // A8.6.105 T1 1114 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2, 1115 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd", 1116 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>, 1117 T1DataProcessing<0b1101> { 1118 bits<3> Rd; 1119 bits<3> Rn; 1120 let Inst{5-3} = Rn; 1121 let Inst{2-0} = Rd; 1122 let AsmMatchConverter = "cvtThumbMultiply"; 1123} 1124 1125def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn, 1126 pred:$p)>; 1127 1128// Move inverse register 1129def tMVN : // A8.6.107 1130 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr, 1131 "mvn", "\t$Rd, $Rn", 1132 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>; 1133 1134// Bitwise or register 1135let isCommutable = 1 in 1136def tORR : // A8.6.114 1137 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1138 IIC_iBITr, 1139 "orr", "\t$Rdn, $Rm", 1140 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1141 1142// Swaps 1143def tREV : // A8.6.134 1144 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1145 IIC_iUNAr, 1146 "rev", "\t$Rd, $Rm", 1147 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>, 1148 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1149 1150def tREV16 : // A8.6.135 1151 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1152 IIC_iUNAr, 1153 "rev16", "\t$Rd, $Rm", 1154 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>, 1155 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1156 1157def tREVSH : // A8.6.136 1158 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1159 IIC_iUNAr, 1160 "revsh", "\t$Rd, $Rm", 1161 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>, 1162 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1163 1164// Rotate right register 1165def tROR : // A8.6.139 1166 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1167 IIC_iMOVsr, 1168 "ror", "\t$Rdn, $Rm", 1169 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>, 1170 Sched<[WriteALU]>; 1171 1172// Negate register 1173def tRSB : // A8.6.141 1174 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn), 1175 IIC_iALUi, 1176 "rsb", "\t$Rd, $Rn, #0", 1177 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>; 1178 1179// Subtract with carry register 1180let Uses = [CPSR] in 1181def tSBC : // A8.6.151 1182 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1183 IIC_iALUr, 1184 "sbc", "\t$Rdn, $Rm", 1185 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>, 1186 Sched<[WriteALU]>; 1187 1188// Subtract immediate 1189def tSUBi3 : // A8.6.210 T1 1190 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 1191 IIC_iALUi, 1192 "sub", "\t$Rd, $Rm, $imm3", 1193 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>, 1194 Sched<[WriteALU]> { 1195 bits<3> imm3; 1196 let Inst{8-6} = imm3; 1197} 1198 1199def tSUBi8 : // A8.6.210 T2 1200 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), 1201 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 1202 "sub", "\t$Rdn, $imm8", 1203 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>, 1204 Sched<[WriteALU]>; 1205 1206// Subtract register 1207def tSUBrr : // A8.6.212 1208 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 1209 IIC_iALUr, 1210 "sub", "\t$Rd, $Rn, $Rm", 1211 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>, 1212 Sched<[WriteALU]>; 1213 1214// Sign-extend byte 1215def tSXTB : // A8.6.222 1216 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1217 IIC_iUNAr, 1218 "sxtb", "\t$Rd, $Rm", 1219 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>, 1220 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1221 Sched<[WriteALU]>; 1222 1223// Sign-extend short 1224def tSXTH : // A8.6.224 1225 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1226 IIC_iUNAr, 1227 "sxth", "\t$Rd, $Rm", 1228 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>, 1229 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1230 Sched<[WriteALU]>; 1231 1232// Test 1233let isCompare = 1, isCommutable = 1, Defs = [CPSR] in 1234def tTST : // A8.6.230 1235 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr, 1236 "tst", "\t$Rn, $Rm", 1237 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>, 1238 Sched<[WriteALU]>; 1239 1240// A8.8.247 UDF - Undefined (Encoding T1) 1241def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8", 1242 [(int_arm_undefined imm0_255:$imm8)]>, Encoding16 { 1243 bits<8> imm8; 1244 let Inst{15-12} = 0b1101; 1245 let Inst{11-8} = 0b1110; 1246 let Inst{7-0} = imm8; 1247} 1248 1249// Zero-extend byte 1250def tUXTB : // A8.6.262 1251 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1252 IIC_iUNAr, 1253 "uxtb", "\t$Rd, $Rm", 1254 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>, 1255 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1256 Sched<[WriteALU]>; 1257 1258// Zero-extend short 1259def tUXTH : // A8.6.264 1260 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1261 IIC_iUNAr, 1262 "uxth", "\t$Rd, $Rm", 1263 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>, 1264 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1265 1266// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation. 1267// Expanded after instruction selection into a branch sequence. 1268let usesCustomInserter = 1 in // Expanded after instruction selection. 1269 def tMOVCCr_pseudo : 1270 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, cmovpred:$p), 1271 NoItinerary, 1272 [(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, cmovpred:$p))]>; 1273 1274// tLEApcrel - Load a pc-relative address into a register without offending the 1275// assembler. 1276 1277def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p), 1278 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>, 1279 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> { 1280 bits<3> Rd; 1281 bits<8> addr; 1282 let Inst{10-8} = Rd; 1283 let Inst{7-0} = addr; 1284 let DecoderMethod = "DecodeThumbAddSpecialReg"; 1285} 1286 1287let hasSideEffects = 0, isReMaterializable = 1 in 1288def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), 1289 2, IIC_iALUi, []>, Sched<[WriteALU]>; 1290 1291let hasSideEffects = 1 in 1292def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd), 1293 (ins i32imm:$label, pred:$p), 1294 2, IIC_iALUi, []>, Sched<[WriteALU]>; 1295 1296//===----------------------------------------------------------------------===// 1297// TLS Instructions 1298// 1299 1300// __aeabi_read_tp preserves the registers r1-r3. 1301// This is a pseudo inst so that we can get the encoding right, 1302// complete with fixup for the aeabi_read_tp function. 1303let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in 1304def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br, 1305 [(set R0, ARMthread_pointer)]>, 1306 Sched<[WriteBr]>; 1307 1308//===----------------------------------------------------------------------===// 1309// SJLJ Exception handling intrinsics 1310// 1311 1312// eh_sjlj_setjmp() is an instruction sequence to store the return address and 1313// save #0 in R0 for the non-longjmp case. Since by its nature we may be coming 1314// from some other function to get here, and we're using the stack frame for the 1315// containing function to save/restore registers, we can't keep anything live in 1316// regs across the eh_sjlj_setjmp(), else it will almost certainly have been 1317// tromped upon when we get here from a longjmp(). We force everything out of 1318// registers except for our own input by listing the relevant registers in 1319// Defs. By doing so, we also cause the prologue/epilogue code to actively 1320// preserve all of the callee-saved resgisters, which is exactly what we want. 1321// $val is a scratch register for our use. 1322let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ], 1323 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 1324 usesCustomInserter = 1 in 1325def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val), 1326 AddrModeNone, 0, NoItinerary, "","", 1327 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>; 1328 1329// FIXME: Non-IOS version(s) 1330let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, 1331 Defs = [ R7, LR, SP ] in 1332def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch), 1333 AddrModeNone, 0, IndexModeNone, 1334 Pseudo, NoItinerary, "", "", 1335 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 1336 Requires<[IsThumb,IsNotWindows]>; 1337 1338let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, 1339 Defs = [ R11, LR, SP ] in 1340def tInt_WIN_eh_sjlj_longjmp 1341 : XI<(outs), (ins GPR:$src, GPR:$scratch), AddrModeNone, 0, IndexModeNone, 1342 Pseudo, NoItinerary, "", "", [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 1343 Requires<[IsThumb,IsWindows]>; 1344 1345//===----------------------------------------------------------------------===// 1346// Non-Instruction Patterns 1347// 1348 1349// Comparisons 1350def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8), 1351 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>; 1352def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm), 1353 (tCMPr tGPR:$Rn, tGPR:$Rm)>; 1354 1355// Add with carry 1356def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs), 1357 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>; 1358def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs), 1359 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>; 1360def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs), 1361 (tADDrr tGPR:$lhs, tGPR:$rhs)>; 1362 1363// Subtract with carry 1364def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs), 1365 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>; 1366def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs), 1367 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>; 1368def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs), 1369 (tSUBrr tGPR:$lhs, tGPR:$rhs)>; 1370 1371// Bswap 16 with load/store 1372def : T1Pat<(srl (bswap (extloadi16 t_addrmode_is2:$addr)), (i32 16)), 1373 (tREV16 (tLDRHi t_addrmode_is2:$addr))>; 1374def : T1Pat<(srl (bswap (extloadi16 t_addrmode_rr:$addr)), (i32 16)), 1375 (tREV16 (tLDRHr t_addrmode_rr:$addr))>; 1376def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)), 1377 t_addrmode_is2:$addr), 1378 (tSTRHi(tREV16 tGPR:$Rn), t_addrmode_is2:$addr)>; 1379def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)), 1380 t_addrmode_rr:$addr), 1381 (tSTRHr (tREV16 tGPR:$Rn), t_addrmode_rr:$addr)>; 1382 1383// ConstantPool 1384def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>; 1385 1386// GlobalAddress 1387def tLDRLIT_ga_pcrel : PseudoInst<(outs tGPR:$dst), (ins i32imm:$addr), 1388 IIC_iLoadiALU, 1389 [(set tGPR:$dst, 1390 (ARMWrapperPIC tglobaladdr:$addr))]>, 1391 Requires<[IsThumb, DontUseMovt]>; 1392 1393def tLDRLIT_ga_abs : PseudoInst<(outs tGPR:$dst), (ins i32imm:$src), 1394 IIC_iLoad_i, 1395 [(set tGPR:$dst, 1396 (ARMWrapper tglobaladdr:$src))]>, 1397 Requires<[IsThumb, DontUseMovt]>; 1398 1399// TLS globals 1400def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 1401 (tLDRLIT_ga_pcrel tglobaltlsaddr:$addr)>, 1402 Requires<[IsThumb, DontUseMovt]>; 1403def : Pat<(ARMWrapper tglobaltlsaddr:$addr), 1404 (tLDRLIT_ga_abs tglobaltlsaddr:$addr)>, 1405 Requires<[IsThumb, DontUseMovt]>; 1406 1407 1408// JumpTable 1409def : T1Pat<(ARMWrapperJT tjumptable:$dst), 1410 (tLEApcrelJT tjumptable:$dst)>; 1411 1412// Direct calls 1413def : T1Pat<(ARMcall texternalsym:$func), (tBL texternalsym:$func)>, 1414 Requires<[IsThumb]>; 1415 1416// zextload i1 -> zextload i8 1417def : T1Pat<(zextloadi1 t_addrmode_is1:$addr), 1418 (tLDRBi t_addrmode_is1:$addr)>; 1419def : T1Pat<(zextloadi1 t_addrmode_rr:$addr), 1420 (tLDRBr t_addrmode_rr:$addr)>; 1421 1422// extload from the stack -> word load from the stack, as it avoids having to 1423// materialize the base in a separate register. This only works when a word 1424// load puts the byte/halfword value in the same place in the register that the 1425// byte/halfword load would, i.e. when little-endian. 1426def : T1Pat<(extloadi1 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>, 1427 Requires<[IsThumb, IsThumb1Only, IsLE]>; 1428def : T1Pat<(extloadi8 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>, 1429 Requires<[IsThumb, IsThumb1Only, IsLE]>; 1430def : T1Pat<(extloadi16 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>, 1431 Requires<[IsThumb, IsThumb1Only, IsLE]>; 1432 1433// extload -> zextload 1434def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1435def : T1Pat<(extloadi1 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>; 1436def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1437def : T1Pat<(extloadi8 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>; 1438def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>; 1439def : T1Pat<(extloadi16 t_addrmode_rr:$addr), (tLDRHr t_addrmode_rr:$addr)>; 1440 1441// If it's impossible to use [r,r] address mode for sextload, select to 1442// ldr{b|h} + sxt{b|h} instead. 1443def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1444 (tSXTB (tLDRBi t_addrmode_is1:$addr))>, 1445 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1446def : T1Pat<(sextloadi8 t_addrmode_rr:$addr), 1447 (tSXTB (tLDRBr t_addrmode_rr:$addr))>, 1448 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1449def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1450 (tSXTH (tLDRHi t_addrmode_is2:$addr))>, 1451 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1452def : T1Pat<(sextloadi16 t_addrmode_rr:$addr), 1453 (tSXTH (tLDRHr t_addrmode_rr:$addr))>, 1454 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1455 1456def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1457 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>; 1458def : T1Pat<(sextloadi8 t_addrmode_rr:$addr), 1459 (tASRri (tLSLri (tLDRBr t_addrmode_rr:$addr), 24), 24)>; 1460def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1461 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>; 1462def : T1Pat<(sextloadi16 t_addrmode_rr:$addr), 1463 (tASRri (tLSLri (tLDRHr t_addrmode_rr:$addr), 16), 16)>; 1464 1465def : T1Pat<(atomic_load_8 t_addrmode_is1:$src), 1466 (tLDRBi t_addrmode_is1:$src)>; 1467def : T1Pat<(atomic_load_8 t_addrmode_rr:$src), 1468 (tLDRBr t_addrmode_rr:$src)>; 1469def : T1Pat<(atomic_load_16 t_addrmode_is2:$src), 1470 (tLDRHi t_addrmode_is2:$src)>; 1471def : T1Pat<(atomic_load_16 t_addrmode_rr:$src), 1472 (tLDRHr t_addrmode_rr:$src)>; 1473def : T1Pat<(atomic_load_32 t_addrmode_is4:$src), 1474 (tLDRi t_addrmode_is4:$src)>; 1475def : T1Pat<(atomic_load_32 t_addrmode_rr:$src), 1476 (tLDRr t_addrmode_rr:$src)>; 1477def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val), 1478 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>; 1479def : T1Pat<(atomic_store_8 t_addrmode_rr:$ptr, tGPR:$val), 1480 (tSTRBr tGPR:$val, t_addrmode_rr:$ptr)>; 1481def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val), 1482 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>; 1483def : T1Pat<(atomic_store_16 t_addrmode_rr:$ptr, tGPR:$val), 1484 (tSTRHr tGPR:$val, t_addrmode_rr:$ptr)>; 1485def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val), 1486 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>; 1487def : T1Pat<(atomic_store_32 t_addrmode_rr:$ptr, tGPR:$val), 1488 (tSTRr tGPR:$val, t_addrmode_rr:$ptr)>; 1489 1490// Large immediate handling. 1491 1492// Two piece imms. 1493def : T1Pat<(i32 thumb_immshifted:$src), 1494 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), 1495 (thumb_immshifted_shamt imm:$src))>; 1496 1497def : T1Pat<(i32 imm0_255_comp:$src), 1498 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>; 1499 1500def : T1Pat<(i32 imm256_510:$src), 1501 (tADDi8 (tMOVi8 255), 1502 (thumb_imm256_510_addend imm:$src))>; 1503 1504// Pseudo instruction that combines ldr from constpool and add pc. This should 1505// be expanded into two instructions late to allow if-conversion and 1506// scheduling. 1507let isReMaterializable = 1 in 1508def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), 1509 NoItinerary, 1510 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 1511 imm:$cp))]>, 1512 Requires<[IsThumb, IsThumb1Only]>; 1513 1514// Pseudo-instruction for merged POP and return. 1515// FIXME: remove when we have a way to marking a MI with these properties. 1516let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 1517 hasExtraDefRegAllocReq = 1 in 1518def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops), 1519 2, IIC_iPop_Br, [], 1520 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>; 1521 1522// Indirect branch using "mov pc, $Rm" 1523let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1524 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p), 1525 2, IIC_Br, [(brind GPR:$Rm)], 1526 (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>; 1527} 1528 1529 1530// In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00 1531// encoding is available on ARMv6K, but we don't differentiate that finely. 1532def : InstAlias<"nop", (tMOVr R8, R8, 14, 0), 0>, Requires<[IsThumb, IsThumb1Only]>; 1533 1534 1535// For round-trip assembly/disassembly, we have to handle a CPS instruction 1536// without any iflags. That's not, strictly speaking, valid syntax, but it's 1537// a useful extension and assembles to defined behaviour (the insn does 1538// nothing). 1539def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1540def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1541 1542// "neg" is and alias for "rsb rd, rn, #0" 1543def : tInstAlias<"neg${s}${p} $Rd, $Rm", 1544 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>; 1545 1546 1547// Implied destination operand forms for shifts. 1548def : tInstAlias<"lsl${s}${p} $Rdm, $imm", 1549 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>; 1550def : tInstAlias<"lsr${s}${p} $Rdm, $imm", 1551 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1552def : tInstAlias<"asr${s}${p} $Rdm, $imm", 1553 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1554 1555// Pseudo instruction ldr Rt, =immediate 1556def tLDRConstPool 1557 : tAsmPseudo<"ldr${p} $Rt, $immediate", 1558 (ins tGPR:$Rt, const_pool_asm_imm:$immediate, pred:$p)>; 1559