1//===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Thumb specific DAG Nodes. 16// 17 18def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall, 19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 20 SDNPVariadic]>; 21 22def imm_sr_XFORM: SDNodeXForm<imm, [{ 23 unsigned Imm = N->getZExtValue(); 24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), SDLoc(N), MVT::i32); 25}]>; 26def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; } 27def imm_sr : Operand<i32>, PatLeaf<(imm), [{ 28 uint64_t Imm = N->getZExtValue(); 29 return Imm > 0 && Imm <= 32; 30}], imm_sr_XFORM> { 31 let PrintMethod = "printThumbSRImm"; 32 let ParserMatchClass = ThumbSRImmAsmOperand; 33} 34 35def imm_comp_XFORM : SDNodeXForm<imm, [{ 36 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N), 37 MVT::i32); 38}]>; 39 40def imm0_7_neg : PatLeaf<(i32 imm), [{ 41 return (uint32_t)-N->getZExtValue() < 8; 42}], imm_neg_XFORM>; 43 44def imm0_255_comp : PatLeaf<(i32 imm), [{ 45 return ~((uint32_t)N->getZExtValue()) < 256; 46}]>; 47 48def imm8_255 : ImmLeaf<i32, [{ 49 return Imm >= 8 && Imm < 256; 50}]>; 51def imm8_255_neg : PatLeaf<(i32 imm), [{ 52 unsigned Val = -N->getZExtValue(); 53 return Val >= 8 && Val < 256; 54}], imm_neg_XFORM>; 55 56// Break imm's up into two pieces: an immediate + a left shift. This uses 57// thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt 58// to get the val/shift pieces. 59def thumb_immshifted : PatLeaf<(imm), [{ 60 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue()); 61}]>; 62 63def thumb_immshifted_val : SDNodeXForm<imm, [{ 64 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue()); 65 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32); 66}]>; 67 68def thumb_immshifted_shamt : SDNodeXForm<imm, [{ 69 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue()); 70 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32); 71}]>; 72 73// Scaled 4 immediate. 74def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; } 75def t_imm0_1020s4 : Operand<i32> { 76 let PrintMethod = "printThumbS4ImmOperand"; 77 let ParserMatchClass = t_imm0_1020s4_asmoperand; 78 let OperandType = "OPERAND_IMMEDIATE"; 79} 80 81def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; } 82def t_imm0_508s4 : Operand<i32> { 83 let PrintMethod = "printThumbS4ImmOperand"; 84 let ParserMatchClass = t_imm0_508s4_asmoperand; 85 let OperandType = "OPERAND_IMMEDIATE"; 86} 87// Alias use only, so no printer is necessary. 88def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; } 89def t_imm0_508s4_neg : Operand<i32> { 90 let ParserMatchClass = t_imm0_508s4_neg_asmoperand; 91 let OperandType = "OPERAND_IMMEDIATE"; 92} 93 94// Define Thumb specific addressing modes. 95 96// unsigned 8-bit, 2-scaled memory offset 97class OperandUnsignedOffset_b8s2 : AsmOperandClass { 98 let Name = "UnsignedOffset_b8s2"; 99 let PredicateMethod = "isUnsignedOffset<8, 2>"; 100} 101 102def UnsignedOffset_b8s2 : OperandUnsignedOffset_b8s2; 103 104// thumb style PC relative operand. signed, 8 bits magnitude, 105// two bits shift. can be represented as either [pc, #imm], #imm, 106// or relocatable expression... 107def ThumbMemPC : AsmOperandClass { 108 let Name = "ThumbMemPC"; 109} 110 111let OperandType = "OPERAND_PCREL" in { 112def t_brtarget : Operand<OtherVT> { 113 let EncoderMethod = "getThumbBRTargetOpValue"; 114 let DecoderMethod = "DecodeThumbBROperand"; 115} 116 117// ADR instruction labels. 118def t_adrlabel : Operand<i32> { 119 let EncoderMethod = "getThumbAdrLabelOpValue"; 120 let PrintMethod = "printAdrLabelOperand<2>"; 121 let ParserMatchClass = UnsignedOffset_b8s2; 122} 123 124def t_bcctarget : Operand<i32> { 125 let EncoderMethod = "getThumbBCCTargetOpValue"; 126 let DecoderMethod = "DecodeThumbBCCTargetOperand"; 127} 128 129def t_cbtarget : Operand<i32> { 130 let EncoderMethod = "getThumbCBTargetOpValue"; 131 let DecoderMethod = "DecodeThumbCmpBROperand"; 132} 133 134def t_bltarget : Operand<i32> { 135 let EncoderMethod = "getThumbBLTargetOpValue"; 136 let DecoderMethod = "DecodeThumbBLTargetOperand"; 137} 138 139def t_blxtarget : Operand<i32> { 140 let EncoderMethod = "getThumbBLXTargetOpValue"; 141 let DecoderMethod = "DecodeThumbBLXOffset"; 142} 143 144// t_addrmode_pc := <label> => pc + imm8 * 4 145// 146def t_addrmode_pc : MemOperand { 147 let EncoderMethod = "getAddrModePCOpValue"; 148 let DecoderMethod = "DecodeThumbAddrModePC"; 149 let PrintMethod = "printThumbLdrLabelOperand"; 150 let ParserMatchClass = ThumbMemPC; 151} 152} 153 154// t_addrmode_rr := reg + reg 155// 156def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; } 157def t_addrmode_rr : MemOperand, 158 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> { 159 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 160 let PrintMethod = "printThumbAddrModeRROperand"; 161 let DecoderMethod = "DecodeThumbAddrModeRR"; 162 let ParserMatchClass = t_addrmode_rr_asm_operand; 163 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 164} 165 166// t_addrmode_rrs := reg + reg 167// 168// We use separate scaled versions because the Select* functions need 169// to explicitly check for a matching constant and return false here so that 170// the reg+imm forms will match instead. This is a horrible way to do that, 171// as it forces tight coupling between the methods, but it's how selectiondag 172// currently works. 173def t_addrmode_rrs1 : MemOperand, 174 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> { 175 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 176 let PrintMethod = "printThumbAddrModeRROperand"; 177 let DecoderMethod = "DecodeThumbAddrModeRR"; 178 let ParserMatchClass = t_addrmode_rr_asm_operand; 179 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 180} 181def t_addrmode_rrs2 : MemOperand, 182 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> { 183 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 184 let DecoderMethod = "DecodeThumbAddrModeRR"; 185 let PrintMethod = "printThumbAddrModeRROperand"; 186 let ParserMatchClass = t_addrmode_rr_asm_operand; 187 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 188} 189def t_addrmode_rrs4 : MemOperand, 190 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> { 191 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 192 let DecoderMethod = "DecodeThumbAddrModeRR"; 193 let PrintMethod = "printThumbAddrModeRROperand"; 194 let ParserMatchClass = t_addrmode_rr_asm_operand; 195 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 196} 197 198// t_addrmode_is4 := reg + imm5 * 4 199// 200def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; } 201def t_addrmode_is4 : MemOperand, 202 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> { 203 let EncoderMethod = "getAddrModeISOpValue"; 204 let DecoderMethod = "DecodeThumbAddrModeIS"; 205 let PrintMethod = "printThumbAddrModeImm5S4Operand"; 206 let ParserMatchClass = t_addrmode_is4_asm_operand; 207 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 208} 209 210// t_addrmode_is2 := reg + imm5 * 2 211// 212def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; } 213def t_addrmode_is2 : MemOperand, 214 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> { 215 let EncoderMethod = "getAddrModeISOpValue"; 216 let DecoderMethod = "DecodeThumbAddrModeIS"; 217 let PrintMethod = "printThumbAddrModeImm5S2Operand"; 218 let ParserMatchClass = t_addrmode_is2_asm_operand; 219 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 220} 221 222// t_addrmode_is1 := reg + imm5 223// 224def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; } 225def t_addrmode_is1 : MemOperand, 226 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> { 227 let EncoderMethod = "getAddrModeISOpValue"; 228 let DecoderMethod = "DecodeThumbAddrModeIS"; 229 let PrintMethod = "printThumbAddrModeImm5S1Operand"; 230 let ParserMatchClass = t_addrmode_is1_asm_operand; 231 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 232} 233 234// t_addrmode_sp := sp + imm8 * 4 235// 236// FIXME: This really shouldn't have an explicit SP operand at all. It should 237// be implicit, just like in the instruction encoding itself. 238def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; } 239def t_addrmode_sp : MemOperand, 240 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { 241 let EncoderMethod = "getAddrModeThumbSPOpValue"; 242 let DecoderMethod = "DecodeThumbAddrModeSP"; 243 let PrintMethod = "printThumbAddrModeSPOperand"; 244 let ParserMatchClass = t_addrmode_sp_asm_operand; 245 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 246} 247 248//===----------------------------------------------------------------------===// 249// Miscellaneous Instructions. 250// 251 252// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 253// from removing one half of the matched pairs. That breaks PEI, which assumes 254// these will always be in pairs, and asserts if it finds otherwise. Better way? 255let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 256def tADJCALLSTACKUP : 257 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, 258 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, 259 Requires<[IsThumb, IsThumb1Only]>; 260 261def tADJCALLSTACKDOWN : 262 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, 263 [(ARMcallseq_start imm:$amt)]>, 264 Requires<[IsThumb, IsThumb1Only]>; 265} 266 267class T1SystemEncoding<bits<8> opc> 268 : T1Encoding<0b101111> { 269 let Inst{9-8} = 0b11; 270 let Inst{7-0} = opc; 271} 272 273def tHINT : T1pI<(outs), (ins imm0_15:$imm), NoItinerary, "hint", "\t$imm", 274 [(int_arm_hint imm0_15:$imm)]>, 275 T1SystemEncoding<0x00>, 276 Requires<[IsThumb, HasV6M]> { 277 bits<4> imm; 278 let Inst{7-4} = imm; 279} 280 281class tHintAlias<string Asm, dag Result> : tInstAlias<Asm, Result> { 282 let Predicates = [IsThumb, HasV6M]; 283} 284 285def : tHintAlias<"nop$p", (tHINT 0, pred:$p)>; // A8.6.110 286def : tHintAlias<"yield$p", (tHINT 1, pred:$p)>; // A8.6.410 287def : tHintAlias<"wfe$p", (tHINT 2, pred:$p)>; // A8.6.408 288def : tHintAlias<"wfi$p", (tHINT 3, pred:$p)>; // A8.6.409 289def : tHintAlias<"sev$p", (tHINT 4, pred:$p)>; // A8.6.157 290def : tInstAlias<"sevl$p", (tHINT 5, pred:$p)> { 291 let Predicates = [IsThumb2, HasV8]; 292} 293 294// The imm operand $val can be used by a debugger to store more information 295// about the breakpoint. 296def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val", 297 []>, 298 T1Encoding<0b101111> { 299 let Inst{9-8} = 0b10; 300 // A8.6.22 301 bits<8> val; 302 let Inst{7-0} = val; 303} 304// default immediate for breakpoint mnemonic 305def : InstAlias<"bkpt", (tBKPT 0)>, Requires<[IsThumb]>; 306 307def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val", 308 []>, T1Encoding<0b101110>, Requires<[IsThumb, HasV8]> { 309 let Inst{9-6} = 0b1010; 310 bits<6> val; 311 let Inst{5-0} = val; 312} 313 314def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end", 315 []>, T1Encoding<0b101101>, Requires<[IsNotMClass]>, Deprecated<HasV8Ops> { 316 bits<1> end; 317 // A8.6.156 318 let Inst{9-5} = 0b10010; 319 let Inst{4} = 1; 320 let Inst{3} = end; 321 let Inst{2-0} = 0b000; 322} 323 324// Change Processor State is a system instruction -- for disassembly only. 325def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags), 326 NoItinerary, "cps$imod $iflags", []>, 327 T1Misc<0b0110011> { 328 // A8.6.38 & B6.1.1 329 bit imod; 330 bits<3> iflags; 331 332 let Inst{4} = imod; 333 let Inst{3} = 0; 334 let Inst{2-0} = iflags; 335 let DecoderMethod = "DecodeThumbCPS"; 336} 337 338// For both thumb1 and thumb2. 339let isNotDuplicable = 1, isCodeGenOnly = 1 in 340def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "", 341 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>, 342 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 343 // A8.6.6 344 bits<3> dst; 345 let Inst{6-3} = 0b1111; // Rm = pc 346 let Inst{2-0} = dst; 347} 348 349// ADD <Rd>, sp, #<imm8> 350// FIXME: This should not be marked as having side effects, and it should be 351// rematerializable. Clearing the side effect bit causes miscompilations, 352// probably because the instruction can be moved around. 353def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm), 354 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>, 355 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> { 356 // A6.2 & A8.6.8 357 bits<3> dst; 358 bits<8> imm; 359 let Inst{10-8} = dst; 360 let Inst{7-0} = imm; 361 let DecoderMethod = "DecodeThumbAddSpecialReg"; 362} 363 364// Thumb1 frame lowering is rather fragile, we hope to be able to use 365// tADDrSPi, but we may need to insert a sequence that clobbers CPSR. 366def tADDframe : PseudoInst<(outs tGPR:$dst), (ins i32imm:$base, i32imm:$offset), 367 NoItinerary, []>, 368 Requires<[IsThumb, IsThumb1Only]> { 369 let Defs = [CPSR]; 370} 371 372// ADD sp, sp, #<imm7> 373def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 374 IIC_iALUi, "add", "\t$Rdn, $imm", []>, 375 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> { 376 // A6.2.5 & A8.6.8 377 bits<7> imm; 378 let Inst{6-0} = imm; 379 let DecoderMethod = "DecodeThumbAddSPImm"; 380} 381 382// SUB sp, sp, #<imm7> 383// FIXME: The encoding and the ASM string don't match up. 384def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 385 IIC_iALUi, "sub", "\t$Rdn, $imm", []>, 386 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> { 387 // A6.2.5 & A8.6.214 388 bits<7> imm; 389 let Inst{6-0} = imm; 390 let DecoderMethod = "DecodeThumbAddSPImm"; 391} 392 393def : tInstAlias<"add${p} sp, $imm", 394 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 395def : tInstAlias<"add${p} sp, sp, $imm", 396 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 397 398// Can optionally specify SP as a three operand instruction. 399def : tInstAlias<"add${p} sp, sp, $imm", 400 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>; 401def : tInstAlias<"sub${p} sp, sp, $imm", 402 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>; 403 404// ADD <Rm>, sp 405def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr, 406 "add", "\t$Rdn, $sp, $Rn", []>, 407 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 408 // A8.6.9 Encoding T1 409 bits<4> Rdn; 410 let Inst{7} = Rdn{3}; 411 let Inst{6-3} = 0b1101; 412 let Inst{2-0} = Rdn{2-0}; 413 let DecoderMethod = "DecodeThumbAddSPReg"; 414} 415 416// ADD sp, <Rm> 417def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr, 418 "add", "\t$Rdn, $Rm", []>, 419 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 420 // A8.6.9 Encoding T2 421 bits<4> Rm; 422 let Inst{7} = 1; 423 let Inst{6-3} = Rm; 424 let Inst{2-0} = 0b101; 425 let DecoderMethod = "DecodeThumbAddSPReg"; 426} 427 428//===----------------------------------------------------------------------===// 429// Control Flow Instructions. 430// 431 432// Indirect branches 433let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 434 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>, 435 T1Special<{1,1,0,?}>, Sched<[WriteBr]> { 436 // A6.2.3 & A8.6.25 437 bits<4> Rm; 438 let Inst{6-3} = Rm; 439 let Inst{2-0} = 0b000; 440 let Unpredictable{2-0} = 0b111; 441 } 442 def tBXNS : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bxns${p}\t$Rm", []>, 443 Requires<[IsThumb, Has8MSecExt]>, 444 T1Special<{1,1,0,?}>, Sched<[WriteBr]> { 445 bits<4> Rm; 446 let Inst{6-3} = Rm; 447 let Inst{2-0} = 0b100; 448 let Unpredictable{1-0} = 0b11; 449 } 450} 451 452let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 453 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br, 454 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>; 455 456 // Alternative return instruction used by vararg functions. 457 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p), 458 2, IIC_Br, [], 459 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>; 460} 461 462// All calls clobber the non-callee saved registers. SP is marked as a use to 463// prevent stack-pointer assignments that appear immediately before calls from 464// potentially appearing dead. 465let isCall = 1, 466 Defs = [LR], Uses = [SP] in { 467 // Also used for Thumb2 468 def tBL : TIx2<0b11110, 0b11, 1, 469 (outs), (ins pred:$p, t_bltarget:$func), IIC_Br, 470 "bl${p}\t$func", 471 [(ARMtcall tglobaladdr:$func)]>, 472 Requires<[IsThumb]>, Sched<[WriteBrL]> { 473 bits<24> func; 474 let Inst{26} = func{23}; 475 let Inst{25-16} = func{20-11}; 476 let Inst{13} = func{22}; 477 let Inst{11} = func{21}; 478 let Inst{10-0} = func{10-0}; 479 } 480 481 // ARMv5T and above, also used for Thumb2 482 def tBLXi : TIx2<0b11110, 0b11, 0, 483 (outs), (ins pred:$p, t_blxtarget:$func), IIC_Br, 484 "blx${p}\t$func", 485 [(ARMcall tglobaladdr:$func)]>, 486 Requires<[IsThumb, HasV5T, IsNotMClass]>, Sched<[WriteBrL]> { 487 bits<24> func; 488 let Inst{26} = func{23}; 489 let Inst{25-16} = func{20-11}; 490 let Inst{13} = func{22}; 491 let Inst{11} = func{21}; 492 let Inst{10-1} = func{10-1}; 493 let Inst{0} = 0; // func{0} is assumed zero 494 } 495 496 // Also used for Thumb2 497 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br, 498 "blx${p}\t$func", 499 [(ARMtcall GPR:$func)]>, 500 Requires<[IsThumb, HasV5T]>, 501 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24; 502 bits<4> func; 503 let Inst{6-3} = func; 504 let Inst{2-0} = 0b000; 505 } 506 507 // ARMv8-M Security Extensions 508 def tBLXNSr : TI<(outs), (ins pred:$p, GPRnopc:$func), IIC_Br, 509 "blxns${p}\t$func", []>, 510 Requires<[IsThumb, Has8MSecExt]>, 511 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { 512 bits<4> func; 513 let Inst{6-3} = func; 514 let Inst{2-0} = 0b100; 515 let Unpredictable{1-0} = 0b11; 516 } 517 518 // ARMv4T 519 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func), 520 4, IIC_Br, 521 [(ARMcall_nolink tGPR:$func)]>, 522 Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>; 523} 524 525let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 526 let isPredicable = 1 in 527 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br, 528 "b", "\t$target", [(br bb:$target)]>, 529 T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> { 530 bits<11> target; 531 let Inst{10-0} = target; 532 let AsmMatchConverter = "cvtThumbBranches"; 533 } 534 535 // Far jump 536 // Just a pseudo for a tBL instruction. Needed to let regalloc know about 537 // the clobber of LR. 538 let Defs = [LR] in 539 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p), 540 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>, 541 Sched<[WriteBrTbl]>; 542 543 def tBR_JTr : tPseudoInst<(outs), 544 (ins tGPR:$target, i32imm:$jt), 545 0, IIC_Br, 546 [(ARMbrjt tGPR:$target, tjumptable:$jt)]>, 547 Sched<[WriteBrTbl]> { 548 let Size = 2; 549 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 550 } 551} 552 553// FIXME: should be able to write a pattern for ARMBrcond, but can't use 554// a two-value operand where a dag node expects two operands. :( 555let isBranch = 1, isTerminator = 1 in 556 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br, 557 "b${p}\t$target", 558 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, 559 T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> { 560 bits<4> p; 561 bits<8> target; 562 let Inst{11-8} = p; 563 let Inst{7-0} = target; 564 let AsmMatchConverter = "cvtThumbBranches"; 565} 566 567 568// Tail calls 569let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 570 // IOS versions. 571 let Uses = [SP] in { 572 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst), 573 4, IIC_Br, [], 574 (tBX GPR:$dst, (ops 14, zero_reg))>, 575 Requires<[IsThumb]>, Sched<[WriteBr]>; 576 } 577 // tTAILJMPd: MachO version uses a Thumb2 branch (no Thumb1 tail calls 578 // on MachO), so it's in ARMInstrThumb2.td. 579 // Non-MachO version: 580 let Uses = [SP] in { 581 def tTAILJMPdND : tPseudoExpand<(outs), 582 (ins t_brtarget:$dst, pred:$p), 583 4, IIC_Br, [], 584 (tB t_brtarget:$dst, pred:$p)>, 585 Requires<[IsThumb, IsNotMachO]>, Sched<[WriteBr]>; 586 } 587} 588 589 590// A8.6.218 Supervisor Call (Software Interrupt) 591// A8.6.16 B: Encoding T1 592// If Inst{11-8} == 0b1111 then SEE SVC 593let isCall = 1, Uses = [SP] in 594def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br, 595 "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> { 596 bits<8> imm; 597 let Inst{15-12} = 0b1101; 598 let Inst{11-8} = 0b1111; 599 let Inst{7-0} = imm; 600} 601 602// The assembler uses 0xDEFE for a trap instruction. 603let isBarrier = 1, isTerminator = 1 in 604def tTRAP : TI<(outs), (ins), IIC_Br, 605 "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> { 606 let Inst = 0xdefe; 607} 608 609//===----------------------------------------------------------------------===// 610// Load Store Instructions. 611// 612 613// PC-relative loads need to be matched first as constant pool accesses need to 614// always be PC-relative. We do this using AddedComplexity, as the pattern is 615// simpler than the patterns of the other load instructions. 616let canFoldAsLoad = 1, isReMaterializable = 1, AddedComplexity = 10 in 617def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, 618 "ldr", "\t$Rt, $addr", 619 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>, 620 T1Encoding<{0,1,0,0,1,?}> { 621 // A6.2 & A8.6.59 622 bits<3> Rt; 623 bits<8> addr; 624 let Inst{10-8} = Rt; 625 let Inst{7-0} = addr; 626} 627 628// SP-relative loads should be matched before standard immediate-offset loads as 629// it means we avoid having to move SP to another register. 630let canFoldAsLoad = 1 in 631def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i, 632 "ldr", "\t$Rt, $addr", 633 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>, 634 T1LdStSP<{1,?,?}> { 635 bits<3> Rt; 636 bits<8> addr; 637 let Inst{10-8} = Rt; 638 let Inst{7-0} = addr; 639} 640 641// Loads: reg/reg and reg/imm5 642let canFoldAsLoad = 1, isReMaterializable = 1 in 643multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 644 Operand AddrMode_r, Operand AddrMode_i, 645 AddrMode am, InstrItinClass itin_r, 646 InstrItinClass itin_i, string asm, 647 PatFrag opnode> { 648 // Immediate-offset loads should be matched before register-offset loads as 649 // when the offset is a constant it's simpler to first check if it fits in the 650 // immediate offset field then fall back to register-offset if it doesn't. 651 def i : // reg/imm5 652 T1pILdStEncodeImm<imm_opc, 1 /* Load */, 653 (outs tGPR:$Rt), (ins AddrMode_i:$addr), 654 am, itin_i, asm, "\t$Rt, $addr", 655 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>; 656 // Register-offset loads are matched last. 657 def r : // reg/reg 658 T1pILdStEncode<reg_opc, 659 (outs tGPR:$Rt), (ins AddrMode_r:$addr), 660 am, itin_r, asm, "\t$Rt, $addr", 661 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>; 662} 663// Stores: reg/reg and reg/imm5 664multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 665 Operand AddrMode_r, Operand AddrMode_i, 666 AddrMode am, InstrItinClass itin_r, 667 InstrItinClass itin_i, string asm, 668 PatFrag opnode> { 669 def i : // reg/imm5 670 T1pILdStEncodeImm<imm_opc, 0 /* Store */, 671 (outs), (ins tGPR:$Rt, AddrMode_i:$addr), 672 am, itin_i, asm, "\t$Rt, $addr", 673 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>; 674 def r : // reg/reg 675 T1pILdStEncode<reg_opc, 676 (outs), (ins tGPR:$Rt, AddrMode_r:$addr), 677 am, itin_r, asm, "\t$Rt, $addr", 678 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>; 679} 680 681// A8.6.57 & A8.6.60 682defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rr, 683 t_addrmode_is4, AddrModeT1_4, 684 IIC_iLoad_r, IIC_iLoad_i, "ldr", 685 UnOpFrag<(load node:$Src)>>; 686 687// A8.6.64 & A8.6.61 688defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rr, 689 t_addrmode_is1, AddrModeT1_1, 690 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb", 691 UnOpFrag<(zextloadi8 node:$Src)>>; 692 693// A8.6.76 & A8.6.73 694defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rr, 695 t_addrmode_is2, AddrModeT1_2, 696 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh", 697 UnOpFrag<(zextloadi16 node:$Src)>>; 698 699let AddedComplexity = 10 in 700def tLDRSB : // A8.6.80 701 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 702 AddrModeT1_1, IIC_iLoad_bh_r, 703 "ldrsb", "\t$Rt, $addr", 704 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>; 705 706let AddedComplexity = 10 in 707def tLDRSH : // A8.6.84 708 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 709 AddrModeT1_2, IIC_iLoad_bh_r, 710 "ldrsh", "\t$Rt, $addr", 711 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>; 712 713 714def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i, 715 "str", "\t$Rt, $addr", 716 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>, 717 T1LdStSP<{0,?,?}> { 718 bits<3> Rt; 719 bits<8> addr; 720 let Inst{10-8} = Rt; 721 let Inst{7-0} = addr; 722} 723 724// A8.6.194 & A8.6.192 725defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rr, 726 t_addrmode_is4, AddrModeT1_4, 727 IIC_iStore_r, IIC_iStore_i, "str", 728 BinOpFrag<(store node:$LHS, node:$RHS)>>; 729 730// A8.6.197 & A8.6.195 731defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rr, 732 t_addrmode_is1, AddrModeT1_1, 733 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb", 734 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 735 736// A8.6.207 & A8.6.205 737defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rr, 738 t_addrmode_is2, AddrModeT1_2, 739 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh", 740 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 741 742 743//===----------------------------------------------------------------------===// 744// Load / store multiple Instructions. 745// 746 747// These require base address to be written back or one of the loaded regs. 748let hasSideEffects = 0 in { 749 750let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 751def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 752 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> { 753 bits<3> Rn; 754 bits<8> regs; 755 let Inst{10-8} = Rn; 756 let Inst{7-0} = regs; 757} 758 759// Writeback version is just a pseudo, as there's no encoding difference. 760// Writeback happens iff the base register is not in the destination register 761// list. 762let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 763def tLDMIA_UPD : 764 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, 765 "$Rn = $wb", IIC_iLoad_mu>, 766 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> { 767 let Size = 2; 768 let OutOperandList = (outs GPR:$wb); 769 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops); 770 let Pattern = []; 771 let isCodeGenOnly = 1; 772 let isPseudo = 1; 773 list<Predicate> Predicates = [IsThumb]; 774} 775 776// There is no non-writeback version of STM for Thumb. 777let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 778def tSTMIA_UPD : Thumb1I<(outs GPR:$wb), 779 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 780 AddrModeNone, 2, IIC_iStore_mu, 781 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>, 782 T1Encoding<{1,1,0,0,0,?}> { 783 bits<3> Rn; 784 bits<8> regs; 785 let Inst{10-8} = Rn; 786 let Inst{7-0} = regs; 787} 788 789} // hasSideEffects 790 791def : InstAlias<"ldm${p} $Rn!, $regs", 792 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>, 793 Requires<[IsThumb, IsThumb1Only]>; 794 795let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in 796def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 797 IIC_iPop, 798 "pop${p}\t$regs", []>, 799 T1Misc<{1,1,0,?,?,?,?}> { 800 bits<16> regs; 801 let Inst{8} = regs{15}; 802 let Inst{7-0} = regs{7-0}; 803} 804 805let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in 806def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 807 IIC_iStore_m, 808 "push${p}\t$regs", []>, 809 T1Misc<{0,1,0,?,?,?,?}> { 810 bits<16> regs; 811 let Inst{8} = regs{14}; 812 let Inst{7-0} = regs{7-0}; 813} 814 815//===----------------------------------------------------------------------===// 816// Arithmetic Instructions. 817// 818 819// Helper classes for encoding T1pI patterns: 820class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 821 string opc, string asm, list<dag> pattern> 822 : T1pI<oops, iops, itin, opc, asm, pattern>, 823 T1DataProcessing<opA> { 824 bits<3> Rm; 825 bits<3> Rn; 826 let Inst{5-3} = Rm; 827 let Inst{2-0} = Rn; 828} 829class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin, 830 string opc, string asm, list<dag> pattern> 831 : T1pI<oops, iops, itin, opc, asm, pattern>, 832 T1Misc<opA> { 833 bits<3> Rm; 834 bits<3> Rd; 835 let Inst{5-3} = Rm; 836 let Inst{2-0} = Rd; 837} 838 839// Helper classes for encoding T1sI patterns: 840class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 841 string opc, string asm, list<dag> pattern> 842 : T1sI<oops, iops, itin, opc, asm, pattern>, 843 T1DataProcessing<opA> { 844 bits<3> Rd; 845 bits<3> Rn; 846 let Inst{5-3} = Rn; 847 let Inst{2-0} = Rd; 848} 849class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 850 string opc, string asm, list<dag> pattern> 851 : T1sI<oops, iops, itin, opc, asm, pattern>, 852 T1General<opA> { 853 bits<3> Rm; 854 bits<3> Rn; 855 bits<3> Rd; 856 let Inst{8-6} = Rm; 857 let Inst{5-3} = Rn; 858 let Inst{2-0} = Rd; 859} 860class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 861 string opc, string asm, list<dag> pattern> 862 : T1sI<oops, iops, itin, opc, asm, pattern>, 863 T1General<opA> { 864 bits<3> Rd; 865 bits<3> Rm; 866 let Inst{5-3} = Rm; 867 let Inst{2-0} = Rd; 868} 869 870// Helper classes for encoding T1sIt patterns: 871class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 872 string opc, string asm, list<dag> pattern> 873 : T1sIt<oops, iops, itin, opc, asm, pattern>, 874 T1DataProcessing<opA> { 875 bits<3> Rdn; 876 bits<3> Rm; 877 let Inst{5-3} = Rm; 878 let Inst{2-0} = Rdn; 879} 880class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 881 string opc, string asm, list<dag> pattern> 882 : T1sIt<oops, iops, itin, opc, asm, pattern>, 883 T1General<opA> { 884 bits<3> Rdn; 885 bits<8> imm8; 886 let Inst{10-8} = Rdn; 887 let Inst{7-0} = imm8; 888} 889 890// Add with carry register 891let isCommutable = 1, Uses = [CPSR] in 892def tADC : // A8.6.2 893 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr, 894 "adc", "\t$Rdn, $Rm", 895 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 896 897// Add immediate 898def tADDi3 : // A8.6.4 T1 899 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 900 IIC_iALUi, 901 "add", "\t$Rd, $Rm, $imm3", 902 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>, 903 Sched<[WriteALU]> { 904 bits<3> imm3; 905 let Inst{8-6} = imm3; 906} 907 908def tADDi8 : // A8.6.4 T2 909 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), 910 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 911 "add", "\t$Rdn, $imm8", 912 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>, 913 Sched<[WriteALU]>; 914 915// Add register 916let isCommutable = 1 in 917def tADDrr : // A8.6.6 T1 918 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 919 IIC_iALUr, 920 "add", "\t$Rd, $Rn, $Rm", 921 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 922 923let hasSideEffects = 0 in 924def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr, 925 "add", "\t$Rdn, $Rm", []>, 926 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 927 // A8.6.6 T2 928 bits<4> Rdn; 929 bits<4> Rm; 930 let Inst{7} = Rdn{3}; 931 let Inst{6-3} = Rm; 932 let Inst{2-0} = Rdn{2-0}; 933} 934 935// AND register 936let isCommutable = 1 in 937def tAND : // A8.6.12 938 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 939 IIC_iBITr, 940 "and", "\t$Rdn, $Rm", 941 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 942 943// ASR immediate 944def tASRri : // A8.6.14 945 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 946 IIC_iMOVsi, 947 "asr", "\t$Rd, $Rm, $imm5", 948 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>, 949 Sched<[WriteALU]> { 950 bits<5> imm5; 951 let Inst{10-6} = imm5; 952} 953 954// ASR register 955def tASRrr : // A8.6.15 956 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 957 IIC_iMOVsr, 958 "asr", "\t$Rdn, $Rm", 959 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 960 961// BIC register 962def tBIC : // A8.6.20 963 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 964 IIC_iBITr, 965 "bic", "\t$Rdn, $Rm", 966 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>, 967 Sched<[WriteALU]>; 968 969// CMN register 970let isCompare = 1, Defs = [CPSR] in { 971//FIXME: Disable CMN, as CCodes are backwards from compare expectations 972// Compare-to-zero still works out, just not the relationals 973//def tCMN : // A8.6.33 974// T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs), 975// IIC_iCMPr, 976// "cmn", "\t$lhs, $rhs", 977// [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>; 978 979def tCMNz : // A8.6.33 980 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm), 981 IIC_iCMPr, 982 "cmn", "\t$Rn, $Rm", 983 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>; 984 985} // isCompare = 1, Defs = [CPSR] 986 987// CMP immediate 988let isCompare = 1, Defs = [CPSR] in { 989def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi, 990 "cmp", "\t$Rn, $imm8", 991 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>, 992 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> { 993 // A8.6.35 994 bits<3> Rn; 995 bits<8> imm8; 996 let Inst{10-8} = Rn; 997 let Inst{7-0} = imm8; 998} 999 1000// CMP register 1001def tCMPr : // A8.6.36 T1 1002 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm), 1003 IIC_iCMPr, 1004 "cmp", "\t$Rn, $Rm", 1005 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>; 1006 1007def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr, 1008 "cmp", "\t$Rn, $Rm", []>, 1009 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> { 1010 // A8.6.36 T2 1011 bits<4> Rm; 1012 bits<4> Rn; 1013 let Inst{7} = Rn{3}; 1014 let Inst{6-3} = Rm; 1015 let Inst{2-0} = Rn{2-0}; 1016} 1017} // isCompare = 1, Defs = [CPSR] 1018 1019 1020// XOR register 1021let isCommutable = 1 in 1022def tEOR : // A8.6.45 1023 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1024 IIC_iBITr, 1025 "eor", "\t$Rdn, $Rm", 1026 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1027 1028// LSL immediate 1029def tLSLri : // A8.6.88 1030 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5), 1031 IIC_iMOVsi, 1032 "lsl", "\t$Rd, $Rm, $imm5", 1033 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>, 1034 Sched<[WriteALU]> { 1035 bits<5> imm5; 1036 let Inst{10-6} = imm5; 1037} 1038 1039// LSL register 1040def tLSLrr : // A8.6.89 1041 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1042 IIC_iMOVsr, 1043 "lsl", "\t$Rdn, $Rm", 1044 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1045 1046// LSR immediate 1047def tLSRri : // A8.6.90 1048 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 1049 IIC_iMOVsi, 1050 "lsr", "\t$Rd, $Rm, $imm5", 1051 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>, 1052 Sched<[WriteALU]> { 1053 bits<5> imm5; 1054 let Inst{10-6} = imm5; 1055} 1056 1057// LSR register 1058def tLSRrr : // A8.6.91 1059 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1060 IIC_iMOVsr, 1061 "lsr", "\t$Rdn, $Rm", 1062 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1063 1064// Move register 1065let isMoveImm = 1 in 1066def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi, 1067 "mov", "\t$Rd, $imm8", 1068 [(set tGPR:$Rd, imm0_255:$imm8)]>, 1069 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> { 1070 // A8.6.96 1071 bits<3> Rd; 1072 bits<8> imm8; 1073 let Inst{10-8} = Rd; 1074 let Inst{7-0} = imm8; 1075} 1076// Because we have an explicit tMOVSr below, we need an alias to handle 1077// the immediate "movs" form here. Blech. 1078def : tInstAlias <"movs $Rdn, $imm", 1079 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>; 1080 1081// A7-73: MOV(2) - mov setting flag. 1082 1083let hasSideEffects = 0 in { 1084def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone, 1085 2, IIC_iMOVr, 1086 "mov", "\t$Rd, $Rm", "", []>, 1087 T1Special<{1,0,?,?}>, Sched<[WriteALU]> { 1088 // A8.6.97 1089 bits<4> Rd; 1090 bits<4> Rm; 1091 let Inst{7} = Rd{3}; 1092 let Inst{6-3} = Rm; 1093 let Inst{2-0} = Rd{2-0}; 1094} 1095let Defs = [CPSR] in 1096def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr, 1097 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> { 1098 // A8.6.97 1099 bits<3> Rd; 1100 bits<3> Rm; 1101 let Inst{15-6} = 0b0000000000; 1102 let Inst{5-3} = Rm; 1103 let Inst{2-0} = Rd; 1104} 1105} // hasSideEffects 1106 1107// Multiply register 1108let isCommutable = 1 in 1109def tMUL : // A8.6.105 T1 1110 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2, 1111 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd", 1112 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>, 1113 T1DataProcessing<0b1101> { 1114 bits<3> Rd; 1115 bits<3> Rn; 1116 let Inst{5-3} = Rn; 1117 let Inst{2-0} = Rd; 1118 let AsmMatchConverter = "cvtThumbMultiply"; 1119} 1120 1121def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn, 1122 pred:$p)>; 1123 1124// Move inverse register 1125def tMVN : // A8.6.107 1126 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr, 1127 "mvn", "\t$Rd, $Rn", 1128 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>; 1129 1130// Bitwise or register 1131let isCommutable = 1 in 1132def tORR : // A8.6.114 1133 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1134 IIC_iBITr, 1135 "orr", "\t$Rdn, $Rm", 1136 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1137 1138// Swaps 1139def tREV : // A8.6.134 1140 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1141 IIC_iUNAr, 1142 "rev", "\t$Rd, $Rm", 1143 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>, 1144 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1145 1146def tREV16 : // A8.6.135 1147 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1148 IIC_iUNAr, 1149 "rev16", "\t$Rd, $Rm", 1150 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>, 1151 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1152 1153def tREVSH : // A8.6.136 1154 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1155 IIC_iUNAr, 1156 "revsh", "\t$Rd, $Rm", 1157 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>, 1158 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1159 1160// Rotate right register 1161def tROR : // A8.6.139 1162 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1163 IIC_iMOVsr, 1164 "ror", "\t$Rdn, $Rm", 1165 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>, 1166 Sched<[WriteALU]>; 1167 1168// Negate register 1169def tRSB : // A8.6.141 1170 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn), 1171 IIC_iALUi, 1172 "rsb", "\t$Rd, $Rn, #0", 1173 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>; 1174 1175// Subtract with carry register 1176let Uses = [CPSR] in 1177def tSBC : // A8.6.151 1178 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1179 IIC_iALUr, 1180 "sbc", "\t$Rdn, $Rm", 1181 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>, 1182 Sched<[WriteALU]>; 1183 1184// Subtract immediate 1185def tSUBi3 : // A8.6.210 T1 1186 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 1187 IIC_iALUi, 1188 "sub", "\t$Rd, $Rm, $imm3", 1189 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>, 1190 Sched<[WriteALU]> { 1191 bits<3> imm3; 1192 let Inst{8-6} = imm3; 1193} 1194 1195def tSUBi8 : // A8.6.210 T2 1196 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), 1197 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 1198 "sub", "\t$Rdn, $imm8", 1199 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>, 1200 Sched<[WriteALU]>; 1201 1202// Subtract register 1203def tSUBrr : // A8.6.212 1204 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 1205 IIC_iALUr, 1206 "sub", "\t$Rd, $Rn, $Rm", 1207 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>, 1208 Sched<[WriteALU]>; 1209 1210// Sign-extend byte 1211def tSXTB : // A8.6.222 1212 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1213 IIC_iUNAr, 1214 "sxtb", "\t$Rd, $Rm", 1215 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>, 1216 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1217 Sched<[WriteALU]>; 1218 1219// Sign-extend short 1220def tSXTH : // A8.6.224 1221 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1222 IIC_iUNAr, 1223 "sxth", "\t$Rd, $Rm", 1224 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>, 1225 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1226 Sched<[WriteALU]>; 1227 1228// Test 1229let isCompare = 1, isCommutable = 1, Defs = [CPSR] in 1230def tTST : // A8.6.230 1231 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr, 1232 "tst", "\t$Rn, $Rm", 1233 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>, 1234 Sched<[WriteALU]>; 1235 1236// A8.8.247 UDF - Undefined (Encoding T1) 1237def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8", 1238 [(int_arm_undefined imm0_255:$imm8)]>, Encoding16 { 1239 bits<8> imm8; 1240 let Inst{15-12} = 0b1101; 1241 let Inst{11-8} = 0b1110; 1242 let Inst{7-0} = imm8; 1243} 1244 1245// Zero-extend byte 1246def tUXTB : // A8.6.262 1247 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1248 IIC_iUNAr, 1249 "uxtb", "\t$Rd, $Rm", 1250 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>, 1251 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1252 Sched<[WriteALU]>; 1253 1254// Zero-extend short 1255def tUXTH : // A8.6.264 1256 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1257 IIC_iUNAr, 1258 "uxth", "\t$Rd, $Rm", 1259 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>, 1260 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1261 1262// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation. 1263// Expanded after instruction selection into a branch sequence. 1264let usesCustomInserter = 1 in // Expanded after instruction selection. 1265 def tMOVCCr_pseudo : 1266 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, cmovpred:$p), 1267 NoItinerary, 1268 [(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, cmovpred:$p))]>; 1269 1270// tLEApcrel - Load a pc-relative address into a register without offending the 1271// assembler. 1272 1273def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p), 1274 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>, 1275 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> { 1276 bits<3> Rd; 1277 bits<8> addr; 1278 let Inst{10-8} = Rd; 1279 let Inst{7-0} = addr; 1280 let DecoderMethod = "DecodeThumbAddSpecialReg"; 1281} 1282 1283let hasSideEffects = 0, isReMaterializable = 1 in 1284def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), 1285 2, IIC_iALUi, []>, Sched<[WriteALU]>; 1286 1287let hasSideEffects = 1 in 1288def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd), 1289 (ins i32imm:$label, pred:$p), 1290 2, IIC_iALUi, []>, Sched<[WriteALU]>; 1291 1292//===----------------------------------------------------------------------===// 1293// TLS Instructions 1294// 1295 1296// __aeabi_read_tp preserves the registers r1-r3. 1297// This is a pseudo inst so that we can get the encoding right, 1298// complete with fixup for the aeabi_read_tp function. 1299let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in 1300def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br, 1301 [(set R0, ARMthread_pointer)]>, 1302 Sched<[WriteBr]>; 1303 1304//===----------------------------------------------------------------------===// 1305// SJLJ Exception handling intrinsics 1306// 1307 1308// eh_sjlj_setjmp() is an instruction sequence to store the return address and 1309// save #0 in R0 for the non-longjmp case. Since by its nature we may be coming 1310// from some other function to get here, and we're using the stack frame for the 1311// containing function to save/restore registers, we can't keep anything live in 1312// regs across the eh_sjlj_setjmp(), else it will almost certainly have been 1313// tromped upon when we get here from a longjmp(). We force everything out of 1314// registers except for our own input by listing the relevant registers in 1315// Defs. By doing so, we also cause the prologue/epilogue code to actively 1316// preserve all of the callee-saved resgisters, which is exactly what we want. 1317// $val is a scratch register for our use. 1318let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ], 1319 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 1320 usesCustomInserter = 1 in 1321def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val), 1322 AddrModeNone, 0, NoItinerary, "","", 1323 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>; 1324 1325// FIXME: Non-IOS version(s) 1326let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, 1327 Defs = [ R7, LR, SP ] in 1328def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch), 1329 AddrModeNone, 0, IndexModeNone, 1330 Pseudo, NoItinerary, "", "", 1331 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 1332 Requires<[IsThumb]>; 1333 1334//===----------------------------------------------------------------------===// 1335// Non-Instruction Patterns 1336// 1337 1338// Comparisons 1339def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8), 1340 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>; 1341def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm), 1342 (tCMPr tGPR:$Rn, tGPR:$Rm)>; 1343 1344// Add with carry 1345def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs), 1346 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>; 1347def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs), 1348 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>; 1349def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs), 1350 (tADDrr tGPR:$lhs, tGPR:$rhs)>; 1351 1352// Subtract with carry 1353def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs), 1354 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>; 1355def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs), 1356 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>; 1357def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs), 1358 (tSUBrr tGPR:$lhs, tGPR:$rhs)>; 1359 1360// Bswap 16 with load/store 1361def : T1Pat<(srl (bswap (extloadi16 t_addrmode_is2:$addr)), (i32 16)), 1362 (tREV16 (tLDRHi t_addrmode_is2:$addr))>; 1363def : T1Pat<(srl (bswap (extloadi16 t_addrmode_rr:$addr)), (i32 16)), 1364 (tREV16 (tLDRHr t_addrmode_rr:$addr))>; 1365def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)), 1366 t_addrmode_is2:$addr), 1367 (tSTRHi(tREV16 tGPR:$Rn), t_addrmode_is2:$addr)>; 1368def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)), 1369 t_addrmode_rr:$addr), 1370 (tSTRHr (tREV16 tGPR:$Rn), t_addrmode_rr:$addr)>; 1371 1372// ConstantPool 1373def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>; 1374 1375// GlobalAddress 1376def tLDRLIT_ga_pcrel : PseudoInst<(outs tGPR:$dst), (ins i32imm:$addr), 1377 IIC_iLoadiALU, 1378 [(set tGPR:$dst, 1379 (ARMWrapperPIC tglobaladdr:$addr))]>, 1380 Requires<[IsThumb, DontUseMovt]>; 1381 1382def tLDRLIT_ga_abs : PseudoInst<(outs tGPR:$dst), (ins i32imm:$src), 1383 IIC_iLoad_i, 1384 [(set tGPR:$dst, 1385 (ARMWrapper tglobaladdr:$src))]>, 1386 Requires<[IsThumb, DontUseMovt]>; 1387 1388// TLS globals 1389def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 1390 (tLDRLIT_ga_pcrel tglobaltlsaddr:$addr)>, 1391 Requires<[IsThumb, DontUseMovt]>; 1392def : Pat<(ARMWrapper tglobaltlsaddr:$addr), 1393 (tLDRLIT_ga_abs tglobaltlsaddr:$addr)>, 1394 Requires<[IsThumb, DontUseMovt]>; 1395 1396 1397// JumpTable 1398def : T1Pat<(ARMWrapperJT tjumptable:$dst), 1399 (tLEApcrelJT tjumptable:$dst)>; 1400 1401// Direct calls 1402def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>, 1403 Requires<[IsThumb]>; 1404 1405def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>, 1406 Requires<[IsThumb, HasV5T, IsNotMClass]>; 1407 1408// Indirect calls to ARM routines 1409def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>, 1410 Requires<[IsThumb, HasV5T]>; 1411 1412// zextload i1 -> zextload i8 1413def : T1Pat<(zextloadi1 t_addrmode_is1:$addr), 1414 (tLDRBi t_addrmode_is1:$addr)>; 1415def : T1Pat<(zextloadi1 t_addrmode_rr:$addr), 1416 (tLDRBr t_addrmode_rr:$addr)>; 1417 1418// extload from the stack -> word load from the stack, as it avoids having to 1419// materialize the base in a separate register. This only works when a word 1420// load puts the byte/halfword value in the same place in the register that the 1421// byte/halfword load would, i.e. when little-endian. 1422def : T1Pat<(extloadi1 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>, 1423 Requires<[IsThumb, IsThumb1Only, IsLE]>; 1424def : T1Pat<(extloadi8 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>, 1425 Requires<[IsThumb, IsThumb1Only, IsLE]>; 1426def : T1Pat<(extloadi16 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>, 1427 Requires<[IsThumb, IsThumb1Only, IsLE]>; 1428 1429// extload -> zextload 1430def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1431def : T1Pat<(extloadi1 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>; 1432def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1433def : T1Pat<(extloadi8 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>; 1434def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>; 1435def : T1Pat<(extloadi16 t_addrmode_rr:$addr), (tLDRHr t_addrmode_rr:$addr)>; 1436 1437// If it's impossible to use [r,r] address mode for sextload, select to 1438// ldr{b|h} + sxt{b|h} instead. 1439def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1440 (tSXTB (tLDRBi t_addrmode_is1:$addr))>, 1441 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1442def : T1Pat<(sextloadi8 t_addrmode_rr:$addr), 1443 (tSXTB (tLDRBr t_addrmode_rr:$addr))>, 1444 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1445def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1446 (tSXTH (tLDRHi t_addrmode_is2:$addr))>, 1447 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1448def : T1Pat<(sextloadi16 t_addrmode_rr:$addr), 1449 (tSXTH (tLDRHr t_addrmode_rr:$addr))>, 1450 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1451 1452def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1453 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>; 1454def : T1Pat<(sextloadi8 t_addrmode_rr:$addr), 1455 (tASRri (tLSLri (tLDRBr t_addrmode_rr:$addr), 24), 24)>; 1456def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1457 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>; 1458def : T1Pat<(sextloadi16 t_addrmode_rr:$addr), 1459 (tASRri (tLSLri (tLDRHr t_addrmode_rr:$addr), 16), 16)>; 1460 1461def : T1Pat<(atomic_load_8 t_addrmode_is1:$src), 1462 (tLDRBi t_addrmode_is1:$src)>; 1463def : T1Pat<(atomic_load_8 t_addrmode_rr:$src), 1464 (tLDRBr t_addrmode_rr:$src)>; 1465def : T1Pat<(atomic_load_16 t_addrmode_is2:$src), 1466 (tLDRHi t_addrmode_is2:$src)>; 1467def : T1Pat<(atomic_load_16 t_addrmode_rr:$src), 1468 (tLDRHr t_addrmode_rr:$src)>; 1469def : T1Pat<(atomic_load_32 t_addrmode_is4:$src), 1470 (tLDRi t_addrmode_is4:$src)>; 1471def : T1Pat<(atomic_load_32 t_addrmode_rr:$src), 1472 (tLDRr t_addrmode_rr:$src)>; 1473def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val), 1474 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>; 1475def : T1Pat<(atomic_store_8 t_addrmode_rr:$ptr, tGPR:$val), 1476 (tSTRBr tGPR:$val, t_addrmode_rr:$ptr)>; 1477def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val), 1478 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>; 1479def : T1Pat<(atomic_store_16 t_addrmode_rr:$ptr, tGPR:$val), 1480 (tSTRHr tGPR:$val, t_addrmode_rr:$ptr)>; 1481def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val), 1482 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>; 1483def : T1Pat<(atomic_store_32 t_addrmode_rr:$ptr, tGPR:$val), 1484 (tSTRr tGPR:$val, t_addrmode_rr:$ptr)>; 1485 1486// Large immediate handling. 1487 1488// Two piece imms. 1489def : T1Pat<(i32 thumb_immshifted:$src), 1490 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), 1491 (thumb_immshifted_shamt imm:$src))>; 1492 1493def : T1Pat<(i32 imm0_255_comp:$src), 1494 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>; 1495 1496// Pseudo instruction that combines ldr from constpool and add pc. This should 1497// be expanded into two instructions late to allow if-conversion and 1498// scheduling. 1499let isReMaterializable = 1 in 1500def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), 1501 NoItinerary, 1502 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 1503 imm:$cp))]>, 1504 Requires<[IsThumb, IsThumb1Only]>; 1505 1506// Pseudo-instruction for merged POP and return. 1507// FIXME: remove when we have a way to marking a MI with these properties. 1508let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 1509 hasExtraDefRegAllocReq = 1 in 1510def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops), 1511 2, IIC_iPop_Br, [], 1512 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>; 1513 1514// Indirect branch using "mov pc, $Rm" 1515let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1516 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p), 1517 2, IIC_Br, [(brind GPR:$Rm)], 1518 (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>; 1519} 1520 1521 1522// In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00 1523// encoding is available on ARMv6K, but we don't differentiate that finely. 1524def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>; 1525 1526 1527// For round-trip assembly/disassembly, we have to handle a CPS instruction 1528// without any iflags. That's not, strictly speaking, valid syntax, but it's 1529// a useful extension and assembles to defined behaviour (the insn does 1530// nothing). 1531def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1532def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1533 1534// "neg" is and alias for "rsb rd, rn, #0" 1535def : tInstAlias<"neg${s}${p} $Rd, $Rm", 1536 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>; 1537 1538 1539// Implied destination operand forms for shifts. 1540def : tInstAlias<"lsl${s}${p} $Rdm, $imm", 1541 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>; 1542def : tInstAlias<"lsr${s}${p} $Rdm, $imm", 1543 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1544def : tInstAlias<"asr${s}${p} $Rdm, $imm", 1545 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1546