1//===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Thumb specific DAG Nodes. 16// 17 18def imm_sr_XFORM: SDNodeXForm<imm, [{ 19 unsigned Imm = N->getZExtValue(); 20 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), SDLoc(N), MVT::i32); 21}]>; 22def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; } 23def imm_sr : Operand<i32>, PatLeaf<(imm), [{ 24 uint64_t Imm = N->getZExtValue(); 25 return Imm > 0 && Imm <= 32; 26}], imm_sr_XFORM> { 27 let PrintMethod = "printThumbSRImm"; 28 let ParserMatchClass = ThumbSRImmAsmOperand; 29} 30 31def imm_comp_XFORM : SDNodeXForm<imm, [{ 32 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N), 33 MVT::i32); 34}]>; 35 36def imm0_7_neg : PatLeaf<(i32 imm), [{ 37 return (uint32_t)-N->getZExtValue() < 8; 38}], imm_neg_XFORM>; 39 40def imm0_255_comp : PatLeaf<(i32 imm), [{ 41 return ~((uint32_t)N->getZExtValue()) < 256; 42}]>; 43 44def imm8_255 : ImmLeaf<i32, [{ 45 return Imm >= 8 && Imm < 256; 46}]>; 47def imm8_255_neg : PatLeaf<(i32 imm), [{ 48 unsigned Val = -N->getZExtValue(); 49 return Val >= 8 && Val < 256; 50}], imm_neg_XFORM>; 51 52// Break imm's up into two pieces: an immediate + a left shift. This uses 53// thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt 54// to get the val/shift pieces. 55def thumb_immshifted : PatLeaf<(imm), [{ 56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue()); 57}]>; 58 59def thumb_immshifted_val : SDNodeXForm<imm, [{ 60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue()); 61 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32); 62}]>; 63 64def thumb_immshifted_shamt : SDNodeXForm<imm, [{ 65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue()); 66 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32); 67}]>; 68 69def imm256_510 : ImmLeaf<i32, [{ 70 return Imm >= 256 && Imm < 511; 71}]>; 72 73def thumb_imm256_510_addend : SDNodeXForm<imm, [{ 74 return CurDAG->getTargetConstant(N->getZExtValue() - 255, SDLoc(N), MVT::i32); 75}]>; 76 77// Scaled 4 immediate. 78def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; } 79def t_imm0_1020s4 : Operand<i32> { 80 let PrintMethod = "printThumbS4ImmOperand"; 81 let ParserMatchClass = t_imm0_1020s4_asmoperand; 82 let OperandType = "OPERAND_IMMEDIATE"; 83} 84 85def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; } 86def t_imm0_508s4 : Operand<i32> { 87 let PrintMethod = "printThumbS4ImmOperand"; 88 let ParserMatchClass = t_imm0_508s4_asmoperand; 89 let OperandType = "OPERAND_IMMEDIATE"; 90} 91// Alias use only, so no printer is necessary. 92def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; } 93def t_imm0_508s4_neg : Operand<i32> { 94 let ParserMatchClass = t_imm0_508s4_neg_asmoperand; 95 let OperandType = "OPERAND_IMMEDIATE"; 96} 97 98// Define Thumb specific addressing modes. 99 100// unsigned 8-bit, 2-scaled memory offset 101class OperandUnsignedOffset_b8s2 : AsmOperandClass { 102 let Name = "UnsignedOffset_b8s2"; 103 let PredicateMethod = "isUnsignedOffset<8, 2>"; 104} 105 106def UnsignedOffset_b8s2 : OperandUnsignedOffset_b8s2; 107 108// thumb style PC relative operand. signed, 8 bits magnitude, 109// two bits shift. can be represented as either [pc, #imm], #imm, 110// or relocatable expression... 111def ThumbMemPC : AsmOperandClass { 112 let Name = "ThumbMemPC"; 113} 114 115let OperandType = "OPERAND_PCREL" in { 116def t_brtarget : Operand<OtherVT> { 117 let EncoderMethod = "getThumbBRTargetOpValue"; 118 let DecoderMethod = "DecodeThumbBROperand"; 119} 120 121// ADR instruction labels. 122def t_adrlabel : Operand<i32> { 123 let EncoderMethod = "getThumbAdrLabelOpValue"; 124 let PrintMethod = "printAdrLabelOperand<2>"; 125 let ParserMatchClass = UnsignedOffset_b8s2; 126} 127 128 129def thumb_br_target : Operand<OtherVT> { 130 let ParserMatchClass = ThumbBranchTarget; 131 let EncoderMethod = "getThumbBranchTargetOpValue"; 132 let OperandType = "OPERAND_PCREL"; 133} 134 135def thumb_bl_target : Operand<i32> { 136 let ParserMatchClass = ThumbBranchTarget; 137 let EncoderMethod = "getThumbBLTargetOpValue"; 138 let DecoderMethod = "DecodeThumbBLTargetOperand"; 139} 140 141// Target for BLX *from* thumb mode. 142def thumb_blx_target : Operand<i32> { 143 let ParserMatchClass = ARMBranchTarget; 144 let EncoderMethod = "getThumbBLXTargetOpValue"; 145 let DecoderMethod = "DecodeThumbBLXOffset"; 146} 147 148def thumb_bcc_target : Operand<OtherVT> { 149 let ParserMatchClass = ThumbBranchTarget; 150 let EncoderMethod = "getThumbBCCTargetOpValue"; 151 let DecoderMethod = "DecodeThumbBCCTargetOperand"; 152} 153 154def thumb_cb_target : Operand<OtherVT> { 155 let ParserMatchClass = ThumbBranchTarget; 156 let EncoderMethod = "getThumbCBTargetOpValue"; 157 let DecoderMethod = "DecodeThumbCmpBROperand"; 158} 159 160// t_addrmode_pc := <label> => pc + imm8 * 4 161// 162def t_addrmode_pc : MemOperand { 163 let EncoderMethod = "getAddrModePCOpValue"; 164 let DecoderMethod = "DecodeThumbAddrModePC"; 165 let PrintMethod = "printThumbLdrLabelOperand"; 166 let ParserMatchClass = ThumbMemPC; 167} 168} 169 170// t_addrmode_rr := reg + reg 171// 172def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; } 173def t_addrmode_rr : MemOperand, 174 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> { 175 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 176 let PrintMethod = "printThumbAddrModeRROperand"; 177 let DecoderMethod = "DecodeThumbAddrModeRR"; 178 let ParserMatchClass = t_addrmode_rr_asm_operand; 179 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 180} 181 182// t_addrmode_rrs := reg + reg 183// 184// We use separate scaled versions because the Select* functions need 185// to explicitly check for a matching constant and return false here so that 186// the reg+imm forms will match instead. This is a horrible way to do that, 187// as it forces tight coupling between the methods, but it's how selectiondag 188// currently works. 189def t_addrmode_rrs1 : MemOperand, 190 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> { 191 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 192 let PrintMethod = "printThumbAddrModeRROperand"; 193 let DecoderMethod = "DecodeThumbAddrModeRR"; 194 let ParserMatchClass = t_addrmode_rr_asm_operand; 195 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 196} 197def t_addrmode_rrs2 : MemOperand, 198 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> { 199 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 200 let DecoderMethod = "DecodeThumbAddrModeRR"; 201 let PrintMethod = "printThumbAddrModeRROperand"; 202 let ParserMatchClass = t_addrmode_rr_asm_operand; 203 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 204} 205def t_addrmode_rrs4 : MemOperand, 206 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> { 207 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 208 let DecoderMethod = "DecodeThumbAddrModeRR"; 209 let PrintMethod = "printThumbAddrModeRROperand"; 210 let ParserMatchClass = t_addrmode_rr_asm_operand; 211 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 212} 213 214// t_addrmode_is4 := reg + imm5 * 4 215// 216def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; } 217def t_addrmode_is4 : MemOperand, 218 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> { 219 let EncoderMethod = "getAddrModeISOpValue"; 220 let DecoderMethod = "DecodeThumbAddrModeIS"; 221 let PrintMethod = "printThumbAddrModeImm5S4Operand"; 222 let ParserMatchClass = t_addrmode_is4_asm_operand; 223 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 224} 225 226// t_addrmode_is2 := reg + imm5 * 2 227// 228def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; } 229def t_addrmode_is2 : MemOperand, 230 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> { 231 let EncoderMethod = "getAddrModeISOpValue"; 232 let DecoderMethod = "DecodeThumbAddrModeIS"; 233 let PrintMethod = "printThumbAddrModeImm5S2Operand"; 234 let ParserMatchClass = t_addrmode_is2_asm_operand; 235 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 236} 237 238// t_addrmode_is1 := reg + imm5 239// 240def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; } 241def t_addrmode_is1 : MemOperand, 242 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> { 243 let EncoderMethod = "getAddrModeISOpValue"; 244 let DecoderMethod = "DecodeThumbAddrModeIS"; 245 let PrintMethod = "printThumbAddrModeImm5S1Operand"; 246 let ParserMatchClass = t_addrmode_is1_asm_operand; 247 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 248} 249 250// t_addrmode_sp := sp + imm8 * 4 251// 252// FIXME: This really shouldn't have an explicit SP operand at all. It should 253// be implicit, just like in the instruction encoding itself. 254def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; } 255def t_addrmode_sp : MemOperand, 256 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { 257 let EncoderMethod = "getAddrModeThumbSPOpValue"; 258 let DecoderMethod = "DecodeThumbAddrModeSP"; 259 let PrintMethod = "printThumbAddrModeSPOperand"; 260 let ParserMatchClass = t_addrmode_sp_asm_operand; 261 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 262} 263 264//===----------------------------------------------------------------------===// 265// Miscellaneous Instructions. 266// 267 268// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 269// from removing one half of the matched pairs. That breaks PEI, which assumes 270// these will always be in pairs, and asserts if it finds otherwise. Better way? 271let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 272def tADJCALLSTACKUP : 273 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, 274 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, 275 Requires<[IsThumb, IsThumb1Only]>; 276 277def tADJCALLSTACKDOWN : 278 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, 279 [(ARMcallseq_start imm:$amt)]>, 280 Requires<[IsThumb, IsThumb1Only]>; 281} 282 283class T1SystemEncoding<bits<8> opc> 284 : T1Encoding<0b101111> { 285 let Inst{9-8} = 0b11; 286 let Inst{7-0} = opc; 287} 288 289def tHINT : T1pI<(outs), (ins imm0_15:$imm), NoItinerary, "hint", "\t$imm", 290 [(int_arm_hint imm0_15:$imm)]>, 291 T1SystemEncoding<0x00>, 292 Requires<[IsThumb, HasV6M]> { 293 bits<4> imm; 294 let Inst{7-4} = imm; 295} 296 297// Note: When EmitPriority == 1, the alias will be used for printing 298class tHintAlias<string Asm, dag Result, bit EmitPriority = 0> : tInstAlias<Asm, Result, EmitPriority> { 299 let Predicates = [IsThumb, HasV6M]; 300} 301 302def : tHintAlias<"nop$p", (tHINT 0, pred:$p), 1>; // A8.6.110 303def : tHintAlias<"yield$p", (tHINT 1, pred:$p), 1>; // A8.6.410 304def : tHintAlias<"wfe$p", (tHINT 2, pred:$p), 1>; // A8.6.408 305def : tHintAlias<"wfi$p", (tHINT 3, pred:$p), 1>; // A8.6.409 306def : tHintAlias<"sev$p", (tHINT 4, pred:$p), 1>; // A8.6.157 307def : tInstAlias<"sevl$p", (tHINT 5, pred:$p), 1> { 308 let Predicates = [IsThumb2, HasV8]; 309} 310 311// The imm operand $val can be used by a debugger to store more information 312// about the breakpoint. 313def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val", 314 []>, 315 T1Encoding<0b101111> { 316 let Inst{9-8} = 0b10; 317 // A8.6.22 318 bits<8> val; 319 let Inst{7-0} = val; 320} 321// default immediate for breakpoint mnemonic 322def : InstAlias<"bkpt", (tBKPT 0), 0>, Requires<[IsThumb]>; 323 324def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val", 325 []>, T1Encoding<0b101110>, Requires<[IsThumb, HasV8]> { 326 let Inst{9-6} = 0b1010; 327 bits<6> val; 328 let Inst{5-0} = val; 329} 330 331def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end", 332 []>, T1Encoding<0b101101>, Requires<[IsNotMClass]>, Deprecated<HasV8Ops> { 333 bits<1> end; 334 // A8.6.156 335 let Inst{9-5} = 0b10010; 336 let Inst{4} = 1; 337 let Inst{3} = end; 338 let Inst{2-0} = 0b000; 339} 340 341// Change Processor State is a system instruction -- for disassembly only. 342def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags), 343 NoItinerary, "cps$imod $iflags", []>, 344 T1Misc<0b0110011> { 345 // A8.6.38 & B6.1.1 346 bit imod; 347 bits<3> iflags; 348 349 let Inst{4} = imod; 350 let Inst{3} = 0; 351 let Inst{2-0} = iflags; 352 let DecoderMethod = "DecodeThumbCPS"; 353} 354 355// For both thumb1 and thumb2. 356let isNotDuplicable = 1, isCodeGenOnly = 1 in 357def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "", 358 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>, 359 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 360 // A8.6.6 361 bits<3> dst; 362 let Inst{6-3} = 0b1111; // Rm = pc 363 let Inst{2-0} = dst; 364} 365 366// ADD <Rd>, sp, #<imm8> 367// FIXME: This should not be marked as having side effects, and it should be 368// rematerializable. Clearing the side effect bit causes miscompilations, 369// probably because the instruction can be moved around. 370def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm), 371 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>, 372 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> { 373 // A6.2 & A8.6.8 374 bits<3> dst; 375 bits<8> imm; 376 let Inst{10-8} = dst; 377 let Inst{7-0} = imm; 378 let DecoderMethod = "DecodeThumbAddSpecialReg"; 379} 380 381// Thumb1 frame lowering is rather fragile, we hope to be able to use 382// tADDrSPi, but we may need to insert a sequence that clobbers CPSR. 383def tADDframe : PseudoInst<(outs tGPR:$dst), (ins i32imm:$base, i32imm:$offset), 384 NoItinerary, []>, 385 Requires<[IsThumb, IsThumb1Only]> { 386 let Defs = [CPSR]; 387} 388 389// ADD sp, sp, #<imm7> 390def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 391 IIC_iALUi, "add", "\t$Rdn, $imm", []>, 392 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> { 393 // A6.2.5 & A8.6.8 394 bits<7> imm; 395 let Inst{6-0} = imm; 396 let DecoderMethod = "DecodeThumbAddSPImm"; 397} 398 399// SUB sp, sp, #<imm7> 400// FIXME: The encoding and the ASM string don't match up. 401def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 402 IIC_iALUi, "sub", "\t$Rdn, $imm", []>, 403 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> { 404 // A6.2.5 & A8.6.214 405 bits<7> imm; 406 let Inst{6-0} = imm; 407 let DecoderMethod = "DecodeThumbAddSPImm"; 408} 409 410def : tInstAlias<"add${p} sp, $imm", 411 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 412def : tInstAlias<"add${p} sp, sp, $imm", 413 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 414 415// Can optionally specify SP as a three operand instruction. 416def : tInstAlias<"add${p} sp, sp, $imm", 417 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>; 418def : tInstAlias<"sub${p} sp, sp, $imm", 419 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>; 420 421// ADD <Rm>, sp 422def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr, 423 "add", "\t$Rdn, $sp, $Rn", []>, 424 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 425 // A8.6.9 Encoding T1 426 bits<4> Rdn; 427 let Inst{7} = Rdn{3}; 428 let Inst{6-3} = 0b1101; 429 let Inst{2-0} = Rdn{2-0}; 430 let DecoderMethod = "DecodeThumbAddSPReg"; 431} 432 433// ADD sp, <Rm> 434def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr, 435 "add", "\t$Rdn, $Rm", []>, 436 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 437 // A8.6.9 Encoding T2 438 bits<4> Rm; 439 let Inst{7} = 1; 440 let Inst{6-3} = Rm; 441 let Inst{2-0} = 0b101; 442 let DecoderMethod = "DecodeThumbAddSPReg"; 443} 444 445//===----------------------------------------------------------------------===// 446// Control Flow Instructions. 447// 448 449// Indirect branches 450let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 451 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>, 452 T1Special<{1,1,0,?}>, Sched<[WriteBr]> { 453 // A6.2.3 & A8.6.25 454 bits<4> Rm; 455 let Inst{6-3} = Rm; 456 let Inst{2-0} = 0b000; 457 let Unpredictable{2-0} = 0b111; 458 } 459 def tBXNS : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bxns${p}\t$Rm", []>, 460 Requires<[IsThumb, Has8MSecExt]>, 461 T1Special<{1,1,0,?}>, Sched<[WriteBr]> { 462 bits<4> Rm; 463 let Inst{6-3} = Rm; 464 let Inst{2-0} = 0b100; 465 let Unpredictable{1-0} = 0b11; 466 } 467} 468 469let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 470 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br, 471 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>; 472 473 // Alternative return instruction used by vararg functions. 474 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p), 475 2, IIC_Br, [], 476 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>; 477} 478 479// All calls clobber the non-callee saved registers. SP is marked as a use to 480// prevent stack-pointer assignments that appear immediately before calls from 481// potentially appearing dead. 482let isCall = 1, 483 Defs = [LR], Uses = [SP] in { 484 // Also used for Thumb2 485 def tBL : TIx2<0b11110, 0b11, 1, 486 (outs), (ins pred:$p, thumb_bl_target:$func), IIC_Br, 487 "bl${p}\t$func", 488 [(ARMcall tglobaladdr:$func)]>, 489 Requires<[IsThumb]>, Sched<[WriteBrL]> { 490 bits<24> func; 491 let Inst{26} = func{23}; 492 let Inst{25-16} = func{20-11}; 493 let Inst{13} = func{22}; 494 let Inst{11} = func{21}; 495 let Inst{10-0} = func{10-0}; 496 } 497 498 // ARMv5T and above, also used for Thumb2 499 def tBLXi : TIx2<0b11110, 0b11, 0, 500 (outs), (ins pred:$p, thumb_blx_target:$func), IIC_Br, 501 "blx${p}\t$func", []>, 502 Requires<[IsThumb, HasV5T, IsNotMClass]>, Sched<[WriteBrL]> { 503 bits<24> func; 504 let Inst{26} = func{23}; 505 let Inst{25-16} = func{20-11}; 506 let Inst{13} = func{22}; 507 let Inst{11} = func{21}; 508 let Inst{10-1} = func{10-1}; 509 let Inst{0} = 0; // func{0} is assumed zero 510 } 511 512 // Also used for Thumb2 513 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br, 514 "blx${p}\t$func", 515 [(ARMcall GPR:$func)]>, 516 Requires<[IsThumb, HasV5T]>, 517 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24; 518 bits<4> func; 519 let Inst{6-3} = func; 520 let Inst{2-0} = 0b000; 521 } 522 523 // ARMv8-M Security Extensions 524 def tBLXNSr : TI<(outs), (ins pred:$p, GPRnopc:$func), IIC_Br, 525 "blxns${p}\t$func", []>, 526 Requires<[IsThumb, Has8MSecExt]>, 527 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { 528 bits<4> func; 529 let Inst{6-3} = func; 530 let Inst{2-0} = 0b100; 531 let Unpredictable{1-0} = 0b11; 532 } 533 534 // ARMv4T 535 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func), 536 4, IIC_Br, 537 [(ARMcall_nolink tGPR:$func)]>, 538 Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>; 539} 540 541let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 542 let isPredicable = 1 in 543 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br, 544 "b", "\t$target", [(br bb:$target)]>, 545 T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> { 546 bits<11> target; 547 let Inst{10-0} = target; 548 let AsmMatchConverter = "cvtThumbBranches"; 549 } 550 551 // Far jump 552 // Just a pseudo for a tBL instruction. Needed to let regalloc know about 553 // the clobber of LR. 554 let Defs = [LR] in 555 def tBfar : tPseudoExpand<(outs), (ins thumb_bl_target:$target, pred:$p), 556 4, IIC_Br, [], 557 (tBL pred:$p, thumb_bl_target:$target)>, 558 Sched<[WriteBrTbl]>; 559 560 def tBR_JTr : tPseudoInst<(outs), 561 (ins tGPR:$target, i32imm:$jt), 562 0, IIC_Br, 563 [(ARMbrjt tGPR:$target, tjumptable:$jt)]>, 564 Sched<[WriteBrTbl]> { 565 let Size = 2; 566 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 567 } 568} 569 570// FIXME: should be able to write a pattern for ARMBrcond, but can't use 571// a two-value operand where a dag node expects two operands. :( 572let isBranch = 1, isTerminator = 1 in 573 def tBcc : T1I<(outs), (ins thumb_bcc_target:$target, pred:$p), IIC_Br, 574 "b${p}\t$target", 575 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, 576 T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> { 577 bits<4> p; 578 bits<8> target; 579 let Inst{11-8} = p; 580 let Inst{7-0} = target; 581 let AsmMatchConverter = "cvtThumbBranches"; 582} 583 584 585// Tail calls 586let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 587 // IOS versions. 588 let Uses = [SP] in { 589 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst), 590 4, IIC_Br, [], 591 (tBX GPR:$dst, (ops 14, zero_reg))>, 592 Requires<[IsThumb]>, Sched<[WriteBr]>; 593 } 594 // tTAILJMPd: MachO version uses a Thumb2 branch (no Thumb1 tail calls 595 // on MachO), so it's in ARMInstrThumb2.td. 596 // Non-MachO version: 597 let Uses = [SP] in { 598 def tTAILJMPdND : tPseudoExpand<(outs), 599 (ins t_brtarget:$dst, pred:$p), 600 4, IIC_Br, [], 601 (tB t_brtarget:$dst, pred:$p)>, 602 Requires<[IsThumb, IsNotMachO]>, Sched<[WriteBr]>; 603 } 604} 605 606 607// A8.6.218 Supervisor Call (Software Interrupt) 608// A8.6.16 B: Encoding T1 609// If Inst{11-8} == 0b1111 then SEE SVC 610let isCall = 1, Uses = [SP] in 611def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br, 612 "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> { 613 bits<8> imm; 614 let Inst{15-12} = 0b1101; 615 let Inst{11-8} = 0b1111; 616 let Inst{7-0} = imm; 617} 618 619// The assembler uses 0xDEFE for a trap instruction. 620let isBarrier = 1, isTerminator = 1 in 621def tTRAP : TI<(outs), (ins), IIC_Br, 622 "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> { 623 let Inst = 0xdefe; 624} 625 626//===----------------------------------------------------------------------===// 627// Load Store Instructions. 628// 629 630// PC-relative loads need to be matched first as constant pool accesses need to 631// always be PC-relative. We do this using AddedComplexity, as the pattern is 632// simpler than the patterns of the other load instructions. 633let canFoldAsLoad = 1, isReMaterializable = 1, AddedComplexity = 10 in 634def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, 635 "ldr", "\t$Rt, $addr", 636 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>, 637 T1Encoding<{0,1,0,0,1,?}> { 638 // A6.2 & A8.6.59 639 bits<3> Rt; 640 bits<8> addr; 641 let Inst{10-8} = Rt; 642 let Inst{7-0} = addr; 643} 644 645// SP-relative loads should be matched before standard immediate-offset loads as 646// it means we avoid having to move SP to another register. 647let canFoldAsLoad = 1 in 648def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i, 649 "ldr", "\t$Rt, $addr", 650 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>, 651 T1LdStSP<{1,?,?}> { 652 bits<3> Rt; 653 bits<8> addr; 654 let Inst{10-8} = Rt; 655 let Inst{7-0} = addr; 656} 657 658// Loads: reg/reg and reg/imm5 659let canFoldAsLoad = 1, isReMaterializable = 1 in 660multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 661 Operand AddrMode_r, Operand AddrMode_i, 662 AddrMode am, InstrItinClass itin_r, 663 InstrItinClass itin_i, string asm, 664 PatFrag opnode> { 665 // Immediate-offset loads should be matched before register-offset loads as 666 // when the offset is a constant it's simpler to first check if it fits in the 667 // immediate offset field then fall back to register-offset if it doesn't. 668 def i : // reg/imm5 669 T1pILdStEncodeImm<imm_opc, 1 /* Load */, 670 (outs tGPR:$Rt), (ins AddrMode_i:$addr), 671 am, itin_i, asm, "\t$Rt, $addr", 672 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>; 673 // Register-offset loads are matched last. 674 def r : // reg/reg 675 T1pILdStEncode<reg_opc, 676 (outs tGPR:$Rt), (ins AddrMode_r:$addr), 677 am, itin_r, asm, "\t$Rt, $addr", 678 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>; 679} 680// Stores: reg/reg and reg/imm5 681multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 682 Operand AddrMode_r, Operand AddrMode_i, 683 AddrMode am, InstrItinClass itin_r, 684 InstrItinClass itin_i, string asm, 685 PatFrag opnode> { 686 def i : // reg/imm5 687 T1pILdStEncodeImm<imm_opc, 0 /* Store */, 688 (outs), (ins tGPR:$Rt, AddrMode_i:$addr), 689 am, itin_i, asm, "\t$Rt, $addr", 690 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>; 691 def r : // reg/reg 692 T1pILdStEncode<reg_opc, 693 (outs), (ins tGPR:$Rt, AddrMode_r:$addr), 694 am, itin_r, asm, "\t$Rt, $addr", 695 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>; 696} 697 698// A8.6.57 & A8.6.60 699defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rr, 700 t_addrmode_is4, AddrModeT1_4, 701 IIC_iLoad_r, IIC_iLoad_i, "ldr", 702 load>; 703 704// A8.6.64 & A8.6.61 705defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rr, 706 t_addrmode_is1, AddrModeT1_1, 707 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb", 708 zextloadi8>; 709 710// A8.6.76 & A8.6.73 711defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rr, 712 t_addrmode_is2, AddrModeT1_2, 713 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh", 714 zextloadi16>; 715 716let AddedComplexity = 10 in 717def tLDRSB : // A8.6.80 718 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 719 AddrModeT1_1, IIC_iLoad_bh_r, 720 "ldrsb", "\t$Rt, $addr", 721 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>; 722 723let AddedComplexity = 10 in 724def tLDRSH : // A8.6.84 725 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 726 AddrModeT1_2, IIC_iLoad_bh_r, 727 "ldrsh", "\t$Rt, $addr", 728 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>; 729 730 731def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i, 732 "str", "\t$Rt, $addr", 733 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>, 734 T1LdStSP<{0,?,?}> { 735 bits<3> Rt; 736 bits<8> addr; 737 let Inst{10-8} = Rt; 738 let Inst{7-0} = addr; 739} 740 741// A8.6.194 & A8.6.192 742defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rr, 743 t_addrmode_is4, AddrModeT1_4, 744 IIC_iStore_r, IIC_iStore_i, "str", 745 store>; 746 747// A8.6.197 & A8.6.195 748defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rr, 749 t_addrmode_is1, AddrModeT1_1, 750 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb", 751 truncstorei8>; 752 753// A8.6.207 & A8.6.205 754defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rr, 755 t_addrmode_is2, AddrModeT1_2, 756 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh", 757 truncstorei16>; 758 759 760//===----------------------------------------------------------------------===// 761// Load / store multiple Instructions. 762// 763 764// These require base address to be written back or one of the loaded regs. 765let hasSideEffects = 0 in { 766 767let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 768def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 769 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> { 770 bits<3> Rn; 771 bits<8> regs; 772 let Inst{10-8} = Rn; 773 let Inst{7-0} = regs; 774} 775 776// Writeback version is just a pseudo, as there's no encoding difference. 777// Writeback happens iff the base register is not in the destination register 778// list. 779let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 780def tLDMIA_UPD : 781 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, 782 "$Rn = $wb", IIC_iLoad_mu>, 783 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> { 784 let Size = 2; 785 let OutOperandList = (outs GPR:$wb); 786 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops); 787 let Pattern = []; 788 let isCodeGenOnly = 1; 789 let isPseudo = 1; 790 list<Predicate> Predicates = [IsThumb]; 791} 792 793// There is no non-writeback version of STM for Thumb. 794let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 795def tSTMIA_UPD : Thumb1I<(outs GPR:$wb), 796 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 797 AddrModeNone, 2, IIC_iStore_mu, 798 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>, 799 T1Encoding<{1,1,0,0,0,?}> { 800 bits<3> Rn; 801 bits<8> regs; 802 let Inst{10-8} = Rn; 803 let Inst{7-0} = regs; 804} 805 806} // hasSideEffects 807 808def : InstAlias<"ldm${p} $Rn!, $regs", 809 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs), 0>, 810 Requires<[IsThumb, IsThumb1Only]>; 811 812let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in 813def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 814 IIC_iPop, 815 "pop${p}\t$regs", []>, 816 T1Misc<{1,1,0,?,?,?,?}> { 817 bits<16> regs; 818 let Inst{8} = regs{15}; 819 let Inst{7-0} = regs{7-0}; 820} 821 822let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in 823def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 824 IIC_iStore_m, 825 "push${p}\t$regs", []>, 826 T1Misc<{0,1,0,?,?,?,?}> { 827 bits<16> regs; 828 let Inst{8} = regs{14}; 829 let Inst{7-0} = regs{7-0}; 830} 831 832//===----------------------------------------------------------------------===// 833// Arithmetic Instructions. 834// 835 836// Helper classes for encoding T1pI patterns: 837class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 838 string opc, string asm, list<dag> pattern> 839 : T1pI<oops, iops, itin, opc, asm, pattern>, 840 T1DataProcessing<opA> { 841 bits<3> Rm; 842 bits<3> Rn; 843 let Inst{5-3} = Rm; 844 let Inst{2-0} = Rn; 845} 846class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin, 847 string opc, string asm, list<dag> pattern> 848 : T1pI<oops, iops, itin, opc, asm, pattern>, 849 T1Misc<opA> { 850 bits<3> Rm; 851 bits<3> Rd; 852 let Inst{5-3} = Rm; 853 let Inst{2-0} = Rd; 854} 855 856// Helper classes for encoding T1sI patterns: 857class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 858 string opc, string asm, list<dag> pattern> 859 : T1sI<oops, iops, itin, opc, asm, pattern>, 860 T1DataProcessing<opA> { 861 bits<3> Rd; 862 bits<3> Rn; 863 let Inst{5-3} = Rn; 864 let Inst{2-0} = Rd; 865} 866class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 867 string opc, string asm, list<dag> pattern> 868 : T1sI<oops, iops, itin, opc, asm, pattern>, 869 T1General<opA> { 870 bits<3> Rm; 871 bits<3> Rn; 872 bits<3> Rd; 873 let Inst{8-6} = Rm; 874 let Inst{5-3} = Rn; 875 let Inst{2-0} = Rd; 876} 877class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 878 string opc, string asm, list<dag> pattern> 879 : T1sI<oops, iops, itin, opc, asm, pattern>, 880 T1General<opA> { 881 bits<3> Rd; 882 bits<3> Rm; 883 let Inst{5-3} = Rm; 884 let Inst{2-0} = Rd; 885} 886 887// Helper classes for encoding T1sIt patterns: 888class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 889 string opc, string asm, list<dag> pattern> 890 : T1sIt<oops, iops, itin, opc, asm, pattern>, 891 T1DataProcessing<opA> { 892 bits<3> Rdn; 893 bits<3> Rm; 894 let Inst{5-3} = Rm; 895 let Inst{2-0} = Rdn; 896} 897class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 898 string opc, string asm, list<dag> pattern> 899 : T1sIt<oops, iops, itin, opc, asm, pattern>, 900 T1General<opA> { 901 bits<3> Rdn; 902 bits<8> imm8; 903 let Inst{10-8} = Rdn; 904 let Inst{7-0} = imm8; 905} 906 907let isAdd = 1 in { 908 // Add with carry register 909 let isCommutable = 1, Uses = [CPSR] in 910 def tADC : // A8.6.2 911 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr, 912 "adc", "\t$Rdn, $Rm", 913 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 914 915 // Add immediate 916 def tADDi3 : // A8.6.4 T1 917 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 918 IIC_iALUi, 919 "add", "\t$Rd, $Rm, $imm3", 920 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>, 921 Sched<[WriteALU]> { 922 bits<3> imm3; 923 let Inst{8-6} = imm3; 924 } 925 926 def tADDi8 : // A8.6.4 T2 927 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), 928 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 929 "add", "\t$Rdn, $imm8", 930 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>, 931 Sched<[WriteALU]>; 932 933 // Add register 934 let isCommutable = 1 in 935 def tADDrr : // A8.6.6 T1 936 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 937 IIC_iALUr, 938 "add", "\t$Rd, $Rn, $Rm", 939 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 940 941 let hasSideEffects = 0 in 942 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr, 943 "add", "\t$Rdn, $Rm", []>, 944 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 945 // A8.6.6 T2 946 bits<4> Rdn; 947 bits<4> Rm; 948 let Inst{7} = Rdn{3}; 949 let Inst{6-3} = Rm; 950 let Inst{2-0} = Rdn{2-0}; 951 } 952} 953 954// AND register 955let isCommutable = 1 in 956def tAND : // A8.6.12 957 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 958 IIC_iBITr, 959 "and", "\t$Rdn, $Rm", 960 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 961 962// ASR immediate 963def tASRri : // A8.6.14 964 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 965 IIC_iMOVsi, 966 "asr", "\t$Rd, $Rm, $imm5", 967 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>, 968 Sched<[WriteALU]> { 969 bits<5> imm5; 970 let Inst{10-6} = imm5; 971} 972 973// ASR register 974def tASRrr : // A8.6.15 975 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 976 IIC_iMOVsr, 977 "asr", "\t$Rdn, $Rm", 978 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 979 980// BIC register 981def tBIC : // A8.6.20 982 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 983 IIC_iBITr, 984 "bic", "\t$Rdn, $Rm", 985 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>, 986 Sched<[WriteALU]>; 987 988// CMN register 989let isCompare = 1, Defs = [CPSR] in { 990//FIXME: Disable CMN, as CCodes are backwards from compare expectations 991// Compare-to-zero still works out, just not the relationals 992//def tCMN : // A8.6.33 993// T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs), 994// IIC_iCMPr, 995// "cmn", "\t$lhs, $rhs", 996// [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>; 997 998def tCMNz : // A8.6.33 999 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm), 1000 IIC_iCMPr, 1001 "cmn", "\t$Rn, $Rm", 1002 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>; 1003 1004} // isCompare = 1, Defs = [CPSR] 1005 1006// CMP immediate 1007let isCompare = 1, Defs = [CPSR] in { 1008def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi, 1009 "cmp", "\t$Rn, $imm8", 1010 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>, 1011 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> { 1012 // A8.6.35 1013 bits<3> Rn; 1014 bits<8> imm8; 1015 let Inst{10-8} = Rn; 1016 let Inst{7-0} = imm8; 1017} 1018 1019// CMP register 1020def tCMPr : // A8.6.36 T1 1021 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm), 1022 IIC_iCMPr, 1023 "cmp", "\t$Rn, $Rm", 1024 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>; 1025 1026def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr, 1027 "cmp", "\t$Rn, $Rm", []>, 1028 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> { 1029 // A8.6.36 T2 1030 bits<4> Rm; 1031 bits<4> Rn; 1032 let Inst{7} = Rn{3}; 1033 let Inst{6-3} = Rm; 1034 let Inst{2-0} = Rn{2-0}; 1035} 1036} // isCompare = 1, Defs = [CPSR] 1037 1038 1039// XOR register 1040let isCommutable = 1 in 1041def tEOR : // A8.6.45 1042 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1043 IIC_iBITr, 1044 "eor", "\t$Rdn, $Rm", 1045 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1046 1047// LSL immediate 1048def tLSLri : // A8.6.88 1049 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5), 1050 IIC_iMOVsi, 1051 "lsl", "\t$Rd, $Rm, $imm5", 1052 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>, 1053 Sched<[WriteALU]> { 1054 bits<5> imm5; 1055 let Inst{10-6} = imm5; 1056} 1057 1058// LSL register 1059def tLSLrr : // A8.6.89 1060 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1061 IIC_iMOVsr, 1062 "lsl", "\t$Rdn, $Rm", 1063 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1064 1065// LSR immediate 1066def tLSRri : // A8.6.90 1067 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 1068 IIC_iMOVsi, 1069 "lsr", "\t$Rd, $Rm, $imm5", 1070 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>, 1071 Sched<[WriteALU]> { 1072 bits<5> imm5; 1073 let Inst{10-6} = imm5; 1074} 1075 1076// LSR register 1077def tLSRrr : // A8.6.91 1078 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1079 IIC_iMOVsr, 1080 "lsr", "\t$Rdn, $Rm", 1081 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1082 1083// Move register 1084let isMoveImm = 1 in 1085def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi, 1086 "mov", "\t$Rd, $imm8", 1087 [(set tGPR:$Rd, imm0_255:$imm8)]>, 1088 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> { 1089 // A8.6.96 1090 bits<3> Rd; 1091 bits<8> imm8; 1092 let Inst{10-8} = Rd; 1093 let Inst{7-0} = imm8; 1094} 1095// Because we have an explicit tMOVSr below, we need an alias to handle 1096// the immediate "movs" form here. Blech. 1097def : tInstAlias <"movs $Rdn, $imm", 1098 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>; 1099 1100// A7-73: MOV(2) - mov setting flag. 1101 1102let hasSideEffects = 0 in { 1103def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone, 1104 2, IIC_iMOVr, 1105 "mov", "\t$Rd, $Rm", "", []>, 1106 T1Special<{1,0,?,?}>, Sched<[WriteALU]> { 1107 // A8.6.97 1108 bits<4> Rd; 1109 bits<4> Rm; 1110 let Inst{7} = Rd{3}; 1111 let Inst{6-3} = Rm; 1112 let Inst{2-0} = Rd{2-0}; 1113} 1114let Defs = [CPSR] in 1115def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr, 1116 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> { 1117 // A8.6.97 1118 bits<3> Rd; 1119 bits<3> Rm; 1120 let Inst{15-6} = 0b0000000000; 1121 let Inst{5-3} = Rm; 1122 let Inst{2-0} = Rd; 1123} 1124} // hasSideEffects 1125 1126// Multiply register 1127let isCommutable = 1 in 1128def tMUL : // A8.6.105 T1 1129 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2, 1130 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd", 1131 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>, 1132 T1DataProcessing<0b1101> { 1133 bits<3> Rd; 1134 bits<3> Rn; 1135 let Inst{5-3} = Rn; 1136 let Inst{2-0} = Rd; 1137 let AsmMatchConverter = "cvtThumbMultiply"; 1138} 1139 1140def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn, 1141 pred:$p)>; 1142 1143// Move inverse register 1144def tMVN : // A8.6.107 1145 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr, 1146 "mvn", "\t$Rd, $Rn", 1147 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>; 1148 1149// Bitwise or register 1150let isCommutable = 1 in 1151def tORR : // A8.6.114 1152 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1153 IIC_iBITr, 1154 "orr", "\t$Rdn, $Rm", 1155 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1156 1157// Swaps 1158def tREV : // A8.6.134 1159 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1160 IIC_iUNAr, 1161 "rev", "\t$Rd, $Rm", 1162 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>, 1163 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1164 1165def tREV16 : // A8.6.135 1166 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1167 IIC_iUNAr, 1168 "rev16", "\t$Rd, $Rm", 1169 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>, 1170 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1171 1172def tREVSH : // A8.6.136 1173 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1174 IIC_iUNAr, 1175 "revsh", "\t$Rd, $Rm", 1176 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>, 1177 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1178 1179// Rotate right register 1180def tROR : // A8.6.139 1181 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1182 IIC_iMOVsr, 1183 "ror", "\t$Rdn, $Rm", 1184 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>, 1185 Sched<[WriteALU]>; 1186 1187// Negate register 1188def tRSB : // A8.6.141 1189 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn), 1190 IIC_iALUi, 1191 "rsb", "\t$Rd, $Rn, #0", 1192 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>; 1193 1194// Subtract with carry register 1195let Uses = [CPSR] in 1196def tSBC : // A8.6.151 1197 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1198 IIC_iALUr, 1199 "sbc", "\t$Rdn, $Rm", 1200 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>, 1201 Sched<[WriteALU]>; 1202 1203// Subtract immediate 1204def tSUBi3 : // A8.6.210 T1 1205 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 1206 IIC_iALUi, 1207 "sub", "\t$Rd, $Rm, $imm3", 1208 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>, 1209 Sched<[WriteALU]> { 1210 bits<3> imm3; 1211 let Inst{8-6} = imm3; 1212} 1213 1214def tSUBi8 : // A8.6.210 T2 1215 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), 1216 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 1217 "sub", "\t$Rdn, $imm8", 1218 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>, 1219 Sched<[WriteALU]>; 1220 1221// Subtract register 1222def tSUBrr : // A8.6.212 1223 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 1224 IIC_iALUr, 1225 "sub", "\t$Rd, $Rn, $Rm", 1226 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>, 1227 Sched<[WriteALU]>; 1228 1229// Sign-extend byte 1230def tSXTB : // A8.6.222 1231 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1232 IIC_iUNAr, 1233 "sxtb", "\t$Rd, $Rm", 1234 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>, 1235 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1236 Sched<[WriteALU]>; 1237 1238// Sign-extend short 1239def tSXTH : // A8.6.224 1240 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1241 IIC_iUNAr, 1242 "sxth", "\t$Rd, $Rm", 1243 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>, 1244 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1245 Sched<[WriteALU]>; 1246 1247// Test 1248let isCompare = 1, isCommutable = 1, Defs = [CPSR] in 1249def tTST : // A8.6.230 1250 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr, 1251 "tst", "\t$Rn, $Rm", 1252 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>, 1253 Sched<[WriteALU]>; 1254 1255// A8.8.247 UDF - Undefined (Encoding T1) 1256def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8", 1257 [(int_arm_undefined imm0_255:$imm8)]>, Encoding16 { 1258 bits<8> imm8; 1259 let Inst{15-12} = 0b1101; 1260 let Inst{11-8} = 0b1110; 1261 let Inst{7-0} = imm8; 1262} 1263 1264def t__brkdiv0 : TI<(outs), (ins), IIC_Br, "__brkdiv0", 1265 [(int_arm_undefined 249)]>, Encoding16, 1266 Requires<[IsThumb, IsWindows]> { 1267 let Inst = 0xdef9; 1268 let isTerminator = 1; 1269} 1270 1271// Zero-extend byte 1272def tUXTB : // A8.6.262 1273 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1274 IIC_iUNAr, 1275 "uxtb", "\t$Rd, $Rm", 1276 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>, 1277 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1278 Sched<[WriteALU]>; 1279 1280// Zero-extend short 1281def tUXTH : // A8.6.264 1282 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1283 IIC_iUNAr, 1284 "uxth", "\t$Rd, $Rm", 1285 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>, 1286 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1287 1288// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation. 1289// Expanded after instruction selection into a branch sequence. 1290let usesCustomInserter = 1 in // Expanded after instruction selection. 1291 def tMOVCCr_pseudo : 1292 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, cmovpred:$p), 1293 NoItinerary, 1294 [(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, cmovpred:$p))]>; 1295 1296// tLEApcrel - Load a pc-relative address into a register without offending the 1297// assembler. 1298 1299def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p), 1300 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>, 1301 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> { 1302 bits<3> Rd; 1303 bits<8> addr; 1304 let Inst{10-8} = Rd; 1305 let Inst{7-0} = addr; 1306 let DecoderMethod = "DecodeThumbAddSpecialReg"; 1307} 1308 1309let hasSideEffects = 0, isReMaterializable = 1 in 1310def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), 1311 2, IIC_iALUi, []>, Sched<[WriteALU]>; 1312 1313let hasSideEffects = 1 in 1314def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd), 1315 (ins i32imm:$label, pred:$p), 1316 2, IIC_iALUi, []>, Sched<[WriteALU]>; 1317 1318// Thumb-1 doesn't have the TBB or TBH instructions, but we can synthesize them 1319// and make use of the same compressed jump table format as Thumb-2. 1320let Size = 2 in { 1321def tTBB_JT : tPseudoInst<(outs), 1322 (ins tGPR:$base, tGPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>, 1323 Sched<[WriteBr]>; 1324 1325def tTBH_JT : tPseudoInst<(outs), 1326 (ins tGPR:$base, tGPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>, 1327 Sched<[WriteBr]>; 1328} 1329 1330//===----------------------------------------------------------------------===// 1331// TLS Instructions 1332// 1333 1334// __aeabi_read_tp preserves the registers r1-r3. 1335// This is a pseudo inst so that we can get the encoding right, 1336// complete with fixup for the aeabi_read_tp function. 1337let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in 1338def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br, 1339 [(set R0, ARMthread_pointer)]>, 1340 Sched<[WriteBr]>; 1341 1342//===----------------------------------------------------------------------===// 1343// SJLJ Exception handling intrinsics 1344// 1345 1346// eh_sjlj_setjmp() is an instruction sequence to store the return address and 1347// save #0 in R0 for the non-longjmp case. Since by its nature we may be coming 1348// from some other function to get here, and we're using the stack frame for the 1349// containing function to save/restore registers, we can't keep anything live in 1350// regs across the eh_sjlj_setjmp(), else it will almost certainly have been 1351// tromped upon when we get here from a longjmp(). We force everything out of 1352// registers except for our own input by listing the relevant registers in 1353// Defs. By doing so, we also cause the prologue/epilogue code to actively 1354// preserve all of the callee-saved resgisters, which is exactly what we want. 1355// $val is a scratch register for our use. 1356let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ], 1357 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 1358 usesCustomInserter = 1 in 1359def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val), 1360 AddrModeNone, 0, NoItinerary, "","", 1361 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>; 1362 1363// FIXME: Non-IOS version(s) 1364let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, 1365 Defs = [ R7, LR, SP ] in 1366def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch), 1367 AddrModeNone, 0, IndexModeNone, 1368 Pseudo, NoItinerary, "", "", 1369 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 1370 Requires<[IsThumb,IsNotWindows]>; 1371 1372let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, 1373 Defs = [ R11, LR, SP ] in 1374def tInt_WIN_eh_sjlj_longjmp 1375 : XI<(outs), (ins GPR:$src, GPR:$scratch), AddrModeNone, 0, IndexModeNone, 1376 Pseudo, NoItinerary, "", "", [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 1377 Requires<[IsThumb,IsWindows]>; 1378 1379//===----------------------------------------------------------------------===// 1380// Non-Instruction Patterns 1381// 1382 1383// Comparisons 1384def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8), 1385 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>; 1386def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm), 1387 (tCMPr tGPR:$Rn, tGPR:$Rm)>; 1388 1389// Add with carry 1390def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs), 1391 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>; 1392def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs), 1393 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>; 1394def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs), 1395 (tADDrr tGPR:$lhs, tGPR:$rhs)>; 1396 1397// Subtract with carry 1398def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs), 1399 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>; 1400def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs), 1401 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>; 1402def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs), 1403 (tSUBrr tGPR:$lhs, tGPR:$rhs)>; 1404 1405// Bswap 16 with load/store 1406def : T1Pat<(srl (bswap (extloadi16 t_addrmode_is2:$addr)), (i32 16)), 1407 (tREV16 (tLDRHi t_addrmode_is2:$addr))>; 1408def : T1Pat<(srl (bswap (extloadi16 t_addrmode_rr:$addr)), (i32 16)), 1409 (tREV16 (tLDRHr t_addrmode_rr:$addr))>; 1410def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)), 1411 t_addrmode_is2:$addr), 1412 (tSTRHi(tREV16 tGPR:$Rn), t_addrmode_is2:$addr)>; 1413def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)), 1414 t_addrmode_rr:$addr), 1415 (tSTRHr (tREV16 tGPR:$Rn), t_addrmode_rr:$addr)>; 1416 1417// ConstantPool 1418def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>; 1419 1420// GlobalAddress 1421def tLDRLIT_ga_pcrel : PseudoInst<(outs tGPR:$dst), (ins i32imm:$addr), 1422 IIC_iLoadiALU, 1423 [(set tGPR:$dst, 1424 (ARMWrapperPIC tglobaladdr:$addr))]>, 1425 Requires<[IsThumb, DontUseMovt]>; 1426 1427def tLDRLIT_ga_abs : PseudoInst<(outs tGPR:$dst), (ins i32imm:$src), 1428 IIC_iLoad_i, 1429 [(set tGPR:$dst, 1430 (ARMWrapper tglobaladdr:$src))]>, 1431 Requires<[IsThumb, DontUseMovt]>; 1432 1433// TLS globals 1434def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 1435 (tLDRLIT_ga_pcrel tglobaltlsaddr:$addr)>, 1436 Requires<[IsThumb, DontUseMovt]>; 1437def : Pat<(ARMWrapper tglobaltlsaddr:$addr), 1438 (tLDRLIT_ga_abs tglobaltlsaddr:$addr)>, 1439 Requires<[IsThumb, DontUseMovt]>; 1440 1441 1442// JumpTable 1443def : T1Pat<(ARMWrapperJT tjumptable:$dst), 1444 (tLEApcrelJT tjumptable:$dst)>; 1445 1446// Direct calls 1447def : T1Pat<(ARMcall texternalsym:$func), (tBL texternalsym:$func)>, 1448 Requires<[IsThumb]>; 1449 1450// zextload i1 -> zextload i8 1451def : T1Pat<(zextloadi1 t_addrmode_is1:$addr), 1452 (tLDRBi t_addrmode_is1:$addr)>; 1453def : T1Pat<(zextloadi1 t_addrmode_rr:$addr), 1454 (tLDRBr t_addrmode_rr:$addr)>; 1455 1456// extload from the stack -> word load from the stack, as it avoids having to 1457// materialize the base in a separate register. This only works when a word 1458// load puts the byte/halfword value in the same place in the register that the 1459// byte/halfword load would, i.e. when little-endian. 1460def : T1Pat<(extloadi1 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>, 1461 Requires<[IsThumb, IsThumb1Only, IsLE]>; 1462def : T1Pat<(extloadi8 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>, 1463 Requires<[IsThumb, IsThumb1Only, IsLE]>; 1464def : T1Pat<(extloadi16 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>, 1465 Requires<[IsThumb, IsThumb1Only, IsLE]>; 1466 1467// extload -> zextload 1468def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1469def : T1Pat<(extloadi1 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>; 1470def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1471def : T1Pat<(extloadi8 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>; 1472def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>; 1473def : T1Pat<(extloadi16 t_addrmode_rr:$addr), (tLDRHr t_addrmode_rr:$addr)>; 1474 1475// post-inc loads and stores 1476 1477// post-inc LDR -> LDM r0!, {r1}. The way operands are layed out in LDMs is 1478// different to how ISel expects them for a post-inc load, so use a pseudo 1479// and expand it just after ISel. 1480let usesCustomInserter = 1, 1481 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in 1482 def tLDR_postidx: tPseudoInst<(outs rGPR:$Rt, rGPR:$Rn_wb), 1483 (ins rGPR:$Rn, pred:$p), 1484 4, IIC_iStore_ru, 1485 []>; 1486 1487// post-inc STR -> STM r0!, {r1}. The layout of this (because it doesn't def 1488// multiple registers) is the same in ISel as MachineInstr, so there's no need 1489// for a pseudo. 1490def : T1Pat<(post_store rGPR:$Rt, rGPR:$Rn, 4), 1491 (tSTMIA_UPD rGPR:$Rn, rGPR:$Rt)>; 1492 1493// If it's impossible to use [r,r] address mode for sextload, select to 1494// ldr{b|h} + sxt{b|h} instead. 1495def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1496 (tSXTB (tLDRBi t_addrmode_is1:$addr))>, 1497 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1498def : T1Pat<(sextloadi8 t_addrmode_rr:$addr), 1499 (tSXTB (tLDRBr t_addrmode_rr:$addr))>, 1500 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1501def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1502 (tSXTH (tLDRHi t_addrmode_is2:$addr))>, 1503 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1504def : T1Pat<(sextloadi16 t_addrmode_rr:$addr), 1505 (tSXTH (tLDRHr t_addrmode_rr:$addr))>, 1506 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1507 1508def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1509 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>; 1510def : T1Pat<(sextloadi8 t_addrmode_rr:$addr), 1511 (tASRri (tLSLri (tLDRBr t_addrmode_rr:$addr), 24), 24)>; 1512def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1513 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>; 1514def : T1Pat<(sextloadi16 t_addrmode_rr:$addr), 1515 (tASRri (tLSLri (tLDRHr t_addrmode_rr:$addr), 16), 16)>; 1516 1517def : T1Pat<(atomic_load_8 t_addrmode_is1:$src), 1518 (tLDRBi t_addrmode_is1:$src)>; 1519def : T1Pat<(atomic_load_8 t_addrmode_rr:$src), 1520 (tLDRBr t_addrmode_rr:$src)>; 1521def : T1Pat<(atomic_load_16 t_addrmode_is2:$src), 1522 (tLDRHi t_addrmode_is2:$src)>; 1523def : T1Pat<(atomic_load_16 t_addrmode_rr:$src), 1524 (tLDRHr t_addrmode_rr:$src)>; 1525def : T1Pat<(atomic_load_32 t_addrmode_is4:$src), 1526 (tLDRi t_addrmode_is4:$src)>; 1527def : T1Pat<(atomic_load_32 t_addrmode_rr:$src), 1528 (tLDRr t_addrmode_rr:$src)>; 1529def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val), 1530 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>; 1531def : T1Pat<(atomic_store_8 t_addrmode_rr:$ptr, tGPR:$val), 1532 (tSTRBr tGPR:$val, t_addrmode_rr:$ptr)>; 1533def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val), 1534 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>; 1535def : T1Pat<(atomic_store_16 t_addrmode_rr:$ptr, tGPR:$val), 1536 (tSTRHr tGPR:$val, t_addrmode_rr:$ptr)>; 1537def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val), 1538 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>; 1539def : T1Pat<(atomic_store_32 t_addrmode_rr:$ptr, tGPR:$val), 1540 (tSTRr tGPR:$val, t_addrmode_rr:$ptr)>; 1541 1542// Large immediate handling. 1543 1544// Two piece imms. 1545def : T1Pat<(i32 thumb_immshifted:$src), 1546 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), 1547 (thumb_immshifted_shamt imm:$src))>; 1548 1549def : T1Pat<(i32 imm0_255_comp:$src), 1550 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>; 1551 1552def : T1Pat<(i32 imm256_510:$src), 1553 (tADDi8 (tMOVi8 255), 1554 (thumb_imm256_510_addend imm:$src))>; 1555 1556// Pseudo instruction that combines ldr from constpool and add pc. This should 1557// be expanded into two instructions late to allow if-conversion and 1558// scheduling. 1559let isReMaterializable = 1 in 1560def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), 1561 NoItinerary, 1562 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 1563 imm:$cp))]>, 1564 Requires<[IsThumb, IsThumb1Only]>; 1565 1566// Pseudo-instruction for merged POP and return. 1567// FIXME: remove when we have a way to marking a MI with these properties. 1568let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 1569 hasExtraDefRegAllocReq = 1 in 1570def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops), 1571 2, IIC_iPop_Br, [], 1572 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>; 1573 1574// Indirect branch using "mov pc, $Rm" 1575let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1576 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p), 1577 2, IIC_Br, [(brind GPR:$Rm)], 1578 (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>; 1579} 1580 1581 1582// In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00 1583// encoding is available on ARMv6K, but we don't differentiate that finely. 1584def : InstAlias<"nop", (tMOVr R8, R8, 14, 0), 0>, Requires<[IsThumb, IsThumb1Only]>; 1585 1586 1587// For round-trip assembly/disassembly, we have to handle a CPS instruction 1588// without any iflags. That's not, strictly speaking, valid syntax, but it's 1589// a useful extension and assembles to defined behaviour (the insn does 1590// nothing). 1591def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1592def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1593 1594// "neg" is and alias for "rsb rd, rn, #0" 1595def : tInstAlias<"neg${s}${p} $Rd, $Rm", 1596 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>; 1597 1598 1599// Implied destination operand forms for shifts. 1600def : tInstAlias<"lsl${s}${p} $Rdm, $imm", 1601 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>; 1602def : tInstAlias<"lsr${s}${p} $Rdm, $imm", 1603 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1604def : tInstAlias<"asr${s}${p} $Rdm, $imm", 1605 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1606 1607// Pseudo instruction ldr Rt, =immediate 1608def tLDRConstPool 1609 : tAsmPseudo<"ldr${p} $Rt, $immediate", 1610 (ins tGPR:$Rt, const_pool_asm_imm:$immediate, pred:$p)>; 1611