1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// ARM specific DAG Nodes. 16// 17 18// Type profiles. 19def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 20def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 21def SDT_ARMStructByVal : SDTypeProfile<0, 4, 22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 24 25def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 26 27def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 28 29def SDT_ARMCMov : SDTypeProfile<1, 3, 30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 31 SDTCisVT<3, i32>]>; 32 33def SDT_ARMBrcond : SDTypeProfile<0, 2, 34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 35 36def SDT_ARMBrJT : SDTypeProfile<0, 2, 37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 38 39def SDT_ARMBr2JT : SDTypeProfile<0, 3, 40 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 41 SDTCisVT<2, i32>]>; 42 43def SDT_ARMBCC_i64 : SDTypeProfile<0, 6, 44 [SDTCisVT<0, i32>, 45 SDTCisVT<1, i32>, SDTCisVT<2, i32>, 46 SDTCisVT<3, i32>, SDTCisVT<4, i32>, 47 SDTCisVT<5, OtherVT>]>; 48 49def SDT_ARMAnd : SDTypeProfile<1, 2, 50 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 51 SDTCisVT<2, i32>]>; 52 53def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 54 55def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 56 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 57 58def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 59def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, 60 SDTCisInt<2>]>; 61def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 62def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>; 63 64def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 65 66def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, 67 SDTCisInt<1>]>; 68 69def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 70 71def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 73 74def SDT_WIN__DBZCHK : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 75 76def SDT_ARMMEMCPY : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 77 SDTCisVT<2, i32>, SDTCisVT<3, i32>, 78 SDTCisVT<4, i32>]>; 79 80def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 81 [SDTCisSameAs<0, 2>, 82 SDTCisSameAs<0, 3>, 83 SDTCisInt<0>, SDTCisVT<1, i32>]>; 84 85// SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR 86def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 87 [SDTCisSameAs<0, 2>, 88 SDTCisSameAs<0, 3>, 89 SDTCisInt<0>, 90 SDTCisVT<1, i32>, 91 SDTCisVT<4, i32>]>; 92 93def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>, 94 SDTCisVT<2, i32>, SDTCisVT<3, i32>, 95 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >; 96def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>; 97def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>; 98 99// Node definitions. 100def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 101def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>; 102def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>; 103 104def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 105 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 106def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 107 [SDNPHasChain, SDNPSideEffect, 108 SDNPOptInGlue, SDNPOutGlue]>; 109def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" , 110 SDT_ARMStructByVal, 111 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 112 SDNPMayStore, SDNPMayLoad]>; 113 114def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 116 SDNPVariadic]>; 117def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 119 SDNPVariadic]>; 120def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 121 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 122 SDNPVariadic]>; 123 124def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, 125 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 126def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall, 127 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 128def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 129 [SDNPInGlue]>; 130 131def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 132 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 133 134def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 135 [SDNPHasChain]>; 136def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, 137 [SDNPHasChain]>; 138 139def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64, 140 [SDNPHasChain]>; 141 142def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 143 [SDNPOutGlue]>; 144 145def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp, 146 [SDNPOutGlue]>; 147 148def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, 149 [SDNPOutGlue, SDNPCommutative]>; 150 151def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 152 153def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 154def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 155def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>; 156 157def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags, 158 [SDNPCommutative]>; 159def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>; 160def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>; 161def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>; 162 163def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 164def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", 165 SDT_ARMEH_SJLJ_Setjmp, 166 [SDNPHasChain, SDNPSideEffect]>; 167def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP", 168 SDT_ARMEH_SJLJ_Longjmp, 169 [SDNPHasChain, SDNPSideEffect]>; 170def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH", 171 SDT_ARMEH_SJLJ_SetupDispatch, 172 [SDNPHasChain, SDNPSideEffect]>; 173 174def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER, 175 [SDNPHasChain, SDNPSideEffect]>; 176def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH, 177 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 178 179def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET, 180 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 181 182def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; 183 184def ARMmemcopy : SDNode<"ARMISD::MEMCPY", SDT_ARMMEMCPY, 185 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 186 SDNPMayStore, SDNPMayLoad]>; 187 188//===----------------------------------------------------------------------===// 189// ARM Instruction Predicate Definitions. 190// 191def HasV4T : Predicate<"Subtarget->hasV4TOps()">, 192 AssemblerPredicate<"HasV4TOps", "armv4t">; 193def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; 194def HasV5T : Predicate<"Subtarget->hasV5TOps()">, 195 AssemblerPredicate<"HasV5TOps", "armv5t">; 196def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, 197 AssemblerPredicate<"HasV5TEOps", "armv5te">; 198def HasV6 : Predicate<"Subtarget->hasV6Ops()">, 199 AssemblerPredicate<"HasV6Ops", "armv6">; 200def NoV6 : Predicate<"!Subtarget->hasV6Ops()">; 201def HasV6M : Predicate<"Subtarget->hasV6MOps()">, 202 AssemblerPredicate<"HasV6MOps", 203 "armv6m or armv6t2">; 204def HasV8MBaseline : Predicate<"Subtarget->hasV8MBaselineOps()">, 205 AssemblerPredicate<"HasV8MBaselineOps", 206 "armv8m.base">; 207def HasV8MMainline : Predicate<"Subtarget->hasV8MMainlineOps()">, 208 AssemblerPredicate<"HasV8MMainlineOps", 209 "armv8m.main">; 210def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, 211 AssemblerPredicate<"HasV6T2Ops", "armv6t2">; 212def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; 213def HasV6K : Predicate<"Subtarget->hasV6KOps()">, 214 AssemblerPredicate<"HasV6KOps", "armv6k">; 215def NoV6K : Predicate<"!Subtarget->hasV6KOps()">; 216def HasV7 : Predicate<"Subtarget->hasV7Ops()">, 217 AssemblerPredicate<"HasV7Ops", "armv7">; 218def HasV8 : Predicate<"Subtarget->hasV8Ops()">, 219 AssemblerPredicate<"HasV8Ops", "armv8">; 220def PreV8 : Predicate<"!Subtarget->hasV8Ops()">, 221 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">; 222def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">, 223 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">; 224def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">, 225 AssemblerPredicate<"HasV8_2aOps", "armv8.2a">; 226def NoVFP : Predicate<"!Subtarget->hasVFP2()">; 227def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, 228 AssemblerPredicate<"FeatureVFP2", "VFP2">; 229def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, 230 AssemblerPredicate<"FeatureVFP3", "VFP3">; 231def HasVFP4 : Predicate<"Subtarget->hasVFP4()">, 232 AssemblerPredicate<"FeatureVFP4", "VFP4">; 233def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">, 234 AssemblerPredicate<"!FeatureVFPOnlySP", 235 "double precision VFP">; 236def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, 237 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">; 238def HasNEON : Predicate<"Subtarget->hasNEON()">, 239 AssemblerPredicate<"FeatureNEON", "NEON">; 240def HasCrypto : Predicate<"Subtarget->hasCrypto()">, 241 AssemblerPredicate<"FeatureCrypto", "crypto">; 242def HasCRC : Predicate<"Subtarget->hasCRC()">, 243 AssemblerPredicate<"FeatureCRC", "crc">; 244def HasFP16 : Predicate<"Subtarget->hasFP16()">, 245 AssemblerPredicate<"FeatureFP16","half-float conversions">; 246def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">, 247 AssemblerPredicate<"FeatureFullFP16","full half-float">; 248def HasDivide : Predicate<"Subtarget->hasDivide()">, 249 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">; 250def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">, 251 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">; 252def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">, 253 AssemblerPredicate<"FeatureT2XtPk", 254 "pack/extract">; 255def HasDSP : Predicate<"Subtarget->hasDSP()">, 256 AssemblerPredicate<"FeatureDSP", "dsp">; 257def HasDB : Predicate<"Subtarget->hasDataBarrier()">, 258 AssemblerPredicate<"FeatureDB", 259 "data-barriers">; 260def HasV7Clrex : Predicate<"Subtarget->hasV7Clrex()">, 261 AssemblerPredicate<"FeatureV7Clrex", 262 "v7 clrex">; 263def HasAcquireRelease : Predicate<"Subtarget->hasAcquireRelease()">, 264 AssemblerPredicate<"FeatureAcquireRelease", 265 "acquire/release">; 266def HasMP : Predicate<"Subtarget->hasMPExtension()">, 267 AssemblerPredicate<"FeatureMP", 268 "mp-extensions">; 269def HasVirtualization: Predicate<"false">, 270 AssemblerPredicate<"FeatureVirtualization", 271 "virtualization-extensions">; 272def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">, 273 AssemblerPredicate<"FeatureTrustZone", 274 "TrustZone">; 275def Has8MSecExt : Predicate<"Subtarget->has8MSecExt()">, 276 AssemblerPredicate<"Feature8MSecExt", 277 "ARMv8-M Security Extensions">; 278def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">; 279def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; 280def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; 281def IsThumb : Predicate<"Subtarget->isThumb()">, 282 AssemblerPredicate<"ModeThumb", "thumb">; 283def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; 284def IsThumb2 : Predicate<"Subtarget->isThumb2()">, 285 AssemblerPredicate<"ModeThumb,FeatureThumb2", 286 "thumb2">; 287def IsMClass : Predicate<"Subtarget->isMClass()">, 288 AssemblerPredicate<"FeatureMClass", "armv*m">; 289def IsNotMClass : Predicate<"!Subtarget->isMClass()">, 290 AssemblerPredicate<"!FeatureMClass", 291 "!armv*m">; 292def IsARM : Predicate<"!Subtarget->isThumb()">, 293 AssemblerPredicate<"!ModeThumb", "arm-mode">; 294def IsMachO : Predicate<"Subtarget->isTargetMachO()">; 295def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">; 296def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 297def IsWindows : Predicate<"Subtarget->isTargetWindows()">; 298def IsNotWindows : Predicate<"!Subtarget->isTargetWindows()">; 299def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">, 300 AssemblerPredicate<"FeatureNaClTrap", "NaCl">; 301def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">; 302 303// FIXME: Eventually this will be just "hasV6T2Ops". 304def UseMovt : Predicate<"Subtarget->useMovt(*MF)">; 305def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">; 306def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">; 307def UseMulOps : Predicate<"Subtarget->useMulOps()">; 308 309// Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available. 310// But only select them if more precision in FP computation is allowed. 311// Do not use them for Darwin platforms. 312def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion ==" 313 " FPOpFusion::Fast && " 314 " Subtarget->hasVFP4()) && " 315 "!Subtarget->isTargetDarwin()">; 316def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion ==" 317 " FPOpFusion::Fast &&" 318 " Subtarget->hasVFP4()) || " 319 "Subtarget->isTargetDarwin()">; 320 321// VGETLNi32 is microcoded on Swift - prefer VMOV. 322def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">; 323def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">; 324 325// VDUP.32 is microcoded on Swift - prefer VMOV. 326def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">; 327def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">; 328 329// Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as 330// this allows more effective execution domain optimization. See 331// setExecutionDomain(). 332def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">; 333def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">; 334 335def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">; 336def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">; 337 338//===----------------------------------------------------------------------===// 339// ARM Flag Definitions. 340 341class RegConstraint<string C> { 342 string Constraints = C; 343} 344 345//===----------------------------------------------------------------------===// 346// ARM specific transformation functions and pattern fragments. 347// 348 349// imm_neg_XFORM - Return the negation of an i32 immediate value. 350def imm_neg_XFORM : SDNodeXForm<imm, [{ 351 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32); 352}]>; 353 354// imm_not_XFORM - Return the complement of a i32 immediate value. 355def imm_not_XFORM : SDNodeXForm<imm, [{ 356 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32); 357}]>; 358 359/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 360def imm16_31 : ImmLeaf<i32, [{ 361 return (int32_t)Imm >= 16 && (int32_t)Imm < 32; 362}]>; 363 364// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 365def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 366 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; 367}]>; 368 369/// Split a 32-bit immediate into two 16 bit parts. 370def hi16 : SDNodeXForm<imm, [{ 371 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N), 372 MVT::i32); 373}]>; 374 375def lo16AllZero : PatLeaf<(i32 imm), [{ 376 // Returns true if all low 16-bits are 0. 377 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 378}], hi16>; 379 380class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 381class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 382 383// An 'and' node with a single use. 384def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 385 return N->hasOneUse(); 386}]>; 387 388// An 'xor' node with a single use. 389def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{ 390 return N->hasOneUse(); 391}]>; 392 393// An 'fmul' node with a single use. 394def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{ 395 return N->hasOneUse(); 396}]>; 397 398// An 'fadd' node which checks for single non-hazardous use. 399def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{ 400 return hasNoVMLxHazardUse(N); 401}]>; 402 403// An 'fsub' node which checks for single non-hazardous use. 404def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{ 405 return hasNoVMLxHazardUse(N); 406}]>; 407 408//===----------------------------------------------------------------------===// 409// Operand Definitions. 410// 411 412// Immediate operands with a shared generic asm render method. 413class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; } 414 415// Operands that are part of a memory addressing mode. 416class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; } 417 418// Branch target. 419// FIXME: rename brtarget to t2_brtarget 420def brtarget : Operand<OtherVT> { 421 let EncoderMethod = "getBranchTargetOpValue"; 422 let OperandType = "OPERAND_PCREL"; 423 let DecoderMethod = "DecodeT2BROperand"; 424} 425 426// FIXME: get rid of this one? 427def uncondbrtarget : Operand<OtherVT> { 428 let EncoderMethod = "getUnconditionalBranchTargetOpValue"; 429 let OperandType = "OPERAND_PCREL"; 430} 431 432// Branch target for ARM. Handles conditional/unconditional 433def br_target : Operand<OtherVT> { 434 let EncoderMethod = "getARMBranchTargetOpValue"; 435 let OperandType = "OPERAND_PCREL"; 436} 437 438// Call target. 439// FIXME: rename bltarget to t2_bl_target? 440def bltarget : Operand<i32> { 441 // Encoded the same as branch targets. 442 let EncoderMethod = "getBranchTargetOpValue"; 443 let OperandType = "OPERAND_PCREL"; 444} 445 446// Call target for ARM. Handles conditional/unconditional 447// FIXME: rename bl_target to t2_bltarget? 448def bl_target : Operand<i32> { 449 let EncoderMethod = "getARMBLTargetOpValue"; 450 let OperandType = "OPERAND_PCREL"; 451} 452 453def blx_target : Operand<i32> { 454 let EncoderMethod = "getARMBLXTargetOpValue"; 455 let OperandType = "OPERAND_PCREL"; 456} 457 458// A list of registers separated by comma. Used by load/store multiple. 459def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; } 460def reglist : Operand<i32> { 461 let EncoderMethod = "getRegisterListOpValue"; 462 let ParserMatchClass = RegListAsmOperand; 463 let PrintMethod = "printRegisterList"; 464 let DecoderMethod = "DecodeRegListOperand"; 465} 466 467def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">; 468 469def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; } 470def dpr_reglist : Operand<i32> { 471 let EncoderMethod = "getRegisterListOpValue"; 472 let ParserMatchClass = DPRRegListAsmOperand; 473 let PrintMethod = "printRegisterList"; 474 let DecoderMethod = "DecodeDPRRegListOperand"; 475} 476 477def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; } 478def spr_reglist : Operand<i32> { 479 let EncoderMethod = "getRegisterListOpValue"; 480 let ParserMatchClass = SPRRegListAsmOperand; 481 let PrintMethod = "printRegisterList"; 482 let DecoderMethod = "DecodeSPRRegListOperand"; 483} 484 485// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 486def cpinst_operand : Operand<i32> { 487 let PrintMethod = "printCPInstOperand"; 488} 489 490// Local PC labels. 491def pclabel : Operand<i32> { 492 let PrintMethod = "printPCLabel"; 493} 494 495// ADR instruction labels. 496def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; } 497def adrlabel : Operand<i32> { 498 let EncoderMethod = "getAdrLabelOpValue"; 499 let ParserMatchClass = AdrLabelAsmOperand; 500 let PrintMethod = "printAdrLabelOperand<0>"; 501} 502 503def neon_vcvt_imm32 : Operand<i32> { 504 let EncoderMethod = "getNEONVcvtImm32OpValue"; 505 let DecoderMethod = "DecodeVCVTImmOperand"; 506} 507 508// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. 509def rot_imm_XFORM: SDNodeXForm<imm, [{ 510 switch (N->getZExtValue()){ 511 default: llvm_unreachable(nullptr); 512 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); 513 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32); 514 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32); 515 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32); 516 } 517}]>; 518def RotImmAsmOperand : AsmOperandClass { 519 let Name = "RotImm"; 520 let ParserMethod = "parseRotImm"; 521} 522def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{ 523 int32_t v = N->getZExtValue(); 524 return v == 8 || v == 16 || v == 24; }], 525 rot_imm_XFORM> { 526 let PrintMethod = "printRotImmOperand"; 527 let ParserMatchClass = RotImmAsmOperand; 528} 529 530// shift_imm: An integer that encodes a shift amount and the type of shift 531// (asr or lsl). The 6-bit immediate encodes as: 532// {5} 0 ==> lsl 533// 1 asr 534// {4-0} imm5 shift amount. 535// asr #32 encoded as imm5 == 0. 536def ShifterImmAsmOperand : AsmOperandClass { 537 let Name = "ShifterImm"; 538 let ParserMethod = "parseShifterImm"; 539} 540def shift_imm : Operand<i32> { 541 let PrintMethod = "printShiftImmOperand"; 542 let ParserMatchClass = ShifterImmAsmOperand; 543} 544 545// shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm. 546def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; } 547def so_reg_reg : Operand<i32>, // reg reg imm 548 ComplexPattern<i32, 3, "SelectRegShifterOperand", 549 [shl, srl, sra, rotr]> { 550 let EncoderMethod = "getSORegRegOpValue"; 551 let PrintMethod = "printSORegRegOperand"; 552 let DecoderMethod = "DecodeSORegRegOperand"; 553 let ParserMatchClass = ShiftedRegAsmOperand; 554 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm); 555} 556 557def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; } 558def so_reg_imm : Operand<i32>, // reg imm 559 ComplexPattern<i32, 2, "SelectImmShifterOperand", 560 [shl, srl, sra, rotr]> { 561 let EncoderMethod = "getSORegImmOpValue"; 562 let PrintMethod = "printSORegImmOperand"; 563 let DecoderMethod = "DecodeSORegImmOperand"; 564 let ParserMatchClass = ShiftedImmAsmOperand; 565 let MIOperandInfo = (ops GPR, i32imm); 566} 567 568// FIXME: Does this need to be distinct from so_reg? 569def shift_so_reg_reg : Operand<i32>, // reg reg imm 570 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand", 571 [shl,srl,sra,rotr]> { 572 let EncoderMethod = "getSORegRegOpValue"; 573 let PrintMethod = "printSORegRegOperand"; 574 let DecoderMethod = "DecodeSORegRegOperand"; 575 let ParserMatchClass = ShiftedRegAsmOperand; 576 let MIOperandInfo = (ops GPR, GPR, i32imm); 577} 578 579// FIXME: Does this need to be distinct from so_reg? 580def shift_so_reg_imm : Operand<i32>, // reg reg imm 581 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand", 582 [shl,srl,sra,rotr]> { 583 let EncoderMethod = "getSORegImmOpValue"; 584 let PrintMethod = "printSORegImmOperand"; 585 let DecoderMethod = "DecodeSORegImmOperand"; 586 let ParserMatchClass = ShiftedImmAsmOperand; 587 let MIOperandInfo = (ops GPR, i32imm); 588} 589 590// mod_imm: match a 32-bit immediate operand, which can be encoded into 591// a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM 592// - "Modified Immediate Constants"). Within the MC layer we keep this 593// immediate in its encoded form. 594def ModImmAsmOperand: AsmOperandClass { 595 let Name = "ModImm"; 596 let ParserMethod = "parseModImm"; 597} 598def mod_imm : Operand<i32>, ImmLeaf<i32, [{ 599 return ARM_AM::getSOImmVal(Imm) != -1; 600 }]> { 601 let EncoderMethod = "getModImmOpValue"; 602 let PrintMethod = "printModImmOperand"; 603 let ParserMatchClass = ModImmAsmOperand; 604} 605 606// Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder 607// method and such, as they are only used on aliases (Pat<> and InstAlias<>). 608// The actual parsing, encoding, decoding are handled by the destination 609// instructions, which use mod_imm. 610 611def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; } 612def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{ 613 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1; 614 }], imm_not_XFORM> { 615 let ParserMatchClass = ModImmNotAsmOperand; 616} 617 618def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; } 619def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{ 620 unsigned Value = -(unsigned)N->getZExtValue(); 621 return Value && ARM_AM::getSOImmVal(Value) != -1; 622 }], imm_neg_XFORM> { 623 let ParserMatchClass = ModImmNegAsmOperand; 624} 625 626/// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal() 627def arm_i32imm : PatLeaf<(imm), [{ 628 if (Subtarget->useMovt(*MF)) 629 return true; 630 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 631}]>; 632 633/// imm0_1 predicate - Immediate in the range [0,1]. 634def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; } 635def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; } 636 637/// imm0_3 predicate - Immediate in the range [0,3]. 638def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; } 639def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; } 640 641/// imm0_7 predicate - Immediate in the range [0,7]. 642def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; } 643def imm0_7 : Operand<i32>, ImmLeaf<i32, [{ 644 return Imm >= 0 && Imm < 8; 645}]> { 646 let ParserMatchClass = Imm0_7AsmOperand; 647} 648 649/// imm8 predicate - Immediate is exactly 8. 650def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; } 651def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> { 652 let ParserMatchClass = Imm8AsmOperand; 653} 654 655/// imm16 predicate - Immediate is exactly 16. 656def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; } 657def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> { 658 let ParserMatchClass = Imm16AsmOperand; 659} 660 661/// imm32 predicate - Immediate is exactly 32. 662def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; } 663def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> { 664 let ParserMatchClass = Imm32AsmOperand; 665} 666 667def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>; 668 669/// imm1_7 predicate - Immediate in the range [1,7]. 670def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; } 671def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> { 672 let ParserMatchClass = Imm1_7AsmOperand; 673} 674 675/// imm1_15 predicate - Immediate in the range [1,15]. 676def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; } 677def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> { 678 let ParserMatchClass = Imm1_15AsmOperand; 679} 680 681/// imm1_31 predicate - Immediate in the range [1,31]. 682def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; } 683def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> { 684 let ParserMatchClass = Imm1_31AsmOperand; 685} 686 687/// imm0_15 predicate - Immediate in the range [0,15]. 688def Imm0_15AsmOperand: ImmAsmOperand { 689 let Name = "Imm0_15"; 690 let DiagnosticType = "ImmRange0_15"; 691} 692def imm0_15 : Operand<i32>, ImmLeaf<i32, [{ 693 return Imm >= 0 && Imm < 16; 694}]> { 695 let ParserMatchClass = Imm0_15AsmOperand; 696} 697 698/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31]. 699def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; } 700def imm0_31 : Operand<i32>, ImmLeaf<i32, [{ 701 return Imm >= 0 && Imm < 32; 702}]> { 703 let ParserMatchClass = Imm0_31AsmOperand; 704} 705 706/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32]. 707def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; } 708def imm0_32 : Operand<i32>, ImmLeaf<i32, [{ 709 return Imm >= 0 && Imm < 32; 710}]> { 711 let ParserMatchClass = Imm0_32AsmOperand; 712} 713 714/// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63]. 715def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; } 716def imm0_63 : Operand<i32>, ImmLeaf<i32, [{ 717 return Imm >= 0 && Imm < 64; 718}]> { 719 let ParserMatchClass = Imm0_63AsmOperand; 720} 721 722/// imm0_239 predicate - Immediate in the range [0,239]. 723def Imm0_239AsmOperand : ImmAsmOperand { 724 let Name = "Imm0_239"; 725 let DiagnosticType = "ImmRange0_239"; 726} 727def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> { 728 let ParserMatchClass = Imm0_239AsmOperand; 729} 730 731/// imm0_255 predicate - Immediate in the range [0,255]. 732def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; } 733def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> { 734 let ParserMatchClass = Imm0_255AsmOperand; 735} 736 737/// imm0_65535 - An immediate is in the range [0.65535]. 738def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; } 739def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{ 740 return Imm >= 0 && Imm < 65536; 741}]> { 742 let ParserMatchClass = Imm0_65535AsmOperand; 743} 744 745// imm0_65535_neg - An immediate whose negative value is in the range [0.65535]. 746def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{ 747 return -Imm >= 0 && -Imm < 65536; 748}]>; 749 750// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference 751// a relocatable expression. 752// 753// FIXME: This really needs a Thumb version separate from the ARM version. 754// While the range is the same, and can thus use the same match class, 755// the encoding is different so it should have a different encoder method. 756def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; } 757def imm0_65535_expr : Operand<i32> { 758 let EncoderMethod = "getHiLo16ImmOpValue"; 759 let ParserMatchClass = Imm0_65535ExprAsmOperand; 760} 761 762def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; } 763def imm256_65535_expr : Operand<i32> { 764 let ParserMatchClass = Imm256_65535ExprAsmOperand; 765} 766 767/// imm24b - True if the 32-bit immediate is encodable in 24 bits. 768def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; } 769def imm24b : Operand<i32>, ImmLeaf<i32, [{ 770 return Imm >= 0 && Imm <= 0xffffff; 771}]> { 772 let ParserMatchClass = Imm24bitAsmOperand; 773} 774 775 776/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield 777/// e.g., 0xf000ffff 778def BitfieldAsmOperand : AsmOperandClass { 779 let Name = "Bitfield"; 780 let ParserMethod = "parseBitfield"; 781} 782 783def bf_inv_mask_imm : Operand<i32>, 784 PatLeaf<(imm), [{ 785 return ARM::isBitFieldInvertedMask(N->getZExtValue()); 786}] > { 787 let EncoderMethod = "getBitfieldInvertedMaskOpValue"; 788 let PrintMethod = "printBitfieldInvMaskImmOperand"; 789 let DecoderMethod = "DecodeBitfieldMaskOperand"; 790 let ParserMatchClass = BitfieldAsmOperand; 791} 792 793def imm1_32_XFORM: SDNodeXForm<imm, [{ 794 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 795 MVT::i32); 796}]>; 797def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; } 798def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ 799 uint64_t Imm = N->getZExtValue(); 800 return Imm > 0 && Imm <= 32; 801 }], 802 imm1_32_XFORM> { 803 let PrintMethod = "printImmPlusOneOperand"; 804 let ParserMatchClass = Imm1_32AsmOperand; 805} 806 807def imm1_16_XFORM: SDNodeXForm<imm, [{ 808 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 809 MVT::i32); 810}]>; 811def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; } 812def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }], 813 imm1_16_XFORM> { 814 let PrintMethod = "printImmPlusOneOperand"; 815 let ParserMatchClass = Imm1_16AsmOperand; 816} 817 818// Define ARM specific addressing modes. 819// addrmode_imm12 := reg +/- imm12 820// 821def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; } 822class AddrMode_Imm12 : MemOperand, 823 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> { 824 // 12-bit immediate operand. Note that instructions using this encode 825 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other 826 // immediate values are as normal. 827 828 let EncoderMethod = "getAddrModeImm12OpValue"; 829 let DecoderMethod = "DecodeAddrModeImm12Operand"; 830 let ParserMatchClass = MemImm12OffsetAsmOperand; 831 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 832} 833 834def addrmode_imm12 : AddrMode_Imm12 { 835 let PrintMethod = "printAddrModeImm12Operand<false>"; 836} 837 838def addrmode_imm12_pre : AddrMode_Imm12 { 839 let PrintMethod = "printAddrModeImm12Operand<true>"; 840} 841 842// ldst_so_reg := reg +/- reg shop imm 843// 844def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; } 845def ldst_so_reg : MemOperand, 846 ComplexPattern<i32, 3, "SelectLdStSOReg", []> { 847 let EncoderMethod = "getLdStSORegOpValue"; 848 // FIXME: Simplify the printer 849 let PrintMethod = "printAddrMode2Operand"; 850 let DecoderMethod = "DecodeSORegMemOperand"; 851 let ParserMatchClass = MemRegOffsetAsmOperand; 852 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift); 853} 854 855// postidx_imm8 := +/- [0,255] 856// 857// 9 bit value: 858// {8} 1 is imm8 is non-negative. 0 otherwise. 859// {7-0} [0,255] imm8 value. 860def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; } 861def postidx_imm8 : MemOperand { 862 let PrintMethod = "printPostIdxImm8Operand"; 863 let ParserMatchClass = PostIdxImm8AsmOperand; 864 let MIOperandInfo = (ops i32imm); 865} 866 867// postidx_imm8s4 := +/- [0,1020] 868// 869// 9 bit value: 870// {8} 1 is imm8 is non-negative. 0 otherwise. 871// {7-0} [0,255] imm8 value, scaled by 4. 872def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; } 873def postidx_imm8s4 : MemOperand { 874 let PrintMethod = "printPostIdxImm8s4Operand"; 875 let ParserMatchClass = PostIdxImm8s4AsmOperand; 876 let MIOperandInfo = (ops i32imm); 877} 878 879 880// postidx_reg := +/- reg 881// 882def PostIdxRegAsmOperand : AsmOperandClass { 883 let Name = "PostIdxReg"; 884 let ParserMethod = "parsePostIdxReg"; 885} 886def postidx_reg : MemOperand { 887 let EncoderMethod = "getPostIdxRegOpValue"; 888 let DecoderMethod = "DecodePostIdxReg"; 889 let PrintMethod = "printPostIdxRegOperand"; 890 let ParserMatchClass = PostIdxRegAsmOperand; 891 let MIOperandInfo = (ops GPRnopc, i32imm); 892} 893 894 895// addrmode2 := reg +/- imm12 896// := reg +/- reg shop imm 897// 898// FIXME: addrmode2 should be refactored the rest of the way to always 899// use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg). 900def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; } 901def addrmode2 : MemOperand, 902 ComplexPattern<i32, 3, "SelectAddrMode2", []> { 903 let EncoderMethod = "getAddrMode2OpValue"; 904 let PrintMethod = "printAddrMode2Operand"; 905 let ParserMatchClass = AddrMode2AsmOperand; 906 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 907} 908 909def PostIdxRegShiftedAsmOperand : AsmOperandClass { 910 let Name = "PostIdxRegShifted"; 911 let ParserMethod = "parsePostIdxReg"; 912} 913def am2offset_reg : MemOperand, 914 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg", 915 [], [SDNPWantRoot]> { 916 let EncoderMethod = "getAddrMode2OffsetOpValue"; 917 let PrintMethod = "printAddrMode2OffsetOperand"; 918 // When using this for assembly, it's always as a post-index offset. 919 let ParserMatchClass = PostIdxRegShiftedAsmOperand; 920 let MIOperandInfo = (ops GPRnopc, i32imm); 921} 922 923// FIXME: am2offset_imm should only need the immediate, not the GPR. Having 924// the GPR is purely vestigal at this point. 925def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; } 926def am2offset_imm : MemOperand, 927 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm", 928 [], [SDNPWantRoot]> { 929 let EncoderMethod = "getAddrMode2OffsetOpValue"; 930 let PrintMethod = "printAddrMode2OffsetOperand"; 931 let ParserMatchClass = AM2OffsetImmAsmOperand; 932 let MIOperandInfo = (ops GPRnopc, i32imm); 933} 934 935 936// addrmode3 := reg +/- reg 937// addrmode3 := reg +/- imm8 938// 939// FIXME: split into imm vs. reg versions. 940def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; } 941class AddrMode3 : MemOperand, 942 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 943 let EncoderMethod = "getAddrMode3OpValue"; 944 let ParserMatchClass = AddrMode3AsmOperand; 945 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 946} 947 948def addrmode3 : AddrMode3 949{ 950 let PrintMethod = "printAddrMode3Operand<false>"; 951} 952 953def addrmode3_pre : AddrMode3 954{ 955 let PrintMethod = "printAddrMode3Operand<true>"; 956} 957 958// FIXME: split into imm vs. reg versions. 959// FIXME: parser method to handle +/- register. 960def AM3OffsetAsmOperand : AsmOperandClass { 961 let Name = "AM3Offset"; 962 let ParserMethod = "parseAM3Offset"; 963} 964def am3offset : MemOperand, 965 ComplexPattern<i32, 2, "SelectAddrMode3Offset", 966 [], [SDNPWantRoot]> { 967 let EncoderMethod = "getAddrMode3OffsetOpValue"; 968 let PrintMethod = "printAddrMode3OffsetOperand"; 969 let ParserMatchClass = AM3OffsetAsmOperand; 970 let MIOperandInfo = (ops GPR, i32imm); 971} 972 973// ldstm_mode := {ia, ib, da, db} 974// 975def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> { 976 let EncoderMethod = "getLdStmModeOpValue"; 977 let PrintMethod = "printLdStmModeOperand"; 978} 979 980// addrmode5 := reg +/- imm8*4 981// 982def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; } 983class AddrMode5 : MemOperand, 984 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 985 let EncoderMethod = "getAddrMode5OpValue"; 986 let DecoderMethod = "DecodeAddrMode5Operand"; 987 let ParserMatchClass = AddrMode5AsmOperand; 988 let MIOperandInfo = (ops GPR:$base, i32imm); 989} 990 991def addrmode5 : AddrMode5 { 992 let PrintMethod = "printAddrMode5Operand<false>"; 993} 994 995def addrmode5_pre : AddrMode5 { 996 let PrintMethod = "printAddrMode5Operand<true>"; 997} 998 999// addrmode5fp16 := reg +/- imm8*2 1000// 1001def AddrMode5FP16AsmOperand : AsmOperandClass { let Name = "AddrMode5FP16"; } 1002class AddrMode5FP16 : Operand<i32>, 1003 ComplexPattern<i32, 2, "SelectAddrMode5FP16", []> { 1004 let EncoderMethod = "getAddrMode5FP16OpValue"; 1005 let DecoderMethod = "DecodeAddrMode5FP16Operand"; 1006 let ParserMatchClass = AddrMode5FP16AsmOperand; 1007 let MIOperandInfo = (ops GPR:$base, i32imm); 1008} 1009 1010def addrmode5fp16 : AddrMode5FP16 { 1011 let PrintMethod = "printAddrMode5FP16Operand<false>"; 1012} 1013 1014// addrmode6 := reg with optional alignment 1015// 1016def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; } 1017def addrmode6 : MemOperand, 1018 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1019 let PrintMethod = "printAddrMode6Operand"; 1020 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1021 let EncoderMethod = "getAddrMode6AddressOpValue"; 1022 let DecoderMethod = "DecodeAddrMode6Operand"; 1023 let ParserMatchClass = AddrMode6AsmOperand; 1024} 1025 1026def am6offset : MemOperand, 1027 ComplexPattern<i32, 1, "SelectAddrMode6Offset", 1028 [], [SDNPWantRoot]> { 1029 let PrintMethod = "printAddrMode6OffsetOperand"; 1030 let MIOperandInfo = (ops GPR); 1031 let EncoderMethod = "getAddrMode6OffsetOpValue"; 1032 let DecoderMethod = "DecodeGPRRegisterClass"; 1033} 1034 1035// Special version of addrmode6 to handle alignment encoding for VST1/VLD1 1036// (single element from one lane) for size 32. 1037def addrmode6oneL32 : MemOperand, 1038 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1039 let PrintMethod = "printAddrMode6Operand"; 1040 let MIOperandInfo = (ops GPR:$addr, i32imm); 1041 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue"; 1042} 1043 1044// Base class for addrmode6 with specific alignment restrictions. 1045class AddrMode6Align : MemOperand, 1046 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1047 let PrintMethod = "printAddrMode6Operand"; 1048 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1049 let EncoderMethod = "getAddrMode6AddressOpValue"; 1050 let DecoderMethod = "DecodeAddrMode6Operand"; 1051} 1052 1053// Special version of addrmode6 to handle no allowed alignment encoding for 1054// VLD/VST instructions and checking the alignment is not specified. 1055def AddrMode6AlignNoneAsmOperand : AsmOperandClass { 1056 let Name = "AlignedMemoryNone"; 1057 let DiagnosticType = "AlignedMemoryRequiresNone"; 1058} 1059def addrmode6alignNone : AddrMode6Align { 1060 // The alignment specifier can only be omitted. 1061 let ParserMatchClass = AddrMode6AlignNoneAsmOperand; 1062} 1063 1064// Special version of addrmode6 to handle 16-bit alignment encoding for 1065// VLD/VST instructions and checking the alignment value. 1066def AddrMode6Align16AsmOperand : AsmOperandClass { 1067 let Name = "AlignedMemory16"; 1068 let DiagnosticType = "AlignedMemoryRequires16"; 1069} 1070def addrmode6align16 : AddrMode6Align { 1071 // The alignment specifier can only be 16 or omitted. 1072 let ParserMatchClass = AddrMode6Align16AsmOperand; 1073} 1074 1075// Special version of addrmode6 to handle 32-bit alignment encoding for 1076// VLD/VST instructions and checking the alignment value. 1077def AddrMode6Align32AsmOperand : AsmOperandClass { 1078 let Name = "AlignedMemory32"; 1079 let DiagnosticType = "AlignedMemoryRequires32"; 1080} 1081def addrmode6align32 : AddrMode6Align { 1082 // The alignment specifier can only be 32 or omitted. 1083 let ParserMatchClass = AddrMode6Align32AsmOperand; 1084} 1085 1086// Special version of addrmode6 to handle 64-bit alignment encoding for 1087// VLD/VST instructions and checking the alignment value. 1088def AddrMode6Align64AsmOperand : AsmOperandClass { 1089 let Name = "AlignedMemory64"; 1090 let DiagnosticType = "AlignedMemoryRequires64"; 1091} 1092def addrmode6align64 : AddrMode6Align { 1093 // The alignment specifier can only be 64 or omitted. 1094 let ParserMatchClass = AddrMode6Align64AsmOperand; 1095} 1096 1097// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1098// for VLD/VST instructions and checking the alignment value. 1099def AddrMode6Align64or128AsmOperand : AsmOperandClass { 1100 let Name = "AlignedMemory64or128"; 1101 let DiagnosticType = "AlignedMemoryRequires64or128"; 1102} 1103def addrmode6align64or128 : AddrMode6Align { 1104 // The alignment specifier can only be 64, 128 or omitted. 1105 let ParserMatchClass = AddrMode6Align64or128AsmOperand; 1106} 1107 1108// Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment 1109// encoding for VLD/VST instructions and checking the alignment value. 1110def AddrMode6Align64or128or256AsmOperand : AsmOperandClass { 1111 let Name = "AlignedMemory64or128or256"; 1112 let DiagnosticType = "AlignedMemoryRequires64or128or256"; 1113} 1114def addrmode6align64or128or256 : AddrMode6Align { 1115 // The alignment specifier can only be 64, 128, 256 or omitted. 1116 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand; 1117} 1118 1119// Special version of addrmode6 to handle alignment encoding for VLD-dup 1120// instructions, specifically VLD4-dup. 1121def addrmode6dup : MemOperand, 1122 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1123 let PrintMethod = "printAddrMode6Operand"; 1124 let MIOperandInfo = (ops GPR:$addr, i32imm); 1125 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1126 // FIXME: This is close, but not quite right. The alignment specifier is 1127 // different. 1128 let ParserMatchClass = AddrMode6AsmOperand; 1129} 1130 1131// Base class for addrmode6dup with specific alignment restrictions. 1132class AddrMode6DupAlign : MemOperand, 1133 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1134 let PrintMethod = "printAddrMode6Operand"; 1135 let MIOperandInfo = (ops GPR:$addr, i32imm); 1136 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1137} 1138 1139// Special version of addrmode6 to handle no allowed alignment encoding for 1140// VLD-dup instruction and checking the alignment is not specified. 1141def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass { 1142 let Name = "DupAlignedMemoryNone"; 1143 let DiagnosticType = "DupAlignedMemoryRequiresNone"; 1144} 1145def addrmode6dupalignNone : AddrMode6DupAlign { 1146 // The alignment specifier can only be omitted. 1147 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand; 1148} 1149 1150// Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup 1151// instruction and checking the alignment value. 1152def AddrMode6dupAlign16AsmOperand : AsmOperandClass { 1153 let Name = "DupAlignedMemory16"; 1154 let DiagnosticType = "DupAlignedMemoryRequires16"; 1155} 1156def addrmode6dupalign16 : AddrMode6DupAlign { 1157 // The alignment specifier can only be 16 or omitted. 1158 let ParserMatchClass = AddrMode6dupAlign16AsmOperand; 1159} 1160 1161// Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup 1162// instruction and checking the alignment value. 1163def AddrMode6dupAlign32AsmOperand : AsmOperandClass { 1164 let Name = "DupAlignedMemory32"; 1165 let DiagnosticType = "DupAlignedMemoryRequires32"; 1166} 1167def addrmode6dupalign32 : AddrMode6DupAlign { 1168 // The alignment specifier can only be 32 or omitted. 1169 let ParserMatchClass = AddrMode6dupAlign32AsmOperand; 1170} 1171 1172// Special version of addrmode6 to handle 64-bit alignment encoding for VLD 1173// instructions and checking the alignment value. 1174def AddrMode6dupAlign64AsmOperand : AsmOperandClass { 1175 let Name = "DupAlignedMemory64"; 1176 let DiagnosticType = "DupAlignedMemoryRequires64"; 1177} 1178def addrmode6dupalign64 : AddrMode6DupAlign { 1179 // The alignment specifier can only be 64 or omitted. 1180 let ParserMatchClass = AddrMode6dupAlign64AsmOperand; 1181} 1182 1183// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1184// for VLD instructions and checking the alignment value. 1185def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass { 1186 let Name = "DupAlignedMemory64or128"; 1187 let DiagnosticType = "DupAlignedMemoryRequires64or128"; 1188} 1189def addrmode6dupalign64or128 : AddrMode6DupAlign { 1190 // The alignment specifier can only be 64, 128 or omitted. 1191 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand; 1192} 1193 1194// addrmodepc := pc + reg 1195// 1196def addrmodepc : MemOperand, 1197 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 1198 let PrintMethod = "printAddrModePCOperand"; 1199 let MIOperandInfo = (ops GPR, i32imm); 1200} 1201 1202// addr_offset_none := reg 1203// 1204def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; } 1205def addr_offset_none : MemOperand, 1206 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> { 1207 let PrintMethod = "printAddrMode7Operand"; 1208 let DecoderMethod = "DecodeAddrMode7Operand"; 1209 let ParserMatchClass = MemNoOffsetAsmOperand; 1210 let MIOperandInfo = (ops GPR:$base); 1211} 1212 1213def nohash_imm : Operand<i32> { 1214 let PrintMethod = "printNoHashImmediate"; 1215} 1216 1217def CoprocNumAsmOperand : AsmOperandClass { 1218 let Name = "CoprocNum"; 1219 let ParserMethod = "parseCoprocNumOperand"; 1220} 1221def p_imm : Operand<i32> { 1222 let PrintMethod = "printPImmediate"; 1223 let ParserMatchClass = CoprocNumAsmOperand; 1224 let DecoderMethod = "DecodeCoprocessor"; 1225} 1226 1227def CoprocRegAsmOperand : AsmOperandClass { 1228 let Name = "CoprocReg"; 1229 let ParserMethod = "parseCoprocRegOperand"; 1230} 1231def c_imm : Operand<i32> { 1232 let PrintMethod = "printCImmediate"; 1233 let ParserMatchClass = CoprocRegAsmOperand; 1234} 1235def CoprocOptionAsmOperand : AsmOperandClass { 1236 let Name = "CoprocOption"; 1237 let ParserMethod = "parseCoprocOptionOperand"; 1238} 1239def coproc_option_imm : Operand<i32> { 1240 let PrintMethod = "printCoprocOptionImm"; 1241 let ParserMatchClass = CoprocOptionAsmOperand; 1242} 1243 1244//===----------------------------------------------------------------------===// 1245 1246include "ARMInstrFormats.td" 1247 1248//===----------------------------------------------------------------------===// 1249// Multiclass helpers... 1250// 1251 1252/// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a 1253/// binop that produces a value. 1254let TwoOperandAliasConstraint = "$Rn = $Rd" in 1255multiclass AsI1_bin_irs<bits<4> opcod, string opc, 1256 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1257 SDPatternOperator opnode, bit Commutable = 0> { 1258 // The register-immediate version is re-materializable. This is useful 1259 // in particular for taking the address of a local. 1260 let isReMaterializable = 1 in { 1261 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1262 iii, opc, "\t$Rd, $Rn, $imm", 1263 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>, 1264 Sched<[WriteALU, ReadALU]> { 1265 bits<4> Rd; 1266 bits<4> Rn; 1267 bits<12> imm; 1268 let Inst{25} = 1; 1269 let Inst{19-16} = Rn; 1270 let Inst{15-12} = Rd; 1271 let Inst{11-0} = imm; 1272 } 1273 } 1274 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1275 iir, opc, "\t$Rd, $Rn, $Rm", 1276 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, 1277 Sched<[WriteALU, ReadALU, ReadALU]> { 1278 bits<4> Rd; 1279 bits<4> Rn; 1280 bits<4> Rm; 1281 let Inst{25} = 0; 1282 let isCommutable = Commutable; 1283 let Inst{19-16} = Rn; 1284 let Inst{15-12} = Rd; 1285 let Inst{11-4} = 0b00000000; 1286 let Inst{3-0} = Rm; 1287 } 1288 1289 def rsi : AsI1<opcod, (outs GPR:$Rd), 1290 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1291 iis, opc, "\t$Rd, $Rn, $shift", 1292 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>, 1293 Sched<[WriteALUsi, ReadALU]> { 1294 bits<4> Rd; 1295 bits<4> Rn; 1296 bits<12> shift; 1297 let Inst{25} = 0; 1298 let Inst{19-16} = Rn; 1299 let Inst{15-12} = Rd; 1300 let Inst{11-5} = shift{11-5}; 1301 let Inst{4} = 0; 1302 let Inst{3-0} = shift{3-0}; 1303 } 1304 1305 def rsr : AsI1<opcod, (outs GPR:$Rd), 1306 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1307 iis, opc, "\t$Rd, $Rn, $shift", 1308 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>, 1309 Sched<[WriteALUsr, ReadALUsr]> { 1310 bits<4> Rd; 1311 bits<4> Rn; 1312 bits<12> shift; 1313 let Inst{25} = 0; 1314 let Inst{19-16} = Rn; 1315 let Inst{15-12} = Rd; 1316 let Inst{11-8} = shift{11-8}; 1317 let Inst{7} = 0; 1318 let Inst{6-5} = shift{6-5}; 1319 let Inst{4} = 1; 1320 let Inst{3-0} = shift{3-0}; 1321 } 1322} 1323 1324/// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are 1325/// reversed. The 'rr' form is only defined for the disassembler; for codegen 1326/// it is equivalent to the AsI1_bin_irs counterpart. 1327let TwoOperandAliasConstraint = "$Rn = $Rd" in 1328multiclass AsI1_rbin_irs<bits<4> opcod, string opc, 1329 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1330 SDNode opnode, bit Commutable = 0> { 1331 // The register-immediate version is re-materializable. This is useful 1332 // in particular for taking the address of a local. 1333 let isReMaterializable = 1 in { 1334 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1335 iii, opc, "\t$Rd, $Rn, $imm", 1336 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>, 1337 Sched<[WriteALU, ReadALU]> { 1338 bits<4> Rd; 1339 bits<4> Rn; 1340 bits<12> imm; 1341 let Inst{25} = 1; 1342 let Inst{19-16} = Rn; 1343 let Inst{15-12} = Rd; 1344 let Inst{11-0} = imm; 1345 } 1346 } 1347 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1348 iir, opc, "\t$Rd, $Rn, $Rm", 1349 [/* pattern left blank */]>, 1350 Sched<[WriteALU, ReadALU, ReadALU]> { 1351 bits<4> Rd; 1352 bits<4> Rn; 1353 bits<4> Rm; 1354 let Inst{11-4} = 0b00000000; 1355 let Inst{25} = 0; 1356 let Inst{3-0} = Rm; 1357 let Inst{15-12} = Rd; 1358 let Inst{19-16} = Rn; 1359 } 1360 1361 def rsi : AsI1<opcod, (outs GPR:$Rd), 1362 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1363 iis, opc, "\t$Rd, $Rn, $shift", 1364 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>, 1365 Sched<[WriteALUsi, ReadALU]> { 1366 bits<4> Rd; 1367 bits<4> Rn; 1368 bits<12> shift; 1369 let Inst{25} = 0; 1370 let Inst{19-16} = Rn; 1371 let Inst{15-12} = Rd; 1372 let Inst{11-5} = shift{11-5}; 1373 let Inst{4} = 0; 1374 let Inst{3-0} = shift{3-0}; 1375 } 1376 1377 def rsr : AsI1<opcod, (outs GPR:$Rd), 1378 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1379 iis, opc, "\t$Rd, $Rn, $shift", 1380 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>, 1381 Sched<[WriteALUsr, ReadALUsr]> { 1382 bits<4> Rd; 1383 bits<4> Rn; 1384 bits<12> shift; 1385 let Inst{25} = 0; 1386 let Inst{19-16} = Rn; 1387 let Inst{15-12} = Rd; 1388 let Inst{11-8} = shift{11-8}; 1389 let Inst{7} = 0; 1390 let Inst{6-5} = shift{6-5}; 1391 let Inst{4} = 1; 1392 let Inst{3-0} = shift{3-0}; 1393 } 1394} 1395 1396/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default. 1397/// 1398/// These opcodes will be converted to the real non-S opcodes by 1399/// AdjustInstrPostInstrSelection after giving them an optional CPSR operand. 1400let hasPostISelHook = 1, Defs = [CPSR] in { 1401multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir, 1402 InstrItinClass iis, SDNode opnode, 1403 bit Commutable = 0> { 1404 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1405 4, iii, 1406 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>, 1407 Sched<[WriteALU, ReadALU]>; 1408 1409 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p), 1410 4, iir, 1411 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>, 1412 Sched<[WriteALU, ReadALU, ReadALU]> { 1413 let isCommutable = Commutable; 1414 } 1415 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1416 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1417 4, iis, 1418 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1419 so_reg_imm:$shift))]>, 1420 Sched<[WriteALUsi, ReadALU]>; 1421 1422 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1423 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1424 4, iis, 1425 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1426 so_reg_reg:$shift))]>, 1427 Sched<[WriteALUSsr, ReadALUsr]>; 1428} 1429} 1430 1431/// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG 1432/// operands are reversed. 1433let hasPostISelHook = 1, Defs = [CPSR] in { 1434multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir, 1435 InstrItinClass iis, SDNode opnode, 1436 bit Commutable = 0> { 1437 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1438 4, iii, 1439 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>, 1440 Sched<[WriteALU, ReadALU]>; 1441 1442 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1443 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1444 4, iis, 1445 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, 1446 GPR:$Rn))]>, 1447 Sched<[WriteALUsi, ReadALU]>; 1448 1449 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1450 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1451 4, iis, 1452 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, 1453 GPR:$Rn))]>, 1454 Sched<[WriteALUSsr, ReadALUsr]>; 1455} 1456} 1457 1458/// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test 1459/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 1460/// a explicit result, only implicitly set CPSR. 1461let isCompare = 1, Defs = [CPSR] in { 1462multiclass AI1_cmp_irs<bits<4> opcod, string opc, 1463 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1464 SDPatternOperator opnode, bit Commutable = 0, 1465 string rrDecoderMethod = ""> { 1466 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii, 1467 opc, "\t$Rn, $imm", 1468 [(opnode GPR:$Rn, mod_imm:$imm)]>, 1469 Sched<[WriteCMP, ReadALU]> { 1470 bits<4> Rn; 1471 bits<12> imm; 1472 let Inst{25} = 1; 1473 let Inst{20} = 1; 1474 let Inst{19-16} = Rn; 1475 let Inst{15-12} = 0b0000; 1476 let Inst{11-0} = imm; 1477 1478 let Unpredictable{15-12} = 0b1111; 1479 } 1480 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir, 1481 opc, "\t$Rn, $Rm", 1482 [(opnode GPR:$Rn, GPR:$Rm)]>, 1483 Sched<[WriteCMP, ReadALU, ReadALU]> { 1484 bits<4> Rn; 1485 bits<4> Rm; 1486 let isCommutable = Commutable; 1487 let Inst{25} = 0; 1488 let Inst{20} = 1; 1489 let Inst{19-16} = Rn; 1490 let Inst{15-12} = 0b0000; 1491 let Inst{11-4} = 0b00000000; 1492 let Inst{3-0} = Rm; 1493 let DecoderMethod = rrDecoderMethod; 1494 1495 let Unpredictable{15-12} = 0b1111; 1496 } 1497 def rsi : AI1<opcod, (outs), 1498 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis, 1499 opc, "\t$Rn, $shift", 1500 [(opnode GPR:$Rn, so_reg_imm:$shift)]>, 1501 Sched<[WriteCMPsi, ReadALU]> { 1502 bits<4> Rn; 1503 bits<12> shift; 1504 let Inst{25} = 0; 1505 let Inst{20} = 1; 1506 let Inst{19-16} = Rn; 1507 let Inst{15-12} = 0b0000; 1508 let Inst{11-5} = shift{11-5}; 1509 let Inst{4} = 0; 1510 let Inst{3-0} = shift{3-0}; 1511 1512 let Unpredictable{15-12} = 0b1111; 1513 } 1514 def rsr : AI1<opcod, (outs), 1515 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis, 1516 opc, "\t$Rn, $shift", 1517 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>, 1518 Sched<[WriteCMPsr, ReadALU]> { 1519 bits<4> Rn; 1520 bits<12> shift; 1521 let Inst{25} = 0; 1522 let Inst{20} = 1; 1523 let Inst{19-16} = Rn; 1524 let Inst{15-12} = 0b0000; 1525 let Inst{11-8} = shift{11-8}; 1526 let Inst{7} = 0; 1527 let Inst{6-5} = shift{6-5}; 1528 let Inst{4} = 1; 1529 let Inst{3-0} = shift{3-0}; 1530 1531 let Unpredictable{15-12} = 0b1111; 1532 } 1533 1534} 1535} 1536 1537/// AI_ext_rrot - A unary operation with two forms: one whose operand is a 1538/// register and one whose operand is a register rotated by 8/16/24. 1539/// FIXME: Remove the 'r' variant. Its rot_imm is zero. 1540class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> 1541 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1542 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", 1543 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1544 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1545 bits<4> Rd; 1546 bits<4> Rm; 1547 bits<2> rot; 1548 let Inst{19-16} = 0b1111; 1549 let Inst{15-12} = Rd; 1550 let Inst{11-10} = rot; 1551 let Inst{3-0} = Rm; 1552} 1553 1554class AI_ext_rrot_np<bits<8> opcod, string opc> 1555 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1556 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>, 1557 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1558 bits<2> rot; 1559 let Inst{19-16} = 0b1111; 1560 let Inst{11-10} = rot; 1561 } 1562 1563/// AI_exta_rrot - A binary operation with two forms: one whose operand is a 1564/// register and one whose operand is a register rotated by 8/16/24. 1565class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> 1566 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1567 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", 1568 [(set GPRnopc:$Rd, (opnode GPR:$Rn, 1569 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1570 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1571 bits<4> Rd; 1572 bits<4> Rm; 1573 bits<4> Rn; 1574 bits<2> rot; 1575 let Inst{19-16} = Rn; 1576 let Inst{15-12} = Rd; 1577 let Inst{11-10} = rot; 1578 let Inst{9-4} = 0b000111; 1579 let Inst{3-0} = Rm; 1580} 1581 1582class AI_exta_rrot_np<bits<8> opcod, string opc> 1583 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1584 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>, 1585 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1586 bits<4> Rn; 1587 bits<2> rot; 1588 let Inst{19-16} = Rn; 1589 let Inst{11-10} = rot; 1590} 1591 1592/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. 1593let TwoOperandAliasConstraint = "$Rn = $Rd" in 1594multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode, 1595 bit Commutable = 0> { 1596 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1597 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1598 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1599 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>, 1600 Requires<[IsARM]>, 1601 Sched<[WriteALU, ReadALU]> { 1602 bits<4> Rd; 1603 bits<4> Rn; 1604 bits<12> imm; 1605 let Inst{25} = 1; 1606 let Inst{15-12} = Rd; 1607 let Inst{19-16} = Rn; 1608 let Inst{11-0} = imm; 1609 } 1610 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1611 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1612 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>, 1613 Requires<[IsARM]>, 1614 Sched<[WriteALU, ReadALU, ReadALU]> { 1615 bits<4> Rd; 1616 bits<4> Rn; 1617 bits<4> Rm; 1618 let Inst{11-4} = 0b00000000; 1619 let Inst{25} = 0; 1620 let isCommutable = Commutable; 1621 let Inst{3-0} = Rm; 1622 let Inst{15-12} = Rd; 1623 let Inst{19-16} = Rn; 1624 } 1625 def rsi : AsI1<opcod, (outs GPR:$Rd), 1626 (ins GPR:$Rn, so_reg_imm:$shift), 1627 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1628 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>, 1629 Requires<[IsARM]>, 1630 Sched<[WriteALUsi, ReadALU]> { 1631 bits<4> Rd; 1632 bits<4> Rn; 1633 bits<12> shift; 1634 let Inst{25} = 0; 1635 let Inst{19-16} = Rn; 1636 let Inst{15-12} = Rd; 1637 let Inst{11-5} = shift{11-5}; 1638 let Inst{4} = 0; 1639 let Inst{3-0} = shift{3-0}; 1640 } 1641 def rsr : AsI1<opcod, (outs GPRnopc:$Rd), 1642 (ins GPRnopc:$Rn, so_reg_reg:$shift), 1643 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1644 [(set GPRnopc:$Rd, CPSR, 1645 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>, 1646 Requires<[IsARM]>, 1647 Sched<[WriteALUsr, ReadALUsr]> { 1648 bits<4> Rd; 1649 bits<4> Rn; 1650 bits<12> shift; 1651 let Inst{25} = 0; 1652 let Inst{19-16} = Rn; 1653 let Inst{15-12} = Rd; 1654 let Inst{11-8} = shift{11-8}; 1655 let Inst{7} = 0; 1656 let Inst{6-5} = shift{6-5}; 1657 let Inst{4} = 1; 1658 let Inst{3-0} = shift{3-0}; 1659 } 1660 } 1661} 1662 1663/// AI1_rsc_irs - Define instructions and patterns for rsc 1664let TwoOperandAliasConstraint = "$Rn = $Rd" in 1665multiclass AI1_rsc_irs<bits<4> opcod, string opc, SDNode opnode> { 1666 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1667 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1668 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1669 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>, 1670 Requires<[IsARM]>, 1671 Sched<[WriteALU, ReadALU]> { 1672 bits<4> Rd; 1673 bits<4> Rn; 1674 bits<12> imm; 1675 let Inst{25} = 1; 1676 let Inst{15-12} = Rd; 1677 let Inst{19-16} = Rn; 1678 let Inst{11-0} = imm; 1679 } 1680 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1681 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1682 [/* pattern left blank */]>, 1683 Sched<[WriteALU, ReadALU, ReadALU]> { 1684 bits<4> Rd; 1685 bits<4> Rn; 1686 bits<4> Rm; 1687 let Inst{11-4} = 0b00000000; 1688 let Inst{25} = 0; 1689 let Inst{3-0} = Rm; 1690 let Inst{15-12} = Rd; 1691 let Inst{19-16} = Rn; 1692 } 1693 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), 1694 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1695 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>, 1696 Requires<[IsARM]>, 1697 Sched<[WriteALUsi, ReadALU]> { 1698 bits<4> Rd; 1699 bits<4> Rn; 1700 bits<12> shift; 1701 let Inst{25} = 0; 1702 let Inst{19-16} = Rn; 1703 let Inst{15-12} = Rd; 1704 let Inst{11-5} = shift{11-5}; 1705 let Inst{4} = 0; 1706 let Inst{3-0} = shift{3-0}; 1707 } 1708 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), 1709 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1710 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>, 1711 Requires<[IsARM]>, 1712 Sched<[WriteALUsr, ReadALUsr]> { 1713 bits<4> Rd; 1714 bits<4> Rn; 1715 bits<12> shift; 1716 let Inst{25} = 0; 1717 let Inst{19-16} = Rn; 1718 let Inst{15-12} = Rd; 1719 let Inst{11-8} = shift{11-8}; 1720 let Inst{7} = 0; 1721 let Inst{6-5} = shift{6-5}; 1722 let Inst{4} = 1; 1723 let Inst{3-0} = shift{3-0}; 1724 } 1725 } 1726} 1727 1728let canFoldAsLoad = 1, isReMaterializable = 1 in { 1729multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii, 1730 InstrItinClass iir, PatFrag opnode> { 1731 // Note: We use the complex addrmode_imm12 rather than just an input 1732 // GPR and a constrained immediate so that we can use this to match 1733 // frame index references and avoid matching constant pool references. 1734 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 1735 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1736 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { 1737 bits<4> Rt; 1738 bits<17> addr; 1739 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1740 let Inst{19-16} = addr{16-13}; // Rn 1741 let Inst{15-12} = Rt; 1742 let Inst{11-0} = addr{11-0}; // imm12 1743 } 1744 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift), 1745 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1746 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { 1747 bits<4> Rt; 1748 bits<17> shift; 1749 let shift{4} = 0; // Inst{4} = 0 1750 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1751 let Inst{19-16} = shift{16-13}; // Rn 1752 let Inst{15-12} = Rt; 1753 let Inst{11-0} = shift{11-0}; 1754 } 1755} 1756} 1757 1758let canFoldAsLoad = 1, isReMaterializable = 1 in { 1759multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii, 1760 InstrItinClass iir, PatFrag opnode> { 1761 // Note: We use the complex addrmode_imm12 rather than just an input 1762 // GPR and a constrained immediate so that we can use this to match 1763 // frame index references and avoid matching constant pool references. 1764 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), 1765 (ins addrmode_imm12:$addr), 1766 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1767 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> { 1768 bits<4> Rt; 1769 bits<17> addr; 1770 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1771 let Inst{19-16} = addr{16-13}; // Rn 1772 let Inst{15-12} = Rt; 1773 let Inst{11-0} = addr{11-0}; // imm12 1774 } 1775 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), 1776 (ins ldst_so_reg:$shift), 1777 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1778 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> { 1779 bits<4> Rt; 1780 bits<17> shift; 1781 let shift{4} = 0; // Inst{4} = 0 1782 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1783 let Inst{19-16} = shift{16-13}; // Rn 1784 let Inst{15-12} = Rt; 1785 let Inst{11-0} = shift{11-0}; 1786 } 1787} 1788} 1789 1790 1791multiclass AI_str1<bit isByte, string opc, InstrItinClass iii, 1792 InstrItinClass iir, PatFrag opnode> { 1793 // Note: We use the complex addrmode_imm12 rather than just an input 1794 // GPR and a constrained immediate so that we can use this to match 1795 // frame index references and avoid matching constant pool references. 1796 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1797 (ins GPR:$Rt, addrmode_imm12:$addr), 1798 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1799 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> { 1800 bits<4> Rt; 1801 bits<17> addr; 1802 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1803 let Inst{19-16} = addr{16-13}; // Rn 1804 let Inst{15-12} = Rt; 1805 let Inst{11-0} = addr{11-0}; // imm12 1806 } 1807 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift), 1808 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1809 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> { 1810 bits<4> Rt; 1811 bits<17> shift; 1812 let shift{4} = 0; // Inst{4} = 0 1813 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1814 let Inst{19-16} = shift{16-13}; // Rn 1815 let Inst{15-12} = Rt; 1816 let Inst{11-0} = shift{11-0}; 1817 } 1818} 1819 1820multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii, 1821 InstrItinClass iir, PatFrag opnode> { 1822 // Note: We use the complex addrmode_imm12 rather than just an input 1823 // GPR and a constrained immediate so that we can use this to match 1824 // frame index references and avoid matching constant pool references. 1825 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1826 (ins GPRnopc:$Rt, addrmode_imm12:$addr), 1827 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1828 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> { 1829 bits<4> Rt; 1830 bits<17> addr; 1831 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1832 let Inst{19-16} = addr{16-13}; // Rn 1833 let Inst{15-12} = Rt; 1834 let Inst{11-0} = addr{11-0}; // imm12 1835 } 1836 def rs : AI2ldst<0b011, 0, isByte, (outs), 1837 (ins GPRnopc:$Rt, ldst_so_reg:$shift), 1838 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1839 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> { 1840 bits<4> Rt; 1841 bits<17> shift; 1842 let shift{4} = 0; // Inst{4} = 0 1843 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1844 let Inst{19-16} = shift{16-13}; // Rn 1845 let Inst{15-12} = Rt; 1846 let Inst{11-0} = shift{11-0}; 1847 } 1848} 1849 1850 1851//===----------------------------------------------------------------------===// 1852// Instructions 1853//===----------------------------------------------------------------------===// 1854 1855//===----------------------------------------------------------------------===// 1856// Miscellaneous Instructions. 1857// 1858 1859/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 1860/// the function. The first operand is the ID# for this instruction, the second 1861/// is the index into the MachineConstantPool that this is, the third is the 1862/// size in bytes of this constant pool entry. 1863let hasSideEffects = 0, isNotDuplicable = 1 in 1864def CONSTPOOL_ENTRY : 1865PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1866 i32imm:$size), NoItinerary, []>; 1867 1868/// A jumptable consisting of direct 32-bit addresses of the destination basic 1869/// blocks (either absolute, or relative to the start of the jump-table in PIC 1870/// mode). Used mostly in ARM and Thumb-1 modes. 1871def JUMPTABLE_ADDRS : 1872PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1873 i32imm:$size), NoItinerary, []>; 1874 1875/// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables 1876/// that cannot be optimised to use TBB or TBH. 1877def JUMPTABLE_INSTS : 1878PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1879 i32imm:$size), NoItinerary, []>; 1880 1881/// A jumptable consisting of 8-bit unsigned integers representing offsets from 1882/// a TBB instruction. 1883def JUMPTABLE_TBB : 1884PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1885 i32imm:$size), NoItinerary, []>; 1886 1887/// A jumptable consisting of 16-bit unsigned integers representing offsets from 1888/// a TBH instruction. 1889def JUMPTABLE_TBH : 1890PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1891 i32imm:$size), NoItinerary, []>; 1892 1893 1894// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 1895// from removing one half of the matched pairs. That breaks PEI, which assumes 1896// these will always be in pairs, and asserts if it finds otherwise. Better way? 1897let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 1898def ADJCALLSTACKUP : 1899PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, 1900 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; 1901 1902def ADJCALLSTACKDOWN : 1903PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary, 1904 [(ARMcallseq_start timm:$amt)]>; 1905} 1906 1907def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary, 1908 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>, 1909 Requires<[IsARM, HasV6]> { 1910 bits<8> imm; 1911 let Inst{27-8} = 0b00110010000011110000; 1912 let Inst{7-0} = imm; 1913} 1914 1915def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>; 1916def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>; 1917def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>; 1918def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>; 1919def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>; 1920def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>; 1921 1922def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel", 1923 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> { 1924 bits<4> Rd; 1925 bits<4> Rn; 1926 bits<4> Rm; 1927 let Inst{3-0} = Rm; 1928 let Inst{15-12} = Rd; 1929 let Inst{19-16} = Rn; 1930 let Inst{27-20} = 0b01101000; 1931 let Inst{7-4} = 0b1011; 1932 let Inst{11-8} = 0b1111; 1933 let Unpredictable{11-8} = 0b1111; 1934} 1935 1936// The 16-bit operand $val can be used by a debugger to store more information 1937// about the breakpoint. 1938def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 1939 "bkpt", "\t$val", []>, Requires<[IsARM]> { 1940 bits<16> val; 1941 let Inst{3-0} = val{3-0}; 1942 let Inst{19-8} = val{15-4}; 1943 let Inst{27-20} = 0b00010010; 1944 let Inst{31-28} = 0xe; // AL 1945 let Inst{7-4} = 0b0111; 1946} 1947// default immediate for breakpoint mnemonic 1948def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>; 1949 1950def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 1951 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> { 1952 bits<16> val; 1953 let Inst{3-0} = val{3-0}; 1954 let Inst{19-8} = val{15-4}; 1955 let Inst{27-20} = 0b00010000; 1956 let Inst{31-28} = 0xe; // AL 1957 let Inst{7-4} = 0b0111; 1958} 1959 1960// Change Processor State 1961// FIXME: We should use InstAlias to handle the optional operands. 1962class CPS<dag iops, string asm_ops> 1963 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops), 1964 []>, Requires<[IsARM]> { 1965 bits<2> imod; 1966 bits<3> iflags; 1967 bits<5> mode; 1968 bit M; 1969 1970 let Inst{31-28} = 0b1111; 1971 let Inst{27-20} = 0b00010000; 1972 let Inst{19-18} = imod; 1973 let Inst{17} = M; // Enabled if mode is set; 1974 let Inst{16-9} = 0b00000000; 1975 let Inst{8-6} = iflags; 1976 let Inst{5} = 0; 1977 let Inst{4-0} = mode; 1978} 1979 1980let DecoderMethod = "DecodeCPSInstruction" in { 1981let M = 1 in 1982 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode), 1983 "$imod\t$iflags, $mode">; 1984let mode = 0, M = 0 in 1985 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">; 1986 1987let imod = 0, iflags = 0, M = 1 in 1988 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">; 1989} 1990 1991// Preload signals the memory system of possible future data/instruction access. 1992multiclass APreLoad<bits<1> read, bits<1> data, string opc> { 1993 1994 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm, 1995 IIC_Preload, !strconcat(opc, "\t$addr"), 1996 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>, 1997 Sched<[WritePreLd]> { 1998 bits<4> Rt; 1999 bits<17> addr; 2000 let Inst{31-26} = 0b111101; 2001 let Inst{25} = 0; // 0 for immediate form 2002 let Inst{24} = data; 2003 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2004 let Inst{22} = read; 2005 let Inst{21-20} = 0b01; 2006 let Inst{19-16} = addr{16-13}; // Rn 2007 let Inst{15-12} = 0b1111; 2008 let Inst{11-0} = addr{11-0}; // imm12 2009 } 2010 2011 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, 2012 !strconcat(opc, "\t$shift"), 2013 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>, 2014 Sched<[WritePreLd]> { 2015 bits<17> shift; 2016 let Inst{31-26} = 0b111101; 2017 let Inst{25} = 1; // 1 for register form 2018 let Inst{24} = data; 2019 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2020 let Inst{22} = read; 2021 let Inst{21-20} = 0b01; 2022 let Inst{19-16} = shift{16-13}; // Rn 2023 let Inst{15-12} = 0b1111; 2024 let Inst{11-0} = shift{11-0}; 2025 let Inst{4} = 0; 2026 } 2027} 2028 2029defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>; 2030defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>; 2031defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>; 2032 2033def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary, 2034 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> { 2035 bits<1> end; 2036 let Inst{31-10} = 0b1111000100000001000000; 2037 let Inst{9} = end; 2038 let Inst{8-0} = 0; 2039} 2040 2041def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", 2042 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> { 2043 bits<4> opt; 2044 let Inst{27-4} = 0b001100100000111100001111; 2045 let Inst{3-0} = opt; 2046} 2047 2048// A8.8.247 UDF - Undefined (Encoding A1) 2049def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary, 2050 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> { 2051 bits<16> imm16; 2052 let Inst{31-28} = 0b1110; // AL 2053 let Inst{27-25} = 0b011; 2054 let Inst{24-20} = 0b11111; 2055 let Inst{19-8} = imm16{15-4}; 2056 let Inst{7-4} = 0b1111; 2057 let Inst{3-0} = imm16{3-0}; 2058} 2059 2060/* 2061 * A5.4 Permanently UNDEFINED instructions. 2062 * 2063 * For most targets use UDF #65006, for which the OS will generate SIGTRAP. 2064 * Other UDF encodings generate SIGILL. 2065 * 2066 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb. 2067 * Encoding A1: 2068 * 1110 0111 1111 iiii iiii iiii 1111 iiii 2069 * Encoding T1: 2070 * 1101 1110 iiii iiii 2071 * It uses the following encoding: 2072 * 1110 0111 1111 1110 1101 1110 1111 0000 2073 * - In ARM: UDF #60896; 2074 * - In Thumb: UDF #254 followed by a branch-to-self. 2075 */ 2076let isBarrier = 1, isTerminator = 1 in 2077def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary, 2078 "trap", [(trap)]>, 2079 Requires<[IsARM,UseNaClTrap]> { 2080 let Inst = 0xe7fedef0; 2081} 2082let isBarrier = 1, isTerminator = 1 in 2083def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, 2084 "trap", [(trap)]>, 2085 Requires<[IsARM,DontUseNaClTrap]> { 2086 let Inst = 0xe7ffdefe; 2087} 2088 2089// Address computation and loads and stores in PIC mode. 2090let isNotDuplicable = 1 in { 2091def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 2092 4, IIC_iALUr, 2093 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>, 2094 Sched<[WriteALU, ReadALU]>; 2095 2096let AddedComplexity = 10 in { 2097def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 2098 4, IIC_iLoad_r, 2099 [(set GPR:$dst, (load addrmodepc:$addr))]>; 2100 2101def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2102 4, IIC_iLoad_bh_r, 2103 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>; 2104 2105def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2106 4, IIC_iLoad_bh_r, 2107 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>; 2108 2109def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2110 4, IIC_iLoad_bh_r, 2111 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>; 2112 2113def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2114 4, IIC_iLoad_bh_r, 2115 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>; 2116} 2117let AddedComplexity = 10 in { 2118def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2119 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>; 2120 2121def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2122 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, 2123 addrmodepc:$addr)]>; 2124 2125def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2126 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 2127} 2128} // isNotDuplicable = 1 2129 2130 2131// LEApcrel - Load a pc-relative address into a register without offending the 2132// assembler. 2133let hasSideEffects = 0, isReMaterializable = 1 in 2134// The 'adr' mnemonic encodes differently if the label is before or after 2135// the instruction. The {24-21} opcode bits are set by the fixup, as we don't 2136// know until then which form of the instruction will be used. 2137def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), 2138 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>, 2139 Sched<[WriteALU, ReadALU]> { 2140 bits<4> Rd; 2141 bits<14> label; 2142 let Inst{27-25} = 0b001; 2143 let Inst{24} = 0; 2144 let Inst{23-22} = label{13-12}; 2145 let Inst{21} = 0; 2146 let Inst{20} = 0; 2147 let Inst{19-16} = 0b1111; 2148 let Inst{15-12} = Rd; 2149 let Inst{11-0} = label{11-0}; 2150} 2151 2152let hasSideEffects = 1 in { 2153def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 2154 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2155 2156def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd), 2157 (ins i32imm:$label, pred:$p), 2158 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2159} 2160 2161//===----------------------------------------------------------------------===// 2162// Control Flow Instructions. 2163// 2164 2165let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 2166 // ARMV4T and above 2167 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2168 "bx", "\tlr", [(ARMretflag)]>, 2169 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2170 let Inst{27-0} = 0b0001001011111111111100011110; 2171 } 2172 2173 // ARMV4 only 2174 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2175 "mov", "\tpc, lr", [(ARMretflag)]>, 2176 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> { 2177 let Inst{27-0} = 0b0001101000001111000000001110; 2178 } 2179 2180 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets 2181 // the user-space one). 2182 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p), 2183 4, IIC_Br, 2184 [(ARMintretflag imm:$offset)]>; 2185} 2186 2187// Indirect branches 2188let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 2189 // ARMV4T and above 2190 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst", 2191 [(brind GPR:$dst)]>, 2192 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2193 bits<4> dst; 2194 let Inst{31-4} = 0b1110000100101111111111110001; 2195 let Inst{3-0} = dst; 2196 } 2197 2198 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, 2199 "bx", "\t$dst", [/* pattern left blank */]>, 2200 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2201 bits<4> dst; 2202 let Inst{27-4} = 0b000100101111111111110001; 2203 let Inst{3-0} = dst; 2204 } 2205} 2206 2207// SP is marked as a use to prevent stack-pointer assignments that appear 2208// immediately before calls from potentially appearing dead. 2209let isCall = 1, 2210 // FIXME: Do we really need a non-predicated version? If so, it should 2211 // at least be a pseudo instruction expanding to the predicated version 2212 // at MC lowering time. 2213 Defs = [LR], Uses = [SP] in { 2214 def BL : ABXI<0b1011, (outs), (ins bl_target:$func), 2215 IIC_Br, "bl\t$func", 2216 [(ARMcall tglobaladdr:$func)]>, 2217 Requires<[IsARM]>, Sched<[WriteBrL]> { 2218 let Inst{31-28} = 0b1110; 2219 bits<24> func; 2220 let Inst{23-0} = func; 2221 let DecoderMethod = "DecodeBranchImmInstruction"; 2222 } 2223 2224 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func), 2225 IIC_Br, "bl", "\t$func", 2226 [(ARMcall_pred tglobaladdr:$func)]>, 2227 Requires<[IsARM]>, Sched<[WriteBrL]> { 2228 bits<24> func; 2229 let Inst{23-0} = func; 2230 let DecoderMethod = "DecodeBranchImmInstruction"; 2231 } 2232 2233 // ARMv5T and above 2234 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm, 2235 IIC_Br, "blx\t$func", 2236 [(ARMcall GPR:$func)]>, 2237 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2238 bits<4> func; 2239 let Inst{31-4} = 0b1110000100101111111111110011; 2240 let Inst{3-0} = func; 2241 } 2242 2243 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm, 2244 IIC_Br, "blx", "\t$func", 2245 [(ARMcall_pred GPR:$func)]>, 2246 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2247 bits<4> func; 2248 let Inst{27-4} = 0b000100101111111111110011; 2249 let Inst{3-0} = func; 2250 } 2251 2252 // ARMv4T 2253 // Note: Restrict $func to the tGPR regclass to prevent it being in LR. 2254 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2255 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2256 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>; 2257 2258 // ARMv4 2259 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2260 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2261 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 2262 2263 // mov lr, pc; b if callee is marked noreturn to avoid confusing the 2264 // return stack predictor. 2265 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func), 2266 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>, 2267 Requires<[IsARM]>, Sched<[WriteBr]>; 2268} 2269 2270let isBranch = 1, isTerminator = 1 in { 2271 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 2272 // a two-value operand where a dag node expects two operands. :( 2273 def Bcc : ABI<0b1010, (outs), (ins br_target:$target), 2274 IIC_Br, "b", "\t$target", 2275 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>, 2276 Sched<[WriteBr]> { 2277 bits<24> target; 2278 let Inst{23-0} = target; 2279 let DecoderMethod = "DecodeBranchImmInstruction"; 2280 } 2281 2282 let isBarrier = 1 in { 2283 // B is "predicable" since it's just a Bcc with an 'always' condition. 2284 let isPredicable = 1 in 2285 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly 2286 // should be sufficient. 2287 // FIXME: Is B really a Barrier? That doesn't seem right. 2288 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br, 2289 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>, 2290 Sched<[WriteBr]>; 2291 2292 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in { 2293 def BR_JTr : ARMPseudoInst<(outs), 2294 (ins GPR:$target, i32imm:$jt), 2295 0, IIC_Br, 2296 [(ARMbrjt GPR:$target, tjumptable:$jt)]>, 2297 Sched<[WriteBr]>; 2298 // FIXME: This shouldn't use the generic "addrmode2," but rather be split 2299 // into i12 and rs suffixed versions. 2300 def BR_JTm : ARMPseudoInst<(outs), 2301 (ins addrmode2:$target, i32imm:$jt), 2302 0, IIC_Br, 2303 [(ARMbrjt (i32 (load addrmode2:$target)), 2304 tjumptable:$jt)]>, Sched<[WriteBrTbl]>; 2305 def BR_JTadd : ARMPseudoInst<(outs), 2306 (ins GPR:$target, GPR:$idx, i32imm:$jt), 2307 0, IIC_Br, 2308 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>, 2309 Sched<[WriteBrTbl]>; 2310 } // isNotDuplicable = 1, isIndirectBranch = 1 2311 } // isBarrier = 1 2312 2313} 2314 2315// BLX (immediate) 2316def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary, 2317 "blx\t$target", []>, 2318 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2319 let Inst{31-25} = 0b1111101; 2320 bits<25> target; 2321 let Inst{23-0} = target{24-1}; 2322 let Inst{24} = target{0}; 2323 let isCall = 1; 2324} 2325 2326// Branch and Exchange Jazelle 2327def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", 2328 [/* pattern left blank */]>, Sched<[WriteBr]> { 2329 bits<4> func; 2330 let Inst{23-20} = 0b0010; 2331 let Inst{19-8} = 0xfff; 2332 let Inst{7-4} = 0b0010; 2333 let Inst{3-0} = func; 2334 let isBranch = 1; 2335} 2336 2337// Tail calls. 2338 2339let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { 2340 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>, 2341 Sched<[WriteBr]>; 2342 2343 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>, 2344 Sched<[WriteBr]>; 2345 2346 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst), 2347 4, IIC_Br, [], 2348 (Bcc br_target:$dst, (ops 14, zero_reg))>, 2349 Requires<[IsARM]>, Sched<[WriteBr]>; 2350 2351 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst), 2352 4, IIC_Br, [], 2353 (BX GPR:$dst)>, Sched<[WriteBr]>, 2354 Requires<[IsARM]>; 2355} 2356 2357// Secure Monitor Call is a system instruction. 2358def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", 2359 []>, Requires<[IsARM, HasTrustZone]> { 2360 bits<4> opt; 2361 let Inst{23-4} = 0b01100000000000000111; 2362 let Inst{3-0} = opt; 2363} 2364def : MnemonicAlias<"smi", "smc">; 2365 2366// Supervisor Call (Software Interrupt) 2367let isCall = 1, Uses = [SP] in { 2368def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>, 2369 Sched<[WriteBr]> { 2370 bits<24> svc; 2371 let Inst{23-0} = svc; 2372} 2373} 2374 2375// Store Return State 2376class SRSI<bit wb, string asm> 2377 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm, 2378 NoItinerary, asm, "", []> { 2379 bits<5> mode; 2380 let Inst{31-28} = 0b1111; 2381 let Inst{27-25} = 0b100; 2382 let Inst{22} = 1; 2383 let Inst{21} = wb; 2384 let Inst{20} = 0; 2385 let Inst{19-16} = 0b1101; // SP 2386 let Inst{15-5} = 0b00000101000; 2387 let Inst{4-0} = mode; 2388} 2389 2390def SRSDA : SRSI<0, "srsda\tsp, $mode"> { 2391 let Inst{24-23} = 0; 2392} 2393def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> { 2394 let Inst{24-23} = 0; 2395} 2396def SRSDB : SRSI<0, "srsdb\tsp, $mode"> { 2397 let Inst{24-23} = 0b10; 2398} 2399def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> { 2400 let Inst{24-23} = 0b10; 2401} 2402def SRSIA : SRSI<0, "srsia\tsp, $mode"> { 2403 let Inst{24-23} = 0b01; 2404} 2405def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> { 2406 let Inst{24-23} = 0b01; 2407} 2408def SRSIB : SRSI<0, "srsib\tsp, $mode"> { 2409 let Inst{24-23} = 0b11; 2410} 2411def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> { 2412 let Inst{24-23} = 0b11; 2413} 2414 2415def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>; 2416def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>; 2417 2418def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>; 2419def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>; 2420 2421def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>; 2422def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>; 2423 2424def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>; 2425def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>; 2426 2427// Return From Exception 2428class RFEI<bit wb, string asm> 2429 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm, 2430 NoItinerary, asm, "", []> { 2431 bits<4> Rn; 2432 let Inst{31-28} = 0b1111; 2433 let Inst{27-25} = 0b100; 2434 let Inst{22} = 0; 2435 let Inst{21} = wb; 2436 let Inst{20} = 1; 2437 let Inst{19-16} = Rn; 2438 let Inst{15-0} = 0xa00; 2439} 2440 2441def RFEDA : RFEI<0, "rfeda\t$Rn"> { 2442 let Inst{24-23} = 0; 2443} 2444def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> { 2445 let Inst{24-23} = 0; 2446} 2447def RFEDB : RFEI<0, "rfedb\t$Rn"> { 2448 let Inst{24-23} = 0b10; 2449} 2450def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> { 2451 let Inst{24-23} = 0b10; 2452} 2453def RFEIA : RFEI<0, "rfeia\t$Rn"> { 2454 let Inst{24-23} = 0b01; 2455} 2456def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> { 2457 let Inst{24-23} = 0b01; 2458} 2459def RFEIB : RFEI<0, "rfeib\t$Rn"> { 2460 let Inst{24-23} = 0b11; 2461} 2462def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> { 2463 let Inst{24-23} = 0b11; 2464} 2465 2466// Hypervisor Call is a system instruction 2467let isCall = 1 in { 2468def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary, 2469 "hvc", "\t$imm", []>, 2470 Requires<[IsARM, HasVirtualization]> { 2471 bits<16> imm; 2472 2473 // Even though HVC isn't predicable, it's encoding includes a condition field. 2474 // The instruction is undefined if the condition field is 0xf otherwise it is 2475 // unpredictable if it isn't condition AL (0xe). 2476 let Inst{31-28} = 0b1110; 2477 let Unpredictable{31-28} = 0b1111; 2478 let Inst{27-24} = 0b0001; 2479 let Inst{23-20} = 0b0100; 2480 let Inst{19-8} = imm{15-4}; 2481 let Inst{7-4} = 0b0111; 2482 let Inst{3-0} = imm{3-0}; 2483} 2484} 2485 2486// Return from exception in Hypervisor mode. 2487let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in 2488def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>, 2489 Requires<[IsARM, HasVirtualization]> { 2490 let Inst{23-0} = 0b011000000000000001101110; 2491} 2492 2493//===----------------------------------------------------------------------===// 2494// Load / Store Instructions. 2495// 2496 2497// Load 2498 2499 2500defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si, load>; 2501defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si, 2502 zextloadi8>; 2503defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si, store>; 2504defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si, 2505 truncstorei8>; 2506 2507// Special LDR for loads from non-pc-relative constpools. 2508let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0, 2509 isReMaterializable = 1, isCodeGenOnly = 1 in 2510def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 2511 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", 2512 []> { 2513 bits<4> Rt; 2514 bits<17> addr; 2515 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2516 let Inst{19-16} = 0b1111; 2517 let Inst{15-12} = Rt; 2518 let Inst{11-0} = addr{11-0}; // imm12 2519} 2520 2521// Loads with zero extension 2522def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2523 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr", 2524 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>; 2525 2526// Loads with sign extension 2527def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2528 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr", 2529 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>; 2530 2531def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2532 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr", 2533 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>; 2534 2535let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in { 2536 // Load doubleword 2537 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr), 2538 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>, 2539 Requires<[IsARM, HasV5TE]>; 2540} 2541 2542def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2543 NoItinerary, "lda", "\t$Rt, $addr", []>; 2544def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2545 NoItinerary, "ldab", "\t$Rt, $addr", []>; 2546def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2547 NoItinerary, "ldah", "\t$Rt, $addr", []>; 2548 2549// Indexed loads 2550multiclass AI2_ldridx<bit isByte, string opc, 2551 InstrItinClass iii, InstrItinClass iir> { 2552 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2553 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii, 2554 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2555 bits<17> addr; 2556 let Inst{25} = 0; 2557 let Inst{23} = addr{12}; 2558 let Inst{19-16} = addr{16-13}; 2559 let Inst{11-0} = addr{11-0}; 2560 let DecoderMethod = "DecodeLDRPreImm"; 2561 } 2562 2563 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2564 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir, 2565 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2566 bits<17> addr; 2567 let Inst{25} = 1; 2568 let Inst{23} = addr{12}; 2569 let Inst{19-16} = addr{16-13}; 2570 let Inst{11-0} = addr{11-0}; 2571 let Inst{4} = 0; 2572 let DecoderMethod = "DecodeLDRPreReg"; 2573 } 2574 2575 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2576 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2577 IndexModePost, LdFrm, iir, 2578 opc, "\t$Rt, $addr, $offset", 2579 "$addr.base = $Rn_wb", []> { 2580 // {12} isAdd 2581 // {11-0} imm12/Rm 2582 bits<14> offset; 2583 bits<4> addr; 2584 let Inst{25} = 1; 2585 let Inst{23} = offset{12}; 2586 let Inst{19-16} = addr; 2587 let Inst{11-0} = offset{11-0}; 2588 let Inst{4} = 0; 2589 2590 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2591 } 2592 2593 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2594 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2595 IndexModePost, LdFrm, iii, 2596 opc, "\t$Rt, $addr, $offset", 2597 "$addr.base = $Rn_wb", []> { 2598 // {12} isAdd 2599 // {11-0} imm12/Rm 2600 bits<14> offset; 2601 bits<4> addr; 2602 let Inst{25} = 0; 2603 let Inst{23} = offset{12}; 2604 let Inst{19-16} = addr; 2605 let Inst{11-0} = offset{11-0}; 2606 2607 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2608 } 2609 2610} 2611 2612let mayLoad = 1, hasSideEffects = 0 in { 2613// FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or 2614// IIC_iLoad_siu depending on whether it the offset register is shifted. 2615defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>; 2616defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>; 2617} 2618 2619multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> { 2620 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2621 (ins addrmode3_pre:$addr), IndexModePre, 2622 LdMiscFrm, itin, 2623 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2624 bits<14> addr; 2625 let Inst{23} = addr{8}; // U bit 2626 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2627 let Inst{19-16} = addr{12-9}; // Rn 2628 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2629 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2630 let DecoderMethod = "DecodeAddrMode3Instruction"; 2631 } 2632 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2633 (ins addr_offset_none:$addr, am3offset:$offset), 2634 IndexModePost, LdMiscFrm, itin, 2635 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2636 []> { 2637 bits<10> offset; 2638 bits<4> addr; 2639 let Inst{23} = offset{8}; // U bit 2640 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2641 let Inst{19-16} = addr; 2642 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2643 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2644 let DecoderMethod = "DecodeAddrMode3Instruction"; 2645 } 2646} 2647 2648let mayLoad = 1, hasSideEffects = 0 in { 2649defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>; 2650defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>; 2651defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>; 2652let hasExtraDefRegAllocReq = 1 in { 2653def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2654 (ins addrmode3_pre:$addr), IndexModePre, 2655 LdMiscFrm, IIC_iLoad_d_ru, 2656 "ldrd", "\t$Rt, $Rt2, $addr!", 2657 "$addr.base = $Rn_wb", []> { 2658 bits<14> addr; 2659 let Inst{23} = addr{8}; // U bit 2660 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2661 let Inst{19-16} = addr{12-9}; // Rn 2662 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2663 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2664 let DecoderMethod = "DecodeAddrMode3Instruction"; 2665} 2666def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2667 (ins addr_offset_none:$addr, am3offset:$offset), 2668 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru, 2669 "ldrd", "\t$Rt, $Rt2, $addr, $offset", 2670 "$addr.base = $Rn_wb", []> { 2671 bits<10> offset; 2672 bits<4> addr; 2673 let Inst{23} = offset{8}; // U bit 2674 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2675 let Inst{19-16} = addr; 2676 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2677 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2678 let DecoderMethod = "DecodeAddrMode3Instruction"; 2679} 2680} // hasExtraDefRegAllocReq = 1 2681} // mayLoad = 1, hasSideEffects = 0 2682 2683// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT. 2684let mayLoad = 1, hasSideEffects = 0 in { 2685def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2686 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2687 IndexModePost, LdFrm, IIC_iLoad_ru, 2688 "ldrt", "\t$Rt, $addr, $offset", 2689 "$addr.base = $Rn_wb", []> { 2690 // {12} isAdd 2691 // {11-0} imm12/Rm 2692 bits<14> offset; 2693 bits<4> addr; 2694 let Inst{25} = 1; 2695 let Inst{23} = offset{12}; 2696 let Inst{21} = 1; // overwrite 2697 let Inst{19-16} = addr; 2698 let Inst{11-5} = offset{11-5}; 2699 let Inst{4} = 0; 2700 let Inst{3-0} = offset{3-0}; 2701 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2702} 2703 2704def LDRT_POST_IMM 2705 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2706 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2707 IndexModePost, LdFrm, IIC_iLoad_ru, 2708 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2709 // {12} isAdd 2710 // {11-0} imm12/Rm 2711 bits<14> offset; 2712 bits<4> addr; 2713 let Inst{25} = 0; 2714 let Inst{23} = offset{12}; 2715 let Inst{21} = 1; // overwrite 2716 let Inst{19-16} = addr; 2717 let Inst{11-0} = offset{11-0}; 2718 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2719} 2720 2721def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2722 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2723 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2724 "ldrbt", "\t$Rt, $addr, $offset", 2725 "$addr.base = $Rn_wb", []> { 2726 // {12} isAdd 2727 // {11-0} imm12/Rm 2728 bits<14> offset; 2729 bits<4> addr; 2730 let Inst{25} = 1; 2731 let Inst{23} = offset{12}; 2732 let Inst{21} = 1; // overwrite 2733 let Inst{19-16} = addr; 2734 let Inst{11-5} = offset{11-5}; 2735 let Inst{4} = 0; 2736 let Inst{3-0} = offset{3-0}; 2737 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2738} 2739 2740def LDRBT_POST_IMM 2741 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2742 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2743 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2744 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2745 // {12} isAdd 2746 // {11-0} imm12/Rm 2747 bits<14> offset; 2748 bits<4> addr; 2749 let Inst{25} = 0; 2750 let Inst{23} = offset{12}; 2751 let Inst{21} = 1; // overwrite 2752 let Inst{19-16} = addr; 2753 let Inst{11-0} = offset{11-0}; 2754 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2755} 2756 2757multiclass AI3ldrT<bits<4> op, string opc> { 2758 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb), 2759 (ins addr_offset_none:$addr, postidx_imm8:$offset), 2760 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2761 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 2762 bits<9> offset; 2763 let Inst{23} = offset{8}; 2764 let Inst{22} = 1; 2765 let Inst{11-8} = offset{7-4}; 2766 let Inst{3-0} = offset{3-0}; 2767 } 2768 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb), 2769 (ins addr_offset_none:$addr, postidx_reg:$Rm), 2770 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2771 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 2772 bits<5> Rm; 2773 let Inst{23} = Rm{4}; 2774 let Inst{22} = 0; 2775 let Inst{11-8} = 0; 2776 let Unpredictable{11-8} = 0b1111; 2777 let Inst{3-0} = Rm{3-0}; 2778 let DecoderMethod = "DecodeLDR"; 2779 } 2780} 2781 2782defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">; 2783defm LDRHT : AI3ldrT<0b1011, "ldrht">; 2784defm LDRSHT : AI3ldrT<0b1111, "ldrsht">; 2785} 2786 2787def LDRT_POST 2788 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2789 (outs GPR:$Rt)>; 2790 2791def LDRBT_POST 2792 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2793 (outs GPR:$Rt)>; 2794 2795// Store 2796 2797// Stores with truncate 2798def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, 2799 IIC_iStore_bh_r, "strh", "\t$Rt, $addr", 2800 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>; 2801 2802// Store doubleword 2803let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 2804 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr), 2805 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>, 2806 Requires<[IsARM, HasV5TE]> { 2807 let Inst{21} = 0; 2808 } 2809} 2810 2811// Indexed stores 2812multiclass AI2_stridx<bit isByte, string opc, 2813 InstrItinClass iii, InstrItinClass iir> { 2814 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2815 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre, 2816 StFrm, iii, 2817 opc, "\t$Rt, $addr!", 2818 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2819 bits<17> addr; 2820 let Inst{25} = 0; 2821 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2822 let Inst{19-16} = addr{16-13}; // Rn 2823 let Inst{11-0} = addr{11-0}; // imm12 2824 let DecoderMethod = "DecodeSTRPreImm"; 2825 } 2826 2827 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2828 (ins GPR:$Rt, ldst_so_reg:$addr), 2829 IndexModePre, StFrm, iir, 2830 opc, "\t$Rt, $addr!", 2831 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2832 bits<17> addr; 2833 let Inst{25} = 1; 2834 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2835 let Inst{19-16} = addr{16-13}; // Rn 2836 let Inst{11-0} = addr{11-0}; 2837 let Inst{4} = 0; // Inst{4} = 0 2838 let DecoderMethod = "DecodeSTRPreReg"; 2839 } 2840 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2841 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2842 IndexModePost, StFrm, iir, 2843 opc, "\t$Rt, $addr, $offset", 2844 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2845 // {12} isAdd 2846 // {11-0} imm12/Rm 2847 bits<14> offset; 2848 bits<4> addr; 2849 let Inst{25} = 1; 2850 let Inst{23} = offset{12}; 2851 let Inst{19-16} = addr; 2852 let Inst{11-0} = offset{11-0}; 2853 let Inst{4} = 0; 2854 2855 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2856 } 2857 2858 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2859 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2860 IndexModePost, StFrm, iii, 2861 opc, "\t$Rt, $addr, $offset", 2862 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2863 // {12} isAdd 2864 // {11-0} imm12/Rm 2865 bits<14> offset; 2866 bits<4> addr; 2867 let Inst{25} = 0; 2868 let Inst{23} = offset{12}; 2869 let Inst{19-16} = addr; 2870 let Inst{11-0} = offset{11-0}; 2871 2872 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2873 } 2874} 2875 2876let mayStore = 1, hasSideEffects = 0 in { 2877// FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or 2878// IIC_iStore_siu depending on whether it the offset register is shifted. 2879defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>; 2880defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>; 2881} 2882 2883def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 2884 am2offset_reg:$offset), 2885 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr, 2886 am2offset_reg:$offset)>; 2887def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 2888 am2offset_imm:$offset), 2889 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr, 2890 am2offset_imm:$offset)>; 2891def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 2892 am2offset_reg:$offset), 2893 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr, 2894 am2offset_reg:$offset)>; 2895def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 2896 am2offset_imm:$offset), 2897 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr, 2898 am2offset_imm:$offset)>; 2899 2900// Pseudo-instructions for pattern matching the pre-indexed stores. We can't 2901// put the patterns on the instruction definitions directly as ISel wants 2902// the address base and offset to be separate operands, not a single 2903// complex operand like we represent the instructions themselves. The 2904// pseudos map between the two. 2905let usesCustomInserter = 1, 2906 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 2907def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2908 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 2909 4, IIC_iStore_ru, 2910 [(set GPR:$Rn_wb, 2911 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 2912def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2913 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 2914 4, IIC_iStore_ru, 2915 [(set GPR:$Rn_wb, 2916 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 2917def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2918 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 2919 4, IIC_iStore_ru, 2920 [(set GPR:$Rn_wb, 2921 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 2922def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2923 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 2924 4, IIC_iStore_ru, 2925 [(set GPR:$Rn_wb, 2926 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 2927def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2928 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p), 2929 4, IIC_iStore_ru, 2930 [(set GPR:$Rn_wb, 2931 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>; 2932} 2933 2934 2935 2936def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb), 2937 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre, 2938 StMiscFrm, IIC_iStore_bh_ru, 2939 "strh", "\t$Rt, $addr!", 2940 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2941 bits<14> addr; 2942 let Inst{23} = addr{8}; // U bit 2943 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2944 let Inst{19-16} = addr{12-9}; // Rn 2945 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2946 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2947 let DecoderMethod = "DecodeAddrMode3Instruction"; 2948} 2949 2950def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb), 2951 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset), 2952 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, 2953 "strh", "\t$Rt, $addr, $offset", 2954 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", 2955 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt, 2956 addr_offset_none:$addr, 2957 am3offset:$offset))]> { 2958 bits<10> offset; 2959 bits<4> addr; 2960 let Inst{23} = offset{8}; // U bit 2961 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2962 let Inst{19-16} = addr; 2963 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2964 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2965 let DecoderMethod = "DecodeAddrMode3Instruction"; 2966} 2967 2968let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 2969def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb), 2970 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr), 2971 IndexModePre, StMiscFrm, IIC_iStore_d_ru, 2972 "strd", "\t$Rt, $Rt2, $addr!", 2973 "$addr.base = $Rn_wb", []> { 2974 bits<14> addr; 2975 let Inst{23} = addr{8}; // U bit 2976 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2977 let Inst{19-16} = addr{12-9}; // Rn 2978 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2979 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2980 let DecoderMethod = "DecodeAddrMode3Instruction"; 2981} 2982 2983def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb), 2984 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr, 2985 am3offset:$offset), 2986 IndexModePost, StMiscFrm, IIC_iStore_d_ru, 2987 "strd", "\t$Rt, $Rt2, $addr, $offset", 2988 "$addr.base = $Rn_wb", []> { 2989 bits<10> offset; 2990 bits<4> addr; 2991 let Inst{23} = offset{8}; // U bit 2992 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2993 let Inst{19-16} = addr; 2994 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2995 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2996 let DecoderMethod = "DecodeAddrMode3Instruction"; 2997} 2998} // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 2999 3000// STRT, STRBT, and STRHT 3001 3002def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3003 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3004 IndexModePost, StFrm, IIC_iStore_bh_ru, 3005 "strbt", "\t$Rt, $addr, $offset", 3006 "$addr.base = $Rn_wb", []> { 3007 // {12} isAdd 3008 // {11-0} imm12/Rm 3009 bits<14> offset; 3010 bits<4> addr; 3011 let Inst{25} = 1; 3012 let Inst{23} = offset{12}; 3013 let Inst{21} = 1; // overwrite 3014 let Inst{19-16} = addr; 3015 let Inst{11-5} = offset{11-5}; 3016 let Inst{4} = 0; 3017 let Inst{3-0} = offset{3-0}; 3018 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3019} 3020 3021def STRBT_POST_IMM 3022 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3023 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3024 IndexModePost, StFrm, IIC_iStore_bh_ru, 3025 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3026 // {12} isAdd 3027 // {11-0} imm12/Rm 3028 bits<14> offset; 3029 bits<4> addr; 3030 let Inst{25} = 0; 3031 let Inst{23} = offset{12}; 3032 let Inst{21} = 1; // overwrite 3033 let Inst{19-16} = addr; 3034 let Inst{11-0} = offset{11-0}; 3035 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3036} 3037 3038def STRBT_POST 3039 : ARMAsmPseudo<"strbt${q} $Rt, $addr", 3040 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3041 3042let mayStore = 1, hasSideEffects = 0 in { 3043def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3044 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3045 IndexModePost, StFrm, IIC_iStore_ru, 3046 "strt", "\t$Rt, $addr, $offset", 3047 "$addr.base = $Rn_wb", []> { 3048 // {12} isAdd 3049 // {11-0} imm12/Rm 3050 bits<14> offset; 3051 bits<4> addr; 3052 let Inst{25} = 1; 3053 let Inst{23} = offset{12}; 3054 let Inst{21} = 1; // overwrite 3055 let Inst{19-16} = addr; 3056 let Inst{11-5} = offset{11-5}; 3057 let Inst{4} = 0; 3058 let Inst{3-0} = offset{3-0}; 3059 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3060} 3061 3062def STRT_POST_IMM 3063 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3064 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3065 IndexModePost, StFrm, IIC_iStore_ru, 3066 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3067 // {12} isAdd 3068 // {11-0} imm12/Rm 3069 bits<14> offset; 3070 bits<4> addr; 3071 let Inst{25} = 0; 3072 let Inst{23} = offset{12}; 3073 let Inst{21} = 1; // overwrite 3074 let Inst{19-16} = addr; 3075 let Inst{11-0} = offset{11-0}; 3076 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3077} 3078} 3079 3080def STRT_POST 3081 : ARMAsmPseudo<"strt${q} $Rt, $addr", 3082 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3083 3084multiclass AI3strT<bits<4> op, string opc> { 3085 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3086 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset), 3087 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3088 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 3089 bits<9> offset; 3090 let Inst{23} = offset{8}; 3091 let Inst{22} = 1; 3092 let Inst{11-8} = offset{7-4}; 3093 let Inst{3-0} = offset{3-0}; 3094 } 3095 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3096 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm), 3097 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3098 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 3099 bits<5> Rm; 3100 let Inst{23} = Rm{4}; 3101 let Inst{22} = 0; 3102 let Inst{11-8} = 0; 3103 let Inst{3-0} = Rm{3-0}; 3104 } 3105} 3106 3107 3108defm STRHT : AI3strT<0b1011, "strht">; 3109 3110def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3111 NoItinerary, "stl", "\t$Rt, $addr", []>; 3112def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3113 NoItinerary, "stlb", "\t$Rt, $addr", []>; 3114def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3115 NoItinerary, "stlh", "\t$Rt, $addr", []>; 3116 3117//===----------------------------------------------------------------------===// 3118// Load / store multiple Instructions. 3119// 3120 3121multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f, 3122 InstrItinClass itin, InstrItinClass itin_upd> { 3123 // IA is the default, so no need for an explicit suffix on the 3124 // mnemonic here. Without it is the canonical spelling. 3125 def IA : 3126 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3127 IndexModeNone, f, itin, 3128 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> { 3129 let Inst{24-23} = 0b01; // Increment After 3130 let Inst{22} = P_bit; 3131 let Inst{21} = 0; // No writeback 3132 let Inst{20} = L_bit; 3133 } 3134 def IA_UPD : 3135 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3136 IndexModeUpd, f, itin_upd, 3137 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3138 let Inst{24-23} = 0b01; // Increment After 3139 let Inst{22} = P_bit; 3140 let Inst{21} = 1; // Writeback 3141 let Inst{20} = L_bit; 3142 3143 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3144 } 3145 def DA : 3146 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3147 IndexModeNone, f, itin, 3148 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> { 3149 let Inst{24-23} = 0b00; // Decrement After 3150 let Inst{22} = P_bit; 3151 let Inst{21} = 0; // No writeback 3152 let Inst{20} = L_bit; 3153 } 3154 def DA_UPD : 3155 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3156 IndexModeUpd, f, itin_upd, 3157 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3158 let Inst{24-23} = 0b00; // Decrement After 3159 let Inst{22} = P_bit; 3160 let Inst{21} = 1; // Writeback 3161 let Inst{20} = L_bit; 3162 3163 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3164 } 3165 def DB : 3166 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3167 IndexModeNone, f, itin, 3168 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> { 3169 let Inst{24-23} = 0b10; // Decrement Before 3170 let Inst{22} = P_bit; 3171 let Inst{21} = 0; // No writeback 3172 let Inst{20} = L_bit; 3173 } 3174 def DB_UPD : 3175 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3176 IndexModeUpd, f, itin_upd, 3177 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3178 let Inst{24-23} = 0b10; // Decrement Before 3179 let Inst{22} = P_bit; 3180 let Inst{21} = 1; // Writeback 3181 let Inst{20} = L_bit; 3182 3183 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3184 } 3185 def IB : 3186 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3187 IndexModeNone, f, itin, 3188 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> { 3189 let Inst{24-23} = 0b11; // Increment Before 3190 let Inst{22} = P_bit; 3191 let Inst{21} = 0; // No writeback 3192 let Inst{20} = L_bit; 3193 } 3194 def IB_UPD : 3195 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3196 IndexModeUpd, f, itin_upd, 3197 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3198 let Inst{24-23} = 0b11; // Increment Before 3199 let Inst{22} = P_bit; 3200 let Inst{21} = 1; // Writeback 3201 let Inst{20} = L_bit; 3202 3203 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3204 } 3205} 3206 3207let hasSideEffects = 0 in { 3208 3209let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 3210defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m, 3211 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">; 3212 3213let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3214defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m, 3215 IIC_iStore_mu>, 3216 ComplexDeprecationPredicate<"ARMStore">; 3217 3218} // hasSideEffects 3219 3220// FIXME: remove when we have a way to marking a MI with these properties. 3221// FIXME: Should pc be an implicit operand like PICADD, etc? 3222let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 3223 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 3224def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 3225 reglist:$regs, variable_ops), 3226 4, IIC_iLoad_mBr, [], 3227 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 3228 RegConstraint<"$Rn = $wb">; 3229 3230let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 3231defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m, 3232 IIC_iLoad_mu>; 3233 3234let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3235defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m, 3236 IIC_iStore_mu>; 3237 3238 3239 3240//===----------------------------------------------------------------------===// 3241// Move Instructions. 3242// 3243 3244let hasSideEffects = 0 in 3245def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr, 3246 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3247 bits<4> Rd; 3248 bits<4> Rm; 3249 3250 let Inst{19-16} = 0b0000; 3251 let Inst{11-4} = 0b00000000; 3252 let Inst{25} = 0; 3253 let Inst{3-0} = Rm; 3254 let Inst{15-12} = Rd; 3255} 3256 3257// A version for the smaller set of tail call registers. 3258let hasSideEffects = 0 in 3259def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, 3260 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3261 bits<4> Rd; 3262 bits<4> Rm; 3263 3264 let Inst{11-4} = 0b00000000; 3265 let Inst{25} = 0; 3266 let Inst{3-0} = Rm; 3267 let Inst{15-12} = Rd; 3268} 3269 3270def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src), 3271 DPSoRegRegFrm, IIC_iMOVsr, 3272 "mov", "\t$Rd, $src", 3273 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP, 3274 Sched<[WriteALU]> { 3275 bits<4> Rd; 3276 bits<12> src; 3277 let Inst{15-12} = Rd; 3278 let Inst{19-16} = 0b0000; 3279 let Inst{11-8} = src{11-8}; 3280 let Inst{7} = 0; 3281 let Inst{6-5} = src{6-5}; 3282 let Inst{4} = 1; 3283 let Inst{3-0} = src{3-0}; 3284 let Inst{25} = 0; 3285} 3286 3287def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src), 3288 DPSoRegImmFrm, IIC_iMOVsr, 3289 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>, 3290 UnaryDP, Sched<[WriteALU]> { 3291 bits<4> Rd; 3292 bits<12> src; 3293 let Inst{15-12} = Rd; 3294 let Inst{19-16} = 0b0000; 3295 let Inst{11-5} = src{11-5}; 3296 let Inst{4} = 0; 3297 let Inst{3-0} = src{3-0}; 3298 let Inst{25} = 0; 3299} 3300 3301let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3302def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi, 3303 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP, 3304 Sched<[WriteALU]> { 3305 bits<4> Rd; 3306 bits<12> imm; 3307 let Inst{25} = 1; 3308 let Inst{15-12} = Rd; 3309 let Inst{19-16} = 0b0000; 3310 let Inst{11-0} = imm; 3311} 3312 3313let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3314def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm), 3315 DPFrm, IIC_iMOVi, 3316 "movw", "\t$Rd, $imm", 3317 [(set GPR:$Rd, imm0_65535:$imm)]>, 3318 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> { 3319 bits<4> Rd; 3320 bits<16> imm; 3321 let Inst{15-12} = Rd; 3322 let Inst{11-0} = imm{11-0}; 3323 let Inst{19-16} = imm{15-12}; 3324 let Inst{20} = 0; 3325 let Inst{25} = 1; 3326 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3327} 3328 3329def : InstAlias<"mov${p} $Rd, $imm", 3330 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>, 3331 Requires<[IsARM]>; 3332 3333def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3334 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3335 Sched<[WriteALU]>; 3336 3337let Constraints = "$src = $Rd" in { 3338def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd), 3339 (ins GPR:$src, imm0_65535_expr:$imm), 3340 DPFrm, IIC_iMOVi, 3341 "movt", "\t$Rd, $imm", 3342 [(set GPRnopc:$Rd, 3343 (or (and GPR:$src, 0xffff), 3344 lo16AllZero:$imm))]>, UnaryDP, 3345 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> { 3346 bits<4> Rd; 3347 bits<16> imm; 3348 let Inst{15-12} = Rd; 3349 let Inst{11-0} = imm{11-0}; 3350 let Inst{19-16} = imm{15-12}; 3351 let Inst{20} = 0; 3352 let Inst{25} = 1; 3353 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3354} 3355 3356def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3357 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3358 Sched<[WriteALU]>; 3359 3360} // Constraints 3361 3362def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>, 3363 Requires<[IsARM, HasV6T2]>; 3364 3365let Uses = [CPSR] in 3366def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, 3367 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP, 3368 Requires<[IsARM]>, Sched<[WriteALU]>; 3369 3370// These aren't really mov instructions, but we have to define them this way 3371// due to flag operands. 3372 3373let Defs = [CPSR] in { 3374def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3375 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP, 3376 Sched<[WriteALU]>, Requires<[IsARM]>; 3377def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3378 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP, 3379 Sched<[WriteALU]>, Requires<[IsARM]>; 3380} 3381 3382//===----------------------------------------------------------------------===// 3383// Extend Instructions. 3384// 3385 3386// Sign extenders 3387 3388def SXTB : AI_ext_rrot<0b01101010, 3389 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 3390def SXTH : AI_ext_rrot<0b01101011, 3391 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 3392 3393def SXTAB : AI_exta_rrot<0b01101010, 3394 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 3395def SXTAH : AI_exta_rrot<0b01101011, 3396 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 3397 3398def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; 3399 3400def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; 3401 3402// Zero extenders 3403 3404let AddedComplexity = 16 in { 3405def UXTB : AI_ext_rrot<0b01101110, 3406 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 3407def UXTH : AI_ext_rrot<0b01101111, 3408 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 3409def UXTB16 : AI_ext_rrot<0b01101100, 3410 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 3411 3412// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 3413// The transformation should probably be done as a combiner action 3414// instead so we can include a check for masking back in the upper 3415// eight bits of the source into the lower eight bits of the result. 3416//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 3417// (UXTB16r_rot GPR:$Src, 3)>; 3418def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 3419 (UXTB16 GPR:$Src, 1)>; 3420 3421def UXTAB : AI_exta_rrot<0b01101110, "uxtab", 3422 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 3423def UXTAH : AI_exta_rrot<0b01101111, "uxtah", 3424 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 3425} 3426 3427// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 3428def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; 3429 3430 3431def SBFX : I<(outs GPRnopc:$Rd), 3432 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3433 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3434 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3435 Requires<[IsARM, HasV6T2]> { 3436 bits<4> Rd; 3437 bits<4> Rn; 3438 bits<5> lsb; 3439 bits<5> width; 3440 let Inst{27-21} = 0b0111101; 3441 let Inst{6-4} = 0b101; 3442 let Inst{20-16} = width; 3443 let Inst{15-12} = Rd; 3444 let Inst{11-7} = lsb; 3445 let Inst{3-0} = Rn; 3446} 3447 3448def UBFX : I<(outs GPRnopc:$Rd), 3449 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3450 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3451 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3452 Requires<[IsARM, HasV6T2]> { 3453 bits<4> Rd; 3454 bits<4> Rn; 3455 bits<5> lsb; 3456 bits<5> width; 3457 let Inst{27-21} = 0b0111111; 3458 let Inst{6-4} = 0b101; 3459 let Inst{20-16} = width; 3460 let Inst{15-12} = Rd; 3461 let Inst{11-7} = lsb; 3462 let Inst{3-0} = Rn; 3463} 3464 3465//===----------------------------------------------------------------------===// 3466// Arithmetic Instructions. 3467// 3468 3469defm ADD : AsI1_bin_irs<0b0100, "add", 3470 IIC_iALUi, IIC_iALUr, IIC_iALUsr, add, 1>; 3471defm SUB : AsI1_bin_irs<0b0010, "sub", 3472 IIC_iALUi, IIC_iALUr, IIC_iALUsr, sub>; 3473 3474// ADD and SUB with 's' bit set. 3475// 3476// Currently, ADDS/SUBS are pseudo opcodes that exist only in the 3477// selection DAG. They are "lowered" to real ADD/SUB opcodes by 3478// AdjustInstrPostInstrSelection where we determine whether or not to 3479// set the "s" bit based on CPSR liveness. 3480// 3481// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen 3482// support for an optional CPSR definition that corresponds to the DAG 3483// node's second value. We can then eliminate the implicit def of CPSR. 3484defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMaddc, 1>; 3485defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>; 3486 3487defm ADC : AI1_adde_sube_irs<0b0101, "adc", ARMadde, 1>; 3488defm SBC : AI1_adde_sube_irs<0b0110, "sbc", ARMsube>; 3489 3490defm RSB : AsI1_rbin_irs<0b0011, "rsb", 3491 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3492 sub>; 3493 3494// FIXME: Eliminate them if we can write def : Pat patterns which defines 3495// CPSR and the implicit def of CPSR is not needed. 3496defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>; 3497 3498defm RSC : AI1_rsc_irs<0b0111, "rsc", ARMsube>; 3499 3500// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 3501// The assume-no-carry-in form uses the negation of the input since add/sub 3502// assume opposite meanings of the carry flag (i.e., carry == !borrow). 3503// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 3504// details. 3505def : ARMPat<(add GPR:$src, mod_imm_neg:$imm), 3506 (SUBri GPR:$src, mod_imm_neg:$imm)>; 3507def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm), 3508 (SUBSri GPR:$src, mod_imm_neg:$imm)>; 3509 3510def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm), 3511 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3512 Requires<[IsARM, HasV6T2]>; 3513def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm), 3514 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3515 Requires<[IsARM, HasV6T2]>; 3516 3517// The with-carry-in form matches bitwise not instead of the negation. 3518// Effectively, the inverse interpretation of the carry flag already accounts 3519// for part of the negation. 3520def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR), 3521 (SBCri GPR:$src, mod_imm_not:$imm)>; 3522def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR), 3523 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>, 3524 Requires<[IsARM, HasV6T2]>; 3525 3526// Note: These are implemented in C++ code, because they have to generate 3527// ADD/SUBrs instructions, which use a complex pattern that a xform function 3528// cannot produce. 3529// (mul X, 2^n+1) -> (add (X << n), X) 3530// (mul X, 2^n-1) -> (rsb X, (X << n)) 3531 3532// ARM Arithmetic Instruction 3533// GPR:$dst = GPR:$a op GPR:$b 3534class AAI<bits<8> op27_20, bits<8> op11_4, string opc, 3535 list<dag> pattern = [], 3536 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm), 3537 string asm = "\t$Rd, $Rn, $Rm"> 3538 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>, 3539 Sched<[WriteALU, ReadALU, ReadALU]> { 3540 bits<4> Rn; 3541 bits<4> Rd; 3542 bits<4> Rm; 3543 let Inst{27-20} = op27_20; 3544 let Inst{11-4} = op11_4; 3545 let Inst{19-16} = Rn; 3546 let Inst{15-12} = Rd; 3547 let Inst{3-0} = Rm; 3548 3549 let Unpredictable{11-8} = 0b1111; 3550} 3551 3552// Saturating add/subtract 3553 3554let DecoderMethod = "DecodeQADDInstruction" in 3555def QADD : AAI<0b00010000, 0b00000101, "qadd", 3556 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))], 3557 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">; 3558 3559def QSUB : AAI<0b00010010, 0b00000101, "qsub", 3560 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))], 3561 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">; 3562def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], 3563 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3564 "\t$Rd, $Rm, $Rn">; 3565def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], 3566 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3567 "\t$Rd, $Rm, $Rn">; 3568 3569def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">; 3570def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">; 3571def QASX : AAI<0b01100010, 0b11110011, "qasx">; 3572def QSAX : AAI<0b01100010, 0b11110101, "qsax">; 3573def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">; 3574def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">; 3575def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">; 3576def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">; 3577def UQASX : AAI<0b01100110, 0b11110011, "uqasx">; 3578def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">; 3579def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">; 3580def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">; 3581 3582// Signed/Unsigned add/subtract 3583 3584def SASX : AAI<0b01100001, 0b11110011, "sasx">; 3585def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">; 3586def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">; 3587def SSAX : AAI<0b01100001, 0b11110101, "ssax">; 3588def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">; 3589def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">; 3590def UASX : AAI<0b01100101, 0b11110011, "uasx">; 3591def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">; 3592def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">; 3593def USAX : AAI<0b01100101, 0b11110101, "usax">; 3594def USUB16 : AAI<0b01100101, 0b11110111, "usub16">; 3595def USUB8 : AAI<0b01100101, 0b11111111, "usub8">; 3596 3597// Signed/Unsigned halving add/subtract 3598 3599def SHASX : AAI<0b01100011, 0b11110011, "shasx">; 3600def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">; 3601def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">; 3602def SHSAX : AAI<0b01100011, 0b11110101, "shsax">; 3603def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">; 3604def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">; 3605def UHASX : AAI<0b01100111, 0b11110011, "uhasx">; 3606def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">; 3607def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">; 3608def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">; 3609def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">; 3610def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">; 3611 3612// Unsigned Sum of Absolute Differences [and Accumulate]. 3613 3614def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3615 MulFrm /* for convenience */, NoItinerary, "usad8", 3616 "\t$Rd, $Rn, $Rm", []>, 3617 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> { 3618 bits<4> Rd; 3619 bits<4> Rn; 3620 bits<4> Rm; 3621 let Inst{27-20} = 0b01111000; 3622 let Inst{15-12} = 0b1111; 3623 let Inst{7-4} = 0b0001; 3624 let Inst{19-16} = Rd; 3625 let Inst{11-8} = Rm; 3626 let Inst{3-0} = Rn; 3627} 3628def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3629 MulFrm /* for convenience */, NoItinerary, "usada8", 3630 "\t$Rd, $Rn, $Rm, $Ra", []>, 3631 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{ 3632 bits<4> Rd; 3633 bits<4> Rn; 3634 bits<4> Rm; 3635 bits<4> Ra; 3636 let Inst{27-20} = 0b01111000; 3637 let Inst{7-4} = 0b0001; 3638 let Inst{19-16} = Rd; 3639 let Inst{15-12} = Ra; 3640 let Inst{11-8} = Rm; 3641 let Inst{3-0} = Rn; 3642} 3643 3644// Signed/Unsigned saturate 3645 3646def SSAT : AI<(outs GPRnopc:$Rd), 3647 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3648 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> { 3649 bits<4> Rd; 3650 bits<5> sat_imm; 3651 bits<4> Rn; 3652 bits<8> sh; 3653 let Inst{27-21} = 0b0110101; 3654 let Inst{5-4} = 0b01; 3655 let Inst{20-16} = sat_imm; 3656 let Inst{15-12} = Rd; 3657 let Inst{11-7} = sh{4-0}; 3658 let Inst{6} = sh{5}; 3659 let Inst{3-0} = Rn; 3660} 3661 3662def SSAT16 : AI<(outs GPRnopc:$Rd), 3663 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm, 3664 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> { 3665 bits<4> Rd; 3666 bits<4> sat_imm; 3667 bits<4> Rn; 3668 let Inst{27-20} = 0b01101010; 3669 let Inst{11-4} = 0b11110011; 3670 let Inst{15-12} = Rd; 3671 let Inst{19-16} = sat_imm; 3672 let Inst{3-0} = Rn; 3673} 3674 3675def USAT : AI<(outs GPRnopc:$Rd), 3676 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3677 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> { 3678 bits<4> Rd; 3679 bits<5> sat_imm; 3680 bits<4> Rn; 3681 bits<8> sh; 3682 let Inst{27-21} = 0b0110111; 3683 let Inst{5-4} = 0b01; 3684 let Inst{15-12} = Rd; 3685 let Inst{11-7} = sh{4-0}; 3686 let Inst{6} = sh{5}; 3687 let Inst{20-16} = sat_imm; 3688 let Inst{3-0} = Rn; 3689} 3690 3691def USAT16 : AI<(outs GPRnopc:$Rd), 3692 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm, 3693 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> { 3694 bits<4> Rd; 3695 bits<4> sat_imm; 3696 bits<4> Rn; 3697 let Inst{27-20} = 0b01101110; 3698 let Inst{11-4} = 0b11110011; 3699 let Inst{15-12} = Rd; 3700 let Inst{19-16} = sat_imm; 3701 let Inst{3-0} = Rn; 3702} 3703 3704def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos), 3705 (SSAT imm1_32:$pos, GPRnopc:$a, 0)>; 3706def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos), 3707 (USAT imm0_31:$pos, GPRnopc:$a, 0)>; 3708 3709//===----------------------------------------------------------------------===// 3710// Bitwise Instructions. 3711// 3712 3713defm AND : AsI1_bin_irs<0b0000, "and", 3714 IIC_iBITi, IIC_iBITr, IIC_iBITsr, and, 1>; 3715defm ORR : AsI1_bin_irs<0b1100, "orr", 3716 IIC_iBITi, IIC_iBITr, IIC_iBITsr, or, 1>; 3717defm EOR : AsI1_bin_irs<0b0001, "eor", 3718 IIC_iBITi, IIC_iBITr, IIC_iBITsr, xor, 1>; 3719defm BIC : AsI1_bin_irs<0b1110, "bic", 3720 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3721 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 3722 3723// FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just 3724// like in the actual instruction encoding. The complexity of mapping the mask 3725// to the lsb/msb pair should be handled by ISel, not encapsulated in the 3726// instruction description. 3727def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), 3728 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3729 "bfc", "\t$Rd, $imm", "$src = $Rd", 3730 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>, 3731 Requires<[IsARM, HasV6T2]> { 3732 bits<4> Rd; 3733 bits<10> imm; 3734 let Inst{27-21} = 0b0111110; 3735 let Inst{6-0} = 0b0011111; 3736 let Inst{15-12} = Rd; 3737 let Inst{11-7} = imm{4-0}; // lsb 3738 let Inst{20-16} = imm{9-5}; // msb 3739} 3740 3741// A8.6.18 BFI - Bitfield insert (Encoding A1) 3742def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm), 3743 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3744 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd", 3745 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn, 3746 bf_inv_mask_imm:$imm))]>, 3747 Requires<[IsARM, HasV6T2]> { 3748 bits<4> Rd; 3749 bits<4> Rn; 3750 bits<10> imm; 3751 let Inst{27-21} = 0b0111110; 3752 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 3753 let Inst{15-12} = Rd; 3754 let Inst{11-7} = imm{4-0}; // lsb 3755 let Inst{20-16} = imm{9-5}; // width 3756 let Inst{3-0} = Rn; 3757} 3758 3759def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr, 3760 "mvn", "\t$Rd, $Rm", 3761 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> { 3762 bits<4> Rd; 3763 bits<4> Rm; 3764 let Inst{25} = 0; 3765 let Inst{19-16} = 0b0000; 3766 let Inst{11-4} = 0b00000000; 3767 let Inst{15-12} = Rd; 3768 let Inst{3-0} = Rm; 3769} 3770def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift), 3771 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3772 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP, 3773 Sched<[WriteALU]> { 3774 bits<4> Rd; 3775 bits<12> shift; 3776 let Inst{25} = 0; 3777 let Inst{19-16} = 0b0000; 3778 let Inst{15-12} = Rd; 3779 let Inst{11-5} = shift{11-5}; 3780 let Inst{4} = 0; 3781 let Inst{3-0} = shift{3-0}; 3782} 3783def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift), 3784 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3785 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP, 3786 Sched<[WriteALU]> { 3787 bits<4> Rd; 3788 bits<12> shift; 3789 let Inst{25} = 0; 3790 let Inst{19-16} = 0b0000; 3791 let Inst{15-12} = Rd; 3792 let Inst{11-8} = shift{11-8}; 3793 let Inst{7} = 0; 3794 let Inst{6-5} = shift{6-5}; 3795 let Inst{4} = 1; 3796 let Inst{3-0} = shift{3-0}; 3797} 3798let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3799def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, 3800 IIC_iMVNi, "mvn", "\t$Rd, $imm", 3801 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> { 3802 bits<4> Rd; 3803 bits<12> imm; 3804 let Inst{25} = 1; 3805 let Inst{19-16} = 0b0000; 3806 let Inst{15-12} = Rd; 3807 let Inst{11-0} = imm; 3808} 3809 3810def : ARMPat<(and GPR:$src, mod_imm_not:$imm), 3811 (BICri GPR:$src, mod_imm_not:$imm)>; 3812 3813//===----------------------------------------------------------------------===// 3814// Multiply Instructions. 3815// 3816class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3817 string opc, string asm, list<dag> pattern> 3818 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3819 bits<4> Rd; 3820 bits<4> Rm; 3821 bits<4> Rn; 3822 let Inst{19-16} = Rd; 3823 let Inst{11-8} = Rm; 3824 let Inst{3-0} = Rn; 3825} 3826class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3827 string opc, string asm, list<dag> pattern> 3828 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3829 bits<4> RdLo; 3830 bits<4> RdHi; 3831 bits<4> Rm; 3832 bits<4> Rn; 3833 let Inst{19-16} = RdHi; 3834 let Inst{15-12} = RdLo; 3835 let Inst{11-8} = Rm; 3836 let Inst{3-0} = Rn; 3837} 3838class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3839 string opc, string asm, list<dag> pattern> 3840 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3841 bits<4> RdLo; 3842 bits<4> RdHi; 3843 bits<4> Rm; 3844 bits<4> Rn; 3845 let Inst{19-16} = RdHi; 3846 let Inst{15-12} = RdLo; 3847 let Inst{11-8} = Rm; 3848 let Inst{3-0} = Rn; 3849} 3850 3851// FIXME: The v5 pseudos are only necessary for the additional Constraint 3852// property. Remove them when it's possible to add those properties 3853// on an individual MachineInstr, not just an instruction description. 3854let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in { 3855def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), 3856 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3857 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", 3858 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>, 3859 Requires<[IsARM, HasV6]> { 3860 let Inst{15-12} = 0b0000; 3861 let Unpredictable{15-12} = 0b1111; 3862} 3863 3864let Constraints = "@earlyclobber $Rd" in 3865def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, 3866 pred:$p, cc_out:$s), 3867 4, IIC_iMUL32, 3868 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))], 3869 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 3870 Requires<[IsARM, NoV6, UseMulOps]>; 3871} 3872 3873def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd), 3874 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra), 3875 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra", 3876 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>, 3877 Requires<[IsARM, HasV6, UseMulOps]> { 3878 bits<4> Ra; 3879 let Inst{15-12} = Ra; 3880} 3881 3882let Constraints = "@earlyclobber $Rd" in 3883def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd), 3884 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 3885 pred:$p, cc_out:$s), 4, IIC_iMAC32, 3886 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))], 3887 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>, 3888 Requires<[IsARM, NoV6]>; 3889 3890def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3891 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra", 3892 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>, 3893 Requires<[IsARM, HasV6T2, UseMulOps]> { 3894 bits<4> Rd; 3895 bits<4> Rm; 3896 bits<4> Rn; 3897 bits<4> Ra; 3898 let Inst{19-16} = Rd; 3899 let Inst{15-12} = Ra; 3900 let Inst{11-8} = Rm; 3901 let Inst{3-0} = Rn; 3902} 3903 3904// Extra precision multiplies with low / high results 3905let hasSideEffects = 0 in { 3906let isCommutable = 1 in { 3907def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi), 3908 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 3909 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3910 Requires<[IsARM, HasV6]>; 3911 3912def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), 3913 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 3914 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3915 Requires<[IsARM, HasV6]>; 3916 3917let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { 3918def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3919 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 3920 4, IIC_iMUL64, [], 3921 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 3922 Requires<[IsARM, NoV6]>; 3923 3924def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3925 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 3926 4, IIC_iMUL64, [], 3927 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 3928 Requires<[IsARM, NoV6]>; 3929} 3930} 3931 3932// Multiply + accumulate 3933def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi), 3934 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 3935 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3936 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>; 3937def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi), 3938 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 3939 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3940 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>; 3941 3942def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi), 3943 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64, 3944 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3945 Requires<[IsARM, HasV6]> { 3946 bits<4> RdLo; 3947 bits<4> RdHi; 3948 bits<4> Rm; 3949 bits<4> Rn; 3950 let Inst{19-16} = RdHi; 3951 let Inst{15-12} = RdLo; 3952 let Inst{11-8} = Rm; 3953 let Inst{3-0} = Rn; 3954} 3955 3956let Constraints = 3957 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in { 3958def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3959 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 3960 4, IIC_iMAC64, [], 3961 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 3962 pred:$p, cc_out:$s)>, 3963 Requires<[IsARM, NoV6]>; 3964def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3965 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 3966 4, IIC_iMAC64, [], 3967 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 3968 pred:$p, cc_out:$s)>, 3969 Requires<[IsARM, NoV6]>; 3970} 3971 3972} // hasSideEffects 3973 3974// Most significant word multiply 3975def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3976 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm", 3977 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>, 3978 Requires<[IsARM, HasV6]> { 3979 let Inst{15-12} = 0b1111; 3980} 3981 3982def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3983 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>, 3984 Requires<[IsARM, HasV6]> { 3985 let Inst{15-12} = 0b1111; 3986} 3987 3988def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd), 3989 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3990 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra", 3991 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, 3992 Requires<[IsARM, HasV6, UseMulOps]>; 3993 3994def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd), 3995 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3996 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>, 3997 Requires<[IsARM, HasV6]>; 3998 3999def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd), 4000 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4001 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>, 4002 Requires<[IsARM, HasV6, UseMulOps]>; 4003 4004def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd), 4005 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4006 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>, 4007 Requires<[IsARM, HasV6]>; 4008 4009multiclass AI_smul<string opc, SDNode opnode> { 4010 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4011 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 4012 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16), 4013 (sext_inreg GPR:$Rm, i16)))]>, 4014 Requires<[IsARM, HasV5TE]>; 4015 4016 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4017 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 4018 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16), 4019 (sra GPR:$Rm, (i32 16))))]>, 4020 Requires<[IsARM, HasV5TE]>; 4021 4022 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4023 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 4024 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)), 4025 (sext_inreg GPR:$Rm, i16)))]>, 4026 Requires<[IsARM, HasV5TE]>; 4027 4028 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4029 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 4030 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)), 4031 (sra GPR:$Rm, (i32 16))))]>, 4032 Requires<[IsARM, HasV5TE]>; 4033 4034 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4035 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 4036 []>, 4037 Requires<[IsARM, HasV5TE]>; 4038 4039 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4040 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 4041 []>, 4042 Requires<[IsARM, HasV5TE]>; 4043} 4044 4045 4046multiclass AI_smla<string opc, SDNode opnode> { 4047 let DecoderMethod = "DecodeSMLAInstruction" in { 4048 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd), 4049 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4050 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 4051 [(set GPRnopc:$Rd, (add GPR:$Ra, 4052 (opnode (sext_inreg GPRnopc:$Rn, i16), 4053 (sext_inreg GPRnopc:$Rm, i16))))]>, 4054 Requires<[IsARM, HasV5TE, UseMulOps]>; 4055 4056 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd), 4057 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4058 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 4059 [(set GPRnopc:$Rd, 4060 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16), 4061 (sra GPRnopc:$Rm, (i32 16)))))]>, 4062 Requires<[IsARM, HasV5TE, UseMulOps]>; 4063 4064 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd), 4065 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4066 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 4067 [(set GPRnopc:$Rd, 4068 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)), 4069 (sext_inreg GPRnopc:$Rm, i16))))]>, 4070 Requires<[IsARM, HasV5TE, UseMulOps]>; 4071 4072 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd), 4073 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4074 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 4075 [(set GPRnopc:$Rd, 4076 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)), 4077 (sra GPRnopc:$Rm, (i32 16)))))]>, 4078 Requires<[IsARM, HasV5TE, UseMulOps]>; 4079 4080 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd), 4081 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4082 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 4083 []>, 4084 Requires<[IsARM, HasV5TE, UseMulOps]>; 4085 4086 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd), 4087 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4088 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 4089 []>, 4090 Requires<[IsARM, HasV5TE, UseMulOps]>; 4091 } 4092} 4093 4094defm SMUL : AI_smul<"smul", mul>; 4095defm SMLA : AI_smla<"smla", mul>; 4096 4097// Halfword multiply accumulate long: SMLAL<x><y>. 4098def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4099 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4100 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4101 Requires<[IsARM, HasV5TE]>; 4102 4103def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4104 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4105 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4106 Requires<[IsARM, HasV5TE]>; 4107 4108def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4109 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4110 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4111 Requires<[IsARM, HasV5TE]>; 4112 4113def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4114 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4115 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4116 Requires<[IsARM, HasV5TE]>; 4117 4118// Helper class for AI_smld. 4119class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops, 4120 InstrItinClass itin, string opc, string asm> 4121 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> { 4122 bits<4> Rn; 4123 bits<4> Rm; 4124 let Inst{27-23} = 0b01110; 4125 let Inst{22} = long; 4126 let Inst{21-20} = 0b00; 4127 let Inst{11-8} = Rm; 4128 let Inst{7} = 0; 4129 let Inst{6} = sub; 4130 let Inst{5} = swap; 4131 let Inst{4} = 1; 4132 let Inst{3-0} = Rn; 4133} 4134class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops, 4135 InstrItinClass itin, string opc, string asm> 4136 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4137 bits<4> Rd; 4138 let Inst{15-12} = 0b1111; 4139 let Inst{19-16} = Rd; 4140} 4141class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops, 4142 InstrItinClass itin, string opc, string asm> 4143 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4144 bits<4> Ra; 4145 bits<4> Rd; 4146 let Inst{19-16} = Rd; 4147 let Inst{15-12} = Ra; 4148} 4149class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops, 4150 InstrItinClass itin, string opc, string asm> 4151 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4152 bits<4> RdLo; 4153 bits<4> RdHi; 4154 let Inst{19-16} = RdHi; 4155 let Inst{15-12} = RdLo; 4156} 4157 4158multiclass AI_smld<bit sub, string opc> { 4159 4160 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd), 4161 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4162 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">; 4163 4164 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd), 4165 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4166 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">; 4167 4168 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4169 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary, 4170 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">; 4171 4172 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4173 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary, 4174 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">; 4175 4176} 4177 4178defm SMLA : AI_smld<0, "smla">; 4179defm SMLS : AI_smld<1, "smls">; 4180 4181multiclass AI_sdml<bit sub, string opc> { 4182 4183 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), 4184 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">; 4185 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm), 4186 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">; 4187} 4188 4189defm SMUA : AI_sdml<0, "smua">; 4190defm SMUS : AI_sdml<1, "smus">; 4191 4192//===----------------------------------------------------------------------===// 4193// Division Instructions (ARMv7-A with virtualization extension) 4194// 4195def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4196 "sdiv", "\t$Rd, $Rn, $Rm", 4197 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>, 4198 Requires<[IsARM, HasDivideInARM]>; 4199 4200def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4201 "udiv", "\t$Rd, $Rn, $Rm", 4202 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>, 4203 Requires<[IsARM, HasDivideInARM]>; 4204 4205//===----------------------------------------------------------------------===// 4206// Misc. Arithmetic Instructions. 4207// 4208 4209def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm), 4210 IIC_iUNAr, "clz", "\t$Rd, $Rm", 4211 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>, 4212 Sched<[WriteALU]>; 4213 4214def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4215 IIC_iUNAr, "rbit", "\t$Rd, $Rm", 4216 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>, 4217 Requires<[IsARM, HasV6T2]>, 4218 Sched<[WriteALU]>; 4219 4220def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4221 IIC_iUNAr, "rev", "\t$Rd, $Rm", 4222 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>, 4223 Sched<[WriteALU]>; 4224 4225let AddedComplexity = 5 in 4226def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4227 IIC_iUNAr, "rev16", "\t$Rd, $Rm", 4228 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>, 4229 Requires<[IsARM, HasV6]>, 4230 Sched<[WriteALU]>; 4231 4232def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)), 4233 (REV16 (LDRH addrmode3:$addr))>; 4234def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr), 4235 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>; 4236 4237let AddedComplexity = 5 in 4238def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4239 IIC_iUNAr, "revsh", "\t$Rd, $Rm", 4240 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>, 4241 Requires<[IsARM, HasV6]>, 4242 Sched<[WriteALU]>; 4243 4244def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)), 4245 (and (srl GPR:$Rm, (i32 8)), 0xFF)), 4246 (REVSH GPR:$Rm)>; 4247 4248def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd), 4249 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh), 4250 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 4251 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF), 4252 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh), 4253 0xFFFF0000)))]>, 4254 Requires<[IsARM, HasV6]>, 4255 Sched<[WriteALUsi, ReadALU]>; 4256 4257// Alternate cases for PKHBT where identities eliminate some nodes. 4258def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)), 4259 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>; 4260def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)), 4261 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>; 4262 4263// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 4264// will match the pattern below. 4265def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd), 4266 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh), 4267 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 4268 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000), 4269 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh), 4270 0xFFFF)))]>, 4271 Requires<[IsARM, HasV6]>, 4272 Sched<[WriteALUsi, ReadALU]>; 4273 4274// Alternate cases for PKHTB where identities eliminate some nodes. Note that 4275// a shift amount of 0 is *not legal* here, it is PKHBT instead. 4276// We also can not replace a srl (17..31) by an arithmetic shift we would use in 4277// pkhtb src1, src2, asr (17..31). 4278def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4279 (srl GPRnopc:$src2, imm16:$sh)), 4280 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>; 4281def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4282 (sra GPRnopc:$src2, imm16_31:$sh)), 4283 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>; 4284def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4285 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)), 4286 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>; 4287 4288//===----------------------------------------------------------------------===// 4289// CRC Instructions 4290// 4291// Polynomials: 4292// + CRC32{B,H,W} 0x04C11DB7 4293// + CRC32C{B,H,W} 0x1EDC6F41 4294// 4295 4296class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin> 4297 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary, 4298 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm", 4299 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>, 4300 Requires<[IsARM, HasV8, HasCRC]> { 4301 bits<4> Rd; 4302 bits<4> Rn; 4303 bits<4> Rm; 4304 4305 let Inst{31-28} = 0b1110; 4306 let Inst{27-23} = 0b00010; 4307 let Inst{22-21} = sz; 4308 let Inst{20} = 0; 4309 let Inst{19-16} = Rn; 4310 let Inst{15-12} = Rd; 4311 let Inst{11-10} = 0b00; 4312 let Inst{9} = C; 4313 let Inst{8} = 0; 4314 let Inst{7-4} = 0b0100; 4315 let Inst{3-0} = Rm; 4316 4317 let Unpredictable{11-8} = 0b1101; 4318} 4319 4320def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>; 4321def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>; 4322def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>; 4323def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>; 4324def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>; 4325def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>; 4326 4327//===----------------------------------------------------------------------===// 4328// ARMv8.1a Privilege Access Never extension 4329// 4330// SETPAN #imm1 4331 4332def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan", 4333 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> { 4334 bits<1> imm; 4335 4336 let Inst{31-28} = 0b1111; 4337 let Inst{27-20} = 0b00010001; 4338 let Inst{19-16} = 0b0000; 4339 let Inst{15-10} = 0b000000; 4340 let Inst{9} = imm; 4341 let Inst{8} = 0b0; 4342 let Inst{7-4} = 0b0000; 4343 let Inst{3-0} = 0b0000; 4344 4345 let Unpredictable{19-16} = 0b1111; 4346 let Unpredictable{15-10} = 0b111111; 4347 let Unpredictable{8} = 0b1; 4348 let Unpredictable{3-0} = 0b1111; 4349} 4350 4351//===----------------------------------------------------------------------===// 4352// Comparison Instructions... 4353// 4354 4355defm CMP : AI1_cmp_irs<0b1010, "cmp", 4356 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, ARMcmp>; 4357 4358// ARMcmpZ can re-use the above instruction definitions. 4359def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm), 4360 (CMPri GPR:$src, mod_imm:$imm)>; 4361def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs), 4362 (CMPrr GPR:$src, GPR:$rhs)>; 4363def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs), 4364 (CMPrsi GPR:$src, so_reg_imm:$rhs)>; 4365def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs), 4366 (CMPrsr GPR:$src, so_reg_reg:$rhs)>; 4367 4368// CMN register-integer 4369let isCompare = 1, Defs = [CPSR] in { 4370def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi, 4371 "cmn", "\t$Rn, $imm", 4372 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>, 4373 Sched<[WriteCMP, ReadALU]> { 4374 bits<4> Rn; 4375 bits<12> imm; 4376 let Inst{25} = 1; 4377 let Inst{20} = 1; 4378 let Inst{19-16} = Rn; 4379 let Inst{15-12} = 0b0000; 4380 let Inst{11-0} = imm; 4381 4382 let Unpredictable{15-12} = 0b1111; 4383} 4384 4385// CMN register-register/shift 4386def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr, 4387 "cmn", "\t$Rn, $Rm", 4388 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4389 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> { 4390 bits<4> Rn; 4391 bits<4> Rm; 4392 let isCommutable = 1; 4393 let Inst{25} = 0; 4394 let Inst{20} = 1; 4395 let Inst{19-16} = Rn; 4396 let Inst{15-12} = 0b0000; 4397 let Inst{11-4} = 0b00000000; 4398 let Inst{3-0} = Rm; 4399 4400 let Unpredictable{15-12} = 0b1111; 4401} 4402 4403def CMNzrsi : AI1<0b1011, (outs), 4404 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr, 4405 "cmn", "\t$Rn, $shift", 4406 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4407 GPR:$Rn, so_reg_imm:$shift)]>, 4408 Sched<[WriteCMPsi, ReadALU]> { 4409 bits<4> Rn; 4410 bits<12> shift; 4411 let Inst{25} = 0; 4412 let Inst{20} = 1; 4413 let Inst{19-16} = Rn; 4414 let Inst{15-12} = 0b0000; 4415 let Inst{11-5} = shift{11-5}; 4416 let Inst{4} = 0; 4417 let Inst{3-0} = shift{3-0}; 4418 4419 let Unpredictable{15-12} = 0b1111; 4420} 4421 4422def CMNzrsr : AI1<0b1011, (outs), 4423 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr, 4424 "cmn", "\t$Rn, $shift", 4425 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4426 GPRnopc:$Rn, so_reg_reg:$shift)]>, 4427 Sched<[WriteCMPsr, ReadALU]> { 4428 bits<4> Rn; 4429 bits<12> shift; 4430 let Inst{25} = 0; 4431 let Inst{20} = 1; 4432 let Inst{19-16} = Rn; 4433 let Inst{15-12} = 0b0000; 4434 let Inst{11-8} = shift{11-8}; 4435 let Inst{7} = 0; 4436 let Inst{6-5} = shift{6-5}; 4437 let Inst{4} = 1; 4438 let Inst{3-0} = shift{3-0}; 4439 4440 let Unpredictable{15-12} = 0b1111; 4441} 4442 4443} 4444 4445def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm), 4446 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4447 4448def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm), 4449 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4450 4451// Note that TST/TEQ don't set all the same flags that CMP does! 4452defm TST : AI1_cmp_irs<0b1000, "tst", 4453 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4454 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1, 4455 "DecodeTSTInstruction">; 4456defm TEQ : AI1_cmp_irs<0b1001, "teq", 4457 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4458 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>; 4459 4460// Pseudo i64 compares for some floating point compares. 4461let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, 4462 Defs = [CPSR] in { 4463def BCCi64 : PseudoInst<(outs), 4464 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst), 4465 IIC_Br, 4466 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>, 4467 Sched<[WriteBr]>; 4468 4469def BCCZi64 : PseudoInst<(outs), 4470 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, 4471 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>, 4472 Sched<[WriteBr]>; 4473} // usesCustomInserter 4474 4475 4476// Conditional moves 4477let hasSideEffects = 0 in { 4478 4479let isCommutable = 1, isSelect = 1 in 4480def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), 4481 (ins GPR:$false, GPR:$Rm, cmovpred:$p), 4482 4, IIC_iCMOVr, 4483 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, 4484 cmovpred:$p))]>, 4485 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4486 4487def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd), 4488 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p), 4489 4, IIC_iCMOVsr, 4490 [(set GPR:$Rd, 4491 (ARMcmov GPR:$false, so_reg_imm:$shift, 4492 cmovpred:$p))]>, 4493 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4494def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd), 4495 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p), 4496 4, IIC_iCMOVsr, 4497 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift, 4498 cmovpred:$p))]>, 4499 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4500 4501 4502let isMoveImm = 1 in 4503def MOVCCi16 4504 : ARMPseudoInst<(outs GPR:$Rd), 4505 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p), 4506 4, IIC_iMOVi, 4507 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm, 4508 cmovpred:$p))]>, 4509 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>, 4510 Sched<[WriteALU]>; 4511 4512let isMoveImm = 1 in 4513def MOVCCi : ARMPseudoInst<(outs GPR:$Rd), 4514 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 4515 4, IIC_iCMOVi, 4516 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm, 4517 cmovpred:$p))]>, 4518 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4519 4520// Two instruction predicate mov immediate. 4521let isMoveImm = 1 in 4522def MOVCCi32imm 4523 : ARMPseudoInst<(outs GPR:$Rd), 4524 (ins GPR:$false, i32imm:$src, cmovpred:$p), 4525 8, IIC_iCMOVix2, 4526 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src, 4527 cmovpred:$p))]>, 4528 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>; 4529 4530let isMoveImm = 1 in 4531def MVNCCi : ARMPseudoInst<(outs GPR:$Rd), 4532 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 4533 4, IIC_iCMOVi, 4534 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm, 4535 cmovpred:$p))]>, 4536 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4537 4538} // hasSideEffects 4539 4540 4541//===----------------------------------------------------------------------===// 4542// Atomic operations intrinsics 4543// 4544 4545def MemBarrierOptOperand : AsmOperandClass { 4546 let Name = "MemBarrierOpt"; 4547 let ParserMethod = "parseMemBarrierOptOperand"; 4548} 4549def memb_opt : Operand<i32> { 4550 let PrintMethod = "printMemBOption"; 4551 let ParserMatchClass = MemBarrierOptOperand; 4552 let DecoderMethod = "DecodeMemBarrierOption"; 4553} 4554 4555def InstSyncBarrierOptOperand : AsmOperandClass { 4556 let Name = "InstSyncBarrierOpt"; 4557 let ParserMethod = "parseInstSyncBarrierOptOperand"; 4558} 4559def instsyncb_opt : Operand<i32> { 4560 let PrintMethod = "printInstSyncBOption"; 4561 let ParserMatchClass = InstSyncBarrierOptOperand; 4562 let DecoderMethod = "DecodeInstSyncBarrierOption"; 4563} 4564 4565// Memory barriers protect the atomic sequences 4566let hasSideEffects = 1 in { 4567def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4568 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>, 4569 Requires<[IsARM, HasDB]> { 4570 bits<4> opt; 4571 let Inst{31-4} = 0xf57ff05; 4572 let Inst{3-0} = opt; 4573} 4574 4575def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4576 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>, 4577 Requires<[IsARM, HasDB]> { 4578 bits<4> opt; 4579 let Inst{31-4} = 0xf57ff04; 4580 let Inst{3-0} = opt; 4581} 4582 4583// ISB has only full system option 4584def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary, 4585 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>, 4586 Requires<[IsARM, HasDB]> { 4587 bits<4> opt; 4588 let Inst{31-4} = 0xf57ff06; 4589 let Inst{3-0} = opt; 4590} 4591} 4592 4593let usesCustomInserter = 1, Defs = [CPSR] in { 4594 4595// Pseudo instruction that combines movs + predicated rsbmi 4596// to implement integer ABS 4597 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>; 4598} 4599 4600let usesCustomInserter = 1 in { 4601 def COPY_STRUCT_BYVAL_I32 : PseudoInst< 4602 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment), 4603 NoItinerary, 4604 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>; 4605} 4606 4607let hasPostISelHook = 1, Constraints = "$newdst = $dst, $newsrc = $src" in { 4608 // %newsrc, %newdst = MEMCPY %dst, %src, N, ...N scratch regs... 4609 // Copies N registers worth of memory from address %src to address %dst 4610 // and returns the incremented addresses. N scratch register will 4611 // be attached for the copy to use. 4612 def MEMCPY : PseudoInst< 4613 (outs GPR:$newdst, GPR:$newsrc), 4614 (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops), 4615 NoItinerary, 4616 [(set GPR:$newdst, GPR:$newsrc, 4617 (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>; 4618} 4619 4620def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4621 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4622}]>; 4623 4624def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4625 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4626}]>; 4627 4628def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4629 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4630}]>; 4631 4632def strex_1 : PatFrag<(ops node:$val, node:$ptr), 4633 (int_arm_strex node:$val, node:$ptr), [{ 4634 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4635}]>; 4636 4637def strex_2 : PatFrag<(ops node:$val, node:$ptr), 4638 (int_arm_strex node:$val, node:$ptr), [{ 4639 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4640}]>; 4641 4642def strex_4 : PatFrag<(ops node:$val, node:$ptr), 4643 (int_arm_strex node:$val, node:$ptr), [{ 4644 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4645}]>; 4646 4647def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4648 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4649}]>; 4650 4651def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4652 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4653}]>; 4654 4655def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4656 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4657}]>; 4658 4659def stlex_1 : PatFrag<(ops node:$val, node:$ptr), 4660 (int_arm_stlex node:$val, node:$ptr), [{ 4661 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4662}]>; 4663 4664def stlex_2 : PatFrag<(ops node:$val, node:$ptr), 4665 (int_arm_stlex node:$val, node:$ptr), [{ 4666 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4667}]>; 4668 4669def stlex_4 : PatFrag<(ops node:$val, node:$ptr), 4670 (int_arm_stlex node:$val, node:$ptr), [{ 4671 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4672}]>; 4673 4674let mayLoad = 1 in { 4675def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4676 NoItinerary, "ldrexb", "\t$Rt, $addr", 4677 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>; 4678def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4679 NoItinerary, "ldrexh", "\t$Rt, $addr", 4680 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>; 4681def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4682 NoItinerary, "ldrex", "\t$Rt, $addr", 4683 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>; 4684let hasExtraDefRegAllocReq = 1 in 4685def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 4686 NoItinerary, "ldrexd", "\t$Rt, $addr", []> { 4687 let DecoderMethod = "DecodeDoubleRegLoad"; 4688} 4689 4690def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4691 NoItinerary, "ldaexb", "\t$Rt, $addr", 4692 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>; 4693def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4694 NoItinerary, "ldaexh", "\t$Rt, $addr", 4695 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>; 4696def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4697 NoItinerary, "ldaex", "\t$Rt, $addr", 4698 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>; 4699let hasExtraDefRegAllocReq = 1 in 4700def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 4701 NoItinerary, "ldaexd", "\t$Rt, $addr", []> { 4702 let DecoderMethod = "DecodeDoubleRegLoad"; 4703} 4704} 4705 4706let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 4707def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4708 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", 4709 [(set GPR:$Rd, (strex_1 GPR:$Rt, 4710 addr_offset_none:$addr))]>; 4711def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4712 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", 4713 [(set GPR:$Rd, (strex_2 GPR:$Rt, 4714 addr_offset_none:$addr))]>; 4715def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4716 NoItinerary, "strex", "\t$Rd, $Rt, $addr", 4717 [(set GPR:$Rd, (strex_4 GPR:$Rt, 4718 addr_offset_none:$addr))]>; 4719let hasExtraSrcRegAllocReq = 1 in 4720def STREXD : AIstrex<0b01, (outs GPR:$Rd), 4721 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 4722 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> { 4723 let DecoderMethod = "DecodeDoubleRegStore"; 4724} 4725def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4726 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr", 4727 [(set GPR:$Rd, 4728 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>; 4729def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4730 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr", 4731 [(set GPR:$Rd, 4732 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>; 4733def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4734 NoItinerary, "stlex", "\t$Rd, $Rt, $addr", 4735 [(set GPR:$Rd, 4736 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>; 4737let hasExtraSrcRegAllocReq = 1 in 4738def STLEXD : AIstlex<0b01, (outs GPR:$Rd), 4739 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 4740 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> { 4741 let DecoderMethod = "DecodeDoubleRegStore"; 4742} 4743} 4744 4745def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", 4746 [(int_arm_clrex)]>, 4747 Requires<[IsARM, HasV6K]> { 4748 let Inst{31-0} = 0b11110101011111111111000000011111; 4749} 4750 4751def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 4752 (STREXB GPR:$Rt, addr_offset_none:$addr)>; 4753def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 4754 (STREXH GPR:$Rt, addr_offset_none:$addr)>; 4755 4756def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 4757 (STLEXB GPR:$Rt, addr_offset_none:$addr)>; 4758def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 4759 (STLEXH GPR:$Rt, addr_offset_none:$addr)>; 4760 4761class acquiring_load<PatFrag base> 4762 : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 4763 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 4764 return isAtLeastAcquire(Ordering); 4765}]>; 4766 4767def atomic_load_acquire_8 : acquiring_load<atomic_load_8>; 4768def atomic_load_acquire_16 : acquiring_load<atomic_load_16>; 4769def atomic_load_acquire_32 : acquiring_load<atomic_load_32>; 4770 4771class releasing_store<PatFrag base> 4772 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 4773 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 4774 return isAtLeastRelease(Ordering); 4775}]>; 4776 4777def atomic_store_release_8 : releasing_store<atomic_store_8>; 4778def atomic_store_release_16 : releasing_store<atomic_store_16>; 4779def atomic_store_release_32 : releasing_store<atomic_store_32>; 4780 4781let AddedComplexity = 8 in { 4782 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>; 4783 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>; 4784 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>; 4785 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>; 4786 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>; 4787 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>; 4788} 4789 4790// SWP/SWPB are deprecated in V6/V7. 4791let mayLoad = 1, mayStore = 1 in { 4792def SWP : AIswp<0, (outs GPRnopc:$Rt), 4793 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>, 4794 Requires<[PreV8]>; 4795def SWPB: AIswp<1, (outs GPRnopc:$Rt), 4796 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>, 4797 Requires<[PreV8]>; 4798} 4799 4800//===----------------------------------------------------------------------===// 4801// Coprocessor Instructions. 4802// 4803 4804def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4805 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4806 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4807 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4808 imm:$CRm, imm:$opc2)]>, 4809 Requires<[PreV8]> { 4810 bits<4> opc1; 4811 bits<4> CRn; 4812 bits<4> CRd; 4813 bits<4> cop; 4814 bits<3> opc2; 4815 bits<4> CRm; 4816 4817 let Inst{3-0} = CRm; 4818 let Inst{4} = 0; 4819 let Inst{7-5} = opc2; 4820 let Inst{11-8} = cop; 4821 let Inst{15-12} = CRd; 4822 let Inst{19-16} = CRn; 4823 let Inst{23-20} = opc1; 4824} 4825 4826def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4827 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4828 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4829 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4830 imm:$CRm, imm:$opc2)]>, 4831 Requires<[PreV8]> { 4832 let Inst{31-28} = 0b1111; 4833 bits<4> opc1; 4834 bits<4> CRn; 4835 bits<4> CRd; 4836 bits<4> cop; 4837 bits<3> opc2; 4838 bits<4> CRm; 4839 4840 let Inst{3-0} = CRm; 4841 let Inst{4} = 0; 4842 let Inst{7-5} = opc2; 4843 let Inst{11-8} = cop; 4844 let Inst{15-12} = CRd; 4845 let Inst{19-16} = CRn; 4846 let Inst{23-20} = opc1; 4847} 4848 4849class ACI<dag oops, dag iops, string opc, string asm, 4850 IndexMode im = IndexModeNone> 4851 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 4852 opc, asm, "", []> { 4853 let Inst{27-25} = 0b110; 4854} 4855class ACInoP<dag oops, dag iops, string opc, string asm, 4856 IndexMode im = IndexModeNone> 4857 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 4858 opc, asm, "", []> { 4859 let Inst{31-28} = 0b1111; 4860 let Inst{27-25} = 0b110; 4861} 4862multiclass LdStCop<bit load, bit Dbit, string asm> { 4863 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 4864 asm, "\t$cop, $CRd, $addr"> { 4865 bits<13> addr; 4866 bits<4> cop; 4867 bits<4> CRd; 4868 let Inst{24} = 1; // P = 1 4869 let Inst{23} = addr{8}; 4870 let Inst{22} = Dbit; 4871 let Inst{21} = 0; // W = 0 4872 let Inst{20} = load; 4873 let Inst{19-16} = addr{12-9}; 4874 let Inst{15-12} = CRd; 4875 let Inst{11-8} = cop; 4876 let Inst{7-0} = addr{7-0}; 4877 let DecoderMethod = "DecodeCopMemInstruction"; 4878 } 4879 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 4880 asm, "\t$cop, $CRd, $addr!", IndexModePre> { 4881 bits<13> addr; 4882 bits<4> cop; 4883 bits<4> CRd; 4884 let Inst{24} = 1; // P = 1 4885 let Inst{23} = addr{8}; 4886 let Inst{22} = Dbit; 4887 let Inst{21} = 1; // W = 1 4888 let Inst{20} = load; 4889 let Inst{19-16} = addr{12-9}; 4890 let Inst{15-12} = CRd; 4891 let Inst{11-8} = cop; 4892 let Inst{7-0} = addr{7-0}; 4893 let DecoderMethod = "DecodeCopMemInstruction"; 4894 } 4895 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4896 postidx_imm8s4:$offset), 4897 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> { 4898 bits<9> offset; 4899 bits<4> addr; 4900 bits<4> cop; 4901 bits<4> CRd; 4902 let Inst{24} = 0; // P = 0 4903 let Inst{23} = offset{8}; 4904 let Inst{22} = Dbit; 4905 let Inst{21} = 1; // W = 1 4906 let Inst{20} = load; 4907 let Inst{19-16} = addr; 4908 let Inst{15-12} = CRd; 4909 let Inst{11-8} = cop; 4910 let Inst{7-0} = offset{7-0}; 4911 let DecoderMethod = "DecodeCopMemInstruction"; 4912 } 4913 def _OPTION : ACI<(outs), 4914 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4915 coproc_option_imm:$option), 4916 asm, "\t$cop, $CRd, $addr, $option"> { 4917 bits<8> option; 4918 bits<4> addr; 4919 bits<4> cop; 4920 bits<4> CRd; 4921 let Inst{24} = 0; // P = 0 4922 let Inst{23} = 1; // U = 1 4923 let Inst{22} = Dbit; 4924 let Inst{21} = 0; // W = 0 4925 let Inst{20} = load; 4926 let Inst{19-16} = addr; 4927 let Inst{15-12} = CRd; 4928 let Inst{11-8} = cop; 4929 let Inst{7-0} = option; 4930 let DecoderMethod = "DecodeCopMemInstruction"; 4931 } 4932} 4933multiclass LdSt2Cop<bit load, bit Dbit, string asm> { 4934 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 4935 asm, "\t$cop, $CRd, $addr"> { 4936 bits<13> addr; 4937 bits<4> cop; 4938 bits<4> CRd; 4939 let Inst{24} = 1; // P = 1 4940 let Inst{23} = addr{8}; 4941 let Inst{22} = Dbit; 4942 let Inst{21} = 0; // W = 0 4943 let Inst{20} = load; 4944 let Inst{19-16} = addr{12-9}; 4945 let Inst{15-12} = CRd; 4946 let Inst{11-8} = cop; 4947 let Inst{7-0} = addr{7-0}; 4948 let DecoderMethod = "DecodeCopMemInstruction"; 4949 } 4950 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 4951 asm, "\t$cop, $CRd, $addr!", IndexModePre> { 4952 bits<13> addr; 4953 bits<4> cop; 4954 bits<4> CRd; 4955 let Inst{24} = 1; // P = 1 4956 let Inst{23} = addr{8}; 4957 let Inst{22} = Dbit; 4958 let Inst{21} = 1; // W = 1 4959 let Inst{20} = load; 4960 let Inst{19-16} = addr{12-9}; 4961 let Inst{15-12} = CRd; 4962 let Inst{11-8} = cop; 4963 let Inst{7-0} = addr{7-0}; 4964 let DecoderMethod = "DecodeCopMemInstruction"; 4965 } 4966 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4967 postidx_imm8s4:$offset), 4968 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> { 4969 bits<9> offset; 4970 bits<4> addr; 4971 bits<4> cop; 4972 bits<4> CRd; 4973 let Inst{24} = 0; // P = 0 4974 let Inst{23} = offset{8}; 4975 let Inst{22} = Dbit; 4976 let Inst{21} = 1; // W = 1 4977 let Inst{20} = load; 4978 let Inst{19-16} = addr; 4979 let Inst{15-12} = CRd; 4980 let Inst{11-8} = cop; 4981 let Inst{7-0} = offset{7-0}; 4982 let DecoderMethod = "DecodeCopMemInstruction"; 4983 } 4984 def _OPTION : ACInoP<(outs), 4985 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4986 coproc_option_imm:$option), 4987 asm, "\t$cop, $CRd, $addr, $option"> { 4988 bits<8> option; 4989 bits<4> addr; 4990 bits<4> cop; 4991 bits<4> CRd; 4992 let Inst{24} = 0; // P = 0 4993 let Inst{23} = 1; // U = 1 4994 let Inst{22} = Dbit; 4995 let Inst{21} = 0; // W = 0 4996 let Inst{20} = load; 4997 let Inst{19-16} = addr; 4998 let Inst{15-12} = CRd; 4999 let Inst{11-8} = cop; 5000 let Inst{7-0} = option; 5001 let DecoderMethod = "DecodeCopMemInstruction"; 5002 } 5003} 5004 5005defm LDC : LdStCop <1, 0, "ldc">; 5006defm LDCL : LdStCop <1, 1, "ldcl">; 5007defm STC : LdStCop <0, 0, "stc">; 5008defm STCL : LdStCop <0, 1, "stcl">; 5009defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>; 5010defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>; 5011defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>; 5012defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>; 5013 5014//===----------------------------------------------------------------------===// 5015// Move between coprocessor and ARM core register. 5016// 5017 5018class MovRCopro<string opc, bit direction, dag oops, dag iops, 5019 list<dag> pattern> 5020 : ABI<0b1110, oops, iops, NoItinerary, opc, 5021 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> { 5022 let Inst{20} = direction; 5023 let Inst{4} = 1; 5024 5025 bits<4> Rt; 5026 bits<4> cop; 5027 bits<3> opc1; 5028 bits<3> opc2; 5029 bits<4> CRm; 5030 bits<4> CRn; 5031 5032 let Inst{15-12} = Rt; 5033 let Inst{11-8} = cop; 5034 let Inst{23-21} = opc1; 5035 let Inst{7-5} = opc2; 5036 let Inst{3-0} = CRm; 5037 let Inst{19-16} = CRn; 5038} 5039 5040def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */, 5041 (outs), 5042 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5043 c_imm:$CRm, imm0_7:$opc2), 5044 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 5045 imm:$CRm, imm:$opc2)]>, 5046 ComplexDeprecationPredicate<"MCR">; 5047def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 5048 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5049 c_imm:$CRm, 0, pred:$p)>; 5050def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, 5051 (outs GPRwithAPSR:$Rt), 5052 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5053 imm0_7:$opc2), []>; 5054def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", 5055 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5056 c_imm:$CRm, 0, pred:$p)>; 5057 5058def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 5059 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 5060 5061class MovRCopro2<string opc, bit direction, dag oops, dag iops, 5062 list<dag> pattern> 5063 : ABXI<0b1110, oops, iops, NoItinerary, 5064 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> { 5065 let Inst{31-24} = 0b11111110; 5066 let Inst{20} = direction; 5067 let Inst{4} = 1; 5068 5069 bits<4> Rt; 5070 bits<4> cop; 5071 bits<3> opc1; 5072 bits<3> opc2; 5073 bits<4> CRm; 5074 bits<4> CRn; 5075 5076 let Inst{15-12} = Rt; 5077 let Inst{11-8} = cop; 5078 let Inst{23-21} = opc1; 5079 let Inst{7-5} = opc2; 5080 let Inst{3-0} = CRm; 5081 let Inst{19-16} = CRn; 5082} 5083 5084def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */, 5085 (outs), 5086 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5087 c_imm:$CRm, imm0_7:$opc2), 5088 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 5089 imm:$CRm, imm:$opc2)]>, 5090 Requires<[PreV8]>; 5091def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm", 5092 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5093 c_imm:$CRm, 0)>; 5094def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, 5095 (outs GPRwithAPSR:$Rt), 5096 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5097 imm0_7:$opc2), []>, 5098 Requires<[PreV8]>; 5099def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm", 5100 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5101 c_imm:$CRm, 0)>; 5102 5103def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, 5104 imm:$CRm, imm:$opc2), 5105 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 5106 5107class MovRRCopro<string opc, bit direction, dag oops, dag iops, list<dag> 5108 pattern = []> 5109 : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", 5110 pattern> { 5111 5112 let Inst{23-21} = 0b010; 5113 let Inst{20} = direction; 5114 5115 bits<4> Rt; 5116 bits<4> Rt2; 5117 bits<4> cop; 5118 bits<4> opc1; 5119 bits<4> CRm; 5120 5121 let Inst{15-12} = Rt; 5122 let Inst{19-16} = Rt2; 5123 let Inst{11-8} = cop; 5124 let Inst{7-4} = opc1; 5125 let Inst{3-0} = CRm; 5126} 5127 5128def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */, 5129 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5130 GPRnopc:$Rt2, c_imm:$CRm), 5131 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt, 5132 GPRnopc:$Rt2, imm:$CRm)]>; 5133def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */, 5134 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5135 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5136 5137class MovRRCopro2<string opc, bit direction, list<dag> pattern = []> 5138 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5139 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary, 5140 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>, 5141 Requires<[PreV8]> { 5142 let Inst{31-28} = 0b1111; 5143 let Inst{23-21} = 0b010; 5144 let Inst{20} = direction; 5145 5146 bits<4> Rt; 5147 bits<4> Rt2; 5148 bits<4> cop; 5149 bits<4> opc1; 5150 bits<4> CRm; 5151 5152 let Inst{15-12} = Rt; 5153 let Inst{19-16} = Rt2; 5154 let Inst{11-8} = cop; 5155 let Inst{7-4} = opc1; 5156 let Inst{3-0} = CRm; 5157 5158 let DecoderMethod = "DecodeMRRC2"; 5159} 5160 5161def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */, 5162 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt, 5163 GPRnopc:$Rt2, imm:$CRm)]>; 5164def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>; 5165 5166//===----------------------------------------------------------------------===// 5167// Move between special register and ARM core register 5168// 5169 5170// Move to ARM core register from Special Register 5171def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5172 "mrs", "\t$Rd, apsr", []> { 5173 bits<4> Rd; 5174 let Inst{23-16} = 0b00001111; 5175 let Unpredictable{19-17} = 0b111; 5176 5177 let Inst{15-12} = Rd; 5178 5179 let Inst{11-0} = 0b000000000000; 5180 let Unpredictable{11-0} = 0b110100001111; 5181} 5182 5183def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>, 5184 Requires<[IsARM]>; 5185 5186// The MRSsys instruction is the MRS instruction from the ARM ARM, 5187// section B9.3.9, with the R bit set to 1. 5188def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5189 "mrs", "\t$Rd, spsr", []> { 5190 bits<4> Rd; 5191 let Inst{23-16} = 0b01001111; 5192 let Unpredictable{19-16} = 0b1111; 5193 5194 let Inst{15-12} = Rd; 5195 5196 let Inst{11-0} = 0b000000000000; 5197 let Unpredictable{11-0} = 0b110100001111; 5198} 5199 5200// However, the MRS (banked register) system instruction (ARMv7VE) *does* have a 5201// separate encoding (distinguished by bit 5. 5202def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked), 5203 NoItinerary, "mrs", "\t$Rd, $banked", []>, 5204 Requires<[IsARM, HasVirtualization]> { 5205 bits<6> banked; 5206 bits<4> Rd; 5207 5208 let Inst{23} = 0; 5209 let Inst{22} = banked{5}; // R bit 5210 let Inst{21-20} = 0b00; 5211 let Inst{19-16} = banked{3-0}; 5212 let Inst{15-12} = Rd; 5213 let Inst{11-9} = 0b001; 5214 let Inst{8} = banked{4}; 5215 let Inst{7-0} = 0b00000000; 5216} 5217 5218// Move from ARM core register to Special Register 5219// 5220// No need to have both system and application versions of MSR (immediate) or 5221// MSR (register), the encodings are the same and the assembly parser has no way 5222// to distinguish between them. The mask operand contains the special register 5223// (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be 5224// accessed in the special register. 5225def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, 5226 "msr", "\t$mask, $Rn", []> { 5227 bits<5> mask; 5228 bits<4> Rn; 5229 5230 let Inst{23} = 0; 5231 let Inst{22} = mask{4}; // R bit 5232 let Inst{21-20} = 0b10; 5233 let Inst{19-16} = mask{3-0}; 5234 let Inst{15-12} = 0b1111; 5235 let Inst{11-4} = 0b00000000; 5236 let Inst{3-0} = Rn; 5237} 5238 5239def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary, 5240 "msr", "\t$mask, $imm", []> { 5241 bits<5> mask; 5242 bits<12> imm; 5243 5244 let Inst{23} = 0; 5245 let Inst{22} = mask{4}; // R bit 5246 let Inst{21-20} = 0b10; 5247 let Inst{19-16} = mask{3-0}; 5248 let Inst{15-12} = 0b1111; 5249 let Inst{11-0} = imm; 5250} 5251 5252// However, the MSR (banked register) system instruction (ARMv7VE) *does* have a 5253// separate encoding (distinguished by bit 5. 5254def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn), 5255 NoItinerary, "msr", "\t$banked, $Rn", []>, 5256 Requires<[IsARM, HasVirtualization]> { 5257 bits<6> banked; 5258 bits<4> Rn; 5259 5260 let Inst{23} = 0; 5261 let Inst{22} = banked{5}; // R bit 5262 let Inst{21-20} = 0b10; 5263 let Inst{19-16} = banked{3-0}; 5264 let Inst{15-12} = 0b1111; 5265 let Inst{11-9} = 0b001; 5266 let Inst{8} = banked{4}; 5267 let Inst{7-4} = 0b0000; 5268 let Inst{3-0} = Rn; 5269} 5270 5271// Dynamic stack allocation yields a _chkstk for Windows targets. These calls 5272// are needed to probe the stack when allocating more than 5273// 4k bytes in one go. Touching the stack at 4K increments is necessary to 5274// ensure that the guard pages used by the OS virtual memory manager are 5275// allocated in correct sequence. 5276// The main point of having separate instruction are extra unmodelled effects 5277// (compared to ordinary calls) like stack pointer change. 5278 5279def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone, 5280 [SDNPHasChain, SDNPSideEffect]>; 5281let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in 5282 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>; 5283 5284def win__dbzchk : SDNode<"ARMISD::WIN__DBZCHK", SDT_WIN__DBZCHK, 5285 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 5286let usesCustomInserter = 1, Defs = [CPSR] in 5287 def WIN__DBZCHK : PseudoInst<(outs), (ins GPR:$divisor), NoItinerary, 5288 [(win__dbzchk GPR:$divisor)]>; 5289 5290//===----------------------------------------------------------------------===// 5291// TLS Instructions 5292// 5293 5294// __aeabi_read_tp preserves the registers r1-r3. 5295// This is a pseudo inst so that we can get the encoding right, 5296// complete with fixup for the aeabi_read_tp function. 5297// TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern 5298// is defined in "ARMInstrThumb.td". 5299let isCall = 1, 5300 Defs = [R0, R12, LR, CPSR], Uses = [SP] in { 5301 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br, 5302 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>; 5303} 5304 5305//===----------------------------------------------------------------------===// 5306// SJLJ Exception handling intrinsics 5307// eh_sjlj_setjmp() is an instruction sequence to store the return 5308// address and save #0 in R0 for the non-longjmp case. 5309// Since by its nature we may be coming from some other function to get 5310// here, and we're using the stack frame for the containing function to 5311// save/restore registers, we can't keep anything live in regs across 5312// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 5313// when we get here from a longjmp(). We force everything out of registers 5314// except for our own input by listing the relevant registers in Defs. By 5315// doing so, we also cause the prologue/epilogue code to actively preserve 5316// all of the callee-saved resgisters, which is exactly what we want. 5317// A constant value is passed in $val, and we use the location as a scratch. 5318// 5319// These are pseudo-instructions and are lowered to individual MC-insts, so 5320// no encoding information is necessary. 5321let Defs = 5322 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 5323 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ], 5324 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5325 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5326 NoItinerary, 5327 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5328 Requires<[IsARM, HasVFP2]>; 5329} 5330 5331let Defs = 5332 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 5333 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5334 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5335 NoItinerary, 5336 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5337 Requires<[IsARM, NoVFP]>; 5338} 5339 5340// FIXME: Non-IOS version(s) 5341let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, 5342 Defs = [ R7, LR, SP ] in { 5343def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch), 5344 NoItinerary, 5345 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 5346 Requires<[IsARM]>; 5347} 5348 5349let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in 5350def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary, 5351 [(ARMeh_sjlj_setup_dispatch)]>; 5352 5353// eh.sjlj.dispatchsetup pseudo-instruction. 5354// This pseudo is used for both ARM and Thumb. Any differences are handled when 5355// the pseudo is expanded (which happens before any passes that need the 5356// instruction size). 5357let isBarrier = 1 in 5358def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>; 5359 5360 5361//===----------------------------------------------------------------------===// 5362// Non-Instruction Patterns 5363// 5364 5365// ARMv4 indirect branch using (MOVr PC, dst) 5366let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in 5367 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst), 5368 4, IIC_Br, [(brind GPR:$dst)], 5369 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5370 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5371 5372// Large immediate handling. 5373 5374// 32-bit immediate using two piece mod_imms or movw + movt. 5375// This is a single pseudo instruction, the benefit is that it can be remat'd 5376// as a single unit instead of having to handle reg inputs. 5377// FIXME: Remove this when we can do generalized remat. 5378let isReMaterializable = 1, isMoveImm = 1 in 5379def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 5380 [(set GPR:$dst, (arm_i32imm:$src))]>, 5381 Requires<[IsARM]>; 5382 5383def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i, 5384 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>, 5385 Requires<[IsARM, DontUseMovt]>; 5386 5387// Pseudo instruction that combines movw + movt + add pc (if PIC). 5388// It also makes it possible to rematerialize the instructions. 5389// FIXME: Remove this when we can do generalized remat and when machine licm 5390// can properly the instructions. 5391let isReMaterializable = 1 in { 5392def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5393 IIC_iMOVix2addpc, 5394 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 5395 Requires<[IsARM, UseMovt]>; 5396 5397def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5398 IIC_iLoadiALU, 5399 [(set GPR:$dst, 5400 (ARMWrapperPIC tglobaladdr:$addr))]>, 5401 Requires<[IsARM, DontUseMovt]>; 5402 5403let AddedComplexity = 10 in 5404def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5405 NoItinerary, 5406 [(set GPR:$dst, 5407 (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5408 Requires<[IsARM, DontUseMovt]>; 5409 5410let AddedComplexity = 10 in 5411def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5412 IIC_iMOVix2ld, 5413 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5414 Requires<[IsARM, UseMovt]>; 5415} // isReMaterializable 5416 5417// The many different faces of TLS access. 5418def : ARMPat<(ARMWrapper tglobaltlsaddr :$dst), 5419 (MOVi32imm tglobaltlsaddr :$dst)>, 5420 Requires<[IsARM, UseMovt]>; 5421 5422def : Pat<(ARMWrapper tglobaltlsaddr:$src), 5423 (LDRLIT_ga_abs tglobaltlsaddr:$src)>, 5424 Requires<[IsARM, DontUseMovt]>; 5425 5426def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5427 (MOV_ga_pcrel tglobaltlsaddr:$addr)>, Requires<[IsARM, UseMovt]>; 5428 5429def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5430 (LDRLIT_ga_pcrel tglobaltlsaddr:$addr)>, 5431 Requires<[IsARM, DontUseMovt]>; 5432let AddedComplexity = 10 in 5433def : Pat<(load (ARMWrapperPIC tglobaltlsaddr:$addr)), 5434 (MOV_ga_pcrel_ldr tglobaltlsaddr:$addr)>, 5435 Requires<[IsARM, UseMovt]>; 5436 5437 5438// ConstantPool, GlobalAddress, and JumpTable 5439def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 5440def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>, 5441 Requires<[IsARM, UseMovt]>; 5442def : ARMPat<(ARMWrapper texternalsym :$dst), (MOVi32imm texternalsym :$dst)>, 5443 Requires<[IsARM, UseMovt]>; 5444def : ARMPat<(ARMWrapperJT tjumptable:$dst), 5445 (LEApcrelJT tjumptable:$dst)>; 5446 5447// TODO: add,sub,and, 3-instr forms? 5448 5449// Tail calls. These patterns also apply to Thumb mode. 5450def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>; 5451def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>; 5452def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>; 5453 5454// Direct calls 5455def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; 5456def : ARMPat<(ARMcall_nolink texternalsym:$func), 5457 (BMOVPCB_CALL texternalsym:$func)>; 5458 5459// zextload i1 -> zextload i8 5460def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5461def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5462 5463// extload -> zextload 5464def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5465def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5466def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5467def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5468 5469def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 5470 5471def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; 5472def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; 5473 5474// smul* and smla* 5475def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5476 (sra (shl GPR:$b, (i32 16)), (i32 16))), 5477 (SMULBB GPR:$a, GPR:$b)>; 5478def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 5479 (SMULBB GPR:$a, GPR:$b)>; 5480def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5481 (sra GPR:$b, (i32 16))), 5482 (SMULBT GPR:$a, GPR:$b)>; 5483def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))), 5484 (SMULBT GPR:$a, GPR:$b)>; 5485def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), 5486 (sra (shl GPR:$b, (i32 16)), (i32 16))), 5487 (SMULTB GPR:$a, GPR:$b)>; 5488def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b), 5489 (SMULTB GPR:$a, GPR:$b)>; 5490 5491def : ARMV5MOPat<(add GPR:$acc, 5492 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5493 (sra (shl GPR:$b, (i32 16)), (i32 16)))), 5494 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5495def : ARMV5MOPat<(add GPR:$acc, 5496 (mul sext_16_node:$a, sext_16_node:$b)), 5497 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5498def : ARMV5MOPat<(add GPR:$acc, 5499 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5500 (sra GPR:$b, (i32 16)))), 5501 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5502def : ARMV5MOPat<(add GPR:$acc, 5503 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))), 5504 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5505def : ARMV5MOPat<(add GPR:$acc, 5506 (mul (sra GPR:$a, (i32 16)), 5507 (sra (shl GPR:$b, (i32 16)), (i32 16)))), 5508 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5509def : ARMV5MOPat<(add GPR:$acc, 5510 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)), 5511 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5512 5513 5514// Pre-v7 uses MCR for synchronization barriers. 5515def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>, 5516 Requires<[IsARM, HasV6]>; 5517 5518// SXT/UXT with no rotate 5519let AddedComplexity = 16 in { 5520def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>; 5521def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>; 5522def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>; 5523def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)), 5524 (UXTAB GPR:$Rn, GPR:$Rm, 0)>; 5525def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)), 5526 (UXTAH GPR:$Rn, GPR:$Rm, 0)>; 5527} 5528 5529def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>; 5530def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; 5531 5532def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)), 5533 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>; 5534def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)), 5535 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>; 5536 5537// Atomic load/store patterns 5538def : ARMPat<(atomic_load_8 ldst_so_reg:$src), 5539 (LDRBrs ldst_so_reg:$src)>; 5540def : ARMPat<(atomic_load_8 addrmode_imm12:$src), 5541 (LDRBi12 addrmode_imm12:$src)>; 5542def : ARMPat<(atomic_load_16 addrmode3:$src), 5543 (LDRH addrmode3:$src)>; 5544def : ARMPat<(atomic_load_32 ldst_so_reg:$src), 5545 (LDRrs ldst_so_reg:$src)>; 5546def : ARMPat<(atomic_load_32 addrmode_imm12:$src), 5547 (LDRi12 addrmode_imm12:$src)>; 5548def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val), 5549 (STRBrs GPR:$val, ldst_so_reg:$ptr)>; 5550def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val), 5551 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>; 5552def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val), 5553 (STRH GPR:$val, addrmode3:$ptr)>; 5554def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val), 5555 (STRrs GPR:$val, ldst_so_reg:$ptr)>; 5556def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val), 5557 (STRi12 GPR:$val, addrmode_imm12:$ptr)>; 5558 5559 5560//===----------------------------------------------------------------------===// 5561// Thumb Support 5562// 5563 5564include "ARMInstrThumb.td" 5565 5566//===----------------------------------------------------------------------===// 5567// Thumb2 Support 5568// 5569 5570include "ARMInstrThumb2.td" 5571 5572//===----------------------------------------------------------------------===// 5573// Floating Point Support 5574// 5575 5576include "ARMInstrVFP.td" 5577 5578//===----------------------------------------------------------------------===// 5579// Advanced SIMD (NEON) Support 5580// 5581 5582include "ARMInstrNEON.td" 5583 5584//===----------------------------------------------------------------------===// 5585// Assembler aliases 5586// 5587 5588// Memory barriers 5589def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>; 5590def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>; 5591def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>; 5592 5593// System instructions 5594def : MnemonicAlias<"swi", "svc">; 5595 5596// Load / Store Multiple 5597def : MnemonicAlias<"ldmfd", "ldm">; 5598def : MnemonicAlias<"ldmia", "ldm">; 5599def : MnemonicAlias<"ldmea", "ldmdb">; 5600def : MnemonicAlias<"stmfd", "stmdb">; 5601def : MnemonicAlias<"stmia", "stm">; 5602def : MnemonicAlias<"stmea", "stm">; 5603 5604// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the 5605// input operands swapped when the shift amount is zero (i.e., unspecified). 5606def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 5607 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>, 5608 Requires<[IsARM, HasV6]>; 5609def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 5610 (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p)>, 5611 Requires<[IsARM, HasV6]>; 5612 5613// PUSH/POP aliases for STM/LDM 5614def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>; 5615def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>; 5616 5617// SSAT/USAT optional shift operand. 5618def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 5619 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5620def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn", 5621 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5622 5623 5624// Extend instruction optional rotate operand. 5625def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm", 5626 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5627def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm", 5628 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5629def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 5630 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5631def : ARMInstAlias<"sxtb${p} $Rd, $Rm", 5632 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5633def : ARMInstAlias<"sxtb16${p} $Rd, $Rm", 5634 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5635def : ARMInstAlias<"sxth${p} $Rd, $Rm", 5636 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5637 5638def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm", 5639 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5640def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm", 5641 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5642def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 5643 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5644def : ARMInstAlias<"uxtb${p} $Rd, $Rm", 5645 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5646def : ARMInstAlias<"uxtb16${p} $Rd, $Rm", 5647 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5648def : ARMInstAlias<"uxth${p} $Rd, $Rm", 5649 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5650 5651 5652// RFE aliases 5653def : MnemonicAlias<"rfefa", "rfeda">; 5654def : MnemonicAlias<"rfeea", "rfedb">; 5655def : MnemonicAlias<"rfefd", "rfeia">; 5656def : MnemonicAlias<"rfeed", "rfeib">; 5657def : MnemonicAlias<"rfe", "rfeia">; 5658 5659// SRS aliases 5660def : MnemonicAlias<"srsfa", "srsib">; 5661def : MnemonicAlias<"srsea", "srsia">; 5662def : MnemonicAlias<"srsfd", "srsdb">; 5663def : MnemonicAlias<"srsed", "srsda">; 5664def : MnemonicAlias<"srs", "srsia">; 5665 5666// QSAX == QSUBADDX 5667def : MnemonicAlias<"qsubaddx", "qsax">; 5668// SASX == SADDSUBX 5669def : MnemonicAlias<"saddsubx", "sasx">; 5670// SHASX == SHADDSUBX 5671def : MnemonicAlias<"shaddsubx", "shasx">; 5672// SHSAX == SHSUBADDX 5673def : MnemonicAlias<"shsubaddx", "shsax">; 5674// SSAX == SSUBADDX 5675def : MnemonicAlias<"ssubaddx", "ssax">; 5676// UASX == UADDSUBX 5677def : MnemonicAlias<"uaddsubx", "uasx">; 5678// UHASX == UHADDSUBX 5679def : MnemonicAlias<"uhaddsubx", "uhasx">; 5680// UHSAX == UHSUBADDX 5681def : MnemonicAlias<"uhsubaddx", "uhsax">; 5682// UQASX == UQADDSUBX 5683def : MnemonicAlias<"uqaddsubx", "uqasx">; 5684// UQSAX == UQSUBADDX 5685def : MnemonicAlias<"uqsubaddx", "uqsax">; 5686// USAX == USUBADDX 5687def : MnemonicAlias<"usubaddx", "usax">; 5688 5689// "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like 5690// for isel. 5691def : ARMInstAlias<"mov${s}${p} $Rd, $imm", 5692 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 5693def : ARMInstAlias<"mvn${s}${p} $Rd, $imm", 5694 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 5695// Same for AND <--> BIC 5696def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm", 5697 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 5698 pred:$p, cc_out:$s)>; 5699def : ARMInstAlias<"bic${s}${p} $Rdn, $imm", 5700 (ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 5701 pred:$p, cc_out:$s)>; 5702def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm", 5703 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 5704 pred:$p, cc_out:$s)>; 5705def : ARMInstAlias<"and${s}${p} $Rdn, $imm", 5706 (BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 5707 pred:$p, cc_out:$s)>; 5708 5709// Likewise, "add Rd, mod_imm_neg" -> sub 5710def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm", 5711 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 5712def : ARMInstAlias<"add${s}${p} $Rd, $imm", 5713 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 5714// Same for CMP <--> CMN via mod_imm_neg 5715def : ARMInstAlias<"cmp${p} $Rd, $imm", 5716 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 5717def : ARMInstAlias<"cmn${p} $Rd, $imm", 5718 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 5719 5720// The shifter forms of the MOV instruction are aliased to the ASR, LSL, 5721// LSR, ROR, and RRX instructions. 5722// FIXME: We need C++ parser hooks to map the alias to the MOV 5723// encoding. It seems we should be able to do that sort of thing 5724// in tblgen, but it could get ugly. 5725let TwoOperandAliasConstraint = "$Rm = $Rd" in { 5726def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm", 5727 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 5728 cc_out:$s)>; 5729def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm", 5730 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 5731 cc_out:$s)>; 5732def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm", 5733 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 5734 cc_out:$s)>; 5735def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm", 5736 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 5737 cc_out:$s)>; 5738} 5739def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm", 5740 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>; 5741let TwoOperandAliasConstraint = "$Rn = $Rd" in { 5742def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm", 5743 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5744 cc_out:$s)>; 5745def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm", 5746 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5747 cc_out:$s)>; 5748def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm", 5749 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5750 cc_out:$s)>; 5751def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm", 5752 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5753 cc_out:$s)>; 5754} 5755 5756// "neg" is and alias for "rsb rd, rn, #0" 5757def : ARMInstAlias<"neg${s}${p} $Rd, $Rm", 5758 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>; 5759 5760// Pre-v6, 'mov r0, r0' was used as a NOP encoding. 5761def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>, 5762 Requires<[IsARM, NoV6]>; 5763 5764// MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but 5765// the instruction definitions need difference constraints pre-v6. 5766// Use these aliases for the assembly parsing on pre-v6. 5767def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm", 5768 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 5769 Requires<[IsARM, NoV6]>; 5770def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra", 5771 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 5772 pred:$p, cc_out:$s)>, 5773 Requires<[IsARM, NoV6]>; 5774def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5775 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5776 Requires<[IsARM, NoV6]>; 5777def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5778 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5779 Requires<[IsARM, NoV6]>; 5780def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5781 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5782 Requires<[IsARM, NoV6]>; 5783def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5784 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5785 Requires<[IsARM, NoV6]>; 5786 5787// 'it' blocks in ARM mode just validate the predicates. The IT itself 5788// is discarded. 5789def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>, 5790 ComplexDeprecationPredicate<"IT">; 5791 5792let mayLoad = 1, mayStore =1, hasSideEffects = 1 in 5793def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn), 5794 NoItinerary, 5795 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>; 5796