1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// ARM specific DAG Nodes. 16// 17 18// Type profiles. 19def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 20 SDTCisVT<1, i32> ]>; 21def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 22def SDT_ARMStructByVal : SDTypeProfile<0, 4, 23 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 24 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 25 26def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 27 28def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 29 30def SDT_ARMCMov : SDTypeProfile<1, 3, 31 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 32 SDTCisVT<3, i32>]>; 33 34def SDT_ARMBrcond : SDTypeProfile<0, 2, 35 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 36 37def SDT_ARMBrJT : SDTypeProfile<0, 2, 38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 39 40def SDT_ARMBr2JT : SDTypeProfile<0, 3, 41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 42 SDTCisVT<2, i32>]>; 43 44def SDT_ARMBCC_i64 : SDTypeProfile<0, 6, 45 [SDTCisVT<0, i32>, 46 SDTCisVT<1, i32>, SDTCisVT<2, i32>, 47 SDTCisVT<3, i32>, SDTCisVT<4, i32>, 48 SDTCisVT<5, OtherVT>]>; 49 50def SDT_ARMAnd : SDTypeProfile<1, 2, 51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 52 SDTCisVT<2, i32>]>; 53 54def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 55def SDT_ARMFCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, 56 SDTCisVT<2, i32>]>; 57 58def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 59 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 60 61def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 62def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, 63 SDTCisInt<2>]>; 64def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 65def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>; 66 67def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 68 69def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, 70 SDTCisInt<1>]>; 71 72def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 73 74def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 75 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 76 77def SDT_WIN__DBZCHK : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 78 79def SDT_ARMMEMCPY : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 80 SDTCisVT<2, i32>, SDTCisVT<3, i32>, 81 SDTCisVT<4, i32>]>; 82 83def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 84 [SDTCisSameAs<0, 2>, 85 SDTCisSameAs<0, 3>, 86 SDTCisInt<0>, SDTCisVT<1, i32>]>; 87 88// SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR 89def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 90 [SDTCisSameAs<0, 2>, 91 SDTCisSameAs<0, 3>, 92 SDTCisInt<0>, 93 SDTCisVT<1, i32>, 94 SDTCisVT<4, i32>]>; 95 96def SDT_LongMac : SDTypeProfile<2, 4, [SDTCisVT<0, i32>, 97 SDTCisSameAs<0, 1>, 98 SDTCisSameAs<0, 2>, 99 SDTCisSameAs<0, 3>, 100 SDTCisSameAs<0, 4>, 101 SDTCisSameAs<0, 5>]>; 102 103def ARMSmlald : SDNode<"ARMISD::SMLALD", SDT_LongMac>; 104def ARMSmlaldx : SDNode<"ARMISD::SMLALDX", SDT_LongMac>; 105def ARMSmlsld : SDNode<"ARMISD::SMLSLD", SDT_LongMac>; 106def ARMSmlsldx : SDNode<"ARMISD::SMLSLDX", SDT_LongMac>; 107 108// Node definitions. 109def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 110def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>; 111def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>; 112 113def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 114 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 115def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 116 [SDNPHasChain, SDNPSideEffect, 117 SDNPOptInGlue, SDNPOutGlue]>; 118def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" , 119 SDT_ARMStructByVal, 120 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 121 SDNPMayStore, SDNPMayLoad]>; 122 123def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 124 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 125 SDNPVariadic]>; 126def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 127 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 128 SDNPVariadic]>; 129def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 130 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 131 SDNPVariadic]>; 132 133def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, 134 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 135def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall, 136 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 137def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 138 [SDNPInGlue]>; 139 140def ARMssatnoshift : SDNode<"ARMISD::SSAT", SDTIntSatNoShOp, []>; 141 142def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 143 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 144 145def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 146 [SDNPHasChain]>; 147def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, 148 [SDNPHasChain]>; 149 150def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64, 151 [SDNPHasChain]>; 152 153def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 154 [SDNPOutGlue]>; 155 156def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp, 157 [SDNPOutGlue]>; 158 159def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, 160 [SDNPOutGlue, SDNPCommutative]>; 161 162def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 163 164def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 165def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 166def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>; 167 168def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags, 169 [SDNPCommutative]>; 170def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>; 171def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>; 172def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>; 173 174def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 175def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", 176 SDT_ARMEH_SJLJ_Setjmp, 177 [SDNPHasChain, SDNPSideEffect]>; 178def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP", 179 SDT_ARMEH_SJLJ_Longjmp, 180 [SDNPHasChain, SDNPSideEffect]>; 181def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH", 182 SDT_ARMEH_SJLJ_SetupDispatch, 183 [SDNPHasChain, SDNPSideEffect]>; 184 185def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER, 186 [SDNPHasChain, SDNPSideEffect]>; 187def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH, 188 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 189 190def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET, 191 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 192 193def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; 194 195def ARMmemcopy : SDNode<"ARMISD::MEMCPY", SDT_ARMMEMCPY, 196 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 197 SDNPMayStore, SDNPMayLoad]>; 198 199def ARMsmulwb : SDNode<"ARMISD::SMULWB", SDTIntBinOp, []>; 200def ARMsmulwt : SDNode<"ARMISD::SMULWT", SDTIntBinOp, []>; 201def ARMsmlalbb : SDNode<"ARMISD::SMLALBB", SDT_LongMac, []>; 202def ARMsmlalbt : SDNode<"ARMISD::SMLALBT", SDT_LongMac, []>; 203def ARMsmlaltb : SDNode<"ARMISD::SMLALTB", SDT_LongMac, []>; 204def ARMsmlaltt : SDNode<"ARMISD::SMLALTT", SDT_LongMac, []>; 205 206//===----------------------------------------------------------------------===// 207// ARM Instruction Predicate Definitions. 208// 209def HasV4T : Predicate<"Subtarget->hasV4TOps()">, 210 AssemblerPredicate<"HasV4TOps", "armv4t">; 211def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; 212def HasV5T : Predicate<"Subtarget->hasV5TOps()">, 213 AssemblerPredicate<"HasV5TOps", "armv5t">; 214def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, 215 AssemblerPredicate<"HasV5TEOps", "armv5te">; 216def HasV6 : Predicate<"Subtarget->hasV6Ops()">, 217 AssemblerPredicate<"HasV6Ops", "armv6">; 218def NoV6 : Predicate<"!Subtarget->hasV6Ops()">; 219def HasV6M : Predicate<"Subtarget->hasV6MOps()">, 220 AssemblerPredicate<"HasV6MOps", 221 "armv6m or armv6t2">; 222def HasV8MBaseline : Predicate<"Subtarget->hasV8MBaselineOps()">, 223 AssemblerPredicate<"HasV8MBaselineOps", 224 "armv8m.base">; 225def HasV8MMainline : Predicate<"Subtarget->hasV8MMainlineOps()">, 226 AssemblerPredicate<"HasV8MMainlineOps", 227 "armv8m.main">; 228def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, 229 AssemblerPredicate<"HasV6T2Ops", "armv6t2">; 230def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; 231def HasV6K : Predicate<"Subtarget->hasV6KOps()">, 232 AssemblerPredicate<"HasV6KOps", "armv6k">; 233def NoV6K : Predicate<"!Subtarget->hasV6KOps()">; 234def HasV7 : Predicate<"Subtarget->hasV7Ops()">, 235 AssemblerPredicate<"HasV7Ops", "armv7">; 236def HasV8 : Predicate<"Subtarget->hasV8Ops()">, 237 AssemblerPredicate<"HasV8Ops", "armv8">; 238def PreV8 : Predicate<"!Subtarget->hasV8Ops()">, 239 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">; 240def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">, 241 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">; 242def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">, 243 AssemblerPredicate<"HasV8_2aOps", "armv8.2a">; 244def HasV8_3a : Predicate<"Subtarget->hasV8_3aOps()">, 245 AssemblerPredicate<"HasV8_3aOps", "armv8.3a">; 246def NoVFP : Predicate<"!Subtarget->hasVFP2()">; 247def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, 248 AssemblerPredicate<"FeatureVFP2", "VFP2">; 249def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, 250 AssemblerPredicate<"FeatureVFP3", "VFP3">; 251def HasVFP4 : Predicate<"Subtarget->hasVFP4()">, 252 AssemblerPredicate<"FeatureVFP4", "VFP4">; 253def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">, 254 AssemblerPredicate<"!FeatureVFPOnlySP", 255 "double precision VFP">; 256def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, 257 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">; 258def HasNEON : Predicate<"Subtarget->hasNEON()">, 259 AssemblerPredicate<"FeatureNEON", "NEON">; 260def HasCrypto : Predicate<"Subtarget->hasCrypto()">, 261 AssemblerPredicate<"FeatureCrypto", "crypto">; 262def HasDotProd : Predicate<"Subtarget->hasDotProd()">, 263 AssemblerPredicate<"FeatureDotProd", "dotprod">; 264def HasCRC : Predicate<"Subtarget->hasCRC()">, 265 AssemblerPredicate<"FeatureCRC", "crc">; 266def HasRAS : Predicate<"Subtarget->hasRAS()">, 267 AssemblerPredicate<"FeatureRAS", "ras">; 268def HasFP16 : Predicate<"Subtarget->hasFP16()">, 269 AssemblerPredicate<"FeatureFP16","half-float conversions">; 270def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">, 271 AssemblerPredicate<"FeatureFullFP16","full half-float">; 272def HasDivideInThumb : Predicate<"Subtarget->hasDivideInThumbMode()">, 273 AssemblerPredicate<"FeatureHWDivThumb", "divide in THUMB">; 274def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">, 275 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">; 276def HasDSP : Predicate<"Subtarget->hasDSP()">, 277 AssemblerPredicate<"FeatureDSP", "dsp">; 278def HasDB : Predicate<"Subtarget->hasDataBarrier()">, 279 AssemblerPredicate<"FeatureDB", 280 "data-barriers">; 281def HasV7Clrex : Predicate<"Subtarget->hasV7Clrex()">, 282 AssemblerPredicate<"FeatureV7Clrex", 283 "v7 clrex">; 284def HasAcquireRelease : Predicate<"Subtarget->hasAcquireRelease()">, 285 AssemblerPredicate<"FeatureAcquireRelease", 286 "acquire/release">; 287def HasMP : Predicate<"Subtarget->hasMPExtension()">, 288 AssemblerPredicate<"FeatureMP", 289 "mp-extensions">; 290def HasVirtualization: Predicate<"false">, 291 AssemblerPredicate<"FeatureVirtualization", 292 "virtualization-extensions">; 293def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">, 294 AssemblerPredicate<"FeatureTrustZone", 295 "TrustZone">; 296def Has8MSecExt : Predicate<"Subtarget->has8MSecExt()">, 297 AssemblerPredicate<"Feature8MSecExt", 298 "ARMv8-M Security Extensions">; 299def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">; 300def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; 301def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; 302def IsThumb : Predicate<"Subtarget->isThumb()">, 303 AssemblerPredicate<"ModeThumb", "thumb">; 304def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; 305def IsThumb2 : Predicate<"Subtarget->isThumb2()">, 306 AssemblerPredicate<"ModeThumb,FeatureThumb2", 307 "thumb2">; 308def IsMClass : Predicate<"Subtarget->isMClass()">, 309 AssemblerPredicate<"FeatureMClass", "armv*m">; 310def IsNotMClass : Predicate<"!Subtarget->isMClass()">, 311 AssemblerPredicate<"!FeatureMClass", 312 "!armv*m">; 313def IsARM : Predicate<"!Subtarget->isThumb()">, 314 AssemblerPredicate<"!ModeThumb", "arm-mode">; 315def IsMachO : Predicate<"Subtarget->isTargetMachO()">; 316def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">; 317def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 318def IsWindows : Predicate<"Subtarget->isTargetWindows()">; 319def IsNotWindows : Predicate<"!Subtarget->isTargetWindows()">; 320def IsReadTPHard : Predicate<"Subtarget->isReadTPHard()">; 321def IsReadTPSoft : Predicate<"!Subtarget->isReadTPHard()">; 322def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">, 323 AssemblerPredicate<"FeatureNaClTrap", "NaCl">; 324def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">; 325 326def UseNegativeImmediates : 327 Predicate<"false">, 328 AssemblerPredicate<"!FeatureNoNegativeImmediates", 329 "NegativeImmediates">; 330 331// FIXME: Eventually this will be just "hasV6T2Ops". 332let RecomputePerFunction = 1 in { 333 def UseMovt : Predicate<"Subtarget->useMovt(*MF)">; 334 def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">; 335 def UseMovtInPic : Predicate<"Subtarget->useMovt(*MF) && Subtarget->allowPositionIndependentMovt()">; 336 def DontUseMovtInPic : Predicate<"!Subtarget->useMovt(*MF) || !Subtarget->allowPositionIndependentMovt()">; 337} 338def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">; 339def UseMulOps : Predicate<"Subtarget->useMulOps()">; 340 341// Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available. 342// But only select them if more precision in FP computation is allowed. 343// Do not use them for Darwin platforms. 344def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion ==" 345 " FPOpFusion::Fast && " 346 " Subtarget->hasVFP4()) && " 347 "!Subtarget->isTargetDarwin()">; 348def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion ==" 349 " FPOpFusion::Fast &&" 350 " Subtarget->hasVFP4()) || " 351 "Subtarget->isTargetDarwin()">; 352 353def HasFastVGETLNi32 : Predicate<"!Subtarget->hasSlowVGETLNi32()">; 354def HasSlowVGETLNi32 : Predicate<"Subtarget->hasSlowVGETLNi32()">; 355 356def HasFastVDUP32 : Predicate<"!Subtarget->hasSlowVDUP32()">; 357def HasSlowVDUP32 : Predicate<"Subtarget->hasSlowVDUP32()">; 358 359def UseVMOVSR : Predicate<"Subtarget->preferVMOVSR() ||" 360 "!Subtarget->useNEONForSinglePrecisionFP()">; 361def DontUseVMOVSR : Predicate<"!Subtarget->preferVMOVSR() &&" 362 "Subtarget->useNEONForSinglePrecisionFP()">; 363 364let RecomputePerFunction = 1 in { 365 def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">; 366 def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">; 367} 368 369def GenExecuteOnly : Predicate<"Subtarget->genExecuteOnly()">; 370 371//===----------------------------------------------------------------------===// 372// ARM Flag Definitions. 373 374class RegConstraint<string C> { 375 string Constraints = C; 376} 377 378//===----------------------------------------------------------------------===// 379// ARM specific transformation functions and pattern fragments. 380// 381 382// imm_neg_XFORM - Return the negation of an i32 immediate value. 383def imm_neg_XFORM : SDNodeXForm<imm, [{ 384 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32); 385}]>; 386 387// imm_not_XFORM - Return the complement of a i32 immediate value. 388def imm_not_XFORM : SDNodeXForm<imm, [{ 389 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32); 390}]>; 391 392/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 393def imm16_31 : ImmLeaf<i32, [{ 394 return (int32_t)Imm >= 16 && (int32_t)Imm < 32; 395}]>; 396 397// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 398def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 399 if (CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17) 400 return true; 401 402 if (N->getOpcode() != ISD::SRA) 403 return false; 404 if (N->getOperand(0).getOpcode() != ISD::SHL) 405 return false; 406 407 auto *ShiftVal = dyn_cast<ConstantSDNode>(N->getOperand(1)); 408 if (!ShiftVal || ShiftVal->getZExtValue() != 16) 409 return false; 410 411 ShiftVal = dyn_cast<ConstantSDNode>(N->getOperand(0)->getOperand(1)); 412 if (!ShiftVal || ShiftVal->getZExtValue() != 16) 413 return false; 414 415 return true; 416}]>; 417 418/// Split a 32-bit immediate into two 16 bit parts. 419def hi16 : SDNodeXForm<imm, [{ 420 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N), 421 MVT::i32); 422}]>; 423 424def lo16AllZero : PatLeaf<(i32 imm), [{ 425 // Returns true if all low 16-bits are 0. 426 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 427}], hi16>; 428 429class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 430class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 431 432// An 'and' node with a single use. 433def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 434 return N->hasOneUse(); 435}]>; 436 437// An 'xor' node with a single use. 438def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{ 439 return N->hasOneUse(); 440}]>; 441 442// An 'fmul' node with a single use. 443def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{ 444 return N->hasOneUse(); 445}]>; 446 447// An 'fadd' node which checks for single non-hazardous use. 448def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{ 449 return hasNoVMLxHazardUse(N); 450}]>; 451 452// An 'fsub' node which checks for single non-hazardous use. 453def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{ 454 return hasNoVMLxHazardUse(N); 455}]>; 456 457//===----------------------------------------------------------------------===// 458// Operand Definitions. 459// 460 461// Immediate operands with a shared generic asm render method. 462class ImmAsmOperand<int Low, int High> : AsmOperandClass { 463 let RenderMethod = "addImmOperands"; 464 let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; 465 let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]"; 466} 467 468class ImmAsmOperandMinusOne<int Low, int High> : AsmOperandClass { 469 let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; 470 let DiagnosticType = "ImmRange" # Low # "_" # High; 471 let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]"; 472} 473 474// Operands that are part of a memory addressing mode. 475class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; } 476 477// Branch target. 478// FIXME: rename brtarget to t2_brtarget 479def brtarget : Operand<OtherVT> { 480 let EncoderMethod = "getBranchTargetOpValue"; 481 let OperandType = "OPERAND_PCREL"; 482 let DecoderMethod = "DecodeT2BROperand"; 483} 484 485// Branches targeting ARM-mode must be divisible by 4 if they're a raw 486// immediate. 487def ARMBranchTarget : AsmOperandClass { 488 let Name = "ARMBranchTarget"; 489} 490 491// Branches targeting Thumb-mode must be divisible by 2 if they're a raw 492// immediate. 493def ThumbBranchTarget : AsmOperandClass { 494 let Name = "ThumbBranchTarget"; 495} 496 497def arm_br_target : Operand<OtherVT> { 498 let ParserMatchClass = ARMBranchTarget; 499 let EncoderMethod = "getARMBranchTargetOpValue"; 500 let OperandType = "OPERAND_PCREL"; 501} 502 503// Call target for ARM. Handles conditional/unconditional 504// FIXME: rename bl_target to t2_bltarget? 505def arm_bl_target : Operand<i32> { 506 let ParserMatchClass = ARMBranchTarget; 507 let EncoderMethod = "getARMBLTargetOpValue"; 508 let OperandType = "OPERAND_PCREL"; 509} 510 511// Target for BLX *from* ARM mode. 512def arm_blx_target : Operand<i32> { 513 let ParserMatchClass = ThumbBranchTarget; 514 let EncoderMethod = "getARMBLXTargetOpValue"; 515 let OperandType = "OPERAND_PCREL"; 516} 517 518// A list of registers separated by comma. Used by load/store multiple. 519def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; } 520def reglist : Operand<i32> { 521 let EncoderMethod = "getRegisterListOpValue"; 522 let ParserMatchClass = RegListAsmOperand; 523 let PrintMethod = "printRegisterList"; 524 let DecoderMethod = "DecodeRegListOperand"; 525} 526 527def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">; 528 529def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; } 530def dpr_reglist : Operand<i32> { 531 let EncoderMethod = "getRegisterListOpValue"; 532 let ParserMatchClass = DPRRegListAsmOperand; 533 let PrintMethod = "printRegisterList"; 534 let DecoderMethod = "DecodeDPRRegListOperand"; 535} 536 537def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; } 538def spr_reglist : Operand<i32> { 539 let EncoderMethod = "getRegisterListOpValue"; 540 let ParserMatchClass = SPRRegListAsmOperand; 541 let PrintMethod = "printRegisterList"; 542 let DecoderMethod = "DecodeSPRRegListOperand"; 543} 544 545// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 546def cpinst_operand : Operand<i32> { 547 let PrintMethod = "printCPInstOperand"; 548} 549 550// Local PC labels. 551def pclabel : Operand<i32> { 552 let PrintMethod = "printPCLabel"; 553} 554 555// ADR instruction labels. 556def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; } 557def adrlabel : Operand<i32> { 558 let EncoderMethod = "getAdrLabelOpValue"; 559 let ParserMatchClass = AdrLabelAsmOperand; 560 let PrintMethod = "printAdrLabelOperand<0>"; 561} 562 563def neon_vcvt_imm32 : Operand<i32> { 564 let EncoderMethod = "getNEONVcvtImm32OpValue"; 565 let DecoderMethod = "DecodeVCVTImmOperand"; 566} 567 568// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. 569def rot_imm_XFORM: SDNodeXForm<imm, [{ 570 switch (N->getZExtValue()){ 571 default: llvm_unreachable(nullptr); 572 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); 573 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32); 574 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32); 575 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32); 576 } 577}]>; 578def RotImmAsmOperand : AsmOperandClass { 579 let Name = "RotImm"; 580 let ParserMethod = "parseRotImm"; 581} 582def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{ 583 int32_t v = N->getZExtValue(); 584 return v == 8 || v == 16 || v == 24; }], 585 rot_imm_XFORM> { 586 let PrintMethod = "printRotImmOperand"; 587 let ParserMatchClass = RotImmAsmOperand; 588} 589 590// shift_imm: An integer that encodes a shift amount and the type of shift 591// (asr or lsl). The 6-bit immediate encodes as: 592// {5} 0 ==> lsl 593// 1 asr 594// {4-0} imm5 shift amount. 595// asr #32 encoded as imm5 == 0. 596def ShifterImmAsmOperand : AsmOperandClass { 597 let Name = "ShifterImm"; 598 let ParserMethod = "parseShifterImm"; 599} 600def shift_imm : Operand<i32> { 601 let PrintMethod = "printShiftImmOperand"; 602 let ParserMatchClass = ShifterImmAsmOperand; 603} 604 605// shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm. 606def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; } 607def so_reg_reg : Operand<i32>, // reg reg imm 608 ComplexPattern<i32, 3, "SelectRegShifterOperand", 609 [shl, srl, sra, rotr]> { 610 let EncoderMethod = "getSORegRegOpValue"; 611 let PrintMethod = "printSORegRegOperand"; 612 let DecoderMethod = "DecodeSORegRegOperand"; 613 let ParserMatchClass = ShiftedRegAsmOperand; 614 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm); 615} 616 617def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; } 618def so_reg_imm : Operand<i32>, // reg imm 619 ComplexPattern<i32, 2, "SelectImmShifterOperand", 620 [shl, srl, sra, rotr]> { 621 let EncoderMethod = "getSORegImmOpValue"; 622 let PrintMethod = "printSORegImmOperand"; 623 let DecoderMethod = "DecodeSORegImmOperand"; 624 let ParserMatchClass = ShiftedImmAsmOperand; 625 let MIOperandInfo = (ops GPR, i32imm); 626} 627 628// FIXME: Does this need to be distinct from so_reg? 629def shift_so_reg_reg : Operand<i32>, // reg reg imm 630 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand", 631 [shl,srl,sra,rotr]> { 632 let EncoderMethod = "getSORegRegOpValue"; 633 let PrintMethod = "printSORegRegOperand"; 634 let DecoderMethod = "DecodeSORegRegOperand"; 635 let ParserMatchClass = ShiftedRegAsmOperand; 636 let MIOperandInfo = (ops GPR, GPR, i32imm); 637} 638 639// FIXME: Does this need to be distinct from so_reg? 640def shift_so_reg_imm : Operand<i32>, // reg reg imm 641 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand", 642 [shl,srl,sra,rotr]> { 643 let EncoderMethod = "getSORegImmOpValue"; 644 let PrintMethod = "printSORegImmOperand"; 645 let DecoderMethod = "DecodeSORegImmOperand"; 646 let ParserMatchClass = ShiftedImmAsmOperand; 647 let MIOperandInfo = (ops GPR, i32imm); 648} 649 650// mod_imm: match a 32-bit immediate operand, which can be encoded into 651// a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM 652// - "Modified Immediate Constants"). Within the MC layer we keep this 653// immediate in its encoded form. 654def ModImmAsmOperand: AsmOperandClass { 655 let Name = "ModImm"; 656 let ParserMethod = "parseModImm"; 657} 658def mod_imm : Operand<i32>, ImmLeaf<i32, [{ 659 return ARM_AM::getSOImmVal(Imm) != -1; 660 }]> { 661 let EncoderMethod = "getModImmOpValue"; 662 let PrintMethod = "printModImmOperand"; 663 let ParserMatchClass = ModImmAsmOperand; 664} 665 666// Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder 667// method and such, as they are only used on aliases (Pat<> and InstAlias<>). 668// The actual parsing, encoding, decoding are handled by the destination 669// instructions, which use mod_imm. 670 671def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; } 672def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{ 673 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1; 674 }], imm_not_XFORM> { 675 let ParserMatchClass = ModImmNotAsmOperand; 676} 677 678def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; } 679def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{ 680 unsigned Value = -(unsigned)N->getZExtValue(); 681 return Value && ARM_AM::getSOImmVal(Value) != -1; 682 }], imm_neg_XFORM> { 683 let ParserMatchClass = ModImmNegAsmOperand; 684} 685 686/// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal() 687def arm_i32imm : PatLeaf<(imm), [{ 688 if (Subtarget->useMovt(*MF)) 689 return true; 690 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 691}]>; 692 693/// imm0_1 predicate - Immediate in the range [0,1]. 694def Imm0_1AsmOperand: ImmAsmOperand<0,1> { let Name = "Imm0_1"; } 695def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; } 696 697/// imm0_3 predicate - Immediate in the range [0,3]. 698def Imm0_3AsmOperand: ImmAsmOperand<0,3> { let Name = "Imm0_3"; } 699def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; } 700 701/// imm0_7 predicate - Immediate in the range [0,7]. 702def Imm0_7AsmOperand: ImmAsmOperand<0,7> { 703 let Name = "Imm0_7"; 704} 705def imm0_7 : Operand<i32>, ImmLeaf<i32, [{ 706 return Imm >= 0 && Imm < 8; 707}]> { 708 let ParserMatchClass = Imm0_7AsmOperand; 709} 710 711/// imm8_255 predicate - Immediate in the range [8,255]. 712def Imm8_255AsmOperand: ImmAsmOperand<8,255> { let Name = "Imm8_255"; } 713def imm8_255 : Operand<i32>, ImmLeaf<i32, [{ 714 return Imm >= 8 && Imm < 256; 715}]> { 716 let ParserMatchClass = Imm8_255AsmOperand; 717} 718 719/// imm8 predicate - Immediate is exactly 8. 720def Imm8AsmOperand: ImmAsmOperand<8,8> { let Name = "Imm8"; } 721def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> { 722 let ParserMatchClass = Imm8AsmOperand; 723} 724 725/// imm16 predicate - Immediate is exactly 16. 726def Imm16AsmOperand: ImmAsmOperand<16,16> { let Name = "Imm16"; } 727def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> { 728 let ParserMatchClass = Imm16AsmOperand; 729} 730 731/// imm32 predicate - Immediate is exactly 32. 732def Imm32AsmOperand: ImmAsmOperand<32,32> { let Name = "Imm32"; } 733def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> { 734 let ParserMatchClass = Imm32AsmOperand; 735} 736 737def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>; 738 739/// imm1_7 predicate - Immediate in the range [1,7]. 740def Imm1_7AsmOperand: ImmAsmOperand<1,7> { let Name = "Imm1_7"; } 741def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> { 742 let ParserMatchClass = Imm1_7AsmOperand; 743} 744 745/// imm1_15 predicate - Immediate in the range [1,15]. 746def Imm1_15AsmOperand: ImmAsmOperand<1,15> { let Name = "Imm1_15"; } 747def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> { 748 let ParserMatchClass = Imm1_15AsmOperand; 749} 750 751/// imm1_31 predicate - Immediate in the range [1,31]. 752def Imm1_31AsmOperand: ImmAsmOperand<1,31> { let Name = "Imm1_31"; } 753def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> { 754 let ParserMatchClass = Imm1_31AsmOperand; 755} 756 757/// imm0_15 predicate - Immediate in the range [0,15]. 758def Imm0_15AsmOperand: ImmAsmOperand<0,15> { 759 let Name = "Imm0_15"; 760} 761def imm0_15 : Operand<i32>, ImmLeaf<i32, [{ 762 return Imm >= 0 && Imm < 16; 763}]> { 764 let ParserMatchClass = Imm0_15AsmOperand; 765} 766 767/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31]. 768def Imm0_31AsmOperand: ImmAsmOperand<0,31> { let Name = "Imm0_31"; } 769def imm0_31 : Operand<i32>, ImmLeaf<i32, [{ 770 return Imm >= 0 && Imm < 32; 771}]> { 772 let ParserMatchClass = Imm0_31AsmOperand; 773} 774 775/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32]. 776def Imm0_32AsmOperand: ImmAsmOperand<0,32> { let Name = "Imm0_32"; } 777def imm0_32 : Operand<i32>, ImmLeaf<i32, [{ 778 return Imm >= 0 && Imm < 33; 779}]> { 780 let ParserMatchClass = Imm0_32AsmOperand; 781} 782 783/// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63]. 784def Imm0_63AsmOperand: ImmAsmOperand<0,63> { let Name = "Imm0_63"; } 785def imm0_63 : Operand<i32>, ImmLeaf<i32, [{ 786 return Imm >= 0 && Imm < 64; 787}]> { 788 let ParserMatchClass = Imm0_63AsmOperand; 789} 790 791/// imm0_239 predicate - Immediate in the range [0,239]. 792def Imm0_239AsmOperand : ImmAsmOperand<0,239> { 793 let Name = "Imm0_239"; 794} 795def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> { 796 let ParserMatchClass = Imm0_239AsmOperand; 797} 798 799/// imm0_255 predicate - Immediate in the range [0,255]. 800def Imm0_255AsmOperand : ImmAsmOperand<0,255> { let Name = "Imm0_255"; } 801def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> { 802 let ParserMatchClass = Imm0_255AsmOperand; 803} 804 805/// imm0_65535 - An immediate is in the range [0,65535]. 806def Imm0_65535AsmOperand: ImmAsmOperand<0,65535> { let Name = "Imm0_65535"; } 807def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{ 808 return Imm >= 0 && Imm < 65536; 809}]> { 810 let ParserMatchClass = Imm0_65535AsmOperand; 811} 812 813// imm0_65535_neg - An immediate whose negative value is in the range [0.65535]. 814def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{ 815 return -Imm >= 0 && -Imm < 65536; 816}]>; 817 818// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference 819// a relocatable expression. 820// 821// FIXME: This really needs a Thumb version separate from the ARM version. 822// While the range is the same, and can thus use the same match class, 823// the encoding is different so it should have a different encoder method. 824def Imm0_65535ExprAsmOperand: AsmOperandClass { 825 let Name = "Imm0_65535Expr"; 826 let RenderMethod = "addImmOperands"; 827 let DiagnosticString = "operand must be an immediate in the range [0,0xffff] or a relocatable expression"; 828} 829 830def imm0_65535_expr : Operand<i32> { 831 let EncoderMethod = "getHiLo16ImmOpValue"; 832 let ParserMatchClass = Imm0_65535ExprAsmOperand; 833} 834 835def Imm256_65535ExprAsmOperand: ImmAsmOperand<256,65535> { let Name = "Imm256_65535Expr"; } 836def imm256_65535_expr : Operand<i32> { 837 let ParserMatchClass = Imm256_65535ExprAsmOperand; 838} 839 840/// imm24b - True if the 32-bit immediate is encodable in 24 bits. 841def Imm24bitAsmOperand: ImmAsmOperand<0,0xffffff> { 842 let Name = "Imm24bit"; 843 let DiagnosticString = "operand must be an immediate in the range [0,0xffffff]"; 844} 845def imm24b : Operand<i32>, ImmLeaf<i32, [{ 846 return Imm >= 0 && Imm <= 0xffffff; 847}]> { 848 let ParserMatchClass = Imm24bitAsmOperand; 849} 850 851 852/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield 853/// e.g., 0xf000ffff 854def BitfieldAsmOperand : AsmOperandClass { 855 let Name = "Bitfield"; 856 let ParserMethod = "parseBitfield"; 857} 858 859def bf_inv_mask_imm : Operand<i32>, 860 PatLeaf<(imm), [{ 861 return ARM::isBitFieldInvertedMask(N->getZExtValue()); 862}] > { 863 let EncoderMethod = "getBitfieldInvertedMaskOpValue"; 864 let PrintMethod = "printBitfieldInvMaskImmOperand"; 865 let DecoderMethod = "DecodeBitfieldMaskOperand"; 866 let ParserMatchClass = BitfieldAsmOperand; 867} 868 869def imm1_32_XFORM: SDNodeXForm<imm, [{ 870 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 871 MVT::i32); 872}]>; 873def Imm1_32AsmOperand: ImmAsmOperandMinusOne<1,32> { 874 let Name = "Imm1_32"; 875} 876def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ 877 uint64_t Imm = N->getZExtValue(); 878 return Imm > 0 && Imm <= 32; 879 }], 880 imm1_32_XFORM> { 881 let PrintMethod = "printImmPlusOneOperand"; 882 let ParserMatchClass = Imm1_32AsmOperand; 883} 884 885def imm1_16_XFORM: SDNodeXForm<imm, [{ 886 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 887 MVT::i32); 888}]>; 889def Imm1_16AsmOperand: ImmAsmOperandMinusOne<1,16> { let Name = "Imm1_16"; } 890def imm1_16 : Operand<i32>, ImmLeaf<i32, [{ 891 return Imm > 0 && Imm <= 16; 892 }], 893 imm1_16_XFORM> { 894 let PrintMethod = "printImmPlusOneOperand"; 895 let ParserMatchClass = Imm1_16AsmOperand; 896} 897 898// Define ARM specific addressing modes. 899// addrmode_imm12 := reg +/- imm12 900// 901def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; } 902class AddrMode_Imm12 : MemOperand, 903 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> { 904 // 12-bit immediate operand. Note that instructions using this encode 905 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other 906 // immediate values are as normal. 907 908 let EncoderMethod = "getAddrModeImm12OpValue"; 909 let DecoderMethod = "DecodeAddrModeImm12Operand"; 910 let ParserMatchClass = MemImm12OffsetAsmOperand; 911 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 912} 913 914def addrmode_imm12 : AddrMode_Imm12 { 915 let PrintMethod = "printAddrModeImm12Operand<false>"; 916} 917 918def addrmode_imm12_pre : AddrMode_Imm12 { 919 let PrintMethod = "printAddrModeImm12Operand<true>"; 920} 921 922// ldst_so_reg := reg +/- reg shop imm 923// 924def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; } 925def ldst_so_reg : MemOperand, 926 ComplexPattern<i32, 3, "SelectLdStSOReg", []> { 927 let EncoderMethod = "getLdStSORegOpValue"; 928 // FIXME: Simplify the printer 929 let PrintMethod = "printAddrMode2Operand"; 930 let DecoderMethod = "DecodeSORegMemOperand"; 931 let ParserMatchClass = MemRegOffsetAsmOperand; 932 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift); 933} 934 935// postidx_imm8 := +/- [0,255] 936// 937// 9 bit value: 938// {8} 1 is imm8 is non-negative. 0 otherwise. 939// {7-0} [0,255] imm8 value. 940def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; } 941def postidx_imm8 : MemOperand { 942 let PrintMethod = "printPostIdxImm8Operand"; 943 let ParserMatchClass = PostIdxImm8AsmOperand; 944 let MIOperandInfo = (ops i32imm); 945} 946 947// postidx_imm8s4 := +/- [0,1020] 948// 949// 9 bit value: 950// {8} 1 is imm8 is non-negative. 0 otherwise. 951// {7-0} [0,255] imm8 value, scaled by 4. 952def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; } 953def postidx_imm8s4 : MemOperand { 954 let PrintMethod = "printPostIdxImm8s4Operand"; 955 let ParserMatchClass = PostIdxImm8s4AsmOperand; 956 let MIOperandInfo = (ops i32imm); 957} 958 959 960// postidx_reg := +/- reg 961// 962def PostIdxRegAsmOperand : AsmOperandClass { 963 let Name = "PostIdxReg"; 964 let ParserMethod = "parsePostIdxReg"; 965} 966def postidx_reg : MemOperand { 967 let EncoderMethod = "getPostIdxRegOpValue"; 968 let DecoderMethod = "DecodePostIdxReg"; 969 let PrintMethod = "printPostIdxRegOperand"; 970 let ParserMatchClass = PostIdxRegAsmOperand; 971 let MIOperandInfo = (ops GPRnopc, i32imm); 972} 973 974 975// addrmode2 := reg +/- imm12 976// := reg +/- reg shop imm 977// 978// FIXME: addrmode2 should be refactored the rest of the way to always 979// use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg). 980def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; } 981def addrmode2 : MemOperand, 982 ComplexPattern<i32, 3, "SelectAddrMode2", []> { 983 let EncoderMethod = "getAddrMode2OpValue"; 984 let PrintMethod = "printAddrMode2Operand"; 985 let ParserMatchClass = AddrMode2AsmOperand; 986 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 987} 988 989def PostIdxRegShiftedAsmOperand : AsmOperandClass { 990 let Name = "PostIdxRegShifted"; 991 let ParserMethod = "parsePostIdxReg"; 992} 993def am2offset_reg : MemOperand, 994 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg", 995 [], [SDNPWantRoot]> { 996 let EncoderMethod = "getAddrMode2OffsetOpValue"; 997 let PrintMethod = "printAddrMode2OffsetOperand"; 998 // When using this for assembly, it's always as a post-index offset. 999 let ParserMatchClass = PostIdxRegShiftedAsmOperand; 1000 let MIOperandInfo = (ops GPRnopc, i32imm); 1001} 1002 1003// FIXME: am2offset_imm should only need the immediate, not the GPR. Having 1004// the GPR is purely vestigal at this point. 1005def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; } 1006def am2offset_imm : MemOperand, 1007 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm", 1008 [], [SDNPWantRoot]> { 1009 let EncoderMethod = "getAddrMode2OffsetOpValue"; 1010 let PrintMethod = "printAddrMode2OffsetOperand"; 1011 let ParserMatchClass = AM2OffsetImmAsmOperand; 1012 let MIOperandInfo = (ops GPRnopc, i32imm); 1013} 1014 1015 1016// addrmode3 := reg +/- reg 1017// addrmode3 := reg +/- imm8 1018// 1019// FIXME: split into imm vs. reg versions. 1020def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; } 1021class AddrMode3 : MemOperand, 1022 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 1023 let EncoderMethod = "getAddrMode3OpValue"; 1024 let ParserMatchClass = AddrMode3AsmOperand; 1025 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 1026} 1027 1028def addrmode3 : AddrMode3 1029{ 1030 let PrintMethod = "printAddrMode3Operand<false>"; 1031} 1032 1033def addrmode3_pre : AddrMode3 1034{ 1035 let PrintMethod = "printAddrMode3Operand<true>"; 1036} 1037 1038// FIXME: split into imm vs. reg versions. 1039// FIXME: parser method to handle +/- register. 1040def AM3OffsetAsmOperand : AsmOperandClass { 1041 let Name = "AM3Offset"; 1042 let ParserMethod = "parseAM3Offset"; 1043} 1044def am3offset : MemOperand, 1045 ComplexPattern<i32, 2, "SelectAddrMode3Offset", 1046 [], [SDNPWantRoot]> { 1047 let EncoderMethod = "getAddrMode3OffsetOpValue"; 1048 let PrintMethod = "printAddrMode3OffsetOperand"; 1049 let ParserMatchClass = AM3OffsetAsmOperand; 1050 let MIOperandInfo = (ops GPR, i32imm); 1051} 1052 1053// ldstm_mode := {ia, ib, da, db} 1054// 1055def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> { 1056 let EncoderMethod = "getLdStmModeOpValue"; 1057 let PrintMethod = "printLdStmModeOperand"; 1058} 1059 1060// addrmode5 := reg +/- imm8*4 1061// 1062def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; } 1063class AddrMode5 : MemOperand, 1064 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 1065 let EncoderMethod = "getAddrMode5OpValue"; 1066 let DecoderMethod = "DecodeAddrMode5Operand"; 1067 let ParserMatchClass = AddrMode5AsmOperand; 1068 let MIOperandInfo = (ops GPR:$base, i32imm); 1069} 1070 1071def addrmode5 : AddrMode5 { 1072 let PrintMethod = "printAddrMode5Operand<false>"; 1073} 1074 1075def addrmode5_pre : AddrMode5 { 1076 let PrintMethod = "printAddrMode5Operand<true>"; 1077} 1078 1079// addrmode5fp16 := reg +/- imm8*2 1080// 1081def AddrMode5FP16AsmOperand : AsmOperandClass { let Name = "AddrMode5FP16"; } 1082class AddrMode5FP16 : Operand<i32>, 1083 ComplexPattern<i32, 2, "SelectAddrMode5FP16", []> { 1084 let EncoderMethod = "getAddrMode5FP16OpValue"; 1085 let DecoderMethod = "DecodeAddrMode5FP16Operand"; 1086 let ParserMatchClass = AddrMode5FP16AsmOperand; 1087 let MIOperandInfo = (ops GPR:$base, i32imm); 1088} 1089 1090def addrmode5fp16 : AddrMode5FP16 { 1091 let PrintMethod = "printAddrMode5FP16Operand<false>"; 1092} 1093 1094// addrmode6 := reg with optional alignment 1095// 1096def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; } 1097def addrmode6 : MemOperand, 1098 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1099 let PrintMethod = "printAddrMode6Operand"; 1100 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1101 let EncoderMethod = "getAddrMode6AddressOpValue"; 1102 let DecoderMethod = "DecodeAddrMode6Operand"; 1103 let ParserMatchClass = AddrMode6AsmOperand; 1104} 1105 1106def am6offset : MemOperand, 1107 ComplexPattern<i32, 1, "SelectAddrMode6Offset", 1108 [], [SDNPWantRoot]> { 1109 let PrintMethod = "printAddrMode6OffsetOperand"; 1110 let MIOperandInfo = (ops GPR); 1111 let EncoderMethod = "getAddrMode6OffsetOpValue"; 1112 let DecoderMethod = "DecodeGPRRegisterClass"; 1113} 1114 1115// Special version of addrmode6 to handle alignment encoding for VST1/VLD1 1116// (single element from one lane) for size 32. 1117def addrmode6oneL32 : MemOperand, 1118 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1119 let PrintMethod = "printAddrMode6Operand"; 1120 let MIOperandInfo = (ops GPR:$addr, i32imm); 1121 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue"; 1122} 1123 1124// Base class for addrmode6 with specific alignment restrictions. 1125class AddrMode6Align : MemOperand, 1126 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1127 let PrintMethod = "printAddrMode6Operand"; 1128 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1129 let EncoderMethod = "getAddrMode6AddressOpValue"; 1130 let DecoderMethod = "DecodeAddrMode6Operand"; 1131} 1132 1133// Special version of addrmode6 to handle no allowed alignment encoding for 1134// VLD/VST instructions and checking the alignment is not specified. 1135def AddrMode6AlignNoneAsmOperand : AsmOperandClass { 1136 let Name = "AlignedMemoryNone"; 1137 let DiagnosticString = "alignment must be omitted"; 1138} 1139def addrmode6alignNone : AddrMode6Align { 1140 // The alignment specifier can only be omitted. 1141 let ParserMatchClass = AddrMode6AlignNoneAsmOperand; 1142} 1143 1144// Special version of addrmode6 to handle 16-bit alignment encoding for 1145// VLD/VST instructions and checking the alignment value. 1146def AddrMode6Align16AsmOperand : AsmOperandClass { 1147 let Name = "AlignedMemory16"; 1148 let DiagnosticString = "alignment must be 16 or omitted"; 1149} 1150def addrmode6align16 : AddrMode6Align { 1151 // The alignment specifier can only be 16 or omitted. 1152 let ParserMatchClass = AddrMode6Align16AsmOperand; 1153} 1154 1155// Special version of addrmode6 to handle 32-bit alignment encoding for 1156// VLD/VST instructions and checking the alignment value. 1157def AddrMode6Align32AsmOperand : AsmOperandClass { 1158 let Name = "AlignedMemory32"; 1159 let DiagnosticString = "alignment must be 32 or omitted"; 1160} 1161def addrmode6align32 : AddrMode6Align { 1162 // The alignment specifier can only be 32 or omitted. 1163 let ParserMatchClass = AddrMode6Align32AsmOperand; 1164} 1165 1166// Special version of addrmode6 to handle 64-bit alignment encoding for 1167// VLD/VST instructions and checking the alignment value. 1168def AddrMode6Align64AsmOperand : AsmOperandClass { 1169 let Name = "AlignedMemory64"; 1170 let DiagnosticString = "alignment must be 64 or omitted"; 1171} 1172def addrmode6align64 : AddrMode6Align { 1173 // The alignment specifier can only be 64 or omitted. 1174 let ParserMatchClass = AddrMode6Align64AsmOperand; 1175} 1176 1177// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1178// for VLD/VST instructions and checking the alignment value. 1179def AddrMode6Align64or128AsmOperand : AsmOperandClass { 1180 let Name = "AlignedMemory64or128"; 1181 let DiagnosticString = "alignment must be 64, 128 or omitted"; 1182} 1183def addrmode6align64or128 : AddrMode6Align { 1184 // The alignment specifier can only be 64, 128 or omitted. 1185 let ParserMatchClass = AddrMode6Align64or128AsmOperand; 1186} 1187 1188// Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment 1189// encoding for VLD/VST instructions and checking the alignment value. 1190def AddrMode6Align64or128or256AsmOperand : AsmOperandClass { 1191 let Name = "AlignedMemory64or128or256"; 1192 let DiagnosticString = "alignment must be 64, 128, 256 or omitted"; 1193} 1194def addrmode6align64or128or256 : AddrMode6Align { 1195 // The alignment specifier can only be 64, 128, 256 or omitted. 1196 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand; 1197} 1198 1199// Special version of addrmode6 to handle alignment encoding for VLD-dup 1200// instructions, specifically VLD4-dup. 1201def addrmode6dup : MemOperand, 1202 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1203 let PrintMethod = "printAddrMode6Operand"; 1204 let MIOperandInfo = (ops GPR:$addr, i32imm); 1205 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1206 // FIXME: This is close, but not quite right. The alignment specifier is 1207 // different. 1208 let ParserMatchClass = AddrMode6AsmOperand; 1209} 1210 1211// Base class for addrmode6dup with specific alignment restrictions. 1212class AddrMode6DupAlign : MemOperand, 1213 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1214 let PrintMethod = "printAddrMode6Operand"; 1215 let MIOperandInfo = (ops GPR:$addr, i32imm); 1216 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1217} 1218 1219// Special version of addrmode6 to handle no allowed alignment encoding for 1220// VLD-dup instruction and checking the alignment is not specified. 1221def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass { 1222 let Name = "DupAlignedMemoryNone"; 1223 let DiagnosticString = "alignment must be omitted"; 1224} 1225def addrmode6dupalignNone : AddrMode6DupAlign { 1226 // The alignment specifier can only be omitted. 1227 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand; 1228} 1229 1230// Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup 1231// instruction and checking the alignment value. 1232def AddrMode6dupAlign16AsmOperand : AsmOperandClass { 1233 let Name = "DupAlignedMemory16"; 1234 let DiagnosticString = "alignment must be 16 or omitted"; 1235} 1236def addrmode6dupalign16 : AddrMode6DupAlign { 1237 // The alignment specifier can only be 16 or omitted. 1238 let ParserMatchClass = AddrMode6dupAlign16AsmOperand; 1239} 1240 1241// Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup 1242// instruction and checking the alignment value. 1243def AddrMode6dupAlign32AsmOperand : AsmOperandClass { 1244 let Name = "DupAlignedMemory32"; 1245 let DiagnosticString = "alignment must be 32 or omitted"; 1246} 1247def addrmode6dupalign32 : AddrMode6DupAlign { 1248 // The alignment specifier can only be 32 or omitted. 1249 let ParserMatchClass = AddrMode6dupAlign32AsmOperand; 1250} 1251 1252// Special version of addrmode6 to handle 64-bit alignment encoding for VLD 1253// instructions and checking the alignment value. 1254def AddrMode6dupAlign64AsmOperand : AsmOperandClass { 1255 let Name = "DupAlignedMemory64"; 1256 let DiagnosticString = "alignment must be 64 or omitted"; 1257} 1258def addrmode6dupalign64 : AddrMode6DupAlign { 1259 // The alignment specifier can only be 64 or omitted. 1260 let ParserMatchClass = AddrMode6dupAlign64AsmOperand; 1261} 1262 1263// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1264// for VLD instructions and checking the alignment value. 1265def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass { 1266 let Name = "DupAlignedMemory64or128"; 1267 let DiagnosticString = "alignment must be 64, 128 or omitted"; 1268} 1269def addrmode6dupalign64or128 : AddrMode6DupAlign { 1270 // The alignment specifier can only be 64, 128 or omitted. 1271 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand; 1272} 1273 1274// addrmodepc := pc + reg 1275// 1276def addrmodepc : MemOperand, 1277 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 1278 let PrintMethod = "printAddrModePCOperand"; 1279 let MIOperandInfo = (ops GPR, i32imm); 1280} 1281 1282// addr_offset_none := reg 1283// 1284def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; } 1285def addr_offset_none : MemOperand, 1286 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> { 1287 let PrintMethod = "printAddrMode7Operand"; 1288 let DecoderMethod = "DecodeAddrMode7Operand"; 1289 let ParserMatchClass = MemNoOffsetAsmOperand; 1290 let MIOperandInfo = (ops GPR:$base); 1291} 1292 1293def nohash_imm : Operand<i32> { 1294 let PrintMethod = "printNoHashImmediate"; 1295} 1296 1297def CoprocNumAsmOperand : AsmOperandClass { 1298 let Name = "CoprocNum"; 1299 let ParserMethod = "parseCoprocNumOperand"; 1300} 1301def p_imm : Operand<i32> { 1302 let PrintMethod = "printPImmediate"; 1303 let ParserMatchClass = CoprocNumAsmOperand; 1304 let DecoderMethod = "DecodeCoprocessor"; 1305} 1306 1307def CoprocRegAsmOperand : AsmOperandClass { 1308 let Name = "CoprocReg"; 1309 let ParserMethod = "parseCoprocRegOperand"; 1310} 1311def c_imm : Operand<i32> { 1312 let PrintMethod = "printCImmediate"; 1313 let ParserMatchClass = CoprocRegAsmOperand; 1314} 1315def CoprocOptionAsmOperand : AsmOperandClass { 1316 let Name = "CoprocOption"; 1317 let ParserMethod = "parseCoprocOptionOperand"; 1318} 1319def coproc_option_imm : Operand<i32> { 1320 let PrintMethod = "printCoprocOptionImm"; 1321 let ParserMatchClass = CoprocOptionAsmOperand; 1322} 1323 1324//===----------------------------------------------------------------------===// 1325 1326include "ARMInstrFormats.td" 1327 1328//===----------------------------------------------------------------------===// 1329// Multiclass helpers... 1330// 1331 1332/// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a 1333/// binop that produces a value. 1334let TwoOperandAliasConstraint = "$Rn = $Rd" in 1335multiclass AsI1_bin_irs<bits<4> opcod, string opc, 1336 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1337 SDPatternOperator opnode, bit Commutable = 0> { 1338 // The register-immediate version is re-materializable. This is useful 1339 // in particular for taking the address of a local. 1340 let isReMaterializable = 1 in { 1341 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1342 iii, opc, "\t$Rd, $Rn, $imm", 1343 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>, 1344 Sched<[WriteALU, ReadALU]> { 1345 bits<4> Rd; 1346 bits<4> Rn; 1347 bits<12> imm; 1348 let Inst{25} = 1; 1349 let Inst{19-16} = Rn; 1350 let Inst{15-12} = Rd; 1351 let Inst{11-0} = imm; 1352 } 1353 } 1354 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1355 iir, opc, "\t$Rd, $Rn, $Rm", 1356 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, 1357 Sched<[WriteALU, ReadALU, ReadALU]> { 1358 bits<4> Rd; 1359 bits<4> Rn; 1360 bits<4> Rm; 1361 let Inst{25} = 0; 1362 let isCommutable = Commutable; 1363 let Inst{19-16} = Rn; 1364 let Inst{15-12} = Rd; 1365 let Inst{11-4} = 0b00000000; 1366 let Inst{3-0} = Rm; 1367 } 1368 1369 def rsi : AsI1<opcod, (outs GPR:$Rd), 1370 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1371 iis, opc, "\t$Rd, $Rn, $shift", 1372 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>, 1373 Sched<[WriteALUsi, ReadALU]> { 1374 bits<4> Rd; 1375 bits<4> Rn; 1376 bits<12> shift; 1377 let Inst{25} = 0; 1378 let Inst{19-16} = Rn; 1379 let Inst{15-12} = Rd; 1380 let Inst{11-5} = shift{11-5}; 1381 let Inst{4} = 0; 1382 let Inst{3-0} = shift{3-0}; 1383 } 1384 1385 def rsr : AsI1<opcod, (outs GPR:$Rd), 1386 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1387 iis, opc, "\t$Rd, $Rn, $shift", 1388 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>, 1389 Sched<[WriteALUsr, ReadALUsr]> { 1390 bits<4> Rd; 1391 bits<4> Rn; 1392 bits<12> shift; 1393 let Inst{25} = 0; 1394 let Inst{19-16} = Rn; 1395 let Inst{15-12} = Rd; 1396 let Inst{11-8} = shift{11-8}; 1397 let Inst{7} = 0; 1398 let Inst{6-5} = shift{6-5}; 1399 let Inst{4} = 1; 1400 let Inst{3-0} = shift{3-0}; 1401 } 1402} 1403 1404/// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are 1405/// reversed. The 'rr' form is only defined for the disassembler; for codegen 1406/// it is equivalent to the AsI1_bin_irs counterpart. 1407let TwoOperandAliasConstraint = "$Rn = $Rd" in 1408multiclass AsI1_rbin_irs<bits<4> opcod, string opc, 1409 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1410 SDNode opnode, bit Commutable = 0> { 1411 // The register-immediate version is re-materializable. This is useful 1412 // in particular for taking the address of a local. 1413 let isReMaterializable = 1 in { 1414 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1415 iii, opc, "\t$Rd, $Rn, $imm", 1416 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>, 1417 Sched<[WriteALU, ReadALU]> { 1418 bits<4> Rd; 1419 bits<4> Rn; 1420 bits<12> imm; 1421 let Inst{25} = 1; 1422 let Inst{19-16} = Rn; 1423 let Inst{15-12} = Rd; 1424 let Inst{11-0} = imm; 1425 } 1426 } 1427 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1428 iir, opc, "\t$Rd, $Rn, $Rm", 1429 [/* pattern left blank */]>, 1430 Sched<[WriteALU, ReadALU, ReadALU]> { 1431 bits<4> Rd; 1432 bits<4> Rn; 1433 bits<4> Rm; 1434 let Inst{11-4} = 0b00000000; 1435 let Inst{25} = 0; 1436 let Inst{3-0} = Rm; 1437 let Inst{15-12} = Rd; 1438 let Inst{19-16} = Rn; 1439 } 1440 1441 def rsi : AsI1<opcod, (outs GPR:$Rd), 1442 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1443 iis, opc, "\t$Rd, $Rn, $shift", 1444 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>, 1445 Sched<[WriteALUsi, ReadALU]> { 1446 bits<4> Rd; 1447 bits<4> Rn; 1448 bits<12> shift; 1449 let Inst{25} = 0; 1450 let Inst{19-16} = Rn; 1451 let Inst{15-12} = Rd; 1452 let Inst{11-5} = shift{11-5}; 1453 let Inst{4} = 0; 1454 let Inst{3-0} = shift{3-0}; 1455 } 1456 1457 def rsr : AsI1<opcod, (outs GPR:$Rd), 1458 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1459 iis, opc, "\t$Rd, $Rn, $shift", 1460 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>, 1461 Sched<[WriteALUsr, ReadALUsr]> { 1462 bits<4> Rd; 1463 bits<4> Rn; 1464 bits<12> shift; 1465 let Inst{25} = 0; 1466 let Inst{19-16} = Rn; 1467 let Inst{15-12} = Rd; 1468 let Inst{11-8} = shift{11-8}; 1469 let Inst{7} = 0; 1470 let Inst{6-5} = shift{6-5}; 1471 let Inst{4} = 1; 1472 let Inst{3-0} = shift{3-0}; 1473 } 1474} 1475 1476/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default. 1477/// 1478/// These opcodes will be converted to the real non-S opcodes by 1479/// AdjustInstrPostInstrSelection after giving them an optional CPSR operand. 1480let hasPostISelHook = 1, Defs = [CPSR] in { 1481multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir, 1482 InstrItinClass iis, SDNode opnode, 1483 bit Commutable = 0> { 1484 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1485 4, iii, 1486 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>, 1487 Sched<[WriteALU, ReadALU]>; 1488 1489 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p), 1490 4, iir, 1491 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>, 1492 Sched<[WriteALU, ReadALU, ReadALU]> { 1493 let isCommutable = Commutable; 1494 } 1495 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1496 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1497 4, iis, 1498 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1499 so_reg_imm:$shift))]>, 1500 Sched<[WriteALUsi, ReadALU]>; 1501 1502 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1503 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1504 4, iis, 1505 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1506 so_reg_reg:$shift))]>, 1507 Sched<[WriteALUSsr, ReadALUsr]>; 1508} 1509} 1510 1511/// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG 1512/// operands are reversed. 1513let hasPostISelHook = 1, Defs = [CPSR] in { 1514multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir, 1515 InstrItinClass iis, SDNode opnode, 1516 bit Commutable = 0> { 1517 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1518 4, iii, 1519 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>, 1520 Sched<[WriteALU, ReadALU]>; 1521 1522 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1523 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1524 4, iis, 1525 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, 1526 GPR:$Rn))]>, 1527 Sched<[WriteALUsi, ReadALU]>; 1528 1529 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1530 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1531 4, iis, 1532 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, 1533 GPR:$Rn))]>, 1534 Sched<[WriteALUSsr, ReadALUsr]>; 1535} 1536} 1537 1538/// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test 1539/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 1540/// a explicit result, only implicitly set CPSR. 1541let isCompare = 1, Defs = [CPSR] in { 1542multiclass AI1_cmp_irs<bits<4> opcod, string opc, 1543 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1544 SDPatternOperator opnode, bit Commutable = 0, 1545 string rrDecoderMethod = ""> { 1546 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii, 1547 opc, "\t$Rn, $imm", 1548 [(opnode GPR:$Rn, mod_imm:$imm)]>, 1549 Sched<[WriteCMP, ReadALU]> { 1550 bits<4> Rn; 1551 bits<12> imm; 1552 let Inst{25} = 1; 1553 let Inst{20} = 1; 1554 let Inst{19-16} = Rn; 1555 let Inst{15-12} = 0b0000; 1556 let Inst{11-0} = imm; 1557 1558 let Unpredictable{15-12} = 0b1111; 1559 } 1560 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir, 1561 opc, "\t$Rn, $Rm", 1562 [(opnode GPR:$Rn, GPR:$Rm)]>, 1563 Sched<[WriteCMP, ReadALU, ReadALU]> { 1564 bits<4> Rn; 1565 bits<4> Rm; 1566 let isCommutable = Commutable; 1567 let Inst{25} = 0; 1568 let Inst{20} = 1; 1569 let Inst{19-16} = Rn; 1570 let Inst{15-12} = 0b0000; 1571 let Inst{11-4} = 0b00000000; 1572 let Inst{3-0} = Rm; 1573 let DecoderMethod = rrDecoderMethod; 1574 1575 let Unpredictable{15-12} = 0b1111; 1576 } 1577 def rsi : AI1<opcod, (outs), 1578 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis, 1579 opc, "\t$Rn, $shift", 1580 [(opnode GPR:$Rn, so_reg_imm:$shift)]>, 1581 Sched<[WriteCMPsi, ReadALU]> { 1582 bits<4> Rn; 1583 bits<12> shift; 1584 let Inst{25} = 0; 1585 let Inst{20} = 1; 1586 let Inst{19-16} = Rn; 1587 let Inst{15-12} = 0b0000; 1588 let Inst{11-5} = shift{11-5}; 1589 let Inst{4} = 0; 1590 let Inst{3-0} = shift{3-0}; 1591 1592 let Unpredictable{15-12} = 0b1111; 1593 } 1594 def rsr : AI1<opcod, (outs), 1595 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis, 1596 opc, "\t$Rn, $shift", 1597 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>, 1598 Sched<[WriteCMPsr, ReadALU]> { 1599 bits<4> Rn; 1600 bits<12> shift; 1601 let Inst{25} = 0; 1602 let Inst{20} = 1; 1603 let Inst{19-16} = Rn; 1604 let Inst{15-12} = 0b0000; 1605 let Inst{11-8} = shift{11-8}; 1606 let Inst{7} = 0; 1607 let Inst{6-5} = shift{6-5}; 1608 let Inst{4} = 1; 1609 let Inst{3-0} = shift{3-0}; 1610 1611 let Unpredictable{15-12} = 0b1111; 1612 } 1613 1614} 1615} 1616 1617/// AI_ext_rrot - A unary operation with two forms: one whose operand is a 1618/// register and one whose operand is a register rotated by 8/16/24. 1619/// FIXME: Remove the 'r' variant. Its rot_imm is zero. 1620class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> 1621 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1622 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", 1623 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1624 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1625 bits<4> Rd; 1626 bits<4> Rm; 1627 bits<2> rot; 1628 let Inst{19-16} = 0b1111; 1629 let Inst{15-12} = Rd; 1630 let Inst{11-10} = rot; 1631 let Inst{3-0} = Rm; 1632} 1633 1634class AI_ext_rrot_np<bits<8> opcod, string opc> 1635 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1636 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>, 1637 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1638 bits<2> rot; 1639 let Inst{19-16} = 0b1111; 1640 let Inst{11-10} = rot; 1641 } 1642 1643/// AI_exta_rrot - A binary operation with two forms: one whose operand is a 1644/// register and one whose operand is a register rotated by 8/16/24. 1645class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> 1646 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1647 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", 1648 [(set GPRnopc:$Rd, (opnode GPR:$Rn, 1649 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1650 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1651 bits<4> Rd; 1652 bits<4> Rm; 1653 bits<4> Rn; 1654 bits<2> rot; 1655 let Inst{19-16} = Rn; 1656 let Inst{15-12} = Rd; 1657 let Inst{11-10} = rot; 1658 let Inst{9-4} = 0b000111; 1659 let Inst{3-0} = Rm; 1660} 1661 1662class AI_exta_rrot_np<bits<8> opcod, string opc> 1663 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1664 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>, 1665 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1666 bits<4> Rn; 1667 bits<2> rot; 1668 let Inst{19-16} = Rn; 1669 let Inst{11-10} = rot; 1670} 1671 1672/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. 1673let TwoOperandAliasConstraint = "$Rn = $Rd" in 1674multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode, 1675 bit Commutable = 0> { 1676 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1677 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1678 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1679 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>, 1680 Requires<[IsARM]>, 1681 Sched<[WriteALU, ReadALU]> { 1682 bits<4> Rd; 1683 bits<4> Rn; 1684 bits<12> imm; 1685 let Inst{25} = 1; 1686 let Inst{15-12} = Rd; 1687 let Inst{19-16} = Rn; 1688 let Inst{11-0} = imm; 1689 } 1690 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1691 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1692 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>, 1693 Requires<[IsARM]>, 1694 Sched<[WriteALU, ReadALU, ReadALU]> { 1695 bits<4> Rd; 1696 bits<4> Rn; 1697 bits<4> Rm; 1698 let Inst{11-4} = 0b00000000; 1699 let Inst{25} = 0; 1700 let isCommutable = Commutable; 1701 let Inst{3-0} = Rm; 1702 let Inst{15-12} = Rd; 1703 let Inst{19-16} = Rn; 1704 } 1705 def rsi : AsI1<opcod, (outs GPR:$Rd), 1706 (ins GPR:$Rn, so_reg_imm:$shift), 1707 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1708 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>, 1709 Requires<[IsARM]>, 1710 Sched<[WriteALUsi, ReadALU]> { 1711 bits<4> Rd; 1712 bits<4> Rn; 1713 bits<12> shift; 1714 let Inst{25} = 0; 1715 let Inst{19-16} = Rn; 1716 let Inst{15-12} = Rd; 1717 let Inst{11-5} = shift{11-5}; 1718 let Inst{4} = 0; 1719 let Inst{3-0} = shift{3-0}; 1720 } 1721 def rsr : AsI1<opcod, (outs GPRnopc:$Rd), 1722 (ins GPRnopc:$Rn, so_reg_reg:$shift), 1723 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1724 [(set GPRnopc:$Rd, CPSR, 1725 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>, 1726 Requires<[IsARM]>, 1727 Sched<[WriteALUsr, ReadALUsr]> { 1728 bits<4> Rd; 1729 bits<4> Rn; 1730 bits<12> shift; 1731 let Inst{25} = 0; 1732 let Inst{19-16} = Rn; 1733 let Inst{15-12} = Rd; 1734 let Inst{11-8} = shift{11-8}; 1735 let Inst{7} = 0; 1736 let Inst{6-5} = shift{6-5}; 1737 let Inst{4} = 1; 1738 let Inst{3-0} = shift{3-0}; 1739 } 1740 } 1741} 1742 1743/// AI1_rsc_irs - Define instructions and patterns for rsc 1744let TwoOperandAliasConstraint = "$Rn = $Rd" in 1745multiclass AI1_rsc_irs<bits<4> opcod, string opc, SDNode opnode> { 1746 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1747 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1748 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1749 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>, 1750 Requires<[IsARM]>, 1751 Sched<[WriteALU, ReadALU]> { 1752 bits<4> Rd; 1753 bits<4> Rn; 1754 bits<12> imm; 1755 let Inst{25} = 1; 1756 let Inst{15-12} = Rd; 1757 let Inst{19-16} = Rn; 1758 let Inst{11-0} = imm; 1759 } 1760 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1761 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1762 [/* pattern left blank */]>, 1763 Sched<[WriteALU, ReadALU, ReadALU]> { 1764 bits<4> Rd; 1765 bits<4> Rn; 1766 bits<4> Rm; 1767 let Inst{11-4} = 0b00000000; 1768 let Inst{25} = 0; 1769 let Inst{3-0} = Rm; 1770 let Inst{15-12} = Rd; 1771 let Inst{19-16} = Rn; 1772 } 1773 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), 1774 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1775 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>, 1776 Requires<[IsARM]>, 1777 Sched<[WriteALUsi, ReadALU]> { 1778 bits<4> Rd; 1779 bits<4> Rn; 1780 bits<12> shift; 1781 let Inst{25} = 0; 1782 let Inst{19-16} = Rn; 1783 let Inst{15-12} = Rd; 1784 let Inst{11-5} = shift{11-5}; 1785 let Inst{4} = 0; 1786 let Inst{3-0} = shift{3-0}; 1787 } 1788 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), 1789 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1790 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>, 1791 Requires<[IsARM]>, 1792 Sched<[WriteALUsr, ReadALUsr]> { 1793 bits<4> Rd; 1794 bits<4> Rn; 1795 bits<12> shift; 1796 let Inst{25} = 0; 1797 let Inst{19-16} = Rn; 1798 let Inst{15-12} = Rd; 1799 let Inst{11-8} = shift{11-8}; 1800 let Inst{7} = 0; 1801 let Inst{6-5} = shift{6-5}; 1802 let Inst{4} = 1; 1803 let Inst{3-0} = shift{3-0}; 1804 } 1805 } 1806} 1807 1808let canFoldAsLoad = 1, isReMaterializable = 1 in { 1809multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii, 1810 InstrItinClass iir, PatFrag opnode> { 1811 // Note: We use the complex addrmode_imm12 rather than just an input 1812 // GPR and a constrained immediate so that we can use this to match 1813 // frame index references and avoid matching constant pool references. 1814 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 1815 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1816 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { 1817 bits<4> Rt; 1818 bits<17> addr; 1819 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1820 let Inst{19-16} = addr{16-13}; // Rn 1821 let Inst{15-12} = Rt; 1822 let Inst{11-0} = addr{11-0}; // imm12 1823 } 1824 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift), 1825 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1826 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { 1827 bits<4> Rt; 1828 bits<17> shift; 1829 let shift{4} = 0; // Inst{4} = 0 1830 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1831 let Inst{19-16} = shift{16-13}; // Rn 1832 let Inst{15-12} = Rt; 1833 let Inst{11-0} = shift{11-0}; 1834 } 1835} 1836} 1837 1838let canFoldAsLoad = 1, isReMaterializable = 1 in { 1839multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii, 1840 InstrItinClass iir, PatFrag opnode> { 1841 // Note: We use the complex addrmode_imm12 rather than just an input 1842 // GPR and a constrained immediate so that we can use this to match 1843 // frame index references and avoid matching constant pool references. 1844 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), 1845 (ins addrmode_imm12:$addr), 1846 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1847 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> { 1848 bits<4> Rt; 1849 bits<17> addr; 1850 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1851 let Inst{19-16} = addr{16-13}; // Rn 1852 let Inst{15-12} = Rt; 1853 let Inst{11-0} = addr{11-0}; // imm12 1854 } 1855 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), 1856 (ins ldst_so_reg:$shift), 1857 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1858 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> { 1859 bits<4> Rt; 1860 bits<17> shift; 1861 let shift{4} = 0; // Inst{4} = 0 1862 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1863 let Inst{19-16} = shift{16-13}; // Rn 1864 let Inst{15-12} = Rt; 1865 let Inst{11-0} = shift{11-0}; 1866 } 1867} 1868} 1869 1870 1871multiclass AI_str1<bit isByte, string opc, InstrItinClass iii, 1872 InstrItinClass iir, PatFrag opnode> { 1873 // Note: We use the complex addrmode_imm12 rather than just an input 1874 // GPR and a constrained immediate so that we can use this to match 1875 // frame index references and avoid matching constant pool references. 1876 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1877 (ins GPR:$Rt, addrmode_imm12:$addr), 1878 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1879 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> { 1880 bits<4> Rt; 1881 bits<17> addr; 1882 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1883 let Inst{19-16} = addr{16-13}; // Rn 1884 let Inst{15-12} = Rt; 1885 let Inst{11-0} = addr{11-0}; // imm12 1886 } 1887 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift), 1888 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1889 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> { 1890 bits<4> Rt; 1891 bits<17> shift; 1892 let shift{4} = 0; // Inst{4} = 0 1893 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1894 let Inst{19-16} = shift{16-13}; // Rn 1895 let Inst{15-12} = Rt; 1896 let Inst{11-0} = shift{11-0}; 1897 } 1898} 1899 1900multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii, 1901 InstrItinClass iir, PatFrag opnode> { 1902 // Note: We use the complex addrmode_imm12 rather than just an input 1903 // GPR and a constrained immediate so that we can use this to match 1904 // frame index references and avoid matching constant pool references. 1905 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1906 (ins GPRnopc:$Rt, addrmode_imm12:$addr), 1907 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1908 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> { 1909 bits<4> Rt; 1910 bits<17> addr; 1911 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1912 let Inst{19-16} = addr{16-13}; // Rn 1913 let Inst{15-12} = Rt; 1914 let Inst{11-0} = addr{11-0}; // imm12 1915 } 1916 def rs : AI2ldst<0b011, 0, isByte, (outs), 1917 (ins GPRnopc:$Rt, ldst_so_reg:$shift), 1918 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1919 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> { 1920 bits<4> Rt; 1921 bits<17> shift; 1922 let shift{4} = 0; // Inst{4} = 0 1923 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1924 let Inst{19-16} = shift{16-13}; // Rn 1925 let Inst{15-12} = Rt; 1926 let Inst{11-0} = shift{11-0}; 1927 } 1928} 1929 1930 1931//===----------------------------------------------------------------------===// 1932// Instructions 1933//===----------------------------------------------------------------------===// 1934 1935//===----------------------------------------------------------------------===// 1936// Miscellaneous Instructions. 1937// 1938 1939/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 1940/// the function. The first operand is the ID# for this instruction, the second 1941/// is the index into the MachineConstantPool that this is, the third is the 1942/// size in bytes of this constant pool entry. 1943let hasSideEffects = 0, isNotDuplicable = 1 in 1944def CONSTPOOL_ENTRY : 1945PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1946 i32imm:$size), NoItinerary, []>; 1947 1948/// A jumptable consisting of direct 32-bit addresses of the destination basic 1949/// blocks (either absolute, or relative to the start of the jump-table in PIC 1950/// mode). Used mostly in ARM and Thumb-1 modes. 1951def JUMPTABLE_ADDRS : 1952PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1953 i32imm:$size), NoItinerary, []>; 1954 1955/// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables 1956/// that cannot be optimised to use TBB or TBH. 1957def JUMPTABLE_INSTS : 1958PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1959 i32imm:$size), NoItinerary, []>; 1960 1961/// A jumptable consisting of 8-bit unsigned integers representing offsets from 1962/// a TBB instruction. 1963def JUMPTABLE_TBB : 1964PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1965 i32imm:$size), NoItinerary, []>; 1966 1967/// A jumptable consisting of 16-bit unsigned integers representing offsets from 1968/// a TBH instruction. 1969def JUMPTABLE_TBH : 1970PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1971 i32imm:$size), NoItinerary, []>; 1972 1973 1974// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 1975// from removing one half of the matched pairs. That breaks PEI, which assumes 1976// these will always be in pairs, and asserts if it finds otherwise. Better way? 1977let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 1978def ADJCALLSTACKUP : 1979PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, 1980 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; 1981 1982def ADJCALLSTACKDOWN : 1983PseudoInst<(outs), (ins i32imm:$amt, i32imm:$amt2, pred:$p), NoItinerary, 1984 [(ARMcallseq_start timm:$amt, timm:$amt2)]>; 1985} 1986 1987def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary, 1988 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>, 1989 Requires<[IsARM, HasV6]> { 1990 bits<8> imm; 1991 let Inst{27-8} = 0b00110010000011110000; 1992 let Inst{7-0} = imm; 1993 let DecoderMethod = "DecodeHINTInstruction"; 1994} 1995 1996def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>; 1997def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>; 1998def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>; 1999def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>; 2000def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>; 2001def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>; 2002def : InstAlias<"esb$p", (HINT 16, pred:$p)>, Requires<[IsARM, HasRAS]>; 2003 2004def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel", 2005 "\t$Rd, $Rn, $Rm", 2006 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>, 2007 Requires<[IsARM, HasV6]> { 2008 bits<4> Rd; 2009 bits<4> Rn; 2010 bits<4> Rm; 2011 let Inst{3-0} = Rm; 2012 let Inst{15-12} = Rd; 2013 let Inst{19-16} = Rn; 2014 let Inst{27-20} = 0b01101000; 2015 let Inst{7-4} = 0b1011; 2016 let Inst{11-8} = 0b1111; 2017 let Unpredictable{11-8} = 0b1111; 2018} 2019 2020// The 16-bit operand $val can be used by a debugger to store more information 2021// about the breakpoint. 2022def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 2023 "bkpt", "\t$val", []>, Requires<[IsARM]> { 2024 bits<16> val; 2025 let Inst{3-0} = val{3-0}; 2026 let Inst{19-8} = val{15-4}; 2027 let Inst{27-20} = 0b00010010; 2028 let Inst{31-28} = 0xe; // AL 2029 let Inst{7-4} = 0b0111; 2030} 2031// default immediate for breakpoint mnemonic 2032def : InstAlias<"bkpt", (BKPT 0), 0>, Requires<[IsARM]>; 2033 2034def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 2035 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> { 2036 bits<16> val; 2037 let Inst{3-0} = val{3-0}; 2038 let Inst{19-8} = val{15-4}; 2039 let Inst{27-20} = 0b00010000; 2040 let Inst{31-28} = 0xe; // AL 2041 let Inst{7-4} = 0b0111; 2042} 2043 2044// Change Processor State 2045// FIXME: We should use InstAlias to handle the optional operands. 2046class CPS<dag iops, string asm_ops> 2047 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops), 2048 []>, Requires<[IsARM]> { 2049 bits<2> imod; 2050 bits<3> iflags; 2051 bits<5> mode; 2052 bit M; 2053 2054 let Inst{31-28} = 0b1111; 2055 let Inst{27-20} = 0b00010000; 2056 let Inst{19-18} = imod; 2057 let Inst{17} = M; // Enabled if mode is set; 2058 let Inst{16-9} = 0b00000000; 2059 let Inst{8-6} = iflags; 2060 let Inst{5} = 0; 2061 let Inst{4-0} = mode; 2062} 2063 2064let DecoderMethod = "DecodeCPSInstruction" in { 2065let M = 1 in 2066 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode), 2067 "$imod\t$iflags, $mode">; 2068let mode = 0, M = 0 in 2069 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">; 2070 2071let imod = 0, iflags = 0, M = 1 in 2072 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">; 2073} 2074 2075// Preload signals the memory system of possible future data/instruction access. 2076multiclass APreLoad<bits<1> read, bits<1> data, string opc> { 2077 2078 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm, 2079 IIC_Preload, !strconcat(opc, "\t$addr"), 2080 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>, 2081 Sched<[WritePreLd]> { 2082 bits<4> Rt; 2083 bits<17> addr; 2084 let Inst{31-26} = 0b111101; 2085 let Inst{25} = 0; // 0 for immediate form 2086 let Inst{24} = data; 2087 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2088 let Inst{22} = read; 2089 let Inst{21-20} = 0b01; 2090 let Inst{19-16} = addr{16-13}; // Rn 2091 let Inst{15-12} = 0b1111; 2092 let Inst{11-0} = addr{11-0}; // imm12 2093 } 2094 2095 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, 2096 !strconcat(opc, "\t$shift"), 2097 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>, 2098 Sched<[WritePreLd]> { 2099 bits<17> shift; 2100 let Inst{31-26} = 0b111101; 2101 let Inst{25} = 1; // 1 for register form 2102 let Inst{24} = data; 2103 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2104 let Inst{22} = read; 2105 let Inst{21-20} = 0b01; 2106 let Inst{19-16} = shift{16-13}; // Rn 2107 let Inst{15-12} = 0b1111; 2108 let Inst{11-0} = shift{11-0}; 2109 let Inst{4} = 0; 2110 } 2111} 2112 2113defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>; 2114defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>; 2115defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>; 2116 2117def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary, 2118 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> { 2119 bits<1> end; 2120 let Inst{31-10} = 0b1111000100000001000000; 2121 let Inst{9} = end; 2122 let Inst{8-0} = 0; 2123} 2124 2125def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", 2126 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> { 2127 bits<4> opt; 2128 let Inst{27-4} = 0b001100100000111100001111; 2129 let Inst{3-0} = opt; 2130} 2131 2132// A8.8.247 UDF - Undefined (Encoding A1) 2133def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary, 2134 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> { 2135 bits<16> imm16; 2136 let Inst{31-28} = 0b1110; // AL 2137 let Inst{27-25} = 0b011; 2138 let Inst{24-20} = 0b11111; 2139 let Inst{19-8} = imm16{15-4}; 2140 let Inst{7-4} = 0b1111; 2141 let Inst{3-0} = imm16{3-0}; 2142} 2143 2144/* 2145 * A5.4 Permanently UNDEFINED instructions. 2146 * 2147 * For most targets use UDF #65006, for which the OS will generate SIGTRAP. 2148 * Other UDF encodings generate SIGILL. 2149 * 2150 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb. 2151 * Encoding A1: 2152 * 1110 0111 1111 iiii iiii iiii 1111 iiii 2153 * Encoding T1: 2154 * 1101 1110 iiii iiii 2155 * It uses the following encoding: 2156 * 1110 0111 1111 1110 1101 1110 1111 0000 2157 * - In ARM: UDF #60896; 2158 * - In Thumb: UDF #254 followed by a branch-to-self. 2159 */ 2160let isBarrier = 1, isTerminator = 1 in 2161def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary, 2162 "trap", [(trap)]>, 2163 Requires<[IsARM,UseNaClTrap]> { 2164 let Inst = 0xe7fedef0; 2165} 2166let isBarrier = 1, isTerminator = 1 in 2167def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, 2168 "trap", [(trap)]>, 2169 Requires<[IsARM,DontUseNaClTrap]> { 2170 let Inst = 0xe7ffdefe; 2171} 2172 2173// Address computation and loads and stores in PIC mode. 2174let isNotDuplicable = 1 in { 2175def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 2176 4, IIC_iALUr, 2177 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>, 2178 Sched<[WriteALU, ReadALU]>; 2179 2180let AddedComplexity = 10 in { 2181def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 2182 4, IIC_iLoad_r, 2183 [(set GPR:$dst, (load addrmodepc:$addr))]>; 2184 2185def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2186 4, IIC_iLoad_bh_r, 2187 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>; 2188 2189def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2190 4, IIC_iLoad_bh_r, 2191 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>; 2192 2193def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2194 4, IIC_iLoad_bh_r, 2195 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>; 2196 2197def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2198 4, IIC_iLoad_bh_r, 2199 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>; 2200} 2201let AddedComplexity = 10 in { 2202def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2203 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>; 2204 2205def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2206 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, 2207 addrmodepc:$addr)]>; 2208 2209def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2210 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 2211} 2212} // isNotDuplicable = 1 2213 2214 2215// LEApcrel - Load a pc-relative address into a register without offending the 2216// assembler. 2217let hasSideEffects = 0, isReMaterializable = 1 in 2218// The 'adr' mnemonic encodes differently if the label is before or after 2219// the instruction. The {24-21} opcode bits are set by the fixup, as we don't 2220// know until then which form of the instruction will be used. 2221def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), 2222 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>, 2223 Sched<[WriteALU, ReadALU]> { 2224 bits<4> Rd; 2225 bits<14> label; 2226 let Inst{27-25} = 0b001; 2227 let Inst{24} = 0; 2228 let Inst{23-22} = label{13-12}; 2229 let Inst{21} = 0; 2230 let Inst{20} = 0; 2231 let Inst{19-16} = 0b1111; 2232 let Inst{15-12} = Rd; 2233 let Inst{11-0} = label{11-0}; 2234} 2235 2236let hasSideEffects = 1 in { 2237def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 2238 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2239 2240def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd), 2241 (ins i32imm:$label, pred:$p), 2242 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2243} 2244 2245//===----------------------------------------------------------------------===// 2246// Control Flow Instructions. 2247// 2248 2249let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 2250 // ARMV4T and above 2251 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2252 "bx", "\tlr", [(ARMretflag)]>, 2253 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2254 let Inst{27-0} = 0b0001001011111111111100011110; 2255 } 2256 2257 // ARMV4 only 2258 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2259 "mov", "\tpc, lr", [(ARMretflag)]>, 2260 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> { 2261 let Inst{27-0} = 0b0001101000001111000000001110; 2262 } 2263 2264 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets 2265 // the user-space one). 2266 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p), 2267 4, IIC_Br, 2268 [(ARMintretflag imm:$offset)]>; 2269} 2270 2271// Indirect branches 2272let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 2273 // ARMV4T and above 2274 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst", 2275 [(brind GPR:$dst)]>, 2276 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2277 bits<4> dst; 2278 let Inst{31-4} = 0b1110000100101111111111110001; 2279 let Inst{3-0} = dst; 2280 } 2281 2282 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, 2283 "bx", "\t$dst", [/* pattern left blank */]>, 2284 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2285 bits<4> dst; 2286 let Inst{27-4} = 0b000100101111111111110001; 2287 let Inst{3-0} = dst; 2288 } 2289} 2290 2291// SP is marked as a use to prevent stack-pointer assignments that appear 2292// immediately before calls from potentially appearing dead. 2293let isCall = 1, 2294 // FIXME: Do we really need a non-predicated version? If so, it should 2295 // at least be a pseudo instruction expanding to the predicated version 2296 // at MC lowering time. 2297 Defs = [LR], Uses = [SP] in { 2298 def BL : ABXI<0b1011, (outs), (ins arm_bl_target:$func), 2299 IIC_Br, "bl\t$func", 2300 [(ARMcall tglobaladdr:$func)]>, 2301 Requires<[IsARM]>, Sched<[WriteBrL]> { 2302 let Inst{31-28} = 0b1110; 2303 bits<24> func; 2304 let Inst{23-0} = func; 2305 let DecoderMethod = "DecodeBranchImmInstruction"; 2306 } 2307 2308 def BL_pred : ABI<0b1011, (outs), (ins arm_bl_target:$func), 2309 IIC_Br, "bl", "\t$func", 2310 [(ARMcall_pred tglobaladdr:$func)]>, 2311 Requires<[IsARM]>, Sched<[WriteBrL]> { 2312 bits<24> func; 2313 let Inst{23-0} = func; 2314 let DecoderMethod = "DecodeBranchImmInstruction"; 2315 } 2316 2317 // ARMv5T and above 2318 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm, 2319 IIC_Br, "blx\t$func", 2320 [(ARMcall GPR:$func)]>, 2321 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2322 bits<4> func; 2323 let Inst{31-4} = 0b1110000100101111111111110011; 2324 let Inst{3-0} = func; 2325 } 2326 2327 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm, 2328 IIC_Br, "blx", "\t$func", 2329 [(ARMcall_pred GPR:$func)]>, 2330 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2331 bits<4> func; 2332 let Inst{27-4} = 0b000100101111111111110011; 2333 let Inst{3-0} = func; 2334 } 2335 2336 // ARMv4T 2337 // Note: Restrict $func to the tGPR regclass to prevent it being in LR. 2338 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2339 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2340 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>; 2341 2342 // ARMv4 2343 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2344 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2345 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 2346 2347 // mov lr, pc; b if callee is marked noreturn to avoid confusing the 2348 // return stack predictor. 2349 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins arm_bl_target:$func), 2350 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>, 2351 Requires<[IsARM]>, Sched<[WriteBr]>; 2352} 2353 2354let isBranch = 1, isTerminator = 1 in { 2355 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 2356 // a two-value operand where a dag node expects two operands. :( 2357 def Bcc : ABI<0b1010, (outs), (ins arm_br_target:$target), 2358 IIC_Br, "b", "\t$target", 2359 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>, 2360 Sched<[WriteBr]> { 2361 bits<24> target; 2362 let Inst{23-0} = target; 2363 let DecoderMethod = "DecodeBranchImmInstruction"; 2364 } 2365 2366 let isBarrier = 1 in { 2367 // B is "predicable" since it's just a Bcc with an 'always' condition. 2368 let isPredicable = 1 in 2369 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly 2370 // should be sufficient. 2371 // FIXME: Is B really a Barrier? That doesn't seem right. 2372 def B : ARMPseudoExpand<(outs), (ins arm_br_target:$target), 4, IIC_Br, 2373 [(br bb:$target)], (Bcc arm_br_target:$target, 2374 (ops 14, zero_reg))>, 2375 Sched<[WriteBr]>; 2376 2377 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in { 2378 def BR_JTr : ARMPseudoInst<(outs), 2379 (ins GPR:$target, i32imm:$jt), 2380 0, IIC_Br, 2381 [(ARMbrjt GPR:$target, tjumptable:$jt)]>, 2382 Sched<[WriteBr]>; 2383 // FIXME: This shouldn't use the generic "addrmode2," but rather be split 2384 // into i12 and rs suffixed versions. 2385 def BR_JTm : ARMPseudoInst<(outs), 2386 (ins addrmode2:$target, i32imm:$jt), 2387 0, IIC_Br, 2388 [(ARMbrjt (i32 (load addrmode2:$target)), 2389 tjumptable:$jt)]>, Sched<[WriteBrTbl]>; 2390 def BR_JTadd : ARMPseudoInst<(outs), 2391 (ins GPR:$target, GPR:$idx, i32imm:$jt), 2392 0, IIC_Br, 2393 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>, 2394 Sched<[WriteBrTbl]>; 2395 } // isNotDuplicable = 1, isIndirectBranch = 1 2396 } // isBarrier = 1 2397 2398} 2399 2400// BLX (immediate) 2401def BLXi : AXI<(outs), (ins arm_blx_target:$target), BrMiscFrm, NoItinerary, 2402 "blx\t$target", []>, 2403 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2404 let Inst{31-25} = 0b1111101; 2405 bits<25> target; 2406 let Inst{23-0} = target{24-1}; 2407 let Inst{24} = target{0}; 2408 let isCall = 1; 2409} 2410 2411// Branch and Exchange Jazelle 2412def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", 2413 [/* pattern left blank */]>, Sched<[WriteBr]> { 2414 bits<4> func; 2415 let Inst{23-20} = 0b0010; 2416 let Inst{19-8} = 0xfff; 2417 let Inst{7-4} = 0b0010; 2418 let Inst{3-0} = func; 2419 let isBranch = 1; 2420} 2421 2422// Tail calls. 2423 2424let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { 2425 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>, 2426 Sched<[WriteBr]>; 2427 2428 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>, 2429 Sched<[WriteBr]>; 2430 2431 def TAILJMPd : ARMPseudoExpand<(outs), (ins arm_br_target:$dst), 2432 4, IIC_Br, [], 2433 (Bcc arm_br_target:$dst, (ops 14, zero_reg))>, 2434 Requires<[IsARM]>, Sched<[WriteBr]>; 2435 2436 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst), 2437 4, IIC_Br, [], 2438 (BX GPR:$dst)>, Sched<[WriteBr]>, 2439 Requires<[IsARM, HasV4T]>; 2440} 2441 2442// Secure Monitor Call is a system instruction. 2443def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", 2444 []>, Requires<[IsARM, HasTrustZone]> { 2445 bits<4> opt; 2446 let Inst{23-4} = 0b01100000000000000111; 2447 let Inst{3-0} = opt; 2448} 2449def : MnemonicAlias<"smi", "smc">; 2450 2451// Supervisor Call (Software Interrupt) 2452let isCall = 1, Uses = [SP] in { 2453def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>, 2454 Sched<[WriteBr]> { 2455 bits<24> svc; 2456 let Inst{23-0} = svc; 2457} 2458} 2459 2460// Store Return State 2461class SRSI<bit wb, string asm> 2462 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm, 2463 NoItinerary, asm, "", []> { 2464 bits<5> mode; 2465 let Inst{31-28} = 0b1111; 2466 let Inst{27-25} = 0b100; 2467 let Inst{22} = 1; 2468 let Inst{21} = wb; 2469 let Inst{20} = 0; 2470 let Inst{19-16} = 0b1101; // SP 2471 let Inst{15-5} = 0b00000101000; 2472 let Inst{4-0} = mode; 2473} 2474 2475def SRSDA : SRSI<0, "srsda\tsp, $mode"> { 2476 let Inst{24-23} = 0; 2477} 2478def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> { 2479 let Inst{24-23} = 0; 2480} 2481def SRSDB : SRSI<0, "srsdb\tsp, $mode"> { 2482 let Inst{24-23} = 0b10; 2483} 2484def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> { 2485 let Inst{24-23} = 0b10; 2486} 2487def SRSIA : SRSI<0, "srsia\tsp, $mode"> { 2488 let Inst{24-23} = 0b01; 2489} 2490def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> { 2491 let Inst{24-23} = 0b01; 2492} 2493def SRSIB : SRSI<0, "srsib\tsp, $mode"> { 2494 let Inst{24-23} = 0b11; 2495} 2496def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> { 2497 let Inst{24-23} = 0b11; 2498} 2499 2500def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>; 2501def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>; 2502 2503def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>; 2504def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>; 2505 2506def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>; 2507def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>; 2508 2509def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>; 2510def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>; 2511 2512// Return From Exception 2513class RFEI<bit wb, string asm> 2514 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm, 2515 NoItinerary, asm, "", []> { 2516 bits<4> Rn; 2517 let Inst{31-28} = 0b1111; 2518 let Inst{27-25} = 0b100; 2519 let Inst{22} = 0; 2520 let Inst{21} = wb; 2521 let Inst{20} = 1; 2522 let Inst{19-16} = Rn; 2523 let Inst{15-0} = 0xa00; 2524} 2525 2526def RFEDA : RFEI<0, "rfeda\t$Rn"> { 2527 let Inst{24-23} = 0; 2528} 2529def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> { 2530 let Inst{24-23} = 0; 2531} 2532def RFEDB : RFEI<0, "rfedb\t$Rn"> { 2533 let Inst{24-23} = 0b10; 2534} 2535def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> { 2536 let Inst{24-23} = 0b10; 2537} 2538def RFEIA : RFEI<0, "rfeia\t$Rn"> { 2539 let Inst{24-23} = 0b01; 2540} 2541def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> { 2542 let Inst{24-23} = 0b01; 2543} 2544def RFEIB : RFEI<0, "rfeib\t$Rn"> { 2545 let Inst{24-23} = 0b11; 2546} 2547def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> { 2548 let Inst{24-23} = 0b11; 2549} 2550 2551// Hypervisor Call is a system instruction 2552let isCall = 1 in { 2553def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary, 2554 "hvc", "\t$imm", []>, 2555 Requires<[IsARM, HasVirtualization]> { 2556 bits<16> imm; 2557 2558 // Even though HVC isn't predicable, it's encoding includes a condition field. 2559 // The instruction is undefined if the condition field is 0xf otherwise it is 2560 // unpredictable if it isn't condition AL (0xe). 2561 let Inst{31-28} = 0b1110; 2562 let Unpredictable{31-28} = 0b1111; 2563 let Inst{27-24} = 0b0001; 2564 let Inst{23-20} = 0b0100; 2565 let Inst{19-8} = imm{15-4}; 2566 let Inst{7-4} = 0b0111; 2567 let Inst{3-0} = imm{3-0}; 2568} 2569} 2570 2571// Return from exception in Hypervisor mode. 2572let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in 2573def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>, 2574 Requires<[IsARM, HasVirtualization]> { 2575 let Inst{23-0} = 0b011000000000000001101110; 2576} 2577 2578//===----------------------------------------------------------------------===// 2579// Load / Store Instructions. 2580// 2581 2582// Load 2583 2584 2585defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si, load>; 2586defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si, 2587 zextloadi8>; 2588defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si, store>; 2589defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si, 2590 truncstorei8>; 2591 2592// Special LDR for loads from non-pc-relative constpools. 2593let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0, 2594 isReMaterializable = 1, isCodeGenOnly = 1 in 2595def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 2596 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", 2597 []> { 2598 bits<4> Rt; 2599 bits<17> addr; 2600 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2601 let Inst{19-16} = 0b1111; 2602 let Inst{15-12} = Rt; 2603 let Inst{11-0} = addr{11-0}; // imm12 2604} 2605 2606// Loads with zero extension 2607def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2608 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr", 2609 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>; 2610 2611// Loads with sign extension 2612def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2613 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr", 2614 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>; 2615 2616def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2617 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr", 2618 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>; 2619 2620let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in { 2621 // Load doubleword 2622 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr), 2623 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>, 2624 Requires<[IsARM, HasV5TE]>; 2625} 2626 2627def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2628 NoItinerary, "lda", "\t$Rt, $addr", []>; 2629def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2630 NoItinerary, "ldab", "\t$Rt, $addr", []>; 2631def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2632 NoItinerary, "ldah", "\t$Rt, $addr", []>; 2633 2634// Indexed loads 2635multiclass AI2_ldridx<bit isByte, string opc, 2636 InstrItinClass iii, InstrItinClass iir> { 2637 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2638 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii, 2639 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2640 bits<17> addr; 2641 let Inst{25} = 0; 2642 let Inst{23} = addr{12}; 2643 let Inst{19-16} = addr{16-13}; 2644 let Inst{11-0} = addr{11-0}; 2645 let DecoderMethod = "DecodeLDRPreImm"; 2646 } 2647 2648 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2649 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir, 2650 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2651 bits<17> addr; 2652 let Inst{25} = 1; 2653 let Inst{23} = addr{12}; 2654 let Inst{19-16} = addr{16-13}; 2655 let Inst{11-0} = addr{11-0}; 2656 let Inst{4} = 0; 2657 let DecoderMethod = "DecodeLDRPreReg"; 2658 } 2659 2660 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2661 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2662 IndexModePost, LdFrm, iir, 2663 opc, "\t$Rt, $addr, $offset", 2664 "$addr.base = $Rn_wb", []> { 2665 // {12} isAdd 2666 // {11-0} imm12/Rm 2667 bits<14> offset; 2668 bits<4> addr; 2669 let Inst{25} = 1; 2670 let Inst{23} = offset{12}; 2671 let Inst{19-16} = addr; 2672 let Inst{11-0} = offset{11-0}; 2673 let Inst{4} = 0; 2674 2675 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2676 } 2677 2678 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2679 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2680 IndexModePost, LdFrm, iii, 2681 opc, "\t$Rt, $addr, $offset", 2682 "$addr.base = $Rn_wb", []> { 2683 // {12} isAdd 2684 // {11-0} imm12/Rm 2685 bits<14> offset; 2686 bits<4> addr; 2687 let Inst{25} = 0; 2688 let Inst{23} = offset{12}; 2689 let Inst{19-16} = addr; 2690 let Inst{11-0} = offset{11-0}; 2691 2692 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2693 } 2694 2695} 2696 2697let mayLoad = 1, hasSideEffects = 0 in { 2698// FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or 2699// IIC_iLoad_siu depending on whether it the offset register is shifted. 2700defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>; 2701defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>; 2702} 2703 2704multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> { 2705 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2706 (ins addrmode3_pre:$addr), IndexModePre, 2707 LdMiscFrm, itin, 2708 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2709 bits<14> addr; 2710 let Inst{23} = addr{8}; // U bit 2711 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2712 let Inst{19-16} = addr{12-9}; // Rn 2713 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2714 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2715 let DecoderMethod = "DecodeAddrMode3Instruction"; 2716 } 2717 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2718 (ins addr_offset_none:$addr, am3offset:$offset), 2719 IndexModePost, LdMiscFrm, itin, 2720 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2721 []> { 2722 bits<10> offset; 2723 bits<4> addr; 2724 let Inst{23} = offset{8}; // U bit 2725 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2726 let Inst{19-16} = addr; 2727 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2728 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2729 let DecoderMethod = "DecodeAddrMode3Instruction"; 2730 } 2731} 2732 2733let mayLoad = 1, hasSideEffects = 0 in { 2734defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>; 2735defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>; 2736defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>; 2737let hasExtraDefRegAllocReq = 1 in { 2738def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2739 (ins addrmode3_pre:$addr), IndexModePre, 2740 LdMiscFrm, IIC_iLoad_d_ru, 2741 "ldrd", "\t$Rt, $Rt2, $addr!", 2742 "$addr.base = $Rn_wb", []> { 2743 bits<14> addr; 2744 let Inst{23} = addr{8}; // U bit 2745 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2746 let Inst{19-16} = addr{12-9}; // Rn 2747 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2748 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2749 let DecoderMethod = "DecodeAddrMode3Instruction"; 2750} 2751def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2752 (ins addr_offset_none:$addr, am3offset:$offset), 2753 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru, 2754 "ldrd", "\t$Rt, $Rt2, $addr, $offset", 2755 "$addr.base = $Rn_wb", []> { 2756 bits<10> offset; 2757 bits<4> addr; 2758 let Inst{23} = offset{8}; // U bit 2759 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2760 let Inst{19-16} = addr; 2761 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2762 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2763 let DecoderMethod = "DecodeAddrMode3Instruction"; 2764} 2765} // hasExtraDefRegAllocReq = 1 2766} // mayLoad = 1, hasSideEffects = 0 2767 2768// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT. 2769let mayLoad = 1, hasSideEffects = 0 in { 2770def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2771 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2772 IndexModePost, LdFrm, IIC_iLoad_ru, 2773 "ldrt", "\t$Rt, $addr, $offset", 2774 "$addr.base = $Rn_wb", []> { 2775 // {12} isAdd 2776 // {11-0} imm12/Rm 2777 bits<14> offset; 2778 bits<4> addr; 2779 let Inst{25} = 1; 2780 let Inst{23} = offset{12}; 2781 let Inst{21} = 1; // overwrite 2782 let Inst{19-16} = addr; 2783 let Inst{11-5} = offset{11-5}; 2784 let Inst{4} = 0; 2785 let Inst{3-0} = offset{3-0}; 2786 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2787} 2788 2789def LDRT_POST_IMM 2790 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2791 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2792 IndexModePost, LdFrm, IIC_iLoad_ru, 2793 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2794 // {12} isAdd 2795 // {11-0} imm12/Rm 2796 bits<14> offset; 2797 bits<4> addr; 2798 let Inst{25} = 0; 2799 let Inst{23} = offset{12}; 2800 let Inst{21} = 1; // overwrite 2801 let Inst{19-16} = addr; 2802 let Inst{11-0} = offset{11-0}; 2803 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2804} 2805 2806def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2807 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2808 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2809 "ldrbt", "\t$Rt, $addr, $offset", 2810 "$addr.base = $Rn_wb", []> { 2811 // {12} isAdd 2812 // {11-0} imm12/Rm 2813 bits<14> offset; 2814 bits<4> addr; 2815 let Inst{25} = 1; 2816 let Inst{23} = offset{12}; 2817 let Inst{21} = 1; // overwrite 2818 let Inst{19-16} = addr; 2819 let Inst{11-5} = offset{11-5}; 2820 let Inst{4} = 0; 2821 let Inst{3-0} = offset{3-0}; 2822 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2823} 2824 2825def LDRBT_POST_IMM 2826 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2827 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2828 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2829 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2830 // {12} isAdd 2831 // {11-0} imm12/Rm 2832 bits<14> offset; 2833 bits<4> addr; 2834 let Inst{25} = 0; 2835 let Inst{23} = offset{12}; 2836 let Inst{21} = 1; // overwrite 2837 let Inst{19-16} = addr; 2838 let Inst{11-0} = offset{11-0}; 2839 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2840} 2841 2842multiclass AI3ldrT<bits<4> op, string opc> { 2843 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb), 2844 (ins addr_offset_none:$addr, postidx_imm8:$offset), 2845 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2846 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 2847 bits<9> offset; 2848 let Inst{23} = offset{8}; 2849 let Inst{22} = 1; 2850 let Inst{11-8} = offset{7-4}; 2851 let Inst{3-0} = offset{3-0}; 2852 } 2853 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb), 2854 (ins addr_offset_none:$addr, postidx_reg:$Rm), 2855 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2856 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 2857 bits<5> Rm; 2858 let Inst{23} = Rm{4}; 2859 let Inst{22} = 0; 2860 let Inst{11-8} = 0; 2861 let Unpredictable{11-8} = 0b1111; 2862 let Inst{3-0} = Rm{3-0}; 2863 let DecoderMethod = "DecodeLDR"; 2864 } 2865} 2866 2867defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">; 2868defm LDRHT : AI3ldrT<0b1011, "ldrht">; 2869defm LDRSHT : AI3ldrT<0b1111, "ldrsht">; 2870} 2871 2872def LDRT_POST 2873 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2874 (outs GPR:$Rt)>; 2875 2876def LDRBT_POST 2877 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2878 (outs GPR:$Rt)>; 2879 2880// Pseudo instruction ldr Rt, =immediate 2881def LDRConstPool 2882 : ARMAsmPseudo<"ldr${q} $Rt, $immediate", 2883 (ins const_pool_asm_imm:$immediate, pred:$q), 2884 (outs GPR:$Rt)>; 2885 2886// Store 2887 2888// Stores with truncate 2889def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, 2890 IIC_iStore_bh_r, "strh", "\t$Rt, $addr", 2891 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>; 2892 2893// Store doubleword 2894let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 2895 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr), 2896 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>, 2897 Requires<[IsARM, HasV5TE]> { 2898 let Inst{21} = 0; 2899 } 2900} 2901 2902// Indexed stores 2903multiclass AI2_stridx<bit isByte, string opc, 2904 InstrItinClass iii, InstrItinClass iir> { 2905 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2906 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre, 2907 StFrm, iii, 2908 opc, "\t$Rt, $addr!", 2909 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2910 bits<17> addr; 2911 let Inst{25} = 0; 2912 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2913 let Inst{19-16} = addr{16-13}; // Rn 2914 let Inst{11-0} = addr{11-0}; // imm12 2915 let DecoderMethod = "DecodeSTRPreImm"; 2916 } 2917 2918 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2919 (ins GPR:$Rt, ldst_so_reg:$addr), 2920 IndexModePre, StFrm, iir, 2921 opc, "\t$Rt, $addr!", 2922 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2923 bits<17> addr; 2924 let Inst{25} = 1; 2925 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2926 let Inst{19-16} = addr{16-13}; // Rn 2927 let Inst{11-0} = addr{11-0}; 2928 let Inst{4} = 0; // Inst{4} = 0 2929 let DecoderMethod = "DecodeSTRPreReg"; 2930 } 2931 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2932 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2933 IndexModePost, StFrm, iir, 2934 opc, "\t$Rt, $addr, $offset", 2935 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2936 // {12} isAdd 2937 // {11-0} imm12/Rm 2938 bits<14> offset; 2939 bits<4> addr; 2940 let Inst{25} = 1; 2941 let Inst{23} = offset{12}; 2942 let Inst{19-16} = addr; 2943 let Inst{11-0} = offset{11-0}; 2944 let Inst{4} = 0; 2945 2946 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2947 } 2948 2949 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2950 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2951 IndexModePost, StFrm, iii, 2952 opc, "\t$Rt, $addr, $offset", 2953 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2954 // {12} isAdd 2955 // {11-0} imm12/Rm 2956 bits<14> offset; 2957 bits<4> addr; 2958 let Inst{25} = 0; 2959 let Inst{23} = offset{12}; 2960 let Inst{19-16} = addr; 2961 let Inst{11-0} = offset{11-0}; 2962 2963 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2964 } 2965} 2966 2967let mayStore = 1, hasSideEffects = 0 in { 2968// FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or 2969// IIC_iStore_siu depending on whether it the offset register is shifted. 2970defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>; 2971defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>; 2972} 2973 2974def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 2975 am2offset_reg:$offset), 2976 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr, 2977 am2offset_reg:$offset)>; 2978def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 2979 am2offset_imm:$offset), 2980 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr, 2981 am2offset_imm:$offset)>; 2982def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 2983 am2offset_reg:$offset), 2984 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr, 2985 am2offset_reg:$offset)>; 2986def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 2987 am2offset_imm:$offset), 2988 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr, 2989 am2offset_imm:$offset)>; 2990 2991// Pseudo-instructions for pattern matching the pre-indexed stores. We can't 2992// put the patterns on the instruction definitions directly as ISel wants 2993// the address base and offset to be separate operands, not a single 2994// complex operand like we represent the instructions themselves. The 2995// pseudos map between the two. 2996let usesCustomInserter = 1, 2997 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 2998def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2999 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 3000 4, IIC_iStore_ru, 3001 [(set GPR:$Rn_wb, 3002 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 3003def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3004 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 3005 4, IIC_iStore_ru, 3006 [(set GPR:$Rn_wb, 3007 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 3008def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3009 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 3010 4, IIC_iStore_ru, 3011 [(set GPR:$Rn_wb, 3012 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 3013def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3014 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 3015 4, IIC_iStore_ru, 3016 [(set GPR:$Rn_wb, 3017 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 3018def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3019 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p), 3020 4, IIC_iStore_ru, 3021 [(set GPR:$Rn_wb, 3022 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>; 3023} 3024 3025 3026 3027def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb), 3028 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre, 3029 StMiscFrm, IIC_iStore_bh_ru, 3030 "strh", "\t$Rt, $addr!", 3031 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3032 bits<14> addr; 3033 let Inst{23} = addr{8}; // U bit 3034 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 3035 let Inst{19-16} = addr{12-9}; // Rn 3036 let Inst{11-8} = addr{7-4}; // imm7_4/zero 3037 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 3038 let DecoderMethod = "DecodeAddrMode3Instruction"; 3039} 3040 3041def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb), 3042 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset), 3043 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, 3044 "strh", "\t$Rt, $addr, $offset", 3045 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", 3046 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt, 3047 addr_offset_none:$addr, 3048 am3offset:$offset))]> { 3049 bits<10> offset; 3050 bits<4> addr; 3051 let Inst{23} = offset{8}; // U bit 3052 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 3053 let Inst{19-16} = addr; 3054 let Inst{11-8} = offset{7-4}; // imm7_4/zero 3055 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 3056 let DecoderMethod = "DecodeAddrMode3Instruction"; 3057} 3058 3059let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 3060def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb), 3061 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr), 3062 IndexModePre, StMiscFrm, IIC_iStore_d_ru, 3063 "strd", "\t$Rt, $Rt2, $addr!", 3064 "$addr.base = $Rn_wb", []> { 3065 bits<14> addr; 3066 let Inst{23} = addr{8}; // U bit 3067 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 3068 let Inst{19-16} = addr{12-9}; // Rn 3069 let Inst{11-8} = addr{7-4}; // imm7_4/zero 3070 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 3071 let DecoderMethod = "DecodeAddrMode3Instruction"; 3072} 3073 3074def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb), 3075 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr, 3076 am3offset:$offset), 3077 IndexModePost, StMiscFrm, IIC_iStore_d_ru, 3078 "strd", "\t$Rt, $Rt2, $addr, $offset", 3079 "$addr.base = $Rn_wb", []> { 3080 bits<10> offset; 3081 bits<4> addr; 3082 let Inst{23} = offset{8}; // U bit 3083 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 3084 let Inst{19-16} = addr; 3085 let Inst{11-8} = offset{7-4}; // imm7_4/zero 3086 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 3087 let DecoderMethod = "DecodeAddrMode3Instruction"; 3088} 3089} // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 3090 3091// STRT, STRBT, and STRHT 3092 3093def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3094 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3095 IndexModePost, StFrm, IIC_iStore_bh_ru, 3096 "strbt", "\t$Rt, $addr, $offset", 3097 "$addr.base = $Rn_wb", []> { 3098 // {12} isAdd 3099 // {11-0} imm12/Rm 3100 bits<14> offset; 3101 bits<4> addr; 3102 let Inst{25} = 1; 3103 let Inst{23} = offset{12}; 3104 let Inst{21} = 1; // overwrite 3105 let Inst{19-16} = addr; 3106 let Inst{11-5} = offset{11-5}; 3107 let Inst{4} = 0; 3108 let Inst{3-0} = offset{3-0}; 3109 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3110} 3111 3112def STRBT_POST_IMM 3113 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3114 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3115 IndexModePost, StFrm, IIC_iStore_bh_ru, 3116 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3117 // {12} isAdd 3118 // {11-0} imm12/Rm 3119 bits<14> offset; 3120 bits<4> addr; 3121 let Inst{25} = 0; 3122 let Inst{23} = offset{12}; 3123 let Inst{21} = 1; // overwrite 3124 let Inst{19-16} = addr; 3125 let Inst{11-0} = offset{11-0}; 3126 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3127} 3128 3129def STRBT_POST 3130 : ARMAsmPseudo<"strbt${q} $Rt, $addr", 3131 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3132 3133let mayStore = 1, hasSideEffects = 0 in { 3134def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3135 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3136 IndexModePost, StFrm, IIC_iStore_ru, 3137 "strt", "\t$Rt, $addr, $offset", 3138 "$addr.base = $Rn_wb", []> { 3139 // {12} isAdd 3140 // {11-0} imm12/Rm 3141 bits<14> offset; 3142 bits<4> addr; 3143 let Inst{25} = 1; 3144 let Inst{23} = offset{12}; 3145 let Inst{21} = 1; // overwrite 3146 let Inst{19-16} = addr; 3147 let Inst{11-5} = offset{11-5}; 3148 let Inst{4} = 0; 3149 let Inst{3-0} = offset{3-0}; 3150 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3151} 3152 3153def STRT_POST_IMM 3154 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3155 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3156 IndexModePost, StFrm, IIC_iStore_ru, 3157 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3158 // {12} isAdd 3159 // {11-0} imm12/Rm 3160 bits<14> offset; 3161 bits<4> addr; 3162 let Inst{25} = 0; 3163 let Inst{23} = offset{12}; 3164 let Inst{21} = 1; // overwrite 3165 let Inst{19-16} = addr; 3166 let Inst{11-0} = offset{11-0}; 3167 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3168} 3169} 3170 3171def STRT_POST 3172 : ARMAsmPseudo<"strt${q} $Rt, $addr", 3173 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3174 3175multiclass AI3strT<bits<4> op, string opc> { 3176 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3177 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset), 3178 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3179 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 3180 bits<9> offset; 3181 let Inst{23} = offset{8}; 3182 let Inst{22} = 1; 3183 let Inst{11-8} = offset{7-4}; 3184 let Inst{3-0} = offset{3-0}; 3185 } 3186 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3187 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm), 3188 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3189 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 3190 bits<5> Rm; 3191 let Inst{23} = Rm{4}; 3192 let Inst{22} = 0; 3193 let Inst{11-8} = 0; 3194 let Inst{3-0} = Rm{3-0}; 3195 } 3196} 3197 3198 3199defm STRHT : AI3strT<0b1011, "strht">; 3200 3201def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3202 NoItinerary, "stl", "\t$Rt, $addr", []>; 3203def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3204 NoItinerary, "stlb", "\t$Rt, $addr", []>; 3205def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3206 NoItinerary, "stlh", "\t$Rt, $addr", []>; 3207 3208//===----------------------------------------------------------------------===// 3209// Load / store multiple Instructions. 3210// 3211 3212multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f, 3213 InstrItinClass itin, InstrItinClass itin_upd> { 3214 // IA is the default, so no need for an explicit suffix on the 3215 // mnemonic here. Without it is the canonical spelling. 3216 def IA : 3217 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3218 IndexModeNone, f, itin, 3219 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> { 3220 let Inst{24-23} = 0b01; // Increment After 3221 let Inst{22} = P_bit; 3222 let Inst{21} = 0; // No writeback 3223 let Inst{20} = L_bit; 3224 } 3225 def IA_UPD : 3226 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3227 IndexModeUpd, f, itin_upd, 3228 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3229 let Inst{24-23} = 0b01; // Increment After 3230 let Inst{22} = P_bit; 3231 let Inst{21} = 1; // Writeback 3232 let Inst{20} = L_bit; 3233 3234 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3235 } 3236 def DA : 3237 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3238 IndexModeNone, f, itin, 3239 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> { 3240 let Inst{24-23} = 0b00; // Decrement After 3241 let Inst{22} = P_bit; 3242 let Inst{21} = 0; // No writeback 3243 let Inst{20} = L_bit; 3244 } 3245 def DA_UPD : 3246 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3247 IndexModeUpd, f, itin_upd, 3248 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3249 let Inst{24-23} = 0b00; // Decrement After 3250 let Inst{22} = P_bit; 3251 let Inst{21} = 1; // Writeback 3252 let Inst{20} = L_bit; 3253 3254 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3255 } 3256 def DB : 3257 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3258 IndexModeNone, f, itin, 3259 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> { 3260 let Inst{24-23} = 0b10; // Decrement Before 3261 let Inst{22} = P_bit; 3262 let Inst{21} = 0; // No writeback 3263 let Inst{20} = L_bit; 3264 } 3265 def DB_UPD : 3266 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3267 IndexModeUpd, f, itin_upd, 3268 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3269 let Inst{24-23} = 0b10; // Decrement Before 3270 let Inst{22} = P_bit; 3271 let Inst{21} = 1; // Writeback 3272 let Inst{20} = L_bit; 3273 3274 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3275 } 3276 def IB : 3277 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3278 IndexModeNone, f, itin, 3279 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> { 3280 let Inst{24-23} = 0b11; // Increment Before 3281 let Inst{22} = P_bit; 3282 let Inst{21} = 0; // No writeback 3283 let Inst{20} = L_bit; 3284 } 3285 def IB_UPD : 3286 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3287 IndexModeUpd, f, itin_upd, 3288 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3289 let Inst{24-23} = 0b11; // Increment Before 3290 let Inst{22} = P_bit; 3291 let Inst{21} = 1; // Writeback 3292 let Inst{20} = L_bit; 3293 3294 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3295 } 3296} 3297 3298let hasSideEffects = 0 in { 3299 3300let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 3301defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m, 3302 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">; 3303 3304let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3305defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m, 3306 IIC_iStore_mu>, 3307 ComplexDeprecationPredicate<"ARMStore">; 3308 3309} // hasSideEffects 3310 3311// FIXME: remove when we have a way to marking a MI with these properties. 3312// FIXME: Should pc be an implicit operand like PICADD, etc? 3313let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 3314 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 3315def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 3316 reglist:$regs, variable_ops), 3317 4, IIC_iLoad_mBr, [], 3318 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 3319 RegConstraint<"$Rn = $wb">; 3320 3321let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 3322defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m, 3323 IIC_iLoad_mu>; 3324 3325let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3326defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m, 3327 IIC_iStore_mu>; 3328 3329 3330 3331//===----------------------------------------------------------------------===// 3332// Move Instructions. 3333// 3334 3335let hasSideEffects = 0 in 3336def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr, 3337 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3338 bits<4> Rd; 3339 bits<4> Rm; 3340 3341 let Inst{19-16} = 0b0000; 3342 let Inst{11-4} = 0b00000000; 3343 let Inst{25} = 0; 3344 let Inst{3-0} = Rm; 3345 let Inst{15-12} = Rd; 3346} 3347 3348// A version for the smaller set of tail call registers. 3349let hasSideEffects = 0 in 3350def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, 3351 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3352 bits<4> Rd; 3353 bits<4> Rm; 3354 3355 let Inst{11-4} = 0b00000000; 3356 let Inst{25} = 0; 3357 let Inst{3-0} = Rm; 3358 let Inst{15-12} = Rd; 3359} 3360 3361def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src), 3362 DPSoRegRegFrm, IIC_iMOVsr, 3363 "mov", "\t$Rd, $src", 3364 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP, 3365 Sched<[WriteALU]> { 3366 bits<4> Rd; 3367 bits<12> src; 3368 let Inst{15-12} = Rd; 3369 let Inst{19-16} = 0b0000; 3370 let Inst{11-8} = src{11-8}; 3371 let Inst{7} = 0; 3372 let Inst{6-5} = src{6-5}; 3373 let Inst{4} = 1; 3374 let Inst{3-0} = src{3-0}; 3375 let Inst{25} = 0; 3376} 3377 3378def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src), 3379 DPSoRegImmFrm, IIC_iMOVsr, 3380 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>, 3381 UnaryDP, Sched<[WriteALU]> { 3382 bits<4> Rd; 3383 bits<12> src; 3384 let Inst{15-12} = Rd; 3385 let Inst{19-16} = 0b0000; 3386 let Inst{11-5} = src{11-5}; 3387 let Inst{4} = 0; 3388 let Inst{3-0} = src{3-0}; 3389 let Inst{25} = 0; 3390} 3391 3392let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3393def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi, 3394 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP, 3395 Sched<[WriteALU]> { 3396 bits<4> Rd; 3397 bits<12> imm; 3398 let Inst{25} = 1; 3399 let Inst{15-12} = Rd; 3400 let Inst{19-16} = 0b0000; 3401 let Inst{11-0} = imm; 3402} 3403 3404let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3405def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm), 3406 DPFrm, IIC_iMOVi, 3407 "movw", "\t$Rd, $imm", 3408 [(set GPR:$Rd, imm0_65535:$imm)]>, 3409 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> { 3410 bits<4> Rd; 3411 bits<16> imm; 3412 let Inst{15-12} = Rd; 3413 let Inst{11-0} = imm{11-0}; 3414 let Inst{19-16} = imm{15-12}; 3415 let Inst{20} = 0; 3416 let Inst{25} = 1; 3417 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3418} 3419 3420def : InstAlias<"mov${p} $Rd, $imm", 3421 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p), 0>, 3422 Requires<[IsARM, HasV6T2]>; 3423 3424def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3425 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3426 Sched<[WriteALU]>; 3427 3428let Constraints = "$src = $Rd" in { 3429def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd), 3430 (ins GPR:$src, imm0_65535_expr:$imm), 3431 DPFrm, IIC_iMOVi, 3432 "movt", "\t$Rd, $imm", 3433 [(set GPRnopc:$Rd, 3434 (or (and GPR:$src, 0xffff), 3435 lo16AllZero:$imm))]>, UnaryDP, 3436 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> { 3437 bits<4> Rd; 3438 bits<16> imm; 3439 let Inst{15-12} = Rd; 3440 let Inst{11-0} = imm{11-0}; 3441 let Inst{19-16} = imm{15-12}; 3442 let Inst{20} = 0; 3443 let Inst{25} = 1; 3444 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3445} 3446 3447def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3448 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3449 Sched<[WriteALU]>; 3450 3451} // Constraints 3452 3453def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>, 3454 Requires<[IsARM, HasV6T2]>; 3455 3456let Uses = [CPSR] in 3457def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, 3458 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP, 3459 Requires<[IsARM]>, Sched<[WriteALU]>; 3460 3461// These aren't really mov instructions, but we have to define them this way 3462// due to flag operands. 3463 3464let Defs = [CPSR] in { 3465def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3466 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP, 3467 Sched<[WriteALU]>, Requires<[IsARM]>; 3468def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3469 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP, 3470 Sched<[WriteALU]>, Requires<[IsARM]>; 3471} 3472 3473//===----------------------------------------------------------------------===// 3474// Extend Instructions. 3475// 3476 3477// Sign extenders 3478 3479def SXTB : AI_ext_rrot<0b01101010, 3480 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 3481def SXTH : AI_ext_rrot<0b01101011, 3482 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 3483 3484def SXTAB : AI_exta_rrot<0b01101010, 3485 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 3486def SXTAH : AI_exta_rrot<0b01101011, 3487 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 3488 3489def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8)), 3490 (SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3491def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot), 3492 i16)), 3493 (SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3494 3495def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; 3496def : ARMV6Pat<(int_arm_sxtb16 GPR:$Src), 3497 (SXTB16 GPR:$Src, 0)>; 3498 3499def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; 3500def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, GPR:$RHS), 3501 (SXTAB16 GPR:$LHS, GPR:$RHS, 0)>; 3502 3503// Zero extenders 3504 3505let AddedComplexity = 16 in { 3506def UXTB : AI_ext_rrot<0b01101110, 3507 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 3508def UXTH : AI_ext_rrot<0b01101111, 3509 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 3510def UXTB16 : AI_ext_rrot<0b01101100, 3511 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 3512 3513// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 3514// The transformation should probably be done as a combiner action 3515// instead so we can include a check for masking back in the upper 3516// eight bits of the source into the lower eight bits of the result. 3517//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 3518// (UXTB16r_rot GPR:$Src, 3)>; 3519def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 3520 (UXTB16 GPR:$Src, 1)>; 3521def : ARMV6Pat<(int_arm_uxtb16 GPR:$Src), 3522 (UXTB16 GPR:$Src, 0)>; 3523 3524def UXTAB : AI_exta_rrot<0b01101110, "uxtab", 3525 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 3526def UXTAH : AI_exta_rrot<0b01101111, "uxtah", 3527 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 3528 3529def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 0xFF)), 3530 (UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3531def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 0xFFFF)), 3532 (UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3533} 3534 3535// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 3536def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; 3537def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, GPR:$RHS), 3538 (UXTAB16 GPR:$LHS, GPR:$RHS, 0)>; 3539 3540 3541def SBFX : I<(outs GPRnopc:$Rd), 3542 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3543 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3544 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3545 Requires<[IsARM, HasV6T2]> { 3546 bits<4> Rd; 3547 bits<4> Rn; 3548 bits<5> lsb; 3549 bits<5> width; 3550 let Inst{27-21} = 0b0111101; 3551 let Inst{6-4} = 0b101; 3552 let Inst{20-16} = width; 3553 let Inst{15-12} = Rd; 3554 let Inst{11-7} = lsb; 3555 let Inst{3-0} = Rn; 3556} 3557 3558def UBFX : I<(outs GPRnopc:$Rd), 3559 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3560 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3561 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3562 Requires<[IsARM, HasV6T2]> { 3563 bits<4> Rd; 3564 bits<4> Rn; 3565 bits<5> lsb; 3566 bits<5> width; 3567 let Inst{27-21} = 0b0111111; 3568 let Inst{6-4} = 0b101; 3569 let Inst{20-16} = width; 3570 let Inst{15-12} = Rd; 3571 let Inst{11-7} = lsb; 3572 let Inst{3-0} = Rn; 3573} 3574 3575//===----------------------------------------------------------------------===// 3576// Arithmetic Instructions. 3577// 3578 3579let isAdd = 1 in 3580defm ADD : AsI1_bin_irs<0b0100, "add", 3581 IIC_iALUi, IIC_iALUr, IIC_iALUsr, add, 1>; 3582defm SUB : AsI1_bin_irs<0b0010, "sub", 3583 IIC_iALUi, IIC_iALUr, IIC_iALUsr, sub>; 3584 3585// ADD and SUB with 's' bit set. 3586// 3587// Currently, ADDS/SUBS are pseudo opcodes that exist only in the 3588// selection DAG. They are "lowered" to real ADD/SUB opcodes by 3589// AdjustInstrPostInstrSelection where we determine whether or not to 3590// set the "s" bit based on CPSR liveness. 3591// 3592// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen 3593// support for an optional CPSR definition that corresponds to the DAG 3594// node's second value. We can then eliminate the implicit def of CPSR. 3595let isAdd = 1 in 3596defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMaddc, 1>; 3597defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>; 3598 3599let isAdd = 1 in 3600defm ADC : AI1_adde_sube_irs<0b0101, "adc", ARMadde, 1>; 3601defm SBC : AI1_adde_sube_irs<0b0110, "sbc", ARMsube>; 3602 3603defm RSB : AsI1_rbin_irs<0b0011, "rsb", 3604 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3605 sub>; 3606 3607// FIXME: Eliminate them if we can write def : Pat patterns which defines 3608// CPSR and the implicit def of CPSR is not needed. 3609defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>; 3610 3611defm RSC : AI1_rsc_irs<0b0111, "rsc", ARMsube>; 3612 3613// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 3614// The assume-no-carry-in form uses the negation of the input since add/sub 3615// assume opposite meanings of the carry flag (i.e., carry == !borrow). 3616// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 3617// details. 3618def : ARMPat<(add GPR:$src, mod_imm_neg:$imm), 3619 (SUBri GPR:$src, mod_imm_neg:$imm)>; 3620def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm), 3621 (SUBSri GPR:$src, mod_imm_neg:$imm)>; 3622 3623def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm), 3624 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3625 Requires<[IsARM, HasV6T2]>; 3626def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm), 3627 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3628 Requires<[IsARM, HasV6T2]>; 3629 3630// The with-carry-in form matches bitwise not instead of the negation. 3631// Effectively, the inverse interpretation of the carry flag already accounts 3632// for part of the negation. 3633def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR), 3634 (SBCri GPR:$src, mod_imm_not:$imm)>; 3635def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR), 3636 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>, 3637 Requires<[IsARM, HasV6T2]>; 3638 3639// Note: These are implemented in C++ code, because they have to generate 3640// ADD/SUBrs instructions, which use a complex pattern that a xform function 3641// cannot produce. 3642// (mul X, 2^n+1) -> (add (X << n), X) 3643// (mul X, 2^n-1) -> (rsb X, (X << n)) 3644 3645// ARM Arithmetic Instruction 3646// GPR:$dst = GPR:$a op GPR:$b 3647class AAI<bits<8> op27_20, bits<8> op11_4, string opc, 3648 list<dag> pattern = [], 3649 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm), 3650 string asm = "\t$Rd, $Rn, $Rm"> 3651 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>, 3652 Sched<[WriteALU, ReadALU, ReadALU]> { 3653 bits<4> Rn; 3654 bits<4> Rd; 3655 bits<4> Rm; 3656 let Inst{27-20} = op27_20; 3657 let Inst{11-4} = op11_4; 3658 let Inst{19-16} = Rn; 3659 let Inst{15-12} = Rd; 3660 let Inst{3-0} = Rm; 3661 3662 let Unpredictable{11-8} = 0b1111; 3663} 3664 3665// Wrappers around the AAI class 3666class AAIRevOpr<bits<8> op27_20, bits<8> op11_4, string opc, 3667 list<dag> pattern = []> 3668 : AAI<op27_20, op11_4, opc, 3669 pattern, 3670 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3671 "\t$Rd, $Rm, $Rn">; 3672 3673class AAIIntrinsic<bits<8> op27_20, bits<8> op11_4, string opc, 3674 Intrinsic intrinsic> 3675 : AAI<op27_20, op11_4, opc, 3676 [(set GPRnopc:$Rd, (intrinsic GPRnopc:$Rn, GPRnopc:$Rm))]>; 3677 3678// Saturating add/subtract 3679let hasSideEffects = 1 in { 3680def QADD8 : AAIIntrinsic<0b01100010, 0b11111001, "qadd8", int_arm_qadd8>; 3681def QADD16 : AAIIntrinsic<0b01100010, 0b11110001, "qadd16", int_arm_qadd16>; 3682def QSUB16 : AAIIntrinsic<0b01100010, 0b11110111, "qsub16", int_arm_qsub16>; 3683def QSUB8 : AAIIntrinsic<0b01100010, 0b11111111, "qsub8", int_arm_qsub8>; 3684 3685def QDADD : AAIRevOpr<0b00010100, 0b00000101, "qdadd", 3686 [(set GPRnopc:$Rd, (int_arm_qadd (int_arm_qadd GPRnopc:$Rm, 3687 GPRnopc:$Rm), 3688 GPRnopc:$Rn))]>; 3689def QDSUB : AAIRevOpr<0b00010110, 0b00000101, "qdsub", 3690 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, 3691 (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>; 3692def QSUB : AAIRevOpr<0b00010010, 0b00000101, "qsub", 3693 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))]>; 3694let DecoderMethod = "DecodeQADDInstruction" in 3695 def QADD : AAIRevOpr<0b00010000, 0b00000101, "qadd", 3696 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))]>; 3697} 3698 3699def UQADD16 : AAIIntrinsic<0b01100110, 0b11110001, "uqadd16", int_arm_uqadd16>; 3700def UQADD8 : AAIIntrinsic<0b01100110, 0b11111001, "uqadd8", int_arm_uqadd8>; 3701def UQSUB16 : AAIIntrinsic<0b01100110, 0b11110111, "uqsub16", int_arm_uqsub16>; 3702def UQSUB8 : AAIIntrinsic<0b01100110, 0b11111111, "uqsub8", int_arm_uqsub8>; 3703def QASX : AAIIntrinsic<0b01100010, 0b11110011, "qasx", int_arm_qasx>; 3704def QSAX : AAIIntrinsic<0b01100010, 0b11110101, "qsax", int_arm_qsax>; 3705def UQASX : AAIIntrinsic<0b01100110, 0b11110011, "uqasx", int_arm_uqasx>; 3706def UQSAX : AAIIntrinsic<0b01100110, 0b11110101, "uqsax", int_arm_uqsax>; 3707 3708// Signed/Unsigned add/subtract 3709 3710def SASX : AAIIntrinsic<0b01100001, 0b11110011, "sasx", int_arm_sasx>; 3711def SADD16 : AAIIntrinsic<0b01100001, 0b11110001, "sadd16", int_arm_sadd16>; 3712def SADD8 : AAIIntrinsic<0b01100001, 0b11111001, "sadd8", int_arm_sadd8>; 3713def SSAX : AAIIntrinsic<0b01100001, 0b11110101, "ssax", int_arm_ssax>; 3714def SSUB16 : AAIIntrinsic<0b01100001, 0b11110111, "ssub16", int_arm_ssub16>; 3715def SSUB8 : AAIIntrinsic<0b01100001, 0b11111111, "ssub8", int_arm_ssub8>; 3716def UASX : AAIIntrinsic<0b01100101, 0b11110011, "uasx", int_arm_uasx>; 3717def UADD16 : AAIIntrinsic<0b01100101, 0b11110001, "uadd16", int_arm_uadd16>; 3718def UADD8 : AAIIntrinsic<0b01100101, 0b11111001, "uadd8", int_arm_uadd8>; 3719def USAX : AAIIntrinsic<0b01100101, 0b11110101, "usax", int_arm_usax>; 3720def USUB16 : AAIIntrinsic<0b01100101, 0b11110111, "usub16", int_arm_usub16>; 3721def USUB8 : AAIIntrinsic<0b01100101, 0b11111111, "usub8", int_arm_usub8>; 3722 3723// Signed/Unsigned halving add/subtract 3724 3725def SHASX : AAIIntrinsic<0b01100011, 0b11110011, "shasx", int_arm_shasx>; 3726def SHADD16 : AAIIntrinsic<0b01100011, 0b11110001, "shadd16", int_arm_shadd16>; 3727def SHADD8 : AAIIntrinsic<0b01100011, 0b11111001, "shadd8", int_arm_shadd8>; 3728def SHSAX : AAIIntrinsic<0b01100011, 0b11110101, "shsax", int_arm_shsax>; 3729def SHSUB16 : AAIIntrinsic<0b01100011, 0b11110111, "shsub16", int_arm_shsub16>; 3730def SHSUB8 : AAIIntrinsic<0b01100011, 0b11111111, "shsub8", int_arm_shsub8>; 3731def UHASX : AAIIntrinsic<0b01100111, 0b11110011, "uhasx", int_arm_uhasx>; 3732def UHADD16 : AAIIntrinsic<0b01100111, 0b11110001, "uhadd16", int_arm_uhadd16>; 3733def UHADD8 : AAIIntrinsic<0b01100111, 0b11111001, "uhadd8", int_arm_uhadd8>; 3734def UHSAX : AAIIntrinsic<0b01100111, 0b11110101, "uhsax", int_arm_uhsax>; 3735def UHSUB16 : AAIIntrinsic<0b01100111, 0b11110111, "uhsub16", int_arm_uhsub16>; 3736def UHSUB8 : AAIIntrinsic<0b01100111, 0b11111111, "uhsub8", int_arm_uhsub8>; 3737 3738// Unsigned Sum of Absolute Differences [and Accumulate]. 3739 3740def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3741 MulFrm /* for convenience */, NoItinerary, "usad8", 3742 "\t$Rd, $Rn, $Rm", 3743 [(set GPR:$Rd, (int_arm_usad8 GPR:$Rn, GPR:$Rm))]>, 3744 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> { 3745 bits<4> Rd; 3746 bits<4> Rn; 3747 bits<4> Rm; 3748 let Inst{27-20} = 0b01111000; 3749 let Inst{15-12} = 0b1111; 3750 let Inst{7-4} = 0b0001; 3751 let Inst{19-16} = Rd; 3752 let Inst{11-8} = Rm; 3753 let Inst{3-0} = Rn; 3754} 3755def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3756 MulFrm /* for convenience */, NoItinerary, "usada8", 3757 "\t$Rd, $Rn, $Rm, $Ra", 3758 [(set GPR:$Rd, (int_arm_usada8 GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 3759 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{ 3760 bits<4> Rd; 3761 bits<4> Rn; 3762 bits<4> Rm; 3763 bits<4> Ra; 3764 let Inst{27-20} = 0b01111000; 3765 let Inst{7-4} = 0b0001; 3766 let Inst{19-16} = Rd; 3767 let Inst{15-12} = Ra; 3768 let Inst{11-8} = Rm; 3769 let Inst{3-0} = Rn; 3770} 3771 3772// Signed/Unsigned saturate 3773def SSAT : AI<(outs GPRnopc:$Rd), 3774 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3775 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>, 3776 Requires<[IsARM,HasV6]>{ 3777 bits<4> Rd; 3778 bits<5> sat_imm; 3779 bits<4> Rn; 3780 bits<8> sh; 3781 let Inst{27-21} = 0b0110101; 3782 let Inst{5-4} = 0b01; 3783 let Inst{20-16} = sat_imm; 3784 let Inst{15-12} = Rd; 3785 let Inst{11-7} = sh{4-0}; 3786 let Inst{6} = sh{5}; 3787 let Inst{3-0} = Rn; 3788} 3789 3790def SSAT16 : AI<(outs GPRnopc:$Rd), 3791 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm, 3792 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []>, 3793 Requires<[IsARM,HasV6]>{ 3794 bits<4> Rd; 3795 bits<4> sat_imm; 3796 bits<4> Rn; 3797 let Inst{27-20} = 0b01101010; 3798 let Inst{11-4} = 0b11110011; 3799 let Inst{15-12} = Rd; 3800 let Inst{19-16} = sat_imm; 3801 let Inst{3-0} = Rn; 3802} 3803 3804def USAT : AI<(outs GPRnopc:$Rd), 3805 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3806 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>, 3807 Requires<[IsARM,HasV6]> { 3808 bits<4> Rd; 3809 bits<5> sat_imm; 3810 bits<4> Rn; 3811 bits<8> sh; 3812 let Inst{27-21} = 0b0110111; 3813 let Inst{5-4} = 0b01; 3814 let Inst{15-12} = Rd; 3815 let Inst{11-7} = sh{4-0}; 3816 let Inst{6} = sh{5}; 3817 let Inst{20-16} = sat_imm; 3818 let Inst{3-0} = Rn; 3819} 3820 3821def USAT16 : AI<(outs GPRnopc:$Rd), 3822 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm, 3823 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []>, 3824 Requires<[IsARM,HasV6]>{ 3825 bits<4> Rd; 3826 bits<4> sat_imm; 3827 bits<4> Rn; 3828 let Inst{27-20} = 0b01101110; 3829 let Inst{11-4} = 0b11110011; 3830 let Inst{15-12} = Rd; 3831 let Inst{19-16} = sat_imm; 3832 let Inst{3-0} = Rn; 3833} 3834 3835def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos), 3836 (SSAT imm1_32:$pos, GPRnopc:$a, 0)>; 3837def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos), 3838 (USAT imm0_31:$pos, GPRnopc:$a, 0)>; 3839def : ARMPat<(ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm), 3840 (SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 3841def : ARMV6Pat<(int_arm_ssat16 GPRnopc:$a, imm1_16:$pos), 3842 (SSAT16 imm1_16:$pos, GPRnopc:$a)>; 3843def : ARMV6Pat<(int_arm_usat16 GPRnopc:$a, imm0_15:$pos), 3844 (USAT16 imm0_15:$pos, GPRnopc:$a)>; 3845 3846//===----------------------------------------------------------------------===// 3847// Bitwise Instructions. 3848// 3849 3850defm AND : AsI1_bin_irs<0b0000, "and", 3851 IIC_iBITi, IIC_iBITr, IIC_iBITsr, and, 1>; 3852defm ORR : AsI1_bin_irs<0b1100, "orr", 3853 IIC_iBITi, IIC_iBITr, IIC_iBITsr, or, 1>; 3854defm EOR : AsI1_bin_irs<0b0001, "eor", 3855 IIC_iBITi, IIC_iBITr, IIC_iBITsr, xor, 1>; 3856defm BIC : AsI1_bin_irs<0b1110, "bic", 3857 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3858 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 3859 3860// FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just 3861// like in the actual instruction encoding. The complexity of mapping the mask 3862// to the lsb/msb pair should be handled by ISel, not encapsulated in the 3863// instruction description. 3864def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), 3865 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3866 "bfc", "\t$Rd, $imm", "$src = $Rd", 3867 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>, 3868 Requires<[IsARM, HasV6T2]> { 3869 bits<4> Rd; 3870 bits<10> imm; 3871 let Inst{27-21} = 0b0111110; 3872 let Inst{6-0} = 0b0011111; 3873 let Inst{15-12} = Rd; 3874 let Inst{11-7} = imm{4-0}; // lsb 3875 let Inst{20-16} = imm{9-5}; // msb 3876} 3877 3878// A8.6.18 BFI - Bitfield insert (Encoding A1) 3879def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm), 3880 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3881 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd", 3882 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn, 3883 bf_inv_mask_imm:$imm))]>, 3884 Requires<[IsARM, HasV6T2]> { 3885 bits<4> Rd; 3886 bits<4> Rn; 3887 bits<10> imm; 3888 let Inst{27-21} = 0b0111110; 3889 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 3890 let Inst{15-12} = Rd; 3891 let Inst{11-7} = imm{4-0}; // lsb 3892 let Inst{20-16} = imm{9-5}; // width 3893 let Inst{3-0} = Rn; 3894} 3895 3896def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr, 3897 "mvn", "\t$Rd, $Rm", 3898 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> { 3899 bits<4> Rd; 3900 bits<4> Rm; 3901 let Inst{25} = 0; 3902 let Inst{19-16} = 0b0000; 3903 let Inst{11-4} = 0b00000000; 3904 let Inst{15-12} = Rd; 3905 let Inst{3-0} = Rm; 3906} 3907def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift), 3908 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3909 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP, 3910 Sched<[WriteALU]> { 3911 bits<4> Rd; 3912 bits<12> shift; 3913 let Inst{25} = 0; 3914 let Inst{19-16} = 0b0000; 3915 let Inst{15-12} = Rd; 3916 let Inst{11-5} = shift{11-5}; 3917 let Inst{4} = 0; 3918 let Inst{3-0} = shift{3-0}; 3919} 3920def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift), 3921 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3922 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP, 3923 Sched<[WriteALU]> { 3924 bits<4> Rd; 3925 bits<12> shift; 3926 let Inst{25} = 0; 3927 let Inst{19-16} = 0b0000; 3928 let Inst{15-12} = Rd; 3929 let Inst{11-8} = shift{11-8}; 3930 let Inst{7} = 0; 3931 let Inst{6-5} = shift{6-5}; 3932 let Inst{4} = 1; 3933 let Inst{3-0} = shift{3-0}; 3934} 3935let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3936def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, 3937 IIC_iMVNi, "mvn", "\t$Rd, $imm", 3938 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> { 3939 bits<4> Rd; 3940 bits<12> imm; 3941 let Inst{25} = 1; 3942 let Inst{19-16} = 0b0000; 3943 let Inst{15-12} = Rd; 3944 let Inst{11-0} = imm; 3945} 3946 3947let AddedComplexity = 1 in 3948def : ARMPat<(and GPR:$src, mod_imm_not:$imm), 3949 (BICri GPR:$src, mod_imm_not:$imm)>; 3950 3951//===----------------------------------------------------------------------===// 3952// Multiply Instructions. 3953// 3954class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3955 string opc, string asm, list<dag> pattern> 3956 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3957 bits<4> Rd; 3958 bits<4> Rm; 3959 bits<4> Rn; 3960 let Inst{19-16} = Rd; 3961 let Inst{11-8} = Rm; 3962 let Inst{3-0} = Rn; 3963} 3964class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3965 string opc, string asm, list<dag> pattern> 3966 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3967 bits<4> RdLo; 3968 bits<4> RdHi; 3969 bits<4> Rm; 3970 bits<4> Rn; 3971 let Inst{19-16} = RdHi; 3972 let Inst{15-12} = RdLo; 3973 let Inst{11-8} = Rm; 3974 let Inst{3-0} = Rn; 3975} 3976class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3977 string opc, string asm, list<dag> pattern> 3978 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3979 bits<4> RdLo; 3980 bits<4> RdHi; 3981 bits<4> Rm; 3982 bits<4> Rn; 3983 let Inst{19-16} = RdHi; 3984 let Inst{15-12} = RdLo; 3985 let Inst{11-8} = Rm; 3986 let Inst{3-0} = Rn; 3987} 3988 3989// FIXME: The v5 pseudos are only necessary for the additional Constraint 3990// property. Remove them when it's possible to add those properties 3991// on an individual MachineInstr, not just an instruction description. 3992let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in { 3993def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), 3994 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3995 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", 3996 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>, 3997 Requires<[IsARM, HasV6]>, 3998 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 3999 let Inst{15-12} = 0b0000; 4000 let Unpredictable{15-12} = 0b1111; 4001} 4002 4003let Constraints = "@earlyclobber $Rd" in 4004def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, 4005 pred:$p, cc_out:$s), 4006 4, IIC_iMUL32, 4007 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))], 4008 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 4009 Requires<[IsARM, NoV6, UseMulOps]>, 4010 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4011} 4012 4013def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd), 4014 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra), 4015 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra", 4016 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>, 4017 Requires<[IsARM, HasV6, UseMulOps]>, 4018 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 4019 bits<4> Ra; 4020 let Inst{15-12} = Ra; 4021} 4022 4023let Constraints = "@earlyclobber $Rd" in 4024def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd), 4025 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 4026 pred:$p, cc_out:$s), 4, IIC_iMAC32, 4027 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))], 4028 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>, 4029 Requires<[IsARM, NoV6]>, 4030 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4031 4032def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4033 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra", 4034 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>, 4035 Requires<[IsARM, HasV6T2, UseMulOps]>, 4036 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 4037 bits<4> Rd; 4038 bits<4> Rm; 4039 bits<4> Rn; 4040 bits<4> Ra; 4041 let Inst{19-16} = Rd; 4042 let Inst{15-12} = Ra; 4043 let Inst{11-8} = Rm; 4044 let Inst{3-0} = Rn; 4045} 4046 4047// Extra precision multiplies with low / high results 4048let hasSideEffects = 0 in { 4049let isCommutable = 1 in { 4050def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi), 4051 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 4052 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", 4053 [(set GPR:$RdLo, GPR:$RdHi, 4054 (smullohi GPR:$Rn, GPR:$Rm))]>, 4055 Requires<[IsARM, HasV6]>, 4056 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4057 4058def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), 4059 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 4060 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", 4061 [(set GPR:$RdLo, GPR:$RdHi, 4062 (umullohi GPR:$Rn, GPR:$Rm))]>, 4063 Requires<[IsARM, HasV6]>, 4064 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL]>; 4065 4066let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { 4067def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4068 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 4069 4, IIC_iMUL64, 4070 [(set GPR:$RdLo, GPR:$RdHi, 4071 (smullohi GPR:$Rn, GPR:$Rm))], 4072 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 4073 Requires<[IsARM, NoV6]>, 4074 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4075 4076def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4077 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 4078 4, IIC_iMUL64, 4079 [(set GPR:$RdLo, GPR:$RdHi, 4080 (umullohi GPR:$Rn, GPR:$Rm))], 4081 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 4082 Requires<[IsARM, NoV6]>, 4083 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4084} 4085} 4086 4087// Multiply + accumulate 4088def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi), 4089 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4090 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4091 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4092 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4093def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi), 4094 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4095 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4096 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4097 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4098 4099def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi), 4100 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4101 IIC_iMAC64, 4102 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4103 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4104 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> { 4105 bits<4> RdLo; 4106 bits<4> RdHi; 4107 bits<4> Rm; 4108 bits<4> Rn; 4109 let Inst{19-16} = RdHi; 4110 let Inst{15-12} = RdLo; 4111 let Inst{11-8} = Rm; 4112 let Inst{3-0} = Rn; 4113} 4114 4115let Constraints = 4116 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in { 4117def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4118 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4119 4, IIC_iMAC64, [], 4120 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4121 pred:$p, cc_out:$s)>, 4122 Requires<[IsARM, NoV6]>, 4123 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4124def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4125 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4126 4, IIC_iMAC64, [], 4127 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4128 pred:$p, cc_out:$s)>, 4129 Requires<[IsARM, NoV6]>, 4130 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4131} 4132 4133} // hasSideEffects 4134 4135// Most significant word multiply 4136def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4137 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm", 4138 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>, 4139 Requires<[IsARM, HasV6]>, 4140 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4141 let Inst{15-12} = 0b1111; 4142} 4143 4144def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4145 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>, 4146 Requires<[IsARM, HasV6]>, 4147 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4148 let Inst{15-12} = 0b1111; 4149} 4150 4151def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd), 4152 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4153 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra", 4154 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, 4155 Requires<[IsARM, HasV6, UseMulOps]>, 4156 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4157 4158def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd), 4159 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4160 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>, 4161 Requires<[IsARM, HasV6]>, 4162 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4163 4164def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd), 4165 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4166 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>, 4167 Requires<[IsARM, HasV6, UseMulOps]>, 4168 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4169 4170def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd), 4171 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4172 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>, 4173 Requires<[IsARM, HasV6]>, 4174 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4175 4176multiclass AI_smul<string opc> { 4177 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4178 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 4179 [(set GPR:$Rd, (mul (sext_inreg GPR:$Rn, i16), 4180 (sext_inreg GPR:$Rm, i16)))]>, 4181 Requires<[IsARM, HasV5TE]>, 4182 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4183 4184 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4185 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 4186 [(set GPR:$Rd, (mul (sext_inreg GPR:$Rn, i16), 4187 (sra GPR:$Rm, (i32 16))))]>, 4188 Requires<[IsARM, HasV5TE]>, 4189 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4190 4191 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4192 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 4193 [(set GPR:$Rd, (mul (sra GPR:$Rn, (i32 16)), 4194 (sext_inreg GPR:$Rm, i16)))]>, 4195 Requires<[IsARM, HasV5TE]>, 4196 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4197 4198 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4199 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 4200 [(set GPR:$Rd, (mul (sra GPR:$Rn, (i32 16)), 4201 (sra GPR:$Rm, (i32 16))))]>, 4202 Requires<[IsARM, HasV5TE]>, 4203 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4204 4205 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4206 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 4207 [(set GPR:$Rd, (ARMsmulwb GPR:$Rn, GPR:$Rm))]>, 4208 Requires<[IsARM, HasV5TE]>, 4209 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4210 4211 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4212 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 4213 [(set GPR:$Rd, (ARMsmulwt GPR:$Rn, GPR:$Rm))]>, 4214 Requires<[IsARM, HasV5TE]>, 4215 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4216} 4217 4218 4219multiclass AI_smla<string opc> { 4220 let DecoderMethod = "DecodeSMLAInstruction" in { 4221 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd), 4222 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4223 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 4224 [(set GPRnopc:$Rd, (add GPR:$Ra, 4225 (mul (sext_inreg GPRnopc:$Rn, i16), 4226 (sext_inreg GPRnopc:$Rm, i16))))]>, 4227 Requires<[IsARM, HasV5TE, UseMulOps]>, 4228 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4229 4230 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd), 4231 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4232 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 4233 [(set GPRnopc:$Rd, 4234 (add GPR:$Ra, (mul (sext_inreg GPRnopc:$Rn, i16), 4235 (sra GPRnopc:$Rm, (i32 16)))))]>, 4236 Requires<[IsARM, HasV5TE, UseMulOps]>, 4237 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4238 4239 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd), 4240 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4241 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 4242 [(set GPRnopc:$Rd, 4243 (add GPR:$Ra, (mul (sra GPRnopc:$Rn, (i32 16)), 4244 (sext_inreg GPRnopc:$Rm, i16))))]>, 4245 Requires<[IsARM, HasV5TE, UseMulOps]>, 4246 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4247 4248 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd), 4249 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4250 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 4251 [(set GPRnopc:$Rd, 4252 (add GPR:$Ra, (mul (sra GPRnopc:$Rn, (i32 16)), 4253 (sra GPRnopc:$Rm, (i32 16)))))]>, 4254 Requires<[IsARM, HasV5TE, UseMulOps]>, 4255 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4256 4257 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd), 4258 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4259 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 4260 [(set GPRnopc:$Rd, 4261 (add GPR:$Ra, (ARMsmulwb GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4262 Requires<[IsARM, HasV5TE, UseMulOps]>, 4263 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4264 4265 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd), 4266 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4267 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 4268 [(set GPRnopc:$Rd, 4269 (add GPR:$Ra, (ARMsmulwt GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4270 Requires<[IsARM, HasV5TE, UseMulOps]>, 4271 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4272 } 4273} 4274 4275defm SMUL : AI_smul<"smul">; 4276defm SMLA : AI_smla<"smla">; 4277 4278// Halfword multiply accumulate long: SMLAL<x><y>. 4279class SMLAL<bits<2> opc1, string asm> 4280 : AMulxyI64<0b0001010, opc1, 4281 (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4282 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4283 IIC_iMAC64, asm, "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4284 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4285 Requires<[IsARM, HasV5TE]>, 4286 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4287 4288def SMLALBB : SMLAL<0b00, "smlalbb">; 4289def SMLALBT : SMLAL<0b10, "smlalbt">; 4290def SMLALTB : SMLAL<0b01, "smlaltb">; 4291def SMLALTT : SMLAL<0b11, "smlaltt">; 4292 4293def : ARMV5TEPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4294 (SMLALBB $Rn, $Rm, $RLo, $RHi)>; 4295def : ARMV5TEPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4296 (SMLALBT $Rn, $Rm, $RLo, $RHi)>; 4297def : ARMV5TEPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4298 (SMLALTB $Rn, $Rm, $RLo, $RHi)>; 4299def : ARMV5TEPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4300 (SMLALTT $Rn, $Rm, $RLo, $RHi)>; 4301 4302// Helper class for AI_smld. 4303class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops, 4304 InstrItinClass itin, string opc, string asm> 4305 : AI<oops, iops, MulFrm, itin, opc, asm, []>, 4306 Requires<[IsARM, HasV6]> { 4307 bits<4> Rn; 4308 bits<4> Rm; 4309 let Inst{27-23} = 0b01110; 4310 let Inst{22} = long; 4311 let Inst{21-20} = 0b00; 4312 let Inst{11-8} = Rm; 4313 let Inst{7} = 0; 4314 let Inst{6} = sub; 4315 let Inst{5} = swap; 4316 let Inst{4} = 1; 4317 let Inst{3-0} = Rn; 4318} 4319class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops, 4320 InstrItinClass itin, string opc, string asm> 4321 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4322 bits<4> Rd; 4323 let Inst{15-12} = 0b1111; 4324 let Inst{19-16} = Rd; 4325} 4326class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops, 4327 InstrItinClass itin, string opc, string asm> 4328 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4329 bits<4> Ra; 4330 bits<4> Rd; 4331 let Inst{19-16} = Rd; 4332 let Inst{15-12} = Ra; 4333} 4334class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops, 4335 InstrItinClass itin, string opc, string asm> 4336 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4337 bits<4> RdLo; 4338 bits<4> RdHi; 4339 let Inst{19-16} = RdHi; 4340 let Inst{15-12} = RdLo; 4341} 4342 4343multiclass AI_smld<bit sub, string opc> { 4344 4345 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd), 4346 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4347 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">, 4348 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4349 4350 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd), 4351 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4352 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">, 4353 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4354 4355 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4356 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4357 NoItinerary, 4358 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">, 4359 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4360 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4361 4362 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4363 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4364 NoItinerary, 4365 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">, 4366 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4367 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4368} 4369 4370defm SMLA : AI_smld<0, "smla">; 4371defm SMLS : AI_smld<1, "smls">; 4372 4373def : ARMV6Pat<(int_arm_smlad GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4374 (SMLAD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4375def : ARMV6Pat<(int_arm_smladx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4376 (SMLADX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4377def : ARMV6Pat<(int_arm_smlsd GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4378 (SMLSD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4379def : ARMV6Pat<(int_arm_smlsdx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4380 (SMLSDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4381def : ARMV6Pat<(ARMSmlald GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4382 (SMLALD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4383def : ARMV6Pat<(ARMSmlaldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4384 (SMLALDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4385def : ARMV6Pat<(ARMSmlsld GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4386 (SMLSLD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4387def : ARMV6Pat<(ARMSmlsldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4388 (SMLSLDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4389 4390multiclass AI_sdml<bit sub, string opc> { 4391 4392 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), 4393 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">, 4394 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4395 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm), 4396 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">, 4397 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4398} 4399 4400defm SMUA : AI_sdml<0, "smua">; 4401defm SMUS : AI_sdml<1, "smus">; 4402 4403def : ARMV6Pat<(int_arm_smuad GPRnopc:$Rn, GPRnopc:$Rm), 4404 (SMUAD GPRnopc:$Rn, GPRnopc:$Rm)>; 4405def : ARMV6Pat<(int_arm_smuadx GPRnopc:$Rn, GPRnopc:$Rm), 4406 (SMUADX GPRnopc:$Rn, GPRnopc:$Rm)>; 4407def : ARMV6Pat<(int_arm_smusd GPRnopc:$Rn, GPRnopc:$Rm), 4408 (SMUSD GPRnopc:$Rn, GPRnopc:$Rm)>; 4409def : ARMV6Pat<(int_arm_smusdx GPRnopc:$Rn, GPRnopc:$Rm), 4410 (SMUSDX GPRnopc:$Rn, GPRnopc:$Rm)>; 4411 4412//===----------------------------------------------------------------------===// 4413// Division Instructions (ARMv7-A with virtualization extension) 4414// 4415def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4416 "sdiv", "\t$Rd, $Rn, $Rm", 4417 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>, 4418 Requires<[IsARM, HasDivideInARM]>, 4419 Sched<[WriteDIV]>; 4420 4421def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4422 "udiv", "\t$Rd, $Rn, $Rm", 4423 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>, 4424 Requires<[IsARM, HasDivideInARM]>, 4425 Sched<[WriteDIV]>; 4426 4427//===----------------------------------------------------------------------===// 4428// Misc. Arithmetic Instructions. 4429// 4430 4431def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm), 4432 IIC_iUNAr, "clz", "\t$Rd, $Rm", 4433 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>, 4434 Sched<[WriteALU]>; 4435 4436def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4437 IIC_iUNAr, "rbit", "\t$Rd, $Rm", 4438 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>, 4439 Requires<[IsARM, HasV6T2]>, 4440 Sched<[WriteALU]>; 4441 4442def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4443 IIC_iUNAr, "rev", "\t$Rd, $Rm", 4444 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>, 4445 Sched<[WriteALU]>; 4446 4447let AddedComplexity = 5 in 4448def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4449 IIC_iUNAr, "rev16", "\t$Rd, $Rm", 4450 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>, 4451 Requires<[IsARM, HasV6]>, 4452 Sched<[WriteALU]>; 4453 4454def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)), 4455 (REV16 (LDRH addrmode3:$addr))>; 4456def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr), 4457 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>; 4458 4459let AddedComplexity = 5 in 4460def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4461 IIC_iUNAr, "revsh", "\t$Rd, $Rm", 4462 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>, 4463 Requires<[IsARM, HasV6]>, 4464 Sched<[WriteALU]>; 4465 4466def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)), 4467 (and (srl GPR:$Rm, (i32 8)), 0xFF)), 4468 (REVSH GPR:$Rm)>; 4469 4470def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd), 4471 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh), 4472 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 4473 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF), 4474 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh), 4475 0xFFFF0000)))]>, 4476 Requires<[IsARM, HasV6]>, 4477 Sched<[WriteALUsi, ReadALU]>; 4478 4479// Alternate cases for PKHBT where identities eliminate some nodes. 4480def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)), 4481 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>; 4482def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)), 4483 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>; 4484 4485// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 4486// will match the pattern below. 4487def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd), 4488 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh), 4489 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 4490 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000), 4491 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh), 4492 0xFFFF)))]>, 4493 Requires<[IsARM, HasV6]>, 4494 Sched<[WriteALUsi, ReadALU]>; 4495 4496// Alternate cases for PKHTB where identities eliminate some nodes. Note that 4497// a shift amount of 0 is *not legal* here, it is PKHBT instead. 4498// We also can not replace a srl (17..31) by an arithmetic shift we would use in 4499// pkhtb src1, src2, asr (17..31). 4500def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4501 (srl GPRnopc:$src2, imm16:$sh)), 4502 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>; 4503def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4504 (sra GPRnopc:$src2, imm16_31:$sh)), 4505 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>; 4506def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4507 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)), 4508 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>; 4509 4510//===----------------------------------------------------------------------===// 4511// CRC Instructions 4512// 4513// Polynomials: 4514// + CRC32{B,H,W} 0x04C11DB7 4515// + CRC32C{B,H,W} 0x1EDC6F41 4516// 4517 4518class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin> 4519 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary, 4520 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm", 4521 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>, 4522 Requires<[IsARM, HasV8, HasCRC]> { 4523 bits<4> Rd; 4524 bits<4> Rn; 4525 bits<4> Rm; 4526 4527 let Inst{31-28} = 0b1110; 4528 let Inst{27-23} = 0b00010; 4529 let Inst{22-21} = sz; 4530 let Inst{20} = 0; 4531 let Inst{19-16} = Rn; 4532 let Inst{15-12} = Rd; 4533 let Inst{11-10} = 0b00; 4534 let Inst{9} = C; 4535 let Inst{8} = 0; 4536 let Inst{7-4} = 0b0100; 4537 let Inst{3-0} = Rm; 4538 4539 let Unpredictable{11-8} = 0b1101; 4540} 4541 4542def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>; 4543def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>; 4544def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>; 4545def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>; 4546def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>; 4547def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>; 4548 4549//===----------------------------------------------------------------------===// 4550// ARMv8.1a Privilege Access Never extension 4551// 4552// SETPAN #imm1 4553 4554def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan", 4555 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> { 4556 bits<1> imm; 4557 4558 let Inst{31-28} = 0b1111; 4559 let Inst{27-20} = 0b00010001; 4560 let Inst{19-16} = 0b0000; 4561 let Inst{15-10} = 0b000000; 4562 let Inst{9} = imm; 4563 let Inst{8} = 0b0; 4564 let Inst{7-4} = 0b0000; 4565 let Inst{3-0} = 0b0000; 4566 4567 let Unpredictable{19-16} = 0b1111; 4568 let Unpredictable{15-10} = 0b111111; 4569 let Unpredictable{8} = 0b1; 4570 let Unpredictable{3-0} = 0b1111; 4571} 4572 4573//===----------------------------------------------------------------------===// 4574// Comparison Instructions... 4575// 4576 4577defm CMP : AI1_cmp_irs<0b1010, "cmp", 4578 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, ARMcmp>; 4579 4580// ARMcmpZ can re-use the above instruction definitions. 4581def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm), 4582 (CMPri GPR:$src, mod_imm:$imm)>; 4583def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs), 4584 (CMPrr GPR:$src, GPR:$rhs)>; 4585def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs), 4586 (CMPrsi GPR:$src, so_reg_imm:$rhs)>; 4587def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs), 4588 (CMPrsr GPR:$src, so_reg_reg:$rhs)>; 4589 4590// CMN register-integer 4591let isCompare = 1, Defs = [CPSR] in { 4592def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi, 4593 "cmn", "\t$Rn, $imm", 4594 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>, 4595 Sched<[WriteCMP, ReadALU]> { 4596 bits<4> Rn; 4597 bits<12> imm; 4598 let Inst{25} = 1; 4599 let Inst{20} = 1; 4600 let Inst{19-16} = Rn; 4601 let Inst{15-12} = 0b0000; 4602 let Inst{11-0} = imm; 4603 4604 let Unpredictable{15-12} = 0b1111; 4605} 4606 4607// CMN register-register/shift 4608def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr, 4609 "cmn", "\t$Rn, $Rm", 4610 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4611 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> { 4612 bits<4> Rn; 4613 bits<4> Rm; 4614 let isCommutable = 1; 4615 let Inst{25} = 0; 4616 let Inst{20} = 1; 4617 let Inst{19-16} = Rn; 4618 let Inst{15-12} = 0b0000; 4619 let Inst{11-4} = 0b00000000; 4620 let Inst{3-0} = Rm; 4621 4622 let Unpredictable{15-12} = 0b1111; 4623} 4624 4625def CMNzrsi : AI1<0b1011, (outs), 4626 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr, 4627 "cmn", "\t$Rn, $shift", 4628 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4629 GPR:$Rn, so_reg_imm:$shift)]>, 4630 Sched<[WriteCMPsi, ReadALU]> { 4631 bits<4> Rn; 4632 bits<12> shift; 4633 let Inst{25} = 0; 4634 let Inst{20} = 1; 4635 let Inst{19-16} = Rn; 4636 let Inst{15-12} = 0b0000; 4637 let Inst{11-5} = shift{11-5}; 4638 let Inst{4} = 0; 4639 let Inst{3-0} = shift{3-0}; 4640 4641 let Unpredictable{15-12} = 0b1111; 4642} 4643 4644def CMNzrsr : AI1<0b1011, (outs), 4645 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr, 4646 "cmn", "\t$Rn, $shift", 4647 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4648 GPRnopc:$Rn, so_reg_reg:$shift)]>, 4649 Sched<[WriteCMPsr, ReadALU]> { 4650 bits<4> Rn; 4651 bits<12> shift; 4652 let Inst{25} = 0; 4653 let Inst{20} = 1; 4654 let Inst{19-16} = Rn; 4655 let Inst{15-12} = 0b0000; 4656 let Inst{11-8} = shift{11-8}; 4657 let Inst{7} = 0; 4658 let Inst{6-5} = shift{6-5}; 4659 let Inst{4} = 1; 4660 let Inst{3-0} = shift{3-0}; 4661 4662 let Unpredictable{15-12} = 0b1111; 4663} 4664 4665} 4666 4667def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm), 4668 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4669 4670def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm), 4671 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4672 4673// Note that TST/TEQ don't set all the same flags that CMP does! 4674defm TST : AI1_cmp_irs<0b1000, "tst", 4675 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4676 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1, 4677 "DecodeTSTInstruction">; 4678defm TEQ : AI1_cmp_irs<0b1001, "teq", 4679 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4680 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>; 4681 4682// Pseudo i64 compares for some floating point compares. 4683let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, 4684 Defs = [CPSR] in { 4685def BCCi64 : PseudoInst<(outs), 4686 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst), 4687 IIC_Br, 4688 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>, 4689 Sched<[WriteBr]>; 4690 4691def BCCZi64 : PseudoInst<(outs), 4692 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, 4693 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>, 4694 Sched<[WriteBr]>; 4695} // usesCustomInserter 4696 4697 4698// Conditional moves 4699let hasSideEffects = 0 in { 4700 4701let isCommutable = 1, isSelect = 1 in 4702def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), 4703 (ins GPR:$false, GPR:$Rm, cmovpred:$p), 4704 4, IIC_iCMOVr, 4705 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, 4706 cmovpred:$p))]>, 4707 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4708 4709def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd), 4710 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p), 4711 4, IIC_iCMOVsr, 4712 [(set GPR:$Rd, 4713 (ARMcmov GPR:$false, so_reg_imm:$shift, 4714 cmovpred:$p))]>, 4715 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4716def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd), 4717 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p), 4718 4, IIC_iCMOVsr, 4719 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift, 4720 cmovpred:$p))]>, 4721 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4722 4723 4724let isMoveImm = 1 in 4725def MOVCCi16 4726 : ARMPseudoInst<(outs GPR:$Rd), 4727 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p), 4728 4, IIC_iMOVi, 4729 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm, 4730 cmovpred:$p))]>, 4731 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>, 4732 Sched<[WriteALU]>; 4733 4734let isMoveImm = 1 in 4735def MOVCCi : ARMPseudoInst<(outs GPR:$Rd), 4736 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 4737 4, IIC_iCMOVi, 4738 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm, 4739 cmovpred:$p))]>, 4740 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4741 4742// Two instruction predicate mov immediate. 4743let isMoveImm = 1 in 4744def MOVCCi32imm 4745 : ARMPseudoInst<(outs GPR:$Rd), 4746 (ins GPR:$false, i32imm:$src, cmovpred:$p), 4747 8, IIC_iCMOVix2, 4748 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src, 4749 cmovpred:$p))]>, 4750 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>; 4751 4752let isMoveImm = 1 in 4753def MVNCCi : ARMPseudoInst<(outs GPR:$Rd), 4754 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 4755 4, IIC_iCMOVi, 4756 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm, 4757 cmovpred:$p))]>, 4758 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4759 4760} // hasSideEffects 4761 4762 4763//===----------------------------------------------------------------------===// 4764// Atomic operations intrinsics 4765// 4766 4767def MemBarrierOptOperand : AsmOperandClass { 4768 let Name = "MemBarrierOpt"; 4769 let ParserMethod = "parseMemBarrierOptOperand"; 4770} 4771def memb_opt : Operand<i32> { 4772 let PrintMethod = "printMemBOption"; 4773 let ParserMatchClass = MemBarrierOptOperand; 4774 let DecoderMethod = "DecodeMemBarrierOption"; 4775} 4776 4777def InstSyncBarrierOptOperand : AsmOperandClass { 4778 let Name = "InstSyncBarrierOpt"; 4779 let ParserMethod = "parseInstSyncBarrierOptOperand"; 4780} 4781def instsyncb_opt : Operand<i32> { 4782 let PrintMethod = "printInstSyncBOption"; 4783 let ParserMatchClass = InstSyncBarrierOptOperand; 4784 let DecoderMethod = "DecodeInstSyncBarrierOption"; 4785} 4786 4787// Memory barriers protect the atomic sequences 4788let hasSideEffects = 1 in { 4789def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4790 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>, 4791 Requires<[IsARM, HasDB]> { 4792 bits<4> opt; 4793 let Inst{31-4} = 0xf57ff05; 4794 let Inst{3-0} = opt; 4795} 4796 4797def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4798 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>, 4799 Requires<[IsARM, HasDB]> { 4800 bits<4> opt; 4801 let Inst{31-4} = 0xf57ff04; 4802 let Inst{3-0} = opt; 4803} 4804 4805// ISB has only full system option 4806def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary, 4807 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>, 4808 Requires<[IsARM, HasDB]> { 4809 bits<4> opt; 4810 let Inst{31-4} = 0xf57ff06; 4811 let Inst{3-0} = opt; 4812} 4813} 4814 4815let usesCustomInserter = 1, Defs = [CPSR] in { 4816 4817// Pseudo instruction that combines movs + predicated rsbmi 4818// to implement integer ABS 4819 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>; 4820} 4821 4822let usesCustomInserter = 1 in { 4823 def COPY_STRUCT_BYVAL_I32 : PseudoInst< 4824 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment), 4825 NoItinerary, 4826 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>; 4827} 4828 4829let hasPostISelHook = 1, Constraints = "$newdst = $dst, $newsrc = $src" in { 4830 // %newsrc, %newdst = MEMCPY %dst, %src, N, ...N scratch regs... 4831 // Copies N registers worth of memory from address %src to address %dst 4832 // and returns the incremented addresses. N scratch register will 4833 // be attached for the copy to use. 4834 def MEMCPY : PseudoInst< 4835 (outs GPR:$newdst, GPR:$newsrc), 4836 (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops), 4837 NoItinerary, 4838 [(set GPR:$newdst, GPR:$newsrc, 4839 (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>; 4840} 4841 4842def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4843 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4844}]>; 4845 4846def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4847 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4848}]>; 4849 4850def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4851 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4852}]>; 4853 4854def strex_1 : PatFrag<(ops node:$val, node:$ptr), 4855 (int_arm_strex node:$val, node:$ptr), [{ 4856 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4857}]>; 4858 4859def strex_2 : PatFrag<(ops node:$val, node:$ptr), 4860 (int_arm_strex node:$val, node:$ptr), [{ 4861 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4862}]>; 4863 4864def strex_4 : PatFrag<(ops node:$val, node:$ptr), 4865 (int_arm_strex node:$val, node:$ptr), [{ 4866 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4867}]>; 4868 4869def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4870 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4871}]>; 4872 4873def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4874 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4875}]>; 4876 4877def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4878 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4879}]>; 4880 4881def stlex_1 : PatFrag<(ops node:$val, node:$ptr), 4882 (int_arm_stlex node:$val, node:$ptr), [{ 4883 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4884}]>; 4885 4886def stlex_2 : PatFrag<(ops node:$val, node:$ptr), 4887 (int_arm_stlex node:$val, node:$ptr), [{ 4888 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4889}]>; 4890 4891def stlex_4 : PatFrag<(ops node:$val, node:$ptr), 4892 (int_arm_stlex node:$val, node:$ptr), [{ 4893 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4894}]>; 4895 4896let mayLoad = 1 in { 4897def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4898 NoItinerary, "ldrexb", "\t$Rt, $addr", 4899 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>; 4900def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4901 NoItinerary, "ldrexh", "\t$Rt, $addr", 4902 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>; 4903def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4904 NoItinerary, "ldrex", "\t$Rt, $addr", 4905 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>; 4906let hasExtraDefRegAllocReq = 1 in 4907def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 4908 NoItinerary, "ldrexd", "\t$Rt, $addr", []> { 4909 let DecoderMethod = "DecodeDoubleRegLoad"; 4910} 4911 4912def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4913 NoItinerary, "ldaexb", "\t$Rt, $addr", 4914 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>; 4915def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4916 NoItinerary, "ldaexh", "\t$Rt, $addr", 4917 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>; 4918def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4919 NoItinerary, "ldaex", "\t$Rt, $addr", 4920 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>; 4921let hasExtraDefRegAllocReq = 1 in 4922def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 4923 NoItinerary, "ldaexd", "\t$Rt, $addr", []> { 4924 let DecoderMethod = "DecodeDoubleRegLoad"; 4925} 4926} 4927 4928let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 4929def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4930 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", 4931 [(set GPR:$Rd, (strex_1 GPR:$Rt, 4932 addr_offset_none:$addr))]>; 4933def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4934 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", 4935 [(set GPR:$Rd, (strex_2 GPR:$Rt, 4936 addr_offset_none:$addr))]>; 4937def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4938 NoItinerary, "strex", "\t$Rd, $Rt, $addr", 4939 [(set GPR:$Rd, (strex_4 GPR:$Rt, 4940 addr_offset_none:$addr))]>; 4941let hasExtraSrcRegAllocReq = 1 in 4942def STREXD : AIstrex<0b01, (outs GPR:$Rd), 4943 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 4944 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> { 4945 let DecoderMethod = "DecodeDoubleRegStore"; 4946} 4947def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4948 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr", 4949 [(set GPR:$Rd, 4950 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>; 4951def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4952 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr", 4953 [(set GPR:$Rd, 4954 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>; 4955def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4956 NoItinerary, "stlex", "\t$Rd, $Rt, $addr", 4957 [(set GPR:$Rd, 4958 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>; 4959let hasExtraSrcRegAllocReq = 1 in 4960def STLEXD : AIstlex<0b01, (outs GPR:$Rd), 4961 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 4962 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> { 4963 let DecoderMethod = "DecodeDoubleRegStore"; 4964} 4965} 4966 4967def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", 4968 [(int_arm_clrex)]>, 4969 Requires<[IsARM, HasV6K]> { 4970 let Inst{31-0} = 0b11110101011111111111000000011111; 4971} 4972 4973def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 4974 (STREXB GPR:$Rt, addr_offset_none:$addr)>; 4975def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 4976 (STREXH GPR:$Rt, addr_offset_none:$addr)>; 4977 4978def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 4979 (STLEXB GPR:$Rt, addr_offset_none:$addr)>; 4980def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 4981 (STLEXH GPR:$Rt, addr_offset_none:$addr)>; 4982 4983class acquiring_load<PatFrag base> 4984 : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 4985 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 4986 return isAcquireOrStronger(Ordering); 4987}]>; 4988 4989def atomic_load_acquire_8 : acquiring_load<atomic_load_8>; 4990def atomic_load_acquire_16 : acquiring_load<atomic_load_16>; 4991def atomic_load_acquire_32 : acquiring_load<atomic_load_32>; 4992 4993class releasing_store<PatFrag base> 4994 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 4995 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 4996 return isReleaseOrStronger(Ordering); 4997}]>; 4998 4999def atomic_store_release_8 : releasing_store<atomic_store_8>; 5000def atomic_store_release_16 : releasing_store<atomic_store_16>; 5001def atomic_store_release_32 : releasing_store<atomic_store_32>; 5002 5003let AddedComplexity = 8 in { 5004 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>; 5005 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>; 5006 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>; 5007 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>; 5008 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>; 5009 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>; 5010} 5011 5012// SWP/SWPB are deprecated in V6/V7 and optional in v7VE. 5013// FIXME Use InstAlias to generate LDREX/STREX pairs instead. 5014let mayLoad = 1, mayStore = 1 in { 5015def SWP : AIswp<0, (outs GPRnopc:$Rt), 5016 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>, 5017 Requires<[IsARM,PreV8]>; 5018def SWPB: AIswp<1, (outs GPRnopc:$Rt), 5019 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>, 5020 Requires<[IsARM,PreV8]>; 5021} 5022 5023//===----------------------------------------------------------------------===// 5024// Coprocessor Instructions. 5025// 5026 5027def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5028 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5029 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5030 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 5031 imm:$CRm, imm:$opc2)]>, 5032 Requires<[IsARM,PreV8]> { 5033 bits<4> opc1; 5034 bits<4> CRn; 5035 bits<4> CRd; 5036 bits<4> cop; 5037 bits<3> opc2; 5038 bits<4> CRm; 5039 5040 let Inst{3-0} = CRm; 5041 let Inst{4} = 0; 5042 let Inst{7-5} = opc2; 5043 let Inst{11-8} = cop; 5044 let Inst{15-12} = CRd; 5045 let Inst{19-16} = CRn; 5046 let Inst{23-20} = opc1; 5047 5048 let DecoderNamespace = "CoProc"; 5049} 5050 5051def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5052 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5053 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5054 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 5055 imm:$CRm, imm:$opc2)]>, 5056 Requires<[IsARM,PreV8]> { 5057 let Inst{31-28} = 0b1111; 5058 bits<4> opc1; 5059 bits<4> CRn; 5060 bits<4> CRd; 5061 bits<4> cop; 5062 bits<3> opc2; 5063 bits<4> CRm; 5064 5065 let Inst{3-0} = CRm; 5066 let Inst{4} = 0; 5067 let Inst{7-5} = opc2; 5068 let Inst{11-8} = cop; 5069 let Inst{15-12} = CRd; 5070 let Inst{19-16} = CRn; 5071 let Inst{23-20} = opc1; 5072 5073 let DecoderNamespace = "CoProc"; 5074} 5075 5076class ACI<dag oops, dag iops, string opc, string asm, 5077 list<dag> pattern, IndexMode im = IndexModeNone> 5078 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 5079 opc, asm, "", pattern> { 5080 let Inst{27-25} = 0b110; 5081} 5082class ACInoP<dag oops, dag iops, string opc, string asm, 5083 list<dag> pattern, IndexMode im = IndexModeNone> 5084 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 5085 opc, asm, "", pattern> { 5086 let Inst{31-28} = 0b1111; 5087 let Inst{27-25} = 0b110; 5088} 5089 5090let DecoderNamespace = "CoProc" in { 5091multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> { 5092 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 5093 asm, "\t$cop, $CRd, $addr", pattern> { 5094 bits<13> addr; 5095 bits<4> cop; 5096 bits<4> CRd; 5097 let Inst{24} = 1; // P = 1 5098 let Inst{23} = addr{8}; 5099 let Inst{22} = Dbit; 5100 let Inst{21} = 0; // W = 0 5101 let Inst{20} = load; 5102 let Inst{19-16} = addr{12-9}; 5103 let Inst{15-12} = CRd; 5104 let Inst{11-8} = cop; 5105 let Inst{7-0} = addr{7-0}; 5106 let DecoderMethod = "DecodeCopMemInstruction"; 5107 } 5108 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 5109 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { 5110 bits<13> addr; 5111 bits<4> cop; 5112 bits<4> CRd; 5113 let Inst{24} = 1; // P = 1 5114 let Inst{23} = addr{8}; 5115 let Inst{22} = Dbit; 5116 let Inst{21} = 1; // W = 1 5117 let Inst{20} = load; 5118 let Inst{19-16} = addr{12-9}; 5119 let Inst{15-12} = CRd; 5120 let Inst{11-8} = cop; 5121 let Inst{7-0} = addr{7-0}; 5122 let DecoderMethod = "DecodeCopMemInstruction"; 5123 } 5124 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5125 postidx_imm8s4:$offset), 5126 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { 5127 bits<9> offset; 5128 bits<4> addr; 5129 bits<4> cop; 5130 bits<4> CRd; 5131 let Inst{24} = 0; // P = 0 5132 let Inst{23} = offset{8}; 5133 let Inst{22} = Dbit; 5134 let Inst{21} = 1; // W = 1 5135 let Inst{20} = load; 5136 let Inst{19-16} = addr; 5137 let Inst{15-12} = CRd; 5138 let Inst{11-8} = cop; 5139 let Inst{7-0} = offset{7-0}; 5140 let DecoderMethod = "DecodeCopMemInstruction"; 5141 } 5142 def _OPTION : ACI<(outs), 5143 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5144 coproc_option_imm:$option), 5145 asm, "\t$cop, $CRd, $addr, $option", []> { 5146 bits<8> option; 5147 bits<4> addr; 5148 bits<4> cop; 5149 bits<4> CRd; 5150 let Inst{24} = 0; // P = 0 5151 let Inst{23} = 1; // U = 1 5152 let Inst{22} = Dbit; 5153 let Inst{21} = 0; // W = 0 5154 let Inst{20} = load; 5155 let Inst{19-16} = addr; 5156 let Inst{15-12} = CRd; 5157 let Inst{11-8} = cop; 5158 let Inst{7-0} = option; 5159 let DecoderMethod = "DecodeCopMemInstruction"; 5160 } 5161} 5162multiclass LdSt2Cop<bit load, bit Dbit, string asm, list<dag> pattern> { 5163 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 5164 asm, "\t$cop, $CRd, $addr", pattern> { 5165 bits<13> addr; 5166 bits<4> cop; 5167 bits<4> CRd; 5168 let Inst{24} = 1; // P = 1 5169 let Inst{23} = addr{8}; 5170 let Inst{22} = Dbit; 5171 let Inst{21} = 0; // W = 0 5172 let Inst{20} = load; 5173 let Inst{19-16} = addr{12-9}; 5174 let Inst{15-12} = CRd; 5175 let Inst{11-8} = cop; 5176 let Inst{7-0} = addr{7-0}; 5177 let DecoderMethod = "DecodeCopMemInstruction"; 5178 } 5179 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 5180 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { 5181 bits<13> addr; 5182 bits<4> cop; 5183 bits<4> CRd; 5184 let Inst{24} = 1; // P = 1 5185 let Inst{23} = addr{8}; 5186 let Inst{22} = Dbit; 5187 let Inst{21} = 1; // W = 1 5188 let Inst{20} = load; 5189 let Inst{19-16} = addr{12-9}; 5190 let Inst{15-12} = CRd; 5191 let Inst{11-8} = cop; 5192 let Inst{7-0} = addr{7-0}; 5193 let DecoderMethod = "DecodeCopMemInstruction"; 5194 } 5195 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5196 postidx_imm8s4:$offset), 5197 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { 5198 bits<9> offset; 5199 bits<4> addr; 5200 bits<4> cop; 5201 bits<4> CRd; 5202 let Inst{24} = 0; // P = 0 5203 let Inst{23} = offset{8}; 5204 let Inst{22} = Dbit; 5205 let Inst{21} = 1; // W = 1 5206 let Inst{20} = load; 5207 let Inst{19-16} = addr; 5208 let Inst{15-12} = CRd; 5209 let Inst{11-8} = cop; 5210 let Inst{7-0} = offset{7-0}; 5211 let DecoderMethod = "DecodeCopMemInstruction"; 5212 } 5213 def _OPTION : ACInoP<(outs), 5214 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5215 coproc_option_imm:$option), 5216 asm, "\t$cop, $CRd, $addr, $option", []> { 5217 bits<8> option; 5218 bits<4> addr; 5219 bits<4> cop; 5220 bits<4> CRd; 5221 let Inst{24} = 0; // P = 0 5222 let Inst{23} = 1; // U = 1 5223 let Inst{22} = Dbit; 5224 let Inst{21} = 0; // W = 0 5225 let Inst{20} = load; 5226 let Inst{19-16} = addr; 5227 let Inst{15-12} = CRd; 5228 let Inst{11-8} = cop; 5229 let Inst{7-0} = option; 5230 let DecoderMethod = "DecodeCopMemInstruction"; 5231 } 5232} 5233 5234defm LDC : LdStCop <1, 0, "ldc", [(int_arm_ldc imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5235defm LDCL : LdStCop <1, 1, "ldcl", [(int_arm_ldcl imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5236defm LDC2 : LdSt2Cop<1, 0, "ldc2", [(int_arm_ldc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5237defm LDC2L : LdSt2Cop<1, 1, "ldc2l", [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5238 5239defm STC : LdStCop <0, 0, "stc", [(int_arm_stc imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5240defm STCL : LdStCop <0, 1, "stcl", [(int_arm_stcl imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5241defm STC2 : LdSt2Cop<0, 0, "stc2", [(int_arm_stc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5242defm STC2L : LdSt2Cop<0, 1, "stc2l", [(int_arm_stc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5243 5244} // DecoderNamespace = "CoProc" 5245 5246//===----------------------------------------------------------------------===// 5247// Move between coprocessor and ARM core register. 5248// 5249 5250class MovRCopro<string opc, bit direction, dag oops, dag iops, 5251 list<dag> pattern> 5252 : ABI<0b1110, oops, iops, NoItinerary, opc, 5253 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> { 5254 let Inst{20} = direction; 5255 let Inst{4} = 1; 5256 5257 bits<4> Rt; 5258 bits<4> cop; 5259 bits<3> opc1; 5260 bits<3> opc2; 5261 bits<4> CRm; 5262 bits<4> CRn; 5263 5264 let Inst{15-12} = Rt; 5265 let Inst{11-8} = cop; 5266 let Inst{23-21} = opc1; 5267 let Inst{7-5} = opc2; 5268 let Inst{3-0} = CRm; 5269 let Inst{19-16} = CRn; 5270 5271 let DecoderNamespace = "CoProc"; 5272} 5273 5274def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */, 5275 (outs), 5276 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5277 c_imm:$CRm, imm0_7:$opc2), 5278 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 5279 imm:$CRm, imm:$opc2)]>, 5280 ComplexDeprecationPredicate<"MCR">; 5281def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 5282 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5283 c_imm:$CRm, 0, pred:$p)>; 5284def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, 5285 (outs GPRwithAPSR:$Rt), 5286 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5287 imm0_7:$opc2), []>; 5288def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", 5289 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5290 c_imm:$CRm, 0, pred:$p)>; 5291 5292def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 5293 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 5294 5295class MovRCopro2<string opc, bit direction, dag oops, dag iops, 5296 list<dag> pattern> 5297 : ABXI<0b1110, oops, iops, NoItinerary, 5298 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> { 5299 let Inst{31-24} = 0b11111110; 5300 let Inst{20} = direction; 5301 let Inst{4} = 1; 5302 5303 bits<4> Rt; 5304 bits<4> cop; 5305 bits<3> opc1; 5306 bits<3> opc2; 5307 bits<4> CRm; 5308 bits<4> CRn; 5309 5310 let Inst{15-12} = Rt; 5311 let Inst{11-8} = cop; 5312 let Inst{23-21} = opc1; 5313 let Inst{7-5} = opc2; 5314 let Inst{3-0} = CRm; 5315 let Inst{19-16} = CRn; 5316 5317 let DecoderNamespace = "CoProc"; 5318} 5319 5320def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */, 5321 (outs), 5322 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5323 c_imm:$CRm, imm0_7:$opc2), 5324 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 5325 imm:$CRm, imm:$opc2)]>, 5326 Requires<[IsARM,PreV8]>; 5327def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm", 5328 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5329 c_imm:$CRm, 0)>; 5330def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, 5331 (outs GPRwithAPSR:$Rt), 5332 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5333 imm0_7:$opc2), []>, 5334 Requires<[IsARM,PreV8]>; 5335def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm", 5336 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5337 c_imm:$CRm, 0)>; 5338 5339def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, 5340 imm:$CRm, imm:$opc2), 5341 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 5342 5343class MovRRCopro<string opc, bit direction, dag oops, dag iops, list<dag> 5344 pattern = []> 5345 : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", 5346 pattern> { 5347 5348 let Inst{23-21} = 0b010; 5349 let Inst{20} = direction; 5350 5351 bits<4> Rt; 5352 bits<4> Rt2; 5353 bits<4> cop; 5354 bits<4> opc1; 5355 bits<4> CRm; 5356 5357 let Inst{15-12} = Rt; 5358 let Inst{19-16} = Rt2; 5359 let Inst{11-8} = cop; 5360 let Inst{7-4} = opc1; 5361 let Inst{3-0} = CRm; 5362} 5363 5364def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */, 5365 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5366 GPRnopc:$Rt2, c_imm:$CRm), 5367 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt, 5368 GPRnopc:$Rt2, imm:$CRm)]>; 5369def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */, 5370 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5371 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5372 5373class MovRRCopro2<string opc, bit direction, dag oops, dag iops, 5374 list<dag> pattern = []> 5375 : ABXI<0b1100, oops, iops, NoItinerary, 5376 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>, 5377 Requires<[IsARM,PreV8]> { 5378 let Inst{31-28} = 0b1111; 5379 let Inst{23-21} = 0b010; 5380 let Inst{20} = direction; 5381 5382 bits<4> Rt; 5383 bits<4> Rt2; 5384 bits<4> cop; 5385 bits<4> opc1; 5386 bits<4> CRm; 5387 5388 let Inst{15-12} = Rt; 5389 let Inst{19-16} = Rt2; 5390 let Inst{11-8} = cop; 5391 let Inst{7-4} = opc1; 5392 let Inst{3-0} = CRm; 5393 5394 let DecoderMethod = "DecoderForMRRC2AndMCRR2"; 5395} 5396 5397def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */, 5398 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5399 GPRnopc:$Rt2, c_imm:$CRm), 5400 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt, 5401 GPRnopc:$Rt2, imm:$CRm)]>; 5402 5403def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */, 5404 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5405 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5406 5407//===----------------------------------------------------------------------===// 5408// Move between special register and ARM core register 5409// 5410 5411// Move to ARM core register from Special Register 5412def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5413 "mrs", "\t$Rd, apsr", []> { 5414 bits<4> Rd; 5415 let Inst{23-16} = 0b00001111; 5416 let Unpredictable{19-17} = 0b111; 5417 5418 let Inst{15-12} = Rd; 5419 5420 let Inst{11-0} = 0b000000000000; 5421 let Unpredictable{11-0} = 0b110100001111; 5422} 5423 5424def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p), 0>, 5425 Requires<[IsARM]>; 5426 5427// The MRSsys instruction is the MRS instruction from the ARM ARM, 5428// section B9.3.9, with the R bit set to 1. 5429def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5430 "mrs", "\t$Rd, spsr", []> { 5431 bits<4> Rd; 5432 let Inst{23-16} = 0b01001111; 5433 let Unpredictable{19-16} = 0b1111; 5434 5435 let Inst{15-12} = Rd; 5436 5437 let Inst{11-0} = 0b000000000000; 5438 let Unpredictable{11-0} = 0b110100001111; 5439} 5440 5441// However, the MRS (banked register) system instruction (ARMv7VE) *does* have a 5442// separate encoding (distinguished by bit 5. 5443def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked), 5444 NoItinerary, "mrs", "\t$Rd, $banked", []>, 5445 Requires<[IsARM, HasVirtualization]> { 5446 bits<6> banked; 5447 bits<4> Rd; 5448 5449 let Inst{23} = 0; 5450 let Inst{22} = banked{5}; // R bit 5451 let Inst{21-20} = 0b00; 5452 let Inst{19-16} = banked{3-0}; 5453 let Inst{15-12} = Rd; 5454 let Inst{11-9} = 0b001; 5455 let Inst{8} = banked{4}; 5456 let Inst{7-0} = 0b00000000; 5457} 5458 5459// Move from ARM core register to Special Register 5460// 5461// No need to have both system and application versions of MSR (immediate) or 5462// MSR (register), the encodings are the same and the assembly parser has no way 5463// to distinguish between them. The mask operand contains the special register 5464// (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be 5465// accessed in the special register. 5466let Defs = [CPSR] in 5467def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, 5468 "msr", "\t$mask, $Rn", []> { 5469 bits<5> mask; 5470 bits<4> Rn; 5471 5472 let Inst{23} = 0; 5473 let Inst{22} = mask{4}; // R bit 5474 let Inst{21-20} = 0b10; 5475 let Inst{19-16} = mask{3-0}; 5476 let Inst{15-12} = 0b1111; 5477 let Inst{11-4} = 0b00000000; 5478 let Inst{3-0} = Rn; 5479} 5480 5481let Defs = [CPSR] in 5482def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary, 5483 "msr", "\t$mask, $imm", []> { 5484 bits<5> mask; 5485 bits<12> imm; 5486 5487 let Inst{23} = 0; 5488 let Inst{22} = mask{4}; // R bit 5489 let Inst{21-20} = 0b10; 5490 let Inst{19-16} = mask{3-0}; 5491 let Inst{15-12} = 0b1111; 5492 let Inst{11-0} = imm; 5493} 5494 5495// However, the MSR (banked register) system instruction (ARMv7VE) *does* have a 5496// separate encoding (distinguished by bit 5. 5497def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn), 5498 NoItinerary, "msr", "\t$banked, $Rn", []>, 5499 Requires<[IsARM, HasVirtualization]> { 5500 bits<6> banked; 5501 bits<4> Rn; 5502 5503 let Inst{23} = 0; 5504 let Inst{22} = banked{5}; // R bit 5505 let Inst{21-20} = 0b10; 5506 let Inst{19-16} = banked{3-0}; 5507 let Inst{15-12} = 0b1111; 5508 let Inst{11-9} = 0b001; 5509 let Inst{8} = banked{4}; 5510 let Inst{7-4} = 0b0000; 5511 let Inst{3-0} = Rn; 5512} 5513 5514// Dynamic stack allocation yields a _chkstk for Windows targets. These calls 5515// are needed to probe the stack when allocating more than 5516// 4k bytes in one go. Touching the stack at 4K increments is necessary to 5517// ensure that the guard pages used by the OS virtual memory manager are 5518// allocated in correct sequence. 5519// The main point of having separate instruction are extra unmodelled effects 5520// (compared to ordinary calls) like stack pointer change. 5521 5522def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone, 5523 [SDNPHasChain, SDNPSideEffect]>; 5524let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in 5525 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>; 5526 5527def win__dbzchk : SDNode<"ARMISD::WIN__DBZCHK", SDT_WIN__DBZCHK, 5528 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 5529let usesCustomInserter = 1, Defs = [CPSR] in 5530 def WIN__DBZCHK : PseudoInst<(outs), (ins tGPR:$divisor), NoItinerary, 5531 [(win__dbzchk tGPR:$divisor)]>; 5532 5533//===----------------------------------------------------------------------===// 5534// TLS Instructions 5535// 5536 5537// __aeabi_read_tp preserves the registers r1-r3. 5538// This is a pseudo inst so that we can get the encoding right, 5539// complete with fixup for the aeabi_read_tp function. 5540// TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern 5541// is defined in "ARMInstrThumb.td". 5542let isCall = 1, 5543 Defs = [R0, R12, LR, CPSR], Uses = [SP] in { 5544 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br, 5545 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>, 5546 Requires<[IsARM, IsReadTPSoft]>; 5547} 5548 5549// Reading thread pointer from coprocessor register 5550def : ARMPat<(ARMthread_pointer), (MRC 15, 0, 13, 0, 3)>, 5551 Requires<[IsARM, IsReadTPHard]>; 5552 5553//===----------------------------------------------------------------------===// 5554// SJLJ Exception handling intrinsics 5555// eh_sjlj_setjmp() is an instruction sequence to store the return 5556// address and save #0 in R0 for the non-longjmp case. 5557// Since by its nature we may be coming from some other function to get 5558// here, and we're using the stack frame for the containing function to 5559// save/restore registers, we can't keep anything live in regs across 5560// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 5561// when we get here from a longjmp(). We force everything out of registers 5562// except for our own input by listing the relevant registers in Defs. By 5563// doing so, we also cause the prologue/epilogue code to actively preserve 5564// all of the callee-saved resgisters, which is exactly what we want. 5565// A constant value is passed in $val, and we use the location as a scratch. 5566// 5567// These are pseudo-instructions and are lowered to individual MC-insts, so 5568// no encoding information is necessary. 5569let Defs = 5570 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 5571 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ], 5572 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5573 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5574 NoItinerary, 5575 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5576 Requires<[IsARM, HasVFP2]>; 5577} 5578 5579let Defs = 5580 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 5581 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5582 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5583 NoItinerary, 5584 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5585 Requires<[IsARM, NoVFP]>; 5586} 5587 5588// FIXME: Non-IOS version(s) 5589let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, 5590 Defs = [ R7, LR, SP ] in { 5591def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch), 5592 NoItinerary, 5593 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 5594 Requires<[IsARM]>; 5595} 5596 5597let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in 5598def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary, 5599 [(ARMeh_sjlj_setup_dispatch)]>; 5600 5601// eh.sjlj.dispatchsetup pseudo-instruction. 5602// This pseudo is used for both ARM and Thumb. Any differences are handled when 5603// the pseudo is expanded (which happens before any passes that need the 5604// instruction size). 5605let isBarrier = 1 in 5606def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>; 5607 5608 5609//===----------------------------------------------------------------------===// 5610// Non-Instruction Patterns 5611// 5612 5613// ARMv4 indirect branch using (MOVr PC, dst) 5614let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in 5615 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst), 5616 4, IIC_Br, [(brind GPR:$dst)], 5617 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5618 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5619 5620let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in 5621 def TAILJMPr4 : ARMPseudoExpand<(outs), (ins GPR:$dst), 5622 4, IIC_Br, [], 5623 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5624 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5625 5626// Large immediate handling. 5627 5628// 32-bit immediate using two piece mod_imms or movw + movt. 5629// This is a single pseudo instruction, the benefit is that it can be remat'd 5630// as a single unit instead of having to handle reg inputs. 5631// FIXME: Remove this when we can do generalized remat. 5632let isReMaterializable = 1, isMoveImm = 1 in 5633def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 5634 [(set GPR:$dst, (arm_i32imm:$src))]>, 5635 Requires<[IsARM]>; 5636 5637def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i, 5638 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>, 5639 Requires<[IsARM, DontUseMovt]>; 5640 5641// Pseudo instruction that combines movw + movt + add pc (if PIC). 5642// It also makes it possible to rematerialize the instructions. 5643// FIXME: Remove this when we can do generalized remat and when machine licm 5644// can properly the instructions. 5645let isReMaterializable = 1 in { 5646def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5647 IIC_iMOVix2addpc, 5648 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 5649 Requires<[IsARM, UseMovtInPic]>; 5650 5651def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5652 IIC_iLoadiALU, 5653 [(set GPR:$dst, 5654 (ARMWrapperPIC tglobaladdr:$addr))]>, 5655 Requires<[IsARM, DontUseMovtInPic]>; 5656 5657let AddedComplexity = 10 in 5658def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5659 NoItinerary, 5660 [(set GPR:$dst, 5661 (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5662 Requires<[IsARM, DontUseMovtInPic]>; 5663 5664let AddedComplexity = 10 in 5665def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5666 IIC_iMOVix2ld, 5667 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5668 Requires<[IsARM, UseMovtInPic]>; 5669} // isReMaterializable 5670 5671// The many different faces of TLS access. 5672def : ARMPat<(ARMWrapper tglobaltlsaddr :$dst), 5673 (MOVi32imm tglobaltlsaddr :$dst)>, 5674 Requires<[IsARM, UseMovt]>; 5675 5676def : Pat<(ARMWrapper tglobaltlsaddr:$src), 5677 (LDRLIT_ga_abs tglobaltlsaddr:$src)>, 5678 Requires<[IsARM, DontUseMovt]>; 5679 5680def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5681 (MOV_ga_pcrel tglobaltlsaddr:$addr)>, Requires<[IsARM, UseMovtInPic]>; 5682 5683def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5684 (LDRLIT_ga_pcrel tglobaltlsaddr:$addr)>, 5685 Requires<[IsARM, DontUseMovtInPic]>; 5686let AddedComplexity = 10 in 5687def : Pat<(load (ARMWrapperPIC tglobaltlsaddr:$addr)), 5688 (MOV_ga_pcrel_ldr tglobaltlsaddr:$addr)>, 5689 Requires<[IsARM, UseMovtInPic]>; 5690 5691 5692// ConstantPool, GlobalAddress, and JumpTable 5693def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 5694def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>, 5695 Requires<[IsARM, UseMovt]>; 5696def : ARMPat<(ARMWrapper texternalsym :$dst), (MOVi32imm texternalsym :$dst)>, 5697 Requires<[IsARM, UseMovt]>; 5698def : ARMPat<(ARMWrapperJT tjumptable:$dst), 5699 (LEApcrelJT tjumptable:$dst)>; 5700 5701// TODO: add,sub,and, 3-instr forms? 5702 5703// Tail calls. These patterns also apply to Thumb mode. 5704def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>; 5705def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>; 5706def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>; 5707 5708// Direct calls 5709def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; 5710def : ARMPat<(ARMcall_nolink texternalsym:$func), 5711 (BMOVPCB_CALL texternalsym:$func)>; 5712 5713// zextload i1 -> zextload i8 5714def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5715def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5716 5717// extload -> zextload 5718def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5719def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5720def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5721def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5722 5723def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 5724 5725def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; 5726def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; 5727 5728// smul* and smla* 5729def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 5730 (SMULBB GPR:$a, GPR:$b)>, 5731 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 5732def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))), 5733 (SMULBT GPR:$a, GPR:$b)>, 5734 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 5735def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b), 5736 (SMULTB GPR:$a, GPR:$b)>, 5737 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 5738def : ARMV5MOPat<(add GPR:$acc, 5739 (mul sext_16_node:$a, sext_16_node:$b)), 5740 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>, 5741 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 5742def : ARMV5MOPat<(add GPR:$acc, 5743 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))), 5744 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>, 5745 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 5746def : ARMV5MOPat<(add GPR:$acc, 5747 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)), 5748 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>, 5749 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 5750 5751def : ARMV5TEPat<(int_arm_smulbb GPR:$a, GPR:$b), 5752 (SMULBB GPR:$a, GPR:$b)>; 5753def : ARMV5TEPat<(int_arm_smulbt GPR:$a, GPR:$b), 5754 (SMULBT GPR:$a, GPR:$b)>; 5755def : ARMV5TEPat<(int_arm_smultb GPR:$a, GPR:$b), 5756 (SMULTB GPR:$a, GPR:$b)>; 5757def : ARMV5TEPat<(int_arm_smultt GPR:$a, GPR:$b), 5758 (SMULTT GPR:$a, GPR:$b)>; 5759def : ARMV5TEPat<(int_arm_smulwb GPR:$a, GPR:$b), 5760 (SMULWB GPR:$a, GPR:$b)>; 5761def : ARMV5TEPat<(int_arm_smulwt GPR:$a, GPR:$b), 5762 (SMULWT GPR:$a, GPR:$b)>; 5763 5764def : ARMV5TEPat<(int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc), 5765 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5766def : ARMV5TEPat<(int_arm_smlabt GPR:$a, GPR:$b, GPR:$acc), 5767 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5768def : ARMV5TEPat<(int_arm_smlatb GPR:$a, GPR:$b, GPR:$acc), 5769 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5770def : ARMV5TEPat<(int_arm_smlatt GPR:$a, GPR:$b, GPR:$acc), 5771 (SMLATT GPR:$a, GPR:$b, GPR:$acc)>; 5772def : ARMV5TEPat<(int_arm_smlawb GPR:$a, GPR:$b, GPR:$acc), 5773 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 5774def : ARMV5TEPat<(int_arm_smlawt GPR:$a, GPR:$b, GPR:$acc), 5775 (SMLAWT GPR:$a, GPR:$b, GPR:$acc)>; 5776 5777// Pre-v7 uses MCR for synchronization barriers. 5778def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>, 5779 Requires<[IsARM, HasV6]>; 5780 5781// SXT/UXT with no rotate 5782let AddedComplexity = 16 in { 5783def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>; 5784def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>; 5785def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>; 5786def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)), 5787 (UXTAB GPR:$Rn, GPR:$Rm, 0)>; 5788def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)), 5789 (UXTAH GPR:$Rn, GPR:$Rm, 0)>; 5790} 5791 5792def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>; 5793def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; 5794 5795def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)), 5796 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>; 5797def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)), 5798 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>; 5799 5800// Atomic load/store patterns 5801def : ARMPat<(atomic_load_8 ldst_so_reg:$src), 5802 (LDRBrs ldst_so_reg:$src)>; 5803def : ARMPat<(atomic_load_8 addrmode_imm12:$src), 5804 (LDRBi12 addrmode_imm12:$src)>; 5805def : ARMPat<(atomic_load_16 addrmode3:$src), 5806 (LDRH addrmode3:$src)>; 5807def : ARMPat<(atomic_load_32 ldst_so_reg:$src), 5808 (LDRrs ldst_so_reg:$src)>; 5809def : ARMPat<(atomic_load_32 addrmode_imm12:$src), 5810 (LDRi12 addrmode_imm12:$src)>; 5811def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val), 5812 (STRBrs GPR:$val, ldst_so_reg:$ptr)>; 5813def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val), 5814 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>; 5815def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val), 5816 (STRH GPR:$val, addrmode3:$ptr)>; 5817def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val), 5818 (STRrs GPR:$val, ldst_so_reg:$ptr)>; 5819def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val), 5820 (STRi12 GPR:$val, addrmode_imm12:$ptr)>; 5821 5822 5823//===----------------------------------------------------------------------===// 5824// Thumb Support 5825// 5826 5827include "ARMInstrThumb.td" 5828 5829//===----------------------------------------------------------------------===// 5830// Thumb2 Support 5831// 5832 5833include "ARMInstrThumb2.td" 5834 5835//===----------------------------------------------------------------------===// 5836// Floating Point Support 5837// 5838 5839include "ARMInstrVFP.td" 5840 5841//===----------------------------------------------------------------------===// 5842// Advanced SIMD (NEON) Support 5843// 5844 5845include "ARMInstrNEON.td" 5846 5847//===----------------------------------------------------------------------===// 5848// Assembler aliases 5849// 5850 5851// Memory barriers 5852def : InstAlias<"dmb", (DMB 0xf), 0>, Requires<[IsARM, HasDB]>; 5853def : InstAlias<"dsb", (DSB 0xf), 0>, Requires<[IsARM, HasDB]>; 5854def : InstAlias<"isb", (ISB 0xf), 0>, Requires<[IsARM, HasDB]>; 5855 5856// System instructions 5857def : MnemonicAlias<"swi", "svc">; 5858 5859// Load / Store Multiple 5860def : MnemonicAlias<"ldmfd", "ldm">; 5861def : MnemonicAlias<"ldmia", "ldm">; 5862def : MnemonicAlias<"ldmea", "ldmdb">; 5863def : MnemonicAlias<"stmfd", "stmdb">; 5864def : MnemonicAlias<"stmia", "stm">; 5865def : MnemonicAlias<"stmea", "stm">; 5866 5867// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the 5868// input operands swapped when the shift amount is zero (i.e., unspecified). 5869def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 5870 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p), 0>, 5871 Requires<[IsARM, HasV6]>; 5872def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 5873 (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p), 0>, 5874 Requires<[IsARM, HasV6]>; 5875 5876// PUSH/POP aliases for STM/LDM 5877def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>; 5878def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>; 5879 5880// SSAT/USAT optional shift operand. 5881def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 5882 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5883def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn", 5884 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5885 5886 5887// Extend instruction optional rotate operand. 5888def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm", 5889 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5890def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm", 5891 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5892def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 5893 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5894def : ARMInstAlias<"sxtb${p} $Rd, $Rm", 5895 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5896def : ARMInstAlias<"sxtb16${p} $Rd, $Rm", 5897 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5898def : ARMInstAlias<"sxth${p} $Rd, $Rm", 5899 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5900 5901def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm", 5902 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5903def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm", 5904 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5905def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 5906 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5907def : ARMInstAlias<"uxtb${p} $Rd, $Rm", 5908 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5909def : ARMInstAlias<"uxtb16${p} $Rd, $Rm", 5910 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5911def : ARMInstAlias<"uxth${p} $Rd, $Rm", 5912 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5913 5914 5915// RFE aliases 5916def : MnemonicAlias<"rfefa", "rfeda">; 5917def : MnemonicAlias<"rfeea", "rfedb">; 5918def : MnemonicAlias<"rfefd", "rfeia">; 5919def : MnemonicAlias<"rfeed", "rfeib">; 5920def : MnemonicAlias<"rfe", "rfeia">; 5921 5922// SRS aliases 5923def : MnemonicAlias<"srsfa", "srsib">; 5924def : MnemonicAlias<"srsea", "srsia">; 5925def : MnemonicAlias<"srsfd", "srsdb">; 5926def : MnemonicAlias<"srsed", "srsda">; 5927def : MnemonicAlias<"srs", "srsia">; 5928 5929// QSAX == QSUBADDX 5930def : MnemonicAlias<"qsubaddx", "qsax">; 5931// SASX == SADDSUBX 5932def : MnemonicAlias<"saddsubx", "sasx">; 5933// SHASX == SHADDSUBX 5934def : MnemonicAlias<"shaddsubx", "shasx">; 5935// SHSAX == SHSUBADDX 5936def : MnemonicAlias<"shsubaddx", "shsax">; 5937// SSAX == SSUBADDX 5938def : MnemonicAlias<"ssubaddx", "ssax">; 5939// UASX == UADDSUBX 5940def : MnemonicAlias<"uaddsubx", "uasx">; 5941// UHASX == UHADDSUBX 5942def : MnemonicAlias<"uhaddsubx", "uhasx">; 5943// UHSAX == UHSUBADDX 5944def : MnemonicAlias<"uhsubaddx", "uhsax">; 5945// UQASX == UQADDSUBX 5946def : MnemonicAlias<"uqaddsubx", "uqasx">; 5947// UQSAX == UQSUBADDX 5948def : MnemonicAlias<"uqsubaddx", "uqsax">; 5949// USAX == USUBADDX 5950def : MnemonicAlias<"usubaddx", "usax">; 5951 5952// "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like 5953// for isel. 5954def : ARMInstSubst<"mov${s}${p} $Rd, $imm", 5955 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 5956def : ARMInstSubst<"mvn${s}${p} $Rd, $imm", 5957 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 5958// Same for AND <--> BIC 5959def : ARMInstSubst<"bic${s}${p} $Rd, $Rn, $imm", 5960 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 5961 pred:$p, cc_out:$s)>; 5962def : ARMInstSubst<"bic${s}${p} $Rdn, $imm", 5963 (ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 5964 pred:$p, cc_out:$s)>; 5965def : ARMInstSubst<"and${s}${p} $Rd, $Rn, $imm", 5966 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 5967 pred:$p, cc_out:$s)>; 5968def : ARMInstSubst<"and${s}${p} $Rdn, $imm", 5969 (BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 5970 pred:$p, cc_out:$s)>; 5971 5972// Likewise, "add Rd, mod_imm_neg" -> sub 5973def : ARMInstSubst<"add${s}${p} $Rd, $Rn, $imm", 5974 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 5975def : ARMInstSubst<"add${s}${p} $Rd, $imm", 5976 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 5977// Likewise, "sub Rd, mod_imm_neg" -> add 5978def : ARMInstSubst<"sub${s}${p} $Rd, $Rn, $imm", 5979 (ADDri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 5980def : ARMInstSubst<"sub${s}${p} $Rd, $imm", 5981 (ADDri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 5982 5983 5984def : ARMInstSubst<"adc${s}${p} $Rd, $Rn, $imm", 5985 (SBCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 5986def : ARMInstSubst<"adc${s}${p} $Rdn, $imm", 5987 (SBCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 5988def : ARMInstSubst<"sbc${s}${p} $Rd, $Rn, $imm", 5989 (ADCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 5990def : ARMInstSubst<"sbc${s}${p} $Rdn, $imm", 5991 (ADCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 5992 5993// Same for CMP <--> CMN via mod_imm_neg 5994def : ARMInstSubst<"cmp${p} $Rd, $imm", 5995 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 5996def : ARMInstSubst<"cmn${p} $Rd, $imm", 5997 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 5998 5999// The shifter forms of the MOV instruction are aliased to the ASR, LSL, 6000// LSR, ROR, and RRX instructions. 6001// FIXME: We need C++ parser hooks to map the alias to the MOV 6002// encoding. It seems we should be able to do that sort of thing 6003// in tblgen, but it could get ugly. 6004let TwoOperandAliasConstraint = "$Rm = $Rd" in { 6005def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm", 6006 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 6007 cc_out:$s)>; 6008def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm", 6009 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 6010 cc_out:$s)>; 6011def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm", 6012 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 6013 cc_out:$s)>; 6014def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm", 6015 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 6016 cc_out:$s)>; 6017} 6018def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm", 6019 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>; 6020let TwoOperandAliasConstraint = "$Rn = $Rd" in { 6021def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm", 6022 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6023 cc_out:$s)>; 6024def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm", 6025 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6026 cc_out:$s)>; 6027def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm", 6028 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6029 cc_out:$s)>; 6030def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm", 6031 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6032 cc_out:$s)>; 6033} 6034 6035// "neg" is and alias for "rsb rd, rn, #0" 6036def : ARMInstAlias<"neg${s}${p} $Rd, $Rm", 6037 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>; 6038 6039// Pre-v6, 'mov r0, r0' was used as a NOP encoding. 6040def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>, 6041 Requires<[IsARM, NoV6]>; 6042 6043// MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but 6044// the instruction definitions need difference constraints pre-v6. 6045// Use these aliases for the assembly parsing on pre-v6. 6046def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm", 6047 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s), 0>, 6048 Requires<[IsARM, NoV6]>; 6049def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra", 6050 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 6051 pred:$p, cc_out:$s), 0>, 6052 Requires<[IsARM, NoV6]>; 6053def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6054 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6055 Requires<[IsARM, NoV6]>; 6056def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6057 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6058 Requires<[IsARM, NoV6]>; 6059def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6060 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6061 Requires<[IsARM, NoV6]>; 6062def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6063 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6064 Requires<[IsARM, NoV6]>; 6065 6066// 'it' blocks in ARM mode just validate the predicates. The IT itself 6067// is discarded. 6068def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>, 6069 ComplexDeprecationPredicate<"IT">; 6070 6071let mayLoad = 1, mayStore =1, hasSideEffects = 1 in 6072def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn), 6073 NoItinerary, 6074 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>; 6075 6076//===---------------------------------- 6077// Atomic cmpxchg for -O0 6078//===---------------------------------- 6079 6080// The fast register allocator used during -O0 inserts spills to cover any VRegs 6081// live across basic block boundaries. When this happens between an LDXR and an 6082// STXR it can clear the exclusive monitor, causing all cmpxchg attempts to 6083// fail. 6084 6085// Unfortunately, this means we have to have an alternative (expanded 6086// post-regalloc) path for -O0 compilations. Fortunately this path can be 6087// significantly more naive than the standard expansion: we conservatively 6088// assume seq_cst, strong cmpxchg and omit clrex on failure. 6089 6090let Constraints = "@earlyclobber $Rd,@earlyclobber $temp", 6091 mayLoad = 1, mayStore = 1 in { 6092def CMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6093 (ins GPR:$addr, GPR:$desired, GPR:$new), 6094 NoItinerary, []>, Sched<[]>; 6095 6096def CMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6097 (ins GPR:$addr, GPR:$desired, GPR:$new), 6098 NoItinerary, []>, Sched<[]>; 6099 6100def CMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6101 (ins GPR:$addr, GPR:$desired, GPR:$new), 6102 NoItinerary, []>, Sched<[]>; 6103 6104def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$temp), 6105 (ins GPR:$addr, GPRPair:$desired, GPRPair:$new), 6106 NoItinerary, []>, Sched<[]>; 6107} 6108 6109def CompilerBarrier : PseudoInst<(outs), (ins i32imm:$ordering), NoItinerary, 6110 [(atomic_fence imm:$ordering, 0)]> { 6111 let hasSideEffects = 1; 6112 let Size = 0; 6113 let AsmString = "@ COMPILER BARRIER"; 6114} 6115