1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// ARM specific DAG Nodes. 16// 17 18// Type profiles. 19def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 20def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 21def SDT_ARMStructByVal : SDTypeProfile<0, 4, 22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 24 25def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 26 27def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 28 29def SDT_ARMCMov : SDTypeProfile<1, 3, 30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 31 SDTCisVT<3, i32>]>; 32 33def SDT_ARMBrcond : SDTypeProfile<0, 2, 34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 35 36def SDT_ARMBrJT : SDTypeProfile<0, 3, 37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 38 SDTCisVT<2, i32>]>; 39 40def SDT_ARMBr2JT : SDTypeProfile<0, 4, 41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 43 44def SDT_ARMBCC_i64 : SDTypeProfile<0, 6, 45 [SDTCisVT<0, i32>, 46 SDTCisVT<1, i32>, SDTCisVT<2, i32>, 47 SDTCisVT<3, i32>, SDTCisVT<4, i32>, 48 SDTCisVT<5, OtherVT>]>; 49 50def SDT_ARMAnd : SDTypeProfile<1, 2, 51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 52 SDTCisVT<2, i32>]>; 53 54def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 55 56def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 58 59def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 60def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, 61 SDTCisInt<2>]>; 62def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 63 64def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 65 66def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, 67 SDTCisInt<1>]>; 68 69def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 70 71def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 73 74def SDT_ARMVMAXNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>; 75def SDT_ARMVMINNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>; 76 77def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 78 [SDTCisSameAs<0, 2>, 79 SDTCisSameAs<0, 3>, 80 SDTCisInt<0>, SDTCisVT<1, i32>]>; 81 82// SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR 83def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 84 [SDTCisSameAs<0, 2>, 85 SDTCisSameAs<0, 3>, 86 SDTCisInt<0>, 87 SDTCisVT<1, i32>, 88 SDTCisVT<4, i32>]>; 89 90def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>, 91 SDTCisVT<2, i32>, SDTCisVT<3, i32>, 92 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >; 93def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>; 94def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>; 95 96// Node definitions. 97def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 98def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>; 99def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>; 100 101def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 102 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 103def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 104 [SDNPHasChain, SDNPSideEffect, 105 SDNPOptInGlue, SDNPOutGlue]>; 106def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" , 107 SDT_ARMStructByVal, 108 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 109 SDNPMayStore, SDNPMayLoad]>; 110 111def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 112 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 113 SDNPVariadic]>; 114def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 116 SDNPVariadic]>; 117def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 119 SDNPVariadic]>; 120 121def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, 122 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 123def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall, 124 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 125def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 126 [SDNPInGlue]>; 127 128def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 129 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 130 131def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 132 [SDNPHasChain]>; 133def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, 134 [SDNPHasChain]>; 135 136def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64, 137 [SDNPHasChain]>; 138 139def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 140 [SDNPOutGlue]>; 141 142def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp, 143 [SDNPOutGlue]>; 144 145def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, 146 [SDNPOutGlue, SDNPCommutative]>; 147 148def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 149 150def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 151def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 152def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>; 153 154def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags, 155 [SDNPCommutative]>; 156def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>; 157def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>; 158def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>; 159 160def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 161def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", 162 SDT_ARMEH_SJLJ_Setjmp, 163 [SDNPHasChain, SDNPSideEffect]>; 164def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP", 165 SDT_ARMEH_SJLJ_Longjmp, 166 [SDNPHasChain, SDNPSideEffect]>; 167 168def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER, 169 [SDNPHasChain, SDNPSideEffect]>; 170def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH, 171 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 172 173def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>; 174 175def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET, 176 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 177 178def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; 179 180def ARMvmaxnm : SDNode<"ARMISD::VMAXNM", SDT_ARMVMAXNM, []>; 181def ARMvminnm : SDNode<"ARMISD::VMINNM", SDT_ARMVMINNM, []>; 182 183//===----------------------------------------------------------------------===// 184// ARM Instruction Predicate Definitions. 185// 186def HasV4T : Predicate<"Subtarget->hasV4TOps()">, 187 AssemblerPredicate<"HasV4TOps", "armv4t">; 188def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; 189def HasV5T : Predicate<"Subtarget->hasV5TOps()">, 190 AssemblerPredicate<"HasV5TOps", "armv5t">; 191def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, 192 AssemblerPredicate<"HasV5TEOps", "armv5te">; 193def HasV6 : Predicate<"Subtarget->hasV6Ops()">, 194 AssemblerPredicate<"HasV6Ops", "armv6">; 195def NoV6 : Predicate<"!Subtarget->hasV6Ops()">; 196def HasV6M : Predicate<"Subtarget->hasV6MOps()">, 197 AssemblerPredicate<"HasV6MOps", 198 "armv6m or armv6t2">; 199def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, 200 AssemblerPredicate<"HasV6T2Ops", "armv6t2">; 201def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; 202def HasV7 : Predicate<"Subtarget->hasV7Ops()">, 203 AssemblerPredicate<"HasV7Ops", "armv7">; 204def HasV8 : Predicate<"Subtarget->hasV8Ops()">, 205 AssemblerPredicate<"HasV8Ops", "armv8">; 206def PreV8 : Predicate<"!Subtarget->hasV8Ops()">, 207 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">; 208def NoVFP : Predicate<"!Subtarget->hasVFP2()">; 209def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, 210 AssemblerPredicate<"FeatureVFP2", "VFP2">; 211def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, 212 AssemblerPredicate<"FeatureVFP3", "VFP3">; 213def HasVFP4 : Predicate<"Subtarget->hasVFP4()">, 214 AssemblerPredicate<"FeatureVFP4", "VFP4">; 215def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">, 216 AssemblerPredicate<"!FeatureVFPOnlySP", 217 "double precision VFP">; 218def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, 219 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">; 220def HasNEON : Predicate<"Subtarget->hasNEON()">, 221 AssemblerPredicate<"FeatureNEON", "NEON">; 222def HasCrypto : Predicate<"Subtarget->hasCrypto()">, 223 AssemblerPredicate<"FeatureCrypto", "crypto">; 224def HasCRC : Predicate<"Subtarget->hasCRC()">, 225 AssemblerPredicate<"FeatureCRC", "crc">; 226def HasFP16 : Predicate<"Subtarget->hasFP16()">, 227 AssemblerPredicate<"FeatureFP16","half-float">; 228def HasDivide : Predicate<"Subtarget->hasDivide()">, 229 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">; 230def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">, 231 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">; 232def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">, 233 AssemblerPredicate<"FeatureT2XtPk", 234 "pack/extract">; 235def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">, 236 AssemblerPredicate<"FeatureDSPThumb2", 237 "thumb2-dsp">; 238def HasDB : Predicate<"Subtarget->hasDataBarrier()">, 239 AssemblerPredicate<"FeatureDB", 240 "data-barriers">; 241def HasMP : Predicate<"Subtarget->hasMPExtension()">, 242 AssemblerPredicate<"FeatureMP", 243 "mp-extensions">; 244def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">, 245 AssemblerPredicate<"FeatureTrustZone", 246 "TrustZone">; 247def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; 248def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; 249def IsThumb : Predicate<"Subtarget->isThumb()">, 250 AssemblerPredicate<"ModeThumb", "thumb">; 251def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; 252def IsThumb2 : Predicate<"Subtarget->isThumb2()">, 253 AssemblerPredicate<"ModeThumb,FeatureThumb2", 254 "thumb2">; 255def IsMClass : Predicate<"Subtarget->isMClass()">, 256 AssemblerPredicate<"FeatureMClass", "armv*m">; 257def IsNotMClass : Predicate<"!Subtarget->isMClass()">, 258 AssemblerPredicate<"!FeatureMClass", 259 "!armv*m">; 260def IsARM : Predicate<"!Subtarget->isThumb()">, 261 AssemblerPredicate<"!ModeThumb", "arm-mode">; 262def IsIOS : Predicate<"Subtarget->isTargetIOS()">; 263def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">; 264def IsMachO : Predicate<"Subtarget->isTargetMachO()">; 265def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">; 266def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 267def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">, 268 AssemblerPredicate<"FeatureNaClTrap", "NaCl">; 269def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">; 270 271// FIXME: Eventually this will be just "hasV6T2Ops". 272def UseMovt : Predicate<"Subtarget->useMovt()">; 273def DontUseMovt : Predicate<"!Subtarget->useMovt()">; 274def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">; 275def UseMulOps : Predicate<"Subtarget->useMulOps()">; 276 277// Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available. 278// But only select them if more precision in FP computation is allowed. 279// Do not use them for Darwin platforms. 280def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion ==" 281 " FPOpFusion::Fast && " 282 " Subtarget->hasVFP4()) && " 283 "!Subtarget->isTargetDarwin()">; 284def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion ==" 285 " FPOpFusion::Fast &&" 286 " Subtarget->hasVFP4()) || " 287 "Subtarget->isTargetDarwin()">; 288 289// VGETLNi32 is microcoded on Swift - prefer VMOV. 290def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">; 291def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">; 292 293// VDUP.32 is microcoded on Swift - prefer VMOV. 294def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">; 295def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">; 296 297// Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as 298// this allows more effective execution domain optimization. See 299// setExecutionDomain(). 300def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">; 301def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">; 302 303def IsLE : Predicate<"getTargetLowering()->isLittleEndian()">; 304def IsBE : Predicate<"getTargetLowering()->isBigEndian()">; 305 306//===----------------------------------------------------------------------===// 307// ARM Flag Definitions. 308 309class RegConstraint<string C> { 310 string Constraints = C; 311} 312 313//===----------------------------------------------------------------------===// 314// ARM specific transformation functions and pattern fragments. 315// 316 317// imm_neg_XFORM - Return the negation of an i32 immediate value. 318def imm_neg_XFORM : SDNodeXForm<imm, [{ 319 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32); 320}]>; 321 322// imm_not_XFORM - Return the complement of a i32 immediate value. 323def imm_not_XFORM : SDNodeXForm<imm, [{ 324 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32); 325}]>; 326 327/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 328def imm16_31 : ImmLeaf<i32, [{ 329 return (int32_t)Imm >= 16 && (int32_t)Imm < 32; 330}]>; 331 332def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; } 333def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{ 334 unsigned Value = -(unsigned)N->getZExtValue(); 335 return Value && ARM_AM::getSOImmVal(Value) != -1; 336 }], imm_neg_XFORM> { 337 let ParserMatchClass = so_imm_neg_asmoperand; 338} 339 340// Note: this pattern doesn't require an encoder method and such, as it's 341// only used on aliases (Pat<> and InstAlias<>). The actual encoding 342// is handled by the destination instructions, which use so_imm. 343def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; } 344def so_imm_not : Operand<i32>, PatLeaf<(imm), [{ 345 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1; 346 }], imm_not_XFORM> { 347 let ParserMatchClass = so_imm_not_asmoperand; 348} 349 350// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 351def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 352 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; 353}]>; 354 355/// Split a 32-bit immediate into two 16 bit parts. 356def hi16 : SDNodeXForm<imm, [{ 357 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32); 358}]>; 359 360def lo16AllZero : PatLeaf<(i32 imm), [{ 361 // Returns true if all low 16-bits are 0. 362 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 363}], hi16>; 364 365class BinOpWithFlagFrag<dag res> : 366 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>; 367class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 368class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 369 370// An 'and' node with a single use. 371def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 372 return N->hasOneUse(); 373}]>; 374 375// An 'xor' node with a single use. 376def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{ 377 return N->hasOneUse(); 378}]>; 379 380// An 'fmul' node with a single use. 381def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{ 382 return N->hasOneUse(); 383}]>; 384 385// An 'fadd' node which checks for single non-hazardous use. 386def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{ 387 return hasNoVMLxHazardUse(N); 388}]>; 389 390// An 'fsub' node which checks for single non-hazardous use. 391def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{ 392 return hasNoVMLxHazardUse(N); 393}]>; 394 395//===----------------------------------------------------------------------===// 396// Operand Definitions. 397// 398 399// Immediate operands with a shared generic asm render method. 400class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; } 401 402// Branch target. 403// FIXME: rename brtarget to t2_brtarget 404def brtarget : Operand<OtherVT> { 405 let EncoderMethod = "getBranchTargetOpValue"; 406 let OperandType = "OPERAND_PCREL"; 407 let DecoderMethod = "DecodeT2BROperand"; 408} 409 410// FIXME: get rid of this one? 411def uncondbrtarget : Operand<OtherVT> { 412 let EncoderMethod = "getUnconditionalBranchTargetOpValue"; 413 let OperandType = "OPERAND_PCREL"; 414} 415 416// Branch target for ARM. Handles conditional/unconditional 417def br_target : Operand<OtherVT> { 418 let EncoderMethod = "getARMBranchTargetOpValue"; 419 let OperandType = "OPERAND_PCREL"; 420} 421 422// Call target. 423// FIXME: rename bltarget to t2_bl_target? 424def bltarget : Operand<i32> { 425 // Encoded the same as branch targets. 426 let EncoderMethod = "getBranchTargetOpValue"; 427 let OperandType = "OPERAND_PCREL"; 428} 429 430// Call target for ARM. Handles conditional/unconditional 431// FIXME: rename bl_target to t2_bltarget? 432def bl_target : Operand<i32> { 433 let EncoderMethod = "getARMBLTargetOpValue"; 434 let OperandType = "OPERAND_PCREL"; 435} 436 437def blx_target : Operand<i32> { 438 let EncoderMethod = "getARMBLXTargetOpValue"; 439 let OperandType = "OPERAND_PCREL"; 440} 441 442// A list of registers separated by comma. Used by load/store multiple. 443def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; } 444def reglist : Operand<i32> { 445 let EncoderMethod = "getRegisterListOpValue"; 446 let ParserMatchClass = RegListAsmOperand; 447 let PrintMethod = "printRegisterList"; 448 let DecoderMethod = "DecodeRegListOperand"; 449} 450 451def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">; 452 453def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; } 454def dpr_reglist : Operand<i32> { 455 let EncoderMethod = "getRegisterListOpValue"; 456 let ParserMatchClass = DPRRegListAsmOperand; 457 let PrintMethod = "printRegisterList"; 458 let DecoderMethod = "DecodeDPRRegListOperand"; 459} 460 461def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; } 462def spr_reglist : Operand<i32> { 463 let EncoderMethod = "getRegisterListOpValue"; 464 let ParserMatchClass = SPRRegListAsmOperand; 465 let PrintMethod = "printRegisterList"; 466 let DecoderMethod = "DecodeSPRRegListOperand"; 467} 468 469// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 470def cpinst_operand : Operand<i32> { 471 let PrintMethod = "printCPInstOperand"; 472} 473 474// Local PC labels. 475def pclabel : Operand<i32> { 476 let PrintMethod = "printPCLabel"; 477} 478 479// ADR instruction labels. 480def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; } 481def adrlabel : Operand<i32> { 482 let EncoderMethod = "getAdrLabelOpValue"; 483 let ParserMatchClass = AdrLabelAsmOperand; 484 let PrintMethod = "printAdrLabelOperand<0>"; 485} 486 487def neon_vcvt_imm32 : Operand<i32> { 488 let EncoderMethod = "getNEONVcvtImm32OpValue"; 489 let DecoderMethod = "DecodeVCVTImmOperand"; 490} 491 492// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. 493def rot_imm_XFORM: SDNodeXForm<imm, [{ 494 switch (N->getZExtValue()){ 495 default: assert(0); 496 case 0: return CurDAG->getTargetConstant(0, MVT::i32); 497 case 8: return CurDAG->getTargetConstant(1, MVT::i32); 498 case 16: return CurDAG->getTargetConstant(2, MVT::i32); 499 case 24: return CurDAG->getTargetConstant(3, MVT::i32); 500 } 501}]>; 502def RotImmAsmOperand : AsmOperandClass { 503 let Name = "RotImm"; 504 let ParserMethod = "parseRotImm"; 505} 506def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{ 507 int32_t v = N->getZExtValue(); 508 return v == 8 || v == 16 || v == 24; }], 509 rot_imm_XFORM> { 510 let PrintMethod = "printRotImmOperand"; 511 let ParserMatchClass = RotImmAsmOperand; 512} 513 514// shift_imm: An integer that encodes a shift amount and the type of shift 515// (asr or lsl). The 6-bit immediate encodes as: 516// {5} 0 ==> lsl 517// 1 asr 518// {4-0} imm5 shift amount. 519// asr #32 encoded as imm5 == 0. 520def ShifterImmAsmOperand : AsmOperandClass { 521 let Name = "ShifterImm"; 522 let ParserMethod = "parseShifterImm"; 523} 524def shift_imm : Operand<i32> { 525 let PrintMethod = "printShiftImmOperand"; 526 let ParserMatchClass = ShifterImmAsmOperand; 527} 528 529// shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm. 530def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; } 531def so_reg_reg : Operand<i32>, // reg reg imm 532 ComplexPattern<i32, 3, "SelectRegShifterOperand", 533 [shl, srl, sra, rotr]> { 534 let EncoderMethod = "getSORegRegOpValue"; 535 let PrintMethod = "printSORegRegOperand"; 536 let DecoderMethod = "DecodeSORegRegOperand"; 537 let ParserMatchClass = ShiftedRegAsmOperand; 538 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm); 539} 540 541def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; } 542def so_reg_imm : Operand<i32>, // reg imm 543 ComplexPattern<i32, 2, "SelectImmShifterOperand", 544 [shl, srl, sra, rotr]> { 545 let EncoderMethod = "getSORegImmOpValue"; 546 let PrintMethod = "printSORegImmOperand"; 547 let DecoderMethod = "DecodeSORegImmOperand"; 548 let ParserMatchClass = ShiftedImmAsmOperand; 549 let MIOperandInfo = (ops GPR, i32imm); 550} 551 552// FIXME: Does this need to be distinct from so_reg? 553def shift_so_reg_reg : Operand<i32>, // reg reg imm 554 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand", 555 [shl,srl,sra,rotr]> { 556 let EncoderMethod = "getSORegRegOpValue"; 557 let PrintMethod = "printSORegRegOperand"; 558 let DecoderMethod = "DecodeSORegRegOperand"; 559 let ParserMatchClass = ShiftedRegAsmOperand; 560 let MIOperandInfo = (ops GPR, GPR, i32imm); 561} 562 563// FIXME: Does this need to be distinct from so_reg? 564def shift_so_reg_imm : Operand<i32>, // reg reg imm 565 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand", 566 [shl,srl,sra,rotr]> { 567 let EncoderMethod = "getSORegImmOpValue"; 568 let PrintMethod = "printSORegImmOperand"; 569 let DecoderMethod = "DecodeSORegImmOperand"; 570 let ParserMatchClass = ShiftedImmAsmOperand; 571 let MIOperandInfo = (ops GPR, i32imm); 572} 573 574 575// so_imm - Match a 32-bit shifter_operand immediate operand, which is an 576// 8-bit immediate rotated by an arbitrary number of bits. 577def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; } 578def so_imm : Operand<i32>, ImmLeaf<i32, [{ 579 return ARM_AM::getSOImmVal(Imm) != -1; 580 }]> { 581 let EncoderMethod = "getSOImmOpValue"; 582 let ParserMatchClass = SOImmAsmOperand; 583 let DecoderMethod = "DecodeSOImmOperand"; 584} 585 586// Break so_imm's up into two pieces. This handles immediates with up to 16 587// bits set in them. This uses so_imm2part to match and so_imm2part_[12] to 588// get the first/second pieces. 589def so_imm2part : PatLeaf<(imm), [{ 590 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 591}]>; 592 593/// arm_i32imm - True for +V6T2, or true only if so_imm2part is true. 594/// 595def arm_i32imm : PatLeaf<(imm), [{ 596 if (Subtarget->useMovt()) 597 return true; 598 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 599}]>; 600 601/// imm0_1 predicate - Immediate in the range [0,1]. 602def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; } 603def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; } 604 605/// imm0_3 predicate - Immediate in the range [0,3]. 606def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; } 607def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; } 608 609/// imm0_7 predicate - Immediate in the range [0,7]. 610def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; } 611def imm0_7 : Operand<i32>, ImmLeaf<i32, [{ 612 return Imm >= 0 && Imm < 8; 613}]> { 614 let ParserMatchClass = Imm0_7AsmOperand; 615} 616 617/// imm8 predicate - Immediate is exactly 8. 618def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; } 619def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> { 620 let ParserMatchClass = Imm8AsmOperand; 621} 622 623/// imm16 predicate - Immediate is exactly 16. 624def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; } 625def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> { 626 let ParserMatchClass = Imm16AsmOperand; 627} 628 629/// imm32 predicate - Immediate is exactly 32. 630def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; } 631def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> { 632 let ParserMatchClass = Imm32AsmOperand; 633} 634 635/// imm1_7 predicate - Immediate in the range [1,7]. 636def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; } 637def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> { 638 let ParserMatchClass = Imm1_7AsmOperand; 639} 640 641/// imm1_15 predicate - Immediate in the range [1,15]. 642def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; } 643def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> { 644 let ParserMatchClass = Imm1_15AsmOperand; 645} 646 647/// imm1_31 predicate - Immediate in the range [1,31]. 648def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; } 649def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> { 650 let ParserMatchClass = Imm1_31AsmOperand; 651} 652 653/// imm0_15 predicate - Immediate in the range [0,15]. 654def Imm0_15AsmOperand: ImmAsmOperand { 655 let Name = "Imm0_15"; 656 let DiagnosticType = "ImmRange0_15"; 657} 658def imm0_15 : Operand<i32>, ImmLeaf<i32, [{ 659 return Imm >= 0 && Imm < 16; 660}]> { 661 let ParserMatchClass = Imm0_15AsmOperand; 662} 663 664/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31]. 665def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; } 666def imm0_31 : Operand<i32>, ImmLeaf<i32, [{ 667 return Imm >= 0 && Imm < 32; 668}]> { 669 let ParserMatchClass = Imm0_31AsmOperand; 670} 671 672/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32]. 673def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; } 674def imm0_32 : Operand<i32>, ImmLeaf<i32, [{ 675 return Imm >= 0 && Imm < 32; 676}]> { 677 let ParserMatchClass = Imm0_32AsmOperand; 678} 679 680/// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63]. 681def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; } 682def imm0_63 : Operand<i32>, ImmLeaf<i32, [{ 683 return Imm >= 0 && Imm < 64; 684}]> { 685 let ParserMatchClass = Imm0_63AsmOperand; 686} 687 688/// imm0_239 predicate - Immediate in the range [0,239]. 689def Imm0_239AsmOperand : ImmAsmOperand { 690 let Name = "Imm0_239"; 691 let DiagnosticType = "ImmRange0_239"; 692} 693def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> { 694 let ParserMatchClass = Imm0_239AsmOperand; 695} 696 697/// imm0_255 predicate - Immediate in the range [0,255]. 698def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; } 699def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> { 700 let ParserMatchClass = Imm0_255AsmOperand; 701} 702 703/// imm0_65535 - An immediate is in the range [0.65535]. 704def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; } 705def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{ 706 return Imm >= 0 && Imm < 65536; 707}]> { 708 let ParserMatchClass = Imm0_65535AsmOperand; 709} 710 711// imm0_65535_neg - An immediate whose negative value is in the range [0.65535]. 712def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{ 713 return -Imm >= 0 && -Imm < 65536; 714}]>; 715 716// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference 717// a relocatable expression. 718// 719// FIXME: This really needs a Thumb version separate from the ARM version. 720// While the range is the same, and can thus use the same match class, 721// the encoding is different so it should have a different encoder method. 722def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; } 723def imm0_65535_expr : Operand<i32> { 724 let EncoderMethod = "getHiLo16ImmOpValue"; 725 let ParserMatchClass = Imm0_65535ExprAsmOperand; 726} 727 728def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; } 729def imm256_65535_expr : Operand<i32> { 730 let ParserMatchClass = Imm256_65535ExprAsmOperand; 731} 732 733/// imm24b - True if the 32-bit immediate is encodable in 24 bits. 734def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; } 735def imm24b : Operand<i32>, ImmLeaf<i32, [{ 736 return Imm >= 0 && Imm <= 0xffffff; 737}]> { 738 let ParserMatchClass = Imm24bitAsmOperand; 739} 740 741 742/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield 743/// e.g., 0xf000ffff 744def BitfieldAsmOperand : AsmOperandClass { 745 let Name = "Bitfield"; 746 let ParserMethod = "parseBitfield"; 747} 748 749def bf_inv_mask_imm : Operand<i32>, 750 PatLeaf<(imm), [{ 751 return ARM::isBitFieldInvertedMask(N->getZExtValue()); 752}] > { 753 let EncoderMethod = "getBitfieldInvertedMaskOpValue"; 754 let PrintMethod = "printBitfieldInvMaskImmOperand"; 755 let DecoderMethod = "DecodeBitfieldMaskOperand"; 756 let ParserMatchClass = BitfieldAsmOperand; 757} 758 759def imm1_32_XFORM: SDNodeXForm<imm, [{ 760 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32); 761}]>; 762def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; } 763def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ 764 uint64_t Imm = N->getZExtValue(); 765 return Imm > 0 && Imm <= 32; 766 }], 767 imm1_32_XFORM> { 768 let PrintMethod = "printImmPlusOneOperand"; 769 let ParserMatchClass = Imm1_32AsmOperand; 770} 771 772def imm1_16_XFORM: SDNodeXForm<imm, [{ 773 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32); 774}]>; 775def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; } 776def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }], 777 imm1_16_XFORM> { 778 let PrintMethod = "printImmPlusOneOperand"; 779 let ParserMatchClass = Imm1_16AsmOperand; 780} 781 782// Define ARM specific addressing modes. 783// addrmode_imm12 := reg +/- imm12 784// 785def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; } 786class AddrMode_Imm12 : Operand<i32>, 787 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> { 788 // 12-bit immediate operand. Note that instructions using this encode 789 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other 790 // immediate values are as normal. 791 792 let EncoderMethod = "getAddrModeImm12OpValue"; 793 let DecoderMethod = "DecodeAddrModeImm12Operand"; 794 let ParserMatchClass = MemImm12OffsetAsmOperand; 795 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 796} 797 798def addrmode_imm12 : AddrMode_Imm12 { 799 let PrintMethod = "printAddrModeImm12Operand<false>"; 800} 801 802def addrmode_imm12_pre : AddrMode_Imm12 { 803 let PrintMethod = "printAddrModeImm12Operand<true>"; 804} 805 806// ldst_so_reg := reg +/- reg shop imm 807// 808def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; } 809def ldst_so_reg : Operand<i32>, 810 ComplexPattern<i32, 3, "SelectLdStSOReg", []> { 811 let EncoderMethod = "getLdStSORegOpValue"; 812 // FIXME: Simplify the printer 813 let PrintMethod = "printAddrMode2Operand"; 814 let DecoderMethod = "DecodeSORegMemOperand"; 815 let ParserMatchClass = MemRegOffsetAsmOperand; 816 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift); 817} 818 819// postidx_imm8 := +/- [0,255] 820// 821// 9 bit value: 822// {8} 1 is imm8 is non-negative. 0 otherwise. 823// {7-0} [0,255] imm8 value. 824def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; } 825def postidx_imm8 : Operand<i32> { 826 let PrintMethod = "printPostIdxImm8Operand"; 827 let ParserMatchClass = PostIdxImm8AsmOperand; 828 let MIOperandInfo = (ops i32imm); 829} 830 831// postidx_imm8s4 := +/- [0,1020] 832// 833// 9 bit value: 834// {8} 1 is imm8 is non-negative. 0 otherwise. 835// {7-0} [0,255] imm8 value, scaled by 4. 836def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; } 837def postidx_imm8s4 : Operand<i32> { 838 let PrintMethod = "printPostIdxImm8s4Operand"; 839 let ParserMatchClass = PostIdxImm8s4AsmOperand; 840 let MIOperandInfo = (ops i32imm); 841} 842 843 844// postidx_reg := +/- reg 845// 846def PostIdxRegAsmOperand : AsmOperandClass { 847 let Name = "PostIdxReg"; 848 let ParserMethod = "parsePostIdxReg"; 849} 850def postidx_reg : Operand<i32> { 851 let EncoderMethod = "getPostIdxRegOpValue"; 852 let DecoderMethod = "DecodePostIdxReg"; 853 let PrintMethod = "printPostIdxRegOperand"; 854 let ParserMatchClass = PostIdxRegAsmOperand; 855 let MIOperandInfo = (ops GPRnopc, i32imm); 856} 857 858 859// addrmode2 := reg +/- imm12 860// := reg +/- reg shop imm 861// 862// FIXME: addrmode2 should be refactored the rest of the way to always 863// use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg). 864def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; } 865def addrmode2 : Operand<i32>, 866 ComplexPattern<i32, 3, "SelectAddrMode2", []> { 867 let EncoderMethod = "getAddrMode2OpValue"; 868 let PrintMethod = "printAddrMode2Operand"; 869 let ParserMatchClass = AddrMode2AsmOperand; 870 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 871} 872 873def PostIdxRegShiftedAsmOperand : AsmOperandClass { 874 let Name = "PostIdxRegShifted"; 875 let ParserMethod = "parsePostIdxReg"; 876} 877def am2offset_reg : Operand<i32>, 878 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg", 879 [], [SDNPWantRoot]> { 880 let EncoderMethod = "getAddrMode2OffsetOpValue"; 881 let PrintMethod = "printAddrMode2OffsetOperand"; 882 // When using this for assembly, it's always as a post-index offset. 883 let ParserMatchClass = PostIdxRegShiftedAsmOperand; 884 let MIOperandInfo = (ops GPRnopc, i32imm); 885} 886 887// FIXME: am2offset_imm should only need the immediate, not the GPR. Having 888// the GPR is purely vestigal at this point. 889def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; } 890def am2offset_imm : Operand<i32>, 891 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm", 892 [], [SDNPWantRoot]> { 893 let EncoderMethod = "getAddrMode2OffsetOpValue"; 894 let PrintMethod = "printAddrMode2OffsetOperand"; 895 let ParserMatchClass = AM2OffsetImmAsmOperand; 896 let MIOperandInfo = (ops GPRnopc, i32imm); 897} 898 899 900// addrmode3 := reg +/- reg 901// addrmode3 := reg +/- imm8 902// 903// FIXME: split into imm vs. reg versions. 904def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; } 905class AddrMode3 : Operand<i32>, 906 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 907 let EncoderMethod = "getAddrMode3OpValue"; 908 let ParserMatchClass = AddrMode3AsmOperand; 909 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 910} 911 912def addrmode3 : AddrMode3 913{ 914 let PrintMethod = "printAddrMode3Operand<false>"; 915} 916 917def addrmode3_pre : AddrMode3 918{ 919 let PrintMethod = "printAddrMode3Operand<true>"; 920} 921 922// FIXME: split into imm vs. reg versions. 923// FIXME: parser method to handle +/- register. 924def AM3OffsetAsmOperand : AsmOperandClass { 925 let Name = "AM3Offset"; 926 let ParserMethod = "parseAM3Offset"; 927} 928def am3offset : Operand<i32>, 929 ComplexPattern<i32, 2, "SelectAddrMode3Offset", 930 [], [SDNPWantRoot]> { 931 let EncoderMethod = "getAddrMode3OffsetOpValue"; 932 let PrintMethod = "printAddrMode3OffsetOperand"; 933 let ParserMatchClass = AM3OffsetAsmOperand; 934 let MIOperandInfo = (ops GPR, i32imm); 935} 936 937// ldstm_mode := {ia, ib, da, db} 938// 939def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> { 940 let EncoderMethod = "getLdStmModeOpValue"; 941 let PrintMethod = "printLdStmModeOperand"; 942} 943 944// addrmode5 := reg +/- imm8*4 945// 946def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; } 947class AddrMode5 : Operand<i32>, 948 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 949 let EncoderMethod = "getAddrMode5OpValue"; 950 let DecoderMethod = "DecodeAddrMode5Operand"; 951 let ParserMatchClass = AddrMode5AsmOperand; 952 let MIOperandInfo = (ops GPR:$base, i32imm); 953} 954 955def addrmode5 : AddrMode5 { 956 let PrintMethod = "printAddrMode5Operand<false>"; 957} 958 959def addrmode5_pre : AddrMode5 { 960 let PrintMethod = "printAddrMode5Operand<true>"; 961} 962 963// addrmode6 := reg with optional alignment 964// 965def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; } 966def addrmode6 : Operand<i32>, 967 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 968 let PrintMethod = "printAddrMode6Operand"; 969 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 970 let EncoderMethod = "getAddrMode6AddressOpValue"; 971 let DecoderMethod = "DecodeAddrMode6Operand"; 972 let ParserMatchClass = AddrMode6AsmOperand; 973} 974 975def am6offset : Operand<i32>, 976 ComplexPattern<i32, 1, "SelectAddrMode6Offset", 977 [], [SDNPWantRoot]> { 978 let PrintMethod = "printAddrMode6OffsetOperand"; 979 let MIOperandInfo = (ops GPR); 980 let EncoderMethod = "getAddrMode6OffsetOpValue"; 981 let DecoderMethod = "DecodeGPRRegisterClass"; 982} 983 984// Special version of addrmode6 to handle alignment encoding for VST1/VLD1 985// (single element from one lane) for size 32. 986def addrmode6oneL32 : Operand<i32>, 987 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 988 let PrintMethod = "printAddrMode6Operand"; 989 let MIOperandInfo = (ops GPR:$addr, i32imm); 990 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue"; 991} 992 993// Special version of addrmode6 to handle alignment encoding for VLD-dup 994// instructions, specifically VLD4-dup. 995def addrmode6dup : Operand<i32>, 996 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 997 let PrintMethod = "printAddrMode6Operand"; 998 let MIOperandInfo = (ops GPR:$addr, i32imm); 999 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1000 // FIXME: This is close, but not quite right. The alignment specifier is 1001 // different. 1002 let ParserMatchClass = AddrMode6AsmOperand; 1003} 1004 1005// addrmodepc := pc + reg 1006// 1007def addrmodepc : Operand<i32>, 1008 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 1009 let PrintMethod = "printAddrModePCOperand"; 1010 let MIOperandInfo = (ops GPR, i32imm); 1011} 1012 1013// addr_offset_none := reg 1014// 1015def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; } 1016def addr_offset_none : Operand<i32>, 1017 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> { 1018 let PrintMethod = "printAddrMode7Operand"; 1019 let DecoderMethod = "DecodeAddrMode7Operand"; 1020 let ParserMatchClass = MemNoOffsetAsmOperand; 1021 let MIOperandInfo = (ops GPR:$base); 1022} 1023 1024def nohash_imm : Operand<i32> { 1025 let PrintMethod = "printNoHashImmediate"; 1026} 1027 1028def CoprocNumAsmOperand : AsmOperandClass { 1029 let Name = "CoprocNum"; 1030 let ParserMethod = "parseCoprocNumOperand"; 1031} 1032def p_imm : Operand<i32> { 1033 let PrintMethod = "printPImmediate"; 1034 let ParserMatchClass = CoprocNumAsmOperand; 1035 let DecoderMethod = "DecodeCoprocessor"; 1036} 1037 1038def CoprocRegAsmOperand : AsmOperandClass { 1039 let Name = "CoprocReg"; 1040 let ParserMethod = "parseCoprocRegOperand"; 1041} 1042def c_imm : Operand<i32> { 1043 let PrintMethod = "printCImmediate"; 1044 let ParserMatchClass = CoprocRegAsmOperand; 1045} 1046def CoprocOptionAsmOperand : AsmOperandClass { 1047 let Name = "CoprocOption"; 1048 let ParserMethod = "parseCoprocOptionOperand"; 1049} 1050def coproc_option_imm : Operand<i32> { 1051 let PrintMethod = "printCoprocOptionImm"; 1052 let ParserMatchClass = CoprocOptionAsmOperand; 1053} 1054 1055//===----------------------------------------------------------------------===// 1056 1057include "ARMInstrFormats.td" 1058 1059//===----------------------------------------------------------------------===// 1060// Multiclass helpers... 1061// 1062 1063/// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a 1064/// binop that produces a value. 1065let TwoOperandAliasConstraint = "$Rn = $Rd" in 1066multiclass AsI1_bin_irs<bits<4> opcod, string opc, 1067 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1068 PatFrag opnode, bit Commutable = 0> { 1069 // The register-immediate version is re-materializable. This is useful 1070 // in particular for taking the address of a local. 1071 let isReMaterializable = 1 in { 1072 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, 1073 iii, opc, "\t$Rd, $Rn, $imm", 1074 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>, 1075 Sched<[WriteALU, ReadALU]> { 1076 bits<4> Rd; 1077 bits<4> Rn; 1078 bits<12> imm; 1079 let Inst{25} = 1; 1080 let Inst{19-16} = Rn; 1081 let Inst{15-12} = Rd; 1082 let Inst{11-0} = imm; 1083 } 1084 } 1085 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1086 iir, opc, "\t$Rd, $Rn, $Rm", 1087 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, 1088 Sched<[WriteALU, ReadALU, ReadALU]> { 1089 bits<4> Rd; 1090 bits<4> Rn; 1091 bits<4> Rm; 1092 let Inst{25} = 0; 1093 let isCommutable = Commutable; 1094 let Inst{19-16} = Rn; 1095 let Inst{15-12} = Rd; 1096 let Inst{11-4} = 0b00000000; 1097 let Inst{3-0} = Rm; 1098 } 1099 1100 def rsi : AsI1<opcod, (outs GPR:$Rd), 1101 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1102 iis, opc, "\t$Rd, $Rn, $shift", 1103 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>, 1104 Sched<[WriteALUsi, ReadALU]> { 1105 bits<4> Rd; 1106 bits<4> Rn; 1107 bits<12> shift; 1108 let Inst{25} = 0; 1109 let Inst{19-16} = Rn; 1110 let Inst{15-12} = Rd; 1111 let Inst{11-5} = shift{11-5}; 1112 let Inst{4} = 0; 1113 let Inst{3-0} = shift{3-0}; 1114 } 1115 1116 def rsr : AsI1<opcod, (outs GPR:$Rd), 1117 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1118 iis, opc, "\t$Rd, $Rn, $shift", 1119 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>, 1120 Sched<[WriteALUsr, ReadALUsr]> { 1121 bits<4> Rd; 1122 bits<4> Rn; 1123 bits<12> shift; 1124 let Inst{25} = 0; 1125 let Inst{19-16} = Rn; 1126 let Inst{15-12} = Rd; 1127 let Inst{11-8} = shift{11-8}; 1128 let Inst{7} = 0; 1129 let Inst{6-5} = shift{6-5}; 1130 let Inst{4} = 1; 1131 let Inst{3-0} = shift{3-0}; 1132 } 1133} 1134 1135/// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are 1136/// reversed. The 'rr' form is only defined for the disassembler; for codegen 1137/// it is equivalent to the AsI1_bin_irs counterpart. 1138let TwoOperandAliasConstraint = "$Rn = $Rd" in 1139multiclass AsI1_rbin_irs<bits<4> opcod, string opc, 1140 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1141 PatFrag opnode, bit Commutable = 0> { 1142 // The register-immediate version is re-materializable. This is useful 1143 // in particular for taking the address of a local. 1144 let isReMaterializable = 1 in { 1145 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, 1146 iii, opc, "\t$Rd, $Rn, $imm", 1147 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>, 1148 Sched<[WriteALU, ReadALU]> { 1149 bits<4> Rd; 1150 bits<4> Rn; 1151 bits<12> imm; 1152 let Inst{25} = 1; 1153 let Inst{19-16} = Rn; 1154 let Inst{15-12} = Rd; 1155 let Inst{11-0} = imm; 1156 } 1157 } 1158 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1159 iir, opc, "\t$Rd, $Rn, $Rm", 1160 [/* pattern left blank */]>, 1161 Sched<[WriteALU, ReadALU, ReadALU]> { 1162 bits<4> Rd; 1163 bits<4> Rn; 1164 bits<4> Rm; 1165 let Inst{11-4} = 0b00000000; 1166 let Inst{25} = 0; 1167 let Inst{3-0} = Rm; 1168 let Inst{15-12} = Rd; 1169 let Inst{19-16} = Rn; 1170 } 1171 1172 def rsi : AsI1<opcod, (outs GPR:$Rd), 1173 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1174 iis, opc, "\t$Rd, $Rn, $shift", 1175 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>, 1176 Sched<[WriteALUsi, ReadALU]> { 1177 bits<4> Rd; 1178 bits<4> Rn; 1179 bits<12> shift; 1180 let Inst{25} = 0; 1181 let Inst{19-16} = Rn; 1182 let Inst{15-12} = Rd; 1183 let Inst{11-5} = shift{11-5}; 1184 let Inst{4} = 0; 1185 let Inst{3-0} = shift{3-0}; 1186 } 1187 1188 def rsr : AsI1<opcod, (outs GPR:$Rd), 1189 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1190 iis, opc, "\t$Rd, $Rn, $shift", 1191 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>, 1192 Sched<[WriteALUsr, ReadALUsr]> { 1193 bits<4> Rd; 1194 bits<4> Rn; 1195 bits<12> shift; 1196 let Inst{25} = 0; 1197 let Inst{19-16} = Rn; 1198 let Inst{15-12} = Rd; 1199 let Inst{11-8} = shift{11-8}; 1200 let Inst{7} = 0; 1201 let Inst{6-5} = shift{6-5}; 1202 let Inst{4} = 1; 1203 let Inst{3-0} = shift{3-0}; 1204 } 1205} 1206 1207/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default. 1208/// 1209/// These opcodes will be converted to the real non-S opcodes by 1210/// AdjustInstrPostInstrSelection after giving them an optional CPSR operand. 1211let hasPostISelHook = 1, Defs = [CPSR] in { 1212multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir, 1213 InstrItinClass iis, PatFrag opnode, 1214 bit Commutable = 0> { 1215 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p), 1216 4, iii, 1217 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>, 1218 Sched<[WriteALU, ReadALU]>; 1219 1220 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p), 1221 4, iir, 1222 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>, 1223 Sched<[WriteALU, ReadALU, ReadALU]> { 1224 let isCommutable = Commutable; 1225 } 1226 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1227 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1228 4, iis, 1229 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1230 so_reg_imm:$shift))]>, 1231 Sched<[WriteALUsi, ReadALU]>; 1232 1233 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1234 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1235 4, iis, 1236 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1237 so_reg_reg:$shift))]>, 1238 Sched<[WriteALUSsr, ReadALUsr]>; 1239} 1240} 1241 1242/// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG 1243/// operands are reversed. 1244let hasPostISelHook = 1, Defs = [CPSR] in { 1245multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir, 1246 InstrItinClass iis, PatFrag opnode, 1247 bit Commutable = 0> { 1248 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p), 1249 4, iii, 1250 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>, 1251 Sched<[WriteALU, ReadALU]>; 1252 1253 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1254 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1255 4, iis, 1256 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, 1257 GPR:$Rn))]>, 1258 Sched<[WriteALUsi, ReadALU]>; 1259 1260 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1261 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1262 4, iis, 1263 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, 1264 GPR:$Rn))]>, 1265 Sched<[WriteALUSsr, ReadALUsr]>; 1266} 1267} 1268 1269/// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 1270/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 1271/// a explicit result, only implicitly set CPSR. 1272let isCompare = 1, Defs = [CPSR] in { 1273multiclass AI1_cmp_irs<bits<4> opcod, string opc, 1274 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1275 PatFrag opnode, bit Commutable = 0> { 1276 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii, 1277 opc, "\t$Rn, $imm", 1278 [(opnode GPR:$Rn, so_imm:$imm)]>, 1279 Sched<[WriteCMP, ReadALU]> { 1280 bits<4> Rn; 1281 bits<12> imm; 1282 let Inst{25} = 1; 1283 let Inst{20} = 1; 1284 let Inst{19-16} = Rn; 1285 let Inst{15-12} = 0b0000; 1286 let Inst{11-0} = imm; 1287 1288 let Unpredictable{15-12} = 0b1111; 1289 } 1290 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir, 1291 opc, "\t$Rn, $Rm", 1292 [(opnode GPR:$Rn, GPR:$Rm)]>, 1293 Sched<[WriteCMP, ReadALU, ReadALU]> { 1294 bits<4> Rn; 1295 bits<4> Rm; 1296 let isCommutable = Commutable; 1297 let Inst{25} = 0; 1298 let Inst{20} = 1; 1299 let Inst{19-16} = Rn; 1300 let Inst{15-12} = 0b0000; 1301 let Inst{11-4} = 0b00000000; 1302 let Inst{3-0} = Rm; 1303 1304 let Unpredictable{15-12} = 0b1111; 1305 } 1306 def rsi : AI1<opcod, (outs), 1307 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis, 1308 opc, "\t$Rn, $shift", 1309 [(opnode GPR:$Rn, so_reg_imm:$shift)]>, 1310 Sched<[WriteCMPsi, ReadALU]> { 1311 bits<4> Rn; 1312 bits<12> shift; 1313 let Inst{25} = 0; 1314 let Inst{20} = 1; 1315 let Inst{19-16} = Rn; 1316 let Inst{15-12} = 0b0000; 1317 let Inst{11-5} = shift{11-5}; 1318 let Inst{4} = 0; 1319 let Inst{3-0} = shift{3-0}; 1320 1321 let Unpredictable{15-12} = 0b1111; 1322 } 1323 def rsr : AI1<opcod, (outs), 1324 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis, 1325 opc, "\t$Rn, $shift", 1326 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>, 1327 Sched<[WriteCMPsr, ReadALU]> { 1328 bits<4> Rn; 1329 bits<12> shift; 1330 let Inst{25} = 0; 1331 let Inst{20} = 1; 1332 let Inst{19-16} = Rn; 1333 let Inst{15-12} = 0b0000; 1334 let Inst{11-8} = shift{11-8}; 1335 let Inst{7} = 0; 1336 let Inst{6-5} = shift{6-5}; 1337 let Inst{4} = 1; 1338 let Inst{3-0} = shift{3-0}; 1339 1340 let Unpredictable{15-12} = 0b1111; 1341 } 1342 1343} 1344} 1345 1346/// AI_ext_rrot - A unary operation with two forms: one whose operand is a 1347/// register and one whose operand is a register rotated by 8/16/24. 1348/// FIXME: Remove the 'r' variant. Its rot_imm is zero. 1349class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> 1350 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1351 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", 1352 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1353 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1354 bits<4> Rd; 1355 bits<4> Rm; 1356 bits<2> rot; 1357 let Inst{19-16} = 0b1111; 1358 let Inst{15-12} = Rd; 1359 let Inst{11-10} = rot; 1360 let Inst{3-0} = Rm; 1361} 1362 1363class AI_ext_rrot_np<bits<8> opcod, string opc> 1364 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1365 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>, 1366 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1367 bits<2> rot; 1368 let Inst{19-16} = 0b1111; 1369 let Inst{11-10} = rot; 1370 } 1371 1372/// AI_exta_rrot - A binary operation with two forms: one whose operand is a 1373/// register and one whose operand is a register rotated by 8/16/24. 1374class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> 1375 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1376 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", 1377 [(set GPRnopc:$Rd, (opnode GPR:$Rn, 1378 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1379 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1380 bits<4> Rd; 1381 bits<4> Rm; 1382 bits<4> Rn; 1383 bits<2> rot; 1384 let Inst{19-16} = Rn; 1385 let Inst{15-12} = Rd; 1386 let Inst{11-10} = rot; 1387 let Inst{9-4} = 0b000111; 1388 let Inst{3-0} = Rm; 1389} 1390 1391class AI_exta_rrot_np<bits<8> opcod, string opc> 1392 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1393 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>, 1394 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1395 bits<4> Rn; 1396 bits<2> rot; 1397 let Inst{19-16} = Rn; 1398 let Inst{11-10} = rot; 1399} 1400 1401/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. 1402let TwoOperandAliasConstraint = "$Rn = $Rd" in 1403multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, 1404 bit Commutable = 0> { 1405 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1406 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), 1407 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1408 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>, 1409 Requires<[IsARM]>, 1410 Sched<[WriteALU, ReadALU]> { 1411 bits<4> Rd; 1412 bits<4> Rn; 1413 bits<12> imm; 1414 let Inst{25} = 1; 1415 let Inst{15-12} = Rd; 1416 let Inst{19-16} = Rn; 1417 let Inst{11-0} = imm; 1418 } 1419 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1420 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1421 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>, 1422 Requires<[IsARM]>, 1423 Sched<[WriteALU, ReadALU, ReadALU]> { 1424 bits<4> Rd; 1425 bits<4> Rn; 1426 bits<4> Rm; 1427 let Inst{11-4} = 0b00000000; 1428 let Inst{25} = 0; 1429 let isCommutable = Commutable; 1430 let Inst{3-0} = Rm; 1431 let Inst{15-12} = Rd; 1432 let Inst{19-16} = Rn; 1433 } 1434 def rsi : AsI1<opcod, (outs GPR:$Rd), 1435 (ins GPR:$Rn, so_reg_imm:$shift), 1436 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1437 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>, 1438 Requires<[IsARM]>, 1439 Sched<[WriteALUsi, ReadALU]> { 1440 bits<4> Rd; 1441 bits<4> Rn; 1442 bits<12> shift; 1443 let Inst{25} = 0; 1444 let Inst{19-16} = Rn; 1445 let Inst{15-12} = Rd; 1446 let Inst{11-5} = shift{11-5}; 1447 let Inst{4} = 0; 1448 let Inst{3-0} = shift{3-0}; 1449 } 1450 def rsr : AsI1<opcod, (outs GPRnopc:$Rd), 1451 (ins GPRnopc:$Rn, so_reg_reg:$shift), 1452 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1453 [(set GPRnopc:$Rd, CPSR, 1454 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>, 1455 Requires<[IsARM]>, 1456 Sched<[WriteALUsr, ReadALUsr]> { 1457 bits<4> Rd; 1458 bits<4> Rn; 1459 bits<12> shift; 1460 let Inst{25} = 0; 1461 let Inst{19-16} = Rn; 1462 let Inst{15-12} = Rd; 1463 let Inst{11-8} = shift{11-8}; 1464 let Inst{7} = 0; 1465 let Inst{6-5} = shift{6-5}; 1466 let Inst{4} = 1; 1467 let Inst{3-0} = shift{3-0}; 1468 } 1469 } 1470} 1471 1472/// AI1_rsc_irs - Define instructions and patterns for rsc 1473let TwoOperandAliasConstraint = "$Rn = $Rd" in 1474multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> { 1475 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1476 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), 1477 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1478 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>, 1479 Requires<[IsARM]>, 1480 Sched<[WriteALU, ReadALU]> { 1481 bits<4> Rd; 1482 bits<4> Rn; 1483 bits<12> imm; 1484 let Inst{25} = 1; 1485 let Inst{15-12} = Rd; 1486 let Inst{19-16} = Rn; 1487 let Inst{11-0} = imm; 1488 } 1489 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1490 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1491 [/* pattern left blank */]>, 1492 Sched<[WriteALU, ReadALU, ReadALU]> { 1493 bits<4> Rd; 1494 bits<4> Rn; 1495 bits<4> Rm; 1496 let Inst{11-4} = 0b00000000; 1497 let Inst{25} = 0; 1498 let Inst{3-0} = Rm; 1499 let Inst{15-12} = Rd; 1500 let Inst{19-16} = Rn; 1501 } 1502 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), 1503 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1504 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>, 1505 Requires<[IsARM]>, 1506 Sched<[WriteALUsi, ReadALU]> { 1507 bits<4> Rd; 1508 bits<4> Rn; 1509 bits<12> shift; 1510 let Inst{25} = 0; 1511 let Inst{19-16} = Rn; 1512 let Inst{15-12} = Rd; 1513 let Inst{11-5} = shift{11-5}; 1514 let Inst{4} = 0; 1515 let Inst{3-0} = shift{3-0}; 1516 } 1517 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), 1518 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1519 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>, 1520 Requires<[IsARM]>, 1521 Sched<[WriteALUsr, ReadALUsr]> { 1522 bits<4> Rd; 1523 bits<4> Rn; 1524 bits<12> shift; 1525 let Inst{25} = 0; 1526 let Inst{19-16} = Rn; 1527 let Inst{15-12} = Rd; 1528 let Inst{11-8} = shift{11-8}; 1529 let Inst{7} = 0; 1530 let Inst{6-5} = shift{6-5}; 1531 let Inst{4} = 1; 1532 let Inst{3-0} = shift{3-0}; 1533 } 1534 } 1535} 1536 1537let canFoldAsLoad = 1, isReMaterializable = 1 in { 1538multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii, 1539 InstrItinClass iir, PatFrag opnode> { 1540 // Note: We use the complex addrmode_imm12 rather than just an input 1541 // GPR and a constrained immediate so that we can use this to match 1542 // frame index references and avoid matching constant pool references. 1543 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 1544 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1545 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { 1546 bits<4> Rt; 1547 bits<17> addr; 1548 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1549 let Inst{19-16} = addr{16-13}; // Rn 1550 let Inst{15-12} = Rt; 1551 let Inst{11-0} = addr{11-0}; // imm12 1552 } 1553 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift), 1554 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1555 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { 1556 bits<4> Rt; 1557 bits<17> shift; 1558 let shift{4} = 0; // Inst{4} = 0 1559 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1560 let Inst{19-16} = shift{16-13}; // Rn 1561 let Inst{15-12} = Rt; 1562 let Inst{11-0} = shift{11-0}; 1563 } 1564} 1565} 1566 1567let canFoldAsLoad = 1, isReMaterializable = 1 in { 1568multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii, 1569 InstrItinClass iir, PatFrag opnode> { 1570 // Note: We use the complex addrmode_imm12 rather than just an input 1571 // GPR and a constrained immediate so that we can use this to match 1572 // frame index references and avoid matching constant pool references. 1573 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), 1574 (ins addrmode_imm12:$addr), 1575 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1576 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> { 1577 bits<4> Rt; 1578 bits<17> addr; 1579 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1580 let Inst{19-16} = addr{16-13}; // Rn 1581 let Inst{15-12} = Rt; 1582 let Inst{11-0} = addr{11-0}; // imm12 1583 } 1584 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), 1585 (ins ldst_so_reg:$shift), 1586 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1587 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> { 1588 bits<4> Rt; 1589 bits<17> shift; 1590 let shift{4} = 0; // Inst{4} = 0 1591 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1592 let Inst{19-16} = shift{16-13}; // Rn 1593 let Inst{15-12} = Rt; 1594 let Inst{11-0} = shift{11-0}; 1595 } 1596} 1597} 1598 1599 1600multiclass AI_str1<bit isByte, string opc, InstrItinClass iii, 1601 InstrItinClass iir, PatFrag opnode> { 1602 // Note: We use the complex addrmode_imm12 rather than just an input 1603 // GPR and a constrained immediate so that we can use this to match 1604 // frame index references and avoid matching constant pool references. 1605 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1606 (ins GPR:$Rt, addrmode_imm12:$addr), 1607 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1608 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> { 1609 bits<4> Rt; 1610 bits<17> addr; 1611 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1612 let Inst{19-16} = addr{16-13}; // Rn 1613 let Inst{15-12} = Rt; 1614 let Inst{11-0} = addr{11-0}; // imm12 1615 } 1616 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift), 1617 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1618 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> { 1619 bits<4> Rt; 1620 bits<17> shift; 1621 let shift{4} = 0; // Inst{4} = 0 1622 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1623 let Inst{19-16} = shift{16-13}; // Rn 1624 let Inst{15-12} = Rt; 1625 let Inst{11-0} = shift{11-0}; 1626 } 1627} 1628 1629multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii, 1630 InstrItinClass iir, PatFrag opnode> { 1631 // Note: We use the complex addrmode_imm12 rather than just an input 1632 // GPR and a constrained immediate so that we can use this to match 1633 // frame index references and avoid matching constant pool references. 1634 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1635 (ins GPRnopc:$Rt, addrmode_imm12:$addr), 1636 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1637 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> { 1638 bits<4> Rt; 1639 bits<17> addr; 1640 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1641 let Inst{19-16} = addr{16-13}; // Rn 1642 let Inst{15-12} = Rt; 1643 let Inst{11-0} = addr{11-0}; // imm12 1644 } 1645 def rs : AI2ldst<0b011, 0, isByte, (outs), 1646 (ins GPRnopc:$Rt, ldst_so_reg:$shift), 1647 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1648 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> { 1649 bits<4> Rt; 1650 bits<17> shift; 1651 let shift{4} = 0; // Inst{4} = 0 1652 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1653 let Inst{19-16} = shift{16-13}; // Rn 1654 let Inst{15-12} = Rt; 1655 let Inst{11-0} = shift{11-0}; 1656 } 1657} 1658 1659 1660//===----------------------------------------------------------------------===// 1661// Instructions 1662//===----------------------------------------------------------------------===// 1663 1664//===----------------------------------------------------------------------===// 1665// Miscellaneous Instructions. 1666// 1667 1668/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 1669/// the function. The first operand is the ID# for this instruction, the second 1670/// is the index into the MachineConstantPool that this is, the third is the 1671/// size in bytes of this constant pool entry. 1672let neverHasSideEffects = 1, isNotDuplicable = 1 in 1673def CONSTPOOL_ENTRY : 1674PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1675 i32imm:$size), NoItinerary, []>; 1676 1677// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 1678// from removing one half of the matched pairs. That breaks PEI, which assumes 1679// these will always be in pairs, and asserts if it finds otherwise. Better way? 1680let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 1681def ADJCALLSTACKUP : 1682PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, 1683 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; 1684 1685def ADJCALLSTACKDOWN : 1686PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary, 1687 [(ARMcallseq_start timm:$amt)]>; 1688} 1689 1690def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary, 1691 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> { 1692 bits<8> imm; 1693 let Inst{27-8} = 0b00110010000011110000; 1694 let Inst{7-0} = imm; 1695} 1696 1697def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1698def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1699def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1700def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1701def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1702def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>; 1703 1704def : Pat<(int_arm_sevl), (HINT 5)>; 1705 1706def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel", 1707 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> { 1708 bits<4> Rd; 1709 bits<4> Rn; 1710 bits<4> Rm; 1711 let Inst{3-0} = Rm; 1712 let Inst{15-12} = Rd; 1713 let Inst{19-16} = Rn; 1714 let Inst{27-20} = 0b01101000; 1715 let Inst{7-4} = 0b1011; 1716 let Inst{11-8} = 0b1111; 1717 let Unpredictable{11-8} = 0b1111; 1718} 1719 1720// The 16-bit operand $val can be used by a debugger to store more information 1721// about the breakpoint. 1722def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 1723 "bkpt", "\t$val", []>, Requires<[IsARM]> { 1724 bits<16> val; 1725 let Inst{3-0} = val{3-0}; 1726 let Inst{19-8} = val{15-4}; 1727 let Inst{27-20} = 0b00010010; 1728 let Inst{31-28} = 0xe; // AL 1729 let Inst{7-4} = 0b0111; 1730} 1731// default immediate for breakpoint mnemonic 1732def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>; 1733 1734def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 1735 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> { 1736 bits<16> val; 1737 let Inst{3-0} = val{3-0}; 1738 let Inst{19-8} = val{15-4}; 1739 let Inst{27-20} = 0b00010000; 1740 let Inst{31-28} = 0xe; // AL 1741 let Inst{7-4} = 0b0111; 1742} 1743 1744// Change Processor State 1745// FIXME: We should use InstAlias to handle the optional operands. 1746class CPS<dag iops, string asm_ops> 1747 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops), 1748 []>, Requires<[IsARM]> { 1749 bits<2> imod; 1750 bits<3> iflags; 1751 bits<5> mode; 1752 bit M; 1753 1754 let Inst{31-28} = 0b1111; 1755 let Inst{27-20} = 0b00010000; 1756 let Inst{19-18} = imod; 1757 let Inst{17} = M; // Enabled if mode is set; 1758 let Inst{16-9} = 0b00000000; 1759 let Inst{8-6} = iflags; 1760 let Inst{5} = 0; 1761 let Inst{4-0} = mode; 1762} 1763 1764let DecoderMethod = "DecodeCPSInstruction" in { 1765let M = 1 in 1766 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode), 1767 "$imod\t$iflags, $mode">; 1768let mode = 0, M = 0 in 1769 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">; 1770 1771let imod = 0, iflags = 0, M = 1 in 1772 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">; 1773} 1774 1775// Preload signals the memory system of possible future data/instruction access. 1776multiclass APreLoad<bits<1> read, bits<1> data, string opc> { 1777 1778 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm, 1779 IIC_Preload, !strconcat(opc, "\t$addr"), 1780 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>, 1781 Sched<[WritePreLd]> { 1782 bits<4> Rt; 1783 bits<17> addr; 1784 let Inst{31-26} = 0b111101; 1785 let Inst{25} = 0; // 0 for immediate form 1786 let Inst{24} = data; 1787 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1788 let Inst{22} = read; 1789 let Inst{21-20} = 0b01; 1790 let Inst{19-16} = addr{16-13}; // Rn 1791 let Inst{15-12} = 0b1111; 1792 let Inst{11-0} = addr{11-0}; // imm12 1793 } 1794 1795 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, 1796 !strconcat(opc, "\t$shift"), 1797 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>, 1798 Sched<[WritePreLd]> { 1799 bits<17> shift; 1800 let Inst{31-26} = 0b111101; 1801 let Inst{25} = 1; // 1 for register form 1802 let Inst{24} = data; 1803 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1804 let Inst{22} = read; 1805 let Inst{21-20} = 0b01; 1806 let Inst{19-16} = shift{16-13}; // Rn 1807 let Inst{15-12} = 0b1111; 1808 let Inst{11-0} = shift{11-0}; 1809 let Inst{4} = 0; 1810 } 1811} 1812 1813defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>; 1814defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>; 1815defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>; 1816 1817def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary, 1818 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> { 1819 bits<1> end; 1820 let Inst{31-10} = 0b1111000100000001000000; 1821 let Inst{9} = end; 1822 let Inst{8-0} = 0; 1823} 1824 1825def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", 1826 []>, Requires<[IsARM, HasV7]> { 1827 bits<4> opt; 1828 let Inst{27-4} = 0b001100100000111100001111; 1829 let Inst{3-0} = opt; 1830} 1831 1832/* 1833 * A5.4 Permanently UNDEFINED instructions. 1834 * 1835 * For most targets use UDF #65006, for which the OS will generate SIGTRAP. 1836 * Other UDF encodings generate SIGILL. 1837 * 1838 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb. 1839 * Encoding A1: 1840 * 1110 0111 1111 iiii iiii iiii 1111 iiii 1841 * Encoding T1: 1842 * 1101 1110 iiii iiii 1843 * It uses the following encoding: 1844 * 1110 0111 1111 1110 1101 1110 1111 0000 1845 * - In ARM: UDF #60896; 1846 * - In Thumb: UDF #254 followed by a branch-to-self. 1847 */ 1848let isBarrier = 1, isTerminator = 1 in 1849def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary, 1850 "trap", [(trap)]>, 1851 Requires<[IsARM,UseNaClTrap]> { 1852 let Inst = 0xe7fedef0; 1853} 1854let isBarrier = 1, isTerminator = 1 in 1855def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, 1856 "trap", [(trap)]>, 1857 Requires<[IsARM,DontUseNaClTrap]> { 1858 let Inst = 0xe7ffdefe; 1859} 1860 1861// Address computation and loads and stores in PIC mode. 1862let isNotDuplicable = 1 in { 1863def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 1864 4, IIC_iALUr, 1865 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>, 1866 Sched<[WriteALU, ReadALU]>; 1867 1868let AddedComplexity = 10 in { 1869def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 1870 4, IIC_iLoad_r, 1871 [(set GPR:$dst, (load addrmodepc:$addr))]>; 1872 1873def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 1874 4, IIC_iLoad_bh_r, 1875 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>; 1876 1877def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 1878 4, IIC_iLoad_bh_r, 1879 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>; 1880 1881def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 1882 4, IIC_iLoad_bh_r, 1883 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>; 1884 1885def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 1886 4, IIC_iLoad_bh_r, 1887 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>; 1888} 1889let AddedComplexity = 10 in { 1890def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 1891 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>; 1892 1893def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 1894 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, 1895 addrmodepc:$addr)]>; 1896 1897def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 1898 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 1899} 1900} // isNotDuplicable = 1 1901 1902 1903// LEApcrel - Load a pc-relative address into a register without offending the 1904// assembler. 1905let neverHasSideEffects = 1, isReMaterializable = 1 in 1906// The 'adr' mnemonic encodes differently if the label is before or after 1907// the instruction. The {24-21} opcode bits are set by the fixup, as we don't 1908// know until then which form of the instruction will be used. 1909def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), 1910 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>, 1911 Sched<[WriteALU, ReadALU]> { 1912 bits<4> Rd; 1913 bits<14> label; 1914 let Inst{27-25} = 0b001; 1915 let Inst{24} = 0; 1916 let Inst{23-22} = label{13-12}; 1917 let Inst{21} = 0; 1918 let Inst{20} = 0; 1919 let Inst{19-16} = 0b1111; 1920 let Inst{15-12} = Rd; 1921 let Inst{11-0} = label{11-0}; 1922} 1923 1924let hasSideEffects = 1 in { 1925def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 1926 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 1927 1928def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd), 1929 (ins i32imm:$label, nohash_imm:$id, pred:$p), 1930 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 1931} 1932 1933//===----------------------------------------------------------------------===// 1934// Control Flow Instructions. 1935// 1936 1937let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 1938 // ARMV4T and above 1939 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, 1940 "bx", "\tlr", [(ARMretflag)]>, 1941 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 1942 let Inst{27-0} = 0b0001001011111111111100011110; 1943 } 1944 1945 // ARMV4 only 1946 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br, 1947 "mov", "\tpc, lr", [(ARMretflag)]>, 1948 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> { 1949 let Inst{27-0} = 0b0001101000001111000000001110; 1950 } 1951 1952 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets 1953 // the user-space one). 1954 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p), 1955 4, IIC_Br, 1956 [(ARMintretflag imm:$offset)]>; 1957} 1958 1959// Indirect branches 1960let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1961 // ARMV4T and above 1962 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst", 1963 [(brind GPR:$dst)]>, 1964 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 1965 bits<4> dst; 1966 let Inst{31-4} = 0b1110000100101111111111110001; 1967 let Inst{3-0} = dst; 1968 } 1969 1970 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, 1971 "bx", "\t$dst", [/* pattern left blank */]>, 1972 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 1973 bits<4> dst; 1974 let Inst{27-4} = 0b000100101111111111110001; 1975 let Inst{3-0} = dst; 1976 } 1977} 1978 1979// SP is marked as a use to prevent stack-pointer assignments that appear 1980// immediately before calls from potentially appearing dead. 1981let isCall = 1, 1982 // FIXME: Do we really need a non-predicated version? If so, it should 1983 // at least be a pseudo instruction expanding to the predicated version 1984 // at MC lowering time. 1985 Defs = [LR], Uses = [SP] in { 1986 def BL : ABXI<0b1011, (outs), (ins bl_target:$func), 1987 IIC_Br, "bl\t$func", 1988 [(ARMcall tglobaladdr:$func)]>, 1989 Requires<[IsARM]>, Sched<[WriteBrL]> { 1990 let Inst{31-28} = 0b1110; 1991 bits<24> func; 1992 let Inst{23-0} = func; 1993 let DecoderMethod = "DecodeBranchImmInstruction"; 1994 } 1995 1996 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func), 1997 IIC_Br, "bl", "\t$func", 1998 [(ARMcall_pred tglobaladdr:$func)]>, 1999 Requires<[IsARM]>, Sched<[WriteBrL]> { 2000 bits<24> func; 2001 let Inst{23-0} = func; 2002 let DecoderMethod = "DecodeBranchImmInstruction"; 2003 } 2004 2005 // ARMv5T and above 2006 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm, 2007 IIC_Br, "blx\t$func", 2008 [(ARMcall GPR:$func)]>, 2009 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2010 bits<4> func; 2011 let Inst{31-4} = 0b1110000100101111111111110011; 2012 let Inst{3-0} = func; 2013 } 2014 2015 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm, 2016 IIC_Br, "blx", "\t$func", 2017 [(ARMcall_pred GPR:$func)]>, 2018 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2019 bits<4> func; 2020 let Inst{27-4} = 0b000100101111111111110011; 2021 let Inst{3-0} = func; 2022 } 2023 2024 // ARMv4T 2025 // Note: Restrict $func to the tGPR regclass to prevent it being in LR. 2026 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2027 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2028 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>; 2029 2030 // ARMv4 2031 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2032 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2033 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 2034 2035 // mov lr, pc; b if callee is marked noreturn to avoid confusing the 2036 // return stack predictor. 2037 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func), 2038 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>, 2039 Requires<[IsARM]>, Sched<[WriteBr]>; 2040} 2041 2042let isBranch = 1, isTerminator = 1 in { 2043 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 2044 // a two-value operand where a dag node expects two operands. :( 2045 def Bcc : ABI<0b1010, (outs), (ins br_target:$target), 2046 IIC_Br, "b", "\t$target", 2047 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>, 2048 Sched<[WriteBr]> { 2049 bits<24> target; 2050 let Inst{23-0} = target; 2051 let DecoderMethod = "DecodeBranchImmInstruction"; 2052 } 2053 2054 let isBarrier = 1 in { 2055 // B is "predicable" since it's just a Bcc with an 'always' condition. 2056 let isPredicable = 1 in 2057 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly 2058 // should be sufficient. 2059 // FIXME: Is B really a Barrier? That doesn't seem right. 2060 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br, 2061 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>, 2062 Sched<[WriteBr]>; 2063 2064 let isNotDuplicable = 1, isIndirectBranch = 1 in { 2065 def BR_JTr : ARMPseudoInst<(outs), 2066 (ins GPR:$target, i32imm:$jt, i32imm:$id), 2067 0, IIC_Br, 2068 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>, 2069 Sched<[WriteBr]>; 2070 // FIXME: This shouldn't use the generic "addrmode2," but rather be split 2071 // into i12 and rs suffixed versions. 2072 def BR_JTm : ARMPseudoInst<(outs), 2073 (ins addrmode2:$target, i32imm:$jt, i32imm:$id), 2074 0, IIC_Br, 2075 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt, 2076 imm:$id)]>, Sched<[WriteBrTbl]>; 2077 def BR_JTadd : ARMPseudoInst<(outs), 2078 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id), 2079 0, IIC_Br, 2080 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, 2081 imm:$id)]>, Sched<[WriteBrTbl]>; 2082 } // isNotDuplicable = 1, isIndirectBranch = 1 2083 } // isBarrier = 1 2084 2085} 2086 2087// BLX (immediate) 2088def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary, 2089 "blx\t$target", []>, 2090 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2091 let Inst{31-25} = 0b1111101; 2092 bits<25> target; 2093 let Inst{23-0} = target{24-1}; 2094 let Inst{24} = target{0}; 2095} 2096 2097// Branch and Exchange Jazelle 2098def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", 2099 [/* pattern left blank */]>, Sched<[WriteBr]> { 2100 bits<4> func; 2101 let Inst{23-20} = 0b0010; 2102 let Inst{19-8} = 0xfff; 2103 let Inst{7-4} = 0b0010; 2104 let Inst{3-0} = func; 2105} 2106 2107// Tail calls. 2108 2109let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { 2110 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>, 2111 Sched<[WriteBr]>; 2112 2113 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>, 2114 Sched<[WriteBr]>; 2115 2116 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst), 2117 4, IIC_Br, [], 2118 (Bcc br_target:$dst, (ops 14, zero_reg))>, 2119 Requires<[IsARM]>, Sched<[WriteBr]>; 2120 2121 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst), 2122 4, IIC_Br, [], 2123 (BX GPR:$dst)>, Sched<[WriteBr]>, 2124 Requires<[IsARM]>; 2125} 2126 2127// Secure Monitor Call is a system instruction. 2128def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", 2129 []>, Requires<[IsARM, HasTrustZone]> { 2130 bits<4> opt; 2131 let Inst{23-4} = 0b01100000000000000111; 2132 let Inst{3-0} = opt; 2133} 2134 2135// Supervisor Call (Software Interrupt) 2136let isCall = 1, Uses = [SP] in { 2137def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>, 2138 Sched<[WriteBr]> { 2139 bits<24> svc; 2140 let Inst{23-0} = svc; 2141} 2142} 2143 2144// Store Return State 2145class SRSI<bit wb, string asm> 2146 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm, 2147 NoItinerary, asm, "", []> { 2148 bits<5> mode; 2149 let Inst{31-28} = 0b1111; 2150 let Inst{27-25} = 0b100; 2151 let Inst{22} = 1; 2152 let Inst{21} = wb; 2153 let Inst{20} = 0; 2154 let Inst{19-16} = 0b1101; // SP 2155 let Inst{15-5} = 0b00000101000; 2156 let Inst{4-0} = mode; 2157} 2158 2159def SRSDA : SRSI<0, "srsda\tsp, $mode"> { 2160 let Inst{24-23} = 0; 2161} 2162def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> { 2163 let Inst{24-23} = 0; 2164} 2165def SRSDB : SRSI<0, "srsdb\tsp, $mode"> { 2166 let Inst{24-23} = 0b10; 2167} 2168def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> { 2169 let Inst{24-23} = 0b10; 2170} 2171def SRSIA : SRSI<0, "srsia\tsp, $mode"> { 2172 let Inst{24-23} = 0b01; 2173} 2174def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> { 2175 let Inst{24-23} = 0b01; 2176} 2177def SRSIB : SRSI<0, "srsib\tsp, $mode"> { 2178 let Inst{24-23} = 0b11; 2179} 2180def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> { 2181 let Inst{24-23} = 0b11; 2182} 2183 2184def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>; 2185def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>; 2186 2187def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>; 2188def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>; 2189 2190def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>; 2191def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>; 2192 2193def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>; 2194def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>; 2195 2196// Return From Exception 2197class RFEI<bit wb, string asm> 2198 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm, 2199 NoItinerary, asm, "", []> { 2200 bits<4> Rn; 2201 let Inst{31-28} = 0b1111; 2202 let Inst{27-25} = 0b100; 2203 let Inst{22} = 0; 2204 let Inst{21} = wb; 2205 let Inst{20} = 1; 2206 let Inst{19-16} = Rn; 2207 let Inst{15-0} = 0xa00; 2208} 2209 2210def RFEDA : RFEI<0, "rfeda\t$Rn"> { 2211 let Inst{24-23} = 0; 2212} 2213def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> { 2214 let Inst{24-23} = 0; 2215} 2216def RFEDB : RFEI<0, "rfedb\t$Rn"> { 2217 let Inst{24-23} = 0b10; 2218} 2219def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> { 2220 let Inst{24-23} = 0b10; 2221} 2222def RFEIA : RFEI<0, "rfeia\t$Rn"> { 2223 let Inst{24-23} = 0b01; 2224} 2225def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> { 2226 let Inst{24-23} = 0b01; 2227} 2228def RFEIB : RFEI<0, "rfeib\t$Rn"> { 2229 let Inst{24-23} = 0b11; 2230} 2231def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> { 2232 let Inst{24-23} = 0b11; 2233} 2234 2235//===----------------------------------------------------------------------===// 2236// Load / Store Instructions. 2237// 2238 2239// Load 2240 2241 2242defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si, 2243 UnOpFrag<(load node:$Src)>>; 2244defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si, 2245 UnOpFrag<(zextloadi8 node:$Src)>>; 2246defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si, 2247 BinOpFrag<(store node:$LHS, node:$RHS)>>; 2248defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si, 2249 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 2250 2251// Special LDR for loads from non-pc-relative constpools. 2252let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1, 2253 isReMaterializable = 1, isCodeGenOnly = 1 in 2254def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 2255 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", 2256 []> { 2257 bits<4> Rt; 2258 bits<17> addr; 2259 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2260 let Inst{19-16} = 0b1111; 2261 let Inst{15-12} = Rt; 2262 let Inst{11-0} = addr{11-0}; // imm12 2263} 2264 2265// Loads with zero extension 2266def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2267 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr", 2268 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>; 2269 2270// Loads with sign extension 2271def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2272 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr", 2273 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>; 2274 2275def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2276 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr", 2277 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>; 2278 2279let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { 2280 // Load doubleword 2281 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr), 2282 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>, 2283 Requires<[IsARM, HasV5TE]>; 2284 2285 // GNU Assembler extension (compatibility) 2286 let isAsmParserOnly = 1 in 2287 def LDRD_PAIR : AI3ld<0b1101, 0, (outs GPRPairOp:$Rt), (ins addrmode3:$addr), 2288 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $addr", []>, 2289 Requires<[IsARM, HasV5TE]>; 2290} 2291 2292def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2293 NoItinerary, "lda", "\t$Rt, $addr", []>; 2294def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2295 NoItinerary, "ldab", "\t$Rt, $addr", []>; 2296def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2297 NoItinerary, "ldah", "\t$Rt, $addr", []>; 2298 2299// Indexed loads 2300multiclass AI2_ldridx<bit isByte, string opc, 2301 InstrItinClass iii, InstrItinClass iir> { 2302 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2303 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii, 2304 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2305 bits<17> addr; 2306 let Inst{25} = 0; 2307 let Inst{23} = addr{12}; 2308 let Inst{19-16} = addr{16-13}; 2309 let Inst{11-0} = addr{11-0}; 2310 let DecoderMethod = "DecodeLDRPreImm"; 2311 } 2312 2313 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2314 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir, 2315 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2316 bits<17> addr; 2317 let Inst{25} = 1; 2318 let Inst{23} = addr{12}; 2319 let Inst{19-16} = addr{16-13}; 2320 let Inst{11-0} = addr{11-0}; 2321 let Inst{4} = 0; 2322 let DecoderMethod = "DecodeLDRPreReg"; 2323 } 2324 2325 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2326 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2327 IndexModePost, LdFrm, iir, 2328 opc, "\t$Rt, $addr, $offset", 2329 "$addr.base = $Rn_wb", []> { 2330 // {12} isAdd 2331 // {11-0} imm12/Rm 2332 bits<14> offset; 2333 bits<4> addr; 2334 let Inst{25} = 1; 2335 let Inst{23} = offset{12}; 2336 let Inst{19-16} = addr; 2337 let Inst{11-0} = offset{11-0}; 2338 let Inst{4} = 0; 2339 2340 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2341 } 2342 2343 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2344 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2345 IndexModePost, LdFrm, iii, 2346 opc, "\t$Rt, $addr, $offset", 2347 "$addr.base = $Rn_wb", []> { 2348 // {12} isAdd 2349 // {11-0} imm12/Rm 2350 bits<14> offset; 2351 bits<4> addr; 2352 let Inst{25} = 0; 2353 let Inst{23} = offset{12}; 2354 let Inst{19-16} = addr; 2355 let Inst{11-0} = offset{11-0}; 2356 2357 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2358 } 2359 2360} 2361 2362let mayLoad = 1, neverHasSideEffects = 1 in { 2363// FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or 2364// IIC_iLoad_siu depending on whether it the offset register is shifted. 2365defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>; 2366defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>; 2367} 2368 2369multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> { 2370 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2371 (ins addrmode3_pre:$addr), IndexModePre, 2372 LdMiscFrm, itin, 2373 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2374 bits<14> addr; 2375 let Inst{23} = addr{8}; // U bit 2376 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2377 let Inst{19-16} = addr{12-9}; // Rn 2378 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2379 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2380 let DecoderMethod = "DecodeAddrMode3Instruction"; 2381 } 2382 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2383 (ins addr_offset_none:$addr, am3offset:$offset), 2384 IndexModePost, LdMiscFrm, itin, 2385 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2386 []> { 2387 bits<10> offset; 2388 bits<4> addr; 2389 let Inst{23} = offset{8}; // U bit 2390 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2391 let Inst{19-16} = addr; 2392 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2393 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2394 let DecoderMethod = "DecodeAddrMode3Instruction"; 2395 } 2396} 2397 2398let mayLoad = 1, neverHasSideEffects = 1 in { 2399defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>; 2400defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>; 2401defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>; 2402let hasExtraDefRegAllocReq = 1 in { 2403def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2404 (ins addrmode3_pre:$addr), IndexModePre, 2405 LdMiscFrm, IIC_iLoad_d_ru, 2406 "ldrd", "\t$Rt, $Rt2, $addr!", 2407 "$addr.base = $Rn_wb", []> { 2408 bits<14> addr; 2409 let Inst{23} = addr{8}; // U bit 2410 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2411 let Inst{19-16} = addr{12-9}; // Rn 2412 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2413 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2414 let DecoderMethod = "DecodeAddrMode3Instruction"; 2415} 2416def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2417 (ins addr_offset_none:$addr, am3offset:$offset), 2418 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru, 2419 "ldrd", "\t$Rt, $Rt2, $addr, $offset", 2420 "$addr.base = $Rn_wb", []> { 2421 bits<10> offset; 2422 bits<4> addr; 2423 let Inst{23} = offset{8}; // U bit 2424 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2425 let Inst{19-16} = addr; 2426 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2427 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2428 let DecoderMethod = "DecodeAddrMode3Instruction"; 2429} 2430} // hasExtraDefRegAllocReq = 1 2431} // mayLoad = 1, neverHasSideEffects = 1 2432 2433// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT. 2434let mayLoad = 1, neverHasSideEffects = 1 in { 2435def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2436 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2437 IndexModePost, LdFrm, IIC_iLoad_ru, 2438 "ldrt", "\t$Rt, $addr, $offset", 2439 "$addr.base = $Rn_wb", []> { 2440 // {12} isAdd 2441 // {11-0} imm12/Rm 2442 bits<14> offset; 2443 bits<4> addr; 2444 let Inst{25} = 1; 2445 let Inst{23} = offset{12}; 2446 let Inst{21} = 1; // overwrite 2447 let Inst{19-16} = addr; 2448 let Inst{11-5} = offset{11-5}; 2449 let Inst{4} = 0; 2450 let Inst{3-0} = offset{3-0}; 2451 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2452} 2453 2454def LDRT_POST_IMM 2455 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2456 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2457 IndexModePost, LdFrm, IIC_iLoad_ru, 2458 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2459 // {12} isAdd 2460 // {11-0} imm12/Rm 2461 bits<14> offset; 2462 bits<4> addr; 2463 let Inst{25} = 0; 2464 let Inst{23} = offset{12}; 2465 let Inst{21} = 1; // overwrite 2466 let Inst{19-16} = addr; 2467 let Inst{11-0} = offset{11-0}; 2468 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2469} 2470 2471def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2472 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2473 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2474 "ldrbt", "\t$Rt, $addr, $offset", 2475 "$addr.base = $Rn_wb", []> { 2476 // {12} isAdd 2477 // {11-0} imm12/Rm 2478 bits<14> offset; 2479 bits<4> addr; 2480 let Inst{25} = 1; 2481 let Inst{23} = offset{12}; 2482 let Inst{21} = 1; // overwrite 2483 let Inst{19-16} = addr; 2484 let Inst{11-5} = offset{11-5}; 2485 let Inst{4} = 0; 2486 let Inst{3-0} = offset{3-0}; 2487 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2488} 2489 2490def LDRBT_POST_IMM 2491 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2492 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2493 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2494 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2495 // {12} isAdd 2496 // {11-0} imm12/Rm 2497 bits<14> offset; 2498 bits<4> addr; 2499 let Inst{25} = 0; 2500 let Inst{23} = offset{12}; 2501 let Inst{21} = 1; // overwrite 2502 let Inst{19-16} = addr; 2503 let Inst{11-0} = offset{11-0}; 2504 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2505} 2506 2507multiclass AI3ldrT<bits<4> op, string opc> { 2508 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb), 2509 (ins addr_offset_none:$addr, postidx_imm8:$offset), 2510 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2511 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 2512 bits<9> offset; 2513 let Inst{23} = offset{8}; 2514 let Inst{22} = 1; 2515 let Inst{11-8} = offset{7-4}; 2516 let Inst{3-0} = offset{3-0}; 2517 } 2518 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb), 2519 (ins addr_offset_none:$addr, postidx_reg:$Rm), 2520 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2521 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 2522 bits<5> Rm; 2523 let Inst{23} = Rm{4}; 2524 let Inst{22} = 0; 2525 let Inst{11-8} = 0; 2526 let Unpredictable{11-8} = 0b1111; 2527 let Inst{3-0} = Rm{3-0}; 2528 let DecoderMethod = "DecodeLDR"; 2529 } 2530} 2531 2532defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">; 2533defm LDRHT : AI3ldrT<0b1011, "ldrht">; 2534defm LDRSHT : AI3ldrT<0b1111, "ldrsht">; 2535} 2536 2537def LDRT_POST 2538 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2539 (outs GPR:$Rt)>; 2540 2541def LDRBT_POST 2542 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2543 (outs GPR:$Rt)>; 2544 2545// Store 2546 2547// Stores with truncate 2548def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, 2549 IIC_iStore_bh_r, "strh", "\t$Rt, $addr", 2550 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>; 2551 2552// Store doubleword 2553let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { 2554 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr), 2555 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>, 2556 Requires<[IsARM, HasV5TE]> { 2557 let Inst{21} = 0; 2558 } 2559 2560 // GNU Assembler extension (compatibility) 2561 let isAsmParserOnly = 1 in 2562 def STRD_PAIR : AI3str<0b1111, (outs), (ins GPRPairOp:$Rt, addrmode3:$addr), 2563 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $addr", []>, 2564 Requires<[IsARM, HasV5TE]> { 2565 let Inst{21} = 0; 2566 } 2567} 2568 2569// Indexed stores 2570multiclass AI2_stridx<bit isByte, string opc, 2571 InstrItinClass iii, InstrItinClass iir> { 2572 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2573 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre, 2574 StFrm, iii, 2575 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2576 bits<17> addr; 2577 let Inst{25} = 0; 2578 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2579 let Inst{19-16} = addr{16-13}; // Rn 2580 let Inst{11-0} = addr{11-0}; // imm12 2581 let DecoderMethod = "DecodeSTRPreImm"; 2582 } 2583 2584 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2585 (ins GPR:$Rt, ldst_so_reg:$addr), 2586 IndexModePre, StFrm, iir, 2587 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2588 bits<17> addr; 2589 let Inst{25} = 1; 2590 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2591 let Inst{19-16} = addr{16-13}; // Rn 2592 let Inst{11-0} = addr{11-0}; 2593 let Inst{4} = 0; // Inst{4} = 0 2594 let DecoderMethod = "DecodeSTRPreReg"; 2595 } 2596 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2597 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2598 IndexModePost, StFrm, iir, 2599 opc, "\t$Rt, $addr, $offset", 2600 "$addr.base = $Rn_wb", []> { 2601 // {12} isAdd 2602 // {11-0} imm12/Rm 2603 bits<14> offset; 2604 bits<4> addr; 2605 let Inst{25} = 1; 2606 let Inst{23} = offset{12}; 2607 let Inst{19-16} = addr; 2608 let Inst{11-0} = offset{11-0}; 2609 let Inst{4} = 0; 2610 2611 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2612 } 2613 2614 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2615 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2616 IndexModePost, StFrm, iii, 2617 opc, "\t$Rt, $addr, $offset", 2618 "$addr.base = $Rn_wb", []> { 2619 // {12} isAdd 2620 // {11-0} imm12/Rm 2621 bits<14> offset; 2622 bits<4> addr; 2623 let Inst{25} = 0; 2624 let Inst{23} = offset{12}; 2625 let Inst{19-16} = addr; 2626 let Inst{11-0} = offset{11-0}; 2627 2628 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2629 } 2630} 2631 2632let mayStore = 1, neverHasSideEffects = 1 in { 2633// FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or 2634// IIC_iStore_siu depending on whether it the offset register is shifted. 2635defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>; 2636defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>; 2637} 2638 2639def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 2640 am2offset_reg:$offset), 2641 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr, 2642 am2offset_reg:$offset)>; 2643def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 2644 am2offset_imm:$offset), 2645 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr, 2646 am2offset_imm:$offset)>; 2647def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 2648 am2offset_reg:$offset), 2649 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr, 2650 am2offset_reg:$offset)>; 2651def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 2652 am2offset_imm:$offset), 2653 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr, 2654 am2offset_imm:$offset)>; 2655 2656// Pseudo-instructions for pattern matching the pre-indexed stores. We can't 2657// put the patterns on the instruction definitions directly as ISel wants 2658// the address base and offset to be separate operands, not a single 2659// complex operand like we represent the instructions themselves. The 2660// pseudos map between the two. 2661let usesCustomInserter = 1, 2662 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 2663def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2664 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 2665 4, IIC_iStore_ru, 2666 [(set GPR:$Rn_wb, 2667 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 2668def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2669 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 2670 4, IIC_iStore_ru, 2671 [(set GPR:$Rn_wb, 2672 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 2673def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2674 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 2675 4, IIC_iStore_ru, 2676 [(set GPR:$Rn_wb, 2677 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 2678def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2679 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 2680 4, IIC_iStore_ru, 2681 [(set GPR:$Rn_wb, 2682 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 2683def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2684 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p), 2685 4, IIC_iStore_ru, 2686 [(set GPR:$Rn_wb, 2687 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>; 2688} 2689 2690 2691 2692def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb), 2693 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre, 2694 StMiscFrm, IIC_iStore_bh_ru, 2695 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2696 bits<14> addr; 2697 let Inst{23} = addr{8}; // U bit 2698 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2699 let Inst{19-16} = addr{12-9}; // Rn 2700 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2701 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2702 let DecoderMethod = "DecodeAddrMode3Instruction"; 2703} 2704 2705def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb), 2706 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset), 2707 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, 2708 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2709 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt, 2710 addr_offset_none:$addr, 2711 am3offset:$offset))]> { 2712 bits<10> offset; 2713 bits<4> addr; 2714 let Inst{23} = offset{8}; // U bit 2715 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2716 let Inst{19-16} = addr; 2717 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2718 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2719 let DecoderMethod = "DecodeAddrMode3Instruction"; 2720} 2721 2722let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { 2723def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb), 2724 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr), 2725 IndexModePre, StMiscFrm, IIC_iStore_d_ru, 2726 "strd", "\t$Rt, $Rt2, $addr!", 2727 "$addr.base = $Rn_wb", []> { 2728 bits<14> addr; 2729 let Inst{23} = addr{8}; // U bit 2730 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2731 let Inst{19-16} = addr{12-9}; // Rn 2732 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2733 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2734 let DecoderMethod = "DecodeAddrMode3Instruction"; 2735} 2736 2737def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb), 2738 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr, 2739 am3offset:$offset), 2740 IndexModePost, StMiscFrm, IIC_iStore_d_ru, 2741 "strd", "\t$Rt, $Rt2, $addr, $offset", 2742 "$addr.base = $Rn_wb", []> { 2743 bits<10> offset; 2744 bits<4> addr; 2745 let Inst{23} = offset{8}; // U bit 2746 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2747 let Inst{19-16} = addr; 2748 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2749 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2750 let DecoderMethod = "DecodeAddrMode3Instruction"; 2751} 2752} // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 2753 2754// STRT, STRBT, and STRHT 2755 2756def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 2757 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2758 IndexModePost, StFrm, IIC_iStore_bh_ru, 2759 "strbt", "\t$Rt, $addr, $offset", 2760 "$addr.base = $Rn_wb", []> { 2761 // {12} isAdd 2762 // {11-0} imm12/Rm 2763 bits<14> offset; 2764 bits<4> addr; 2765 let Inst{25} = 1; 2766 let Inst{23} = offset{12}; 2767 let Inst{21} = 1; // overwrite 2768 let Inst{19-16} = addr; 2769 let Inst{11-5} = offset{11-5}; 2770 let Inst{4} = 0; 2771 let Inst{3-0} = offset{3-0}; 2772 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2773} 2774 2775def STRBT_POST_IMM 2776 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 2777 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2778 IndexModePost, StFrm, IIC_iStore_bh_ru, 2779 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2780 // {12} isAdd 2781 // {11-0} imm12/Rm 2782 bits<14> offset; 2783 bits<4> addr; 2784 let Inst{25} = 0; 2785 let Inst{23} = offset{12}; 2786 let Inst{21} = 1; // overwrite 2787 let Inst{19-16} = addr; 2788 let Inst{11-0} = offset{11-0}; 2789 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2790} 2791 2792def STRBT_POST 2793 : ARMAsmPseudo<"strbt${q} $Rt, $addr", 2794 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 2795 2796let mayStore = 1, neverHasSideEffects = 1 in { 2797def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 2798 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2799 IndexModePost, StFrm, IIC_iStore_ru, 2800 "strt", "\t$Rt, $addr, $offset", 2801 "$addr.base = $Rn_wb", []> { 2802 // {12} isAdd 2803 // {11-0} imm12/Rm 2804 bits<14> offset; 2805 bits<4> addr; 2806 let Inst{25} = 1; 2807 let Inst{23} = offset{12}; 2808 let Inst{21} = 1; // overwrite 2809 let Inst{19-16} = addr; 2810 let Inst{11-5} = offset{11-5}; 2811 let Inst{4} = 0; 2812 let Inst{3-0} = offset{3-0}; 2813 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2814} 2815 2816def STRT_POST_IMM 2817 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 2818 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2819 IndexModePost, StFrm, IIC_iStore_ru, 2820 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2821 // {12} isAdd 2822 // {11-0} imm12/Rm 2823 bits<14> offset; 2824 bits<4> addr; 2825 let Inst{25} = 0; 2826 let Inst{23} = offset{12}; 2827 let Inst{21} = 1; // overwrite 2828 let Inst{19-16} = addr; 2829 let Inst{11-0} = offset{11-0}; 2830 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2831} 2832} 2833 2834def STRT_POST 2835 : ARMAsmPseudo<"strt${q} $Rt, $addr", 2836 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 2837 2838multiclass AI3strT<bits<4> op, string opc> { 2839 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 2840 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset), 2841 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 2842 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 2843 bits<9> offset; 2844 let Inst{23} = offset{8}; 2845 let Inst{22} = 1; 2846 let Inst{11-8} = offset{7-4}; 2847 let Inst{3-0} = offset{3-0}; 2848 } 2849 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 2850 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm), 2851 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 2852 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 2853 bits<5> Rm; 2854 let Inst{23} = Rm{4}; 2855 let Inst{22} = 0; 2856 let Inst{11-8} = 0; 2857 let Inst{3-0} = Rm{3-0}; 2858 } 2859} 2860 2861 2862defm STRHT : AI3strT<0b1011, "strht">; 2863 2864def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 2865 NoItinerary, "stl", "\t$Rt, $addr", []>; 2866def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 2867 NoItinerary, "stlb", "\t$Rt, $addr", []>; 2868def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 2869 NoItinerary, "stlh", "\t$Rt, $addr", []>; 2870 2871//===----------------------------------------------------------------------===// 2872// Load / store multiple Instructions. 2873// 2874 2875multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f, 2876 InstrItinClass itin, InstrItinClass itin_upd> { 2877 // IA is the default, so no need for an explicit suffix on the 2878 // mnemonic here. Without it is the canonical spelling. 2879 def IA : 2880 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2881 IndexModeNone, f, itin, 2882 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> { 2883 let Inst{24-23} = 0b01; // Increment After 2884 let Inst{22} = P_bit; 2885 let Inst{21} = 0; // No writeback 2886 let Inst{20} = L_bit; 2887 } 2888 def IA_UPD : 2889 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2890 IndexModeUpd, f, itin_upd, 2891 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 2892 let Inst{24-23} = 0b01; // Increment After 2893 let Inst{22} = P_bit; 2894 let Inst{21} = 1; // Writeback 2895 let Inst{20} = L_bit; 2896 2897 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 2898 } 2899 def DA : 2900 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2901 IndexModeNone, f, itin, 2902 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> { 2903 let Inst{24-23} = 0b00; // Decrement After 2904 let Inst{22} = P_bit; 2905 let Inst{21} = 0; // No writeback 2906 let Inst{20} = L_bit; 2907 } 2908 def DA_UPD : 2909 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2910 IndexModeUpd, f, itin_upd, 2911 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 2912 let Inst{24-23} = 0b00; // Decrement After 2913 let Inst{22} = P_bit; 2914 let Inst{21} = 1; // Writeback 2915 let Inst{20} = L_bit; 2916 2917 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 2918 } 2919 def DB : 2920 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2921 IndexModeNone, f, itin, 2922 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> { 2923 let Inst{24-23} = 0b10; // Decrement Before 2924 let Inst{22} = P_bit; 2925 let Inst{21} = 0; // No writeback 2926 let Inst{20} = L_bit; 2927 } 2928 def DB_UPD : 2929 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2930 IndexModeUpd, f, itin_upd, 2931 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 2932 let Inst{24-23} = 0b10; // Decrement Before 2933 let Inst{22} = P_bit; 2934 let Inst{21} = 1; // Writeback 2935 let Inst{20} = L_bit; 2936 2937 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 2938 } 2939 def IB : 2940 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2941 IndexModeNone, f, itin, 2942 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> { 2943 let Inst{24-23} = 0b11; // Increment Before 2944 let Inst{22} = P_bit; 2945 let Inst{21} = 0; // No writeback 2946 let Inst{20} = L_bit; 2947 } 2948 def IB_UPD : 2949 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2950 IndexModeUpd, f, itin_upd, 2951 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 2952 let Inst{24-23} = 0b11; // Increment Before 2953 let Inst{22} = P_bit; 2954 let Inst{21} = 1; // Writeback 2955 let Inst{20} = L_bit; 2956 2957 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 2958 } 2959} 2960 2961let neverHasSideEffects = 1 in { 2962 2963let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 2964defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m, 2965 IIC_iLoad_mu>; 2966 2967let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 2968defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m, 2969 IIC_iStore_mu>; 2970 2971} // neverHasSideEffects 2972 2973// FIXME: remove when we have a way to marking a MI with these properties. 2974// FIXME: Should pc be an implicit operand like PICADD, etc? 2975let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 2976 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 2977def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 2978 reglist:$regs, variable_ops), 2979 4, IIC_iLoad_mBr, [], 2980 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 2981 RegConstraint<"$Rn = $wb">; 2982 2983let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 2984defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m, 2985 IIC_iLoad_mu>; 2986 2987let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 2988defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m, 2989 IIC_iStore_mu>; 2990 2991 2992 2993//===----------------------------------------------------------------------===// 2994// Move Instructions. 2995// 2996 2997let neverHasSideEffects = 1 in 2998def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr, 2999 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3000 bits<4> Rd; 3001 bits<4> Rm; 3002 3003 let Inst{19-16} = 0b0000; 3004 let Inst{11-4} = 0b00000000; 3005 let Inst{25} = 0; 3006 let Inst{3-0} = Rm; 3007 let Inst{15-12} = Rd; 3008} 3009 3010// A version for the smaller set of tail call registers. 3011let neverHasSideEffects = 1 in 3012def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, 3013 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3014 bits<4> Rd; 3015 bits<4> Rm; 3016 3017 let Inst{11-4} = 0b00000000; 3018 let Inst{25} = 0; 3019 let Inst{3-0} = Rm; 3020 let Inst{15-12} = Rd; 3021} 3022 3023def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src), 3024 DPSoRegRegFrm, IIC_iMOVsr, 3025 "mov", "\t$Rd, $src", 3026 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP, 3027 Sched<[WriteALU]> { 3028 bits<4> Rd; 3029 bits<12> src; 3030 let Inst{15-12} = Rd; 3031 let Inst{19-16} = 0b0000; 3032 let Inst{11-8} = src{11-8}; 3033 let Inst{7} = 0; 3034 let Inst{6-5} = src{6-5}; 3035 let Inst{4} = 1; 3036 let Inst{3-0} = src{3-0}; 3037 let Inst{25} = 0; 3038} 3039 3040def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src), 3041 DPSoRegImmFrm, IIC_iMOVsr, 3042 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>, 3043 UnaryDP, Sched<[WriteALU]> { 3044 bits<4> Rd; 3045 bits<12> src; 3046 let Inst{15-12} = Rd; 3047 let Inst{19-16} = 0b0000; 3048 let Inst{11-5} = src{11-5}; 3049 let Inst{4} = 0; 3050 let Inst{3-0} = src{3-0}; 3051 let Inst{25} = 0; 3052} 3053 3054let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3055def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi, 3056 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP, 3057 Sched<[WriteALU]> { 3058 bits<4> Rd; 3059 bits<12> imm; 3060 let Inst{25} = 1; 3061 let Inst{15-12} = Rd; 3062 let Inst{19-16} = 0b0000; 3063 let Inst{11-0} = imm; 3064} 3065 3066let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3067def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm), 3068 DPFrm, IIC_iMOVi, 3069 "movw", "\t$Rd, $imm", 3070 [(set GPR:$Rd, imm0_65535:$imm)]>, 3071 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> { 3072 bits<4> Rd; 3073 bits<16> imm; 3074 let Inst{15-12} = Rd; 3075 let Inst{11-0} = imm{11-0}; 3076 let Inst{19-16} = imm{15-12}; 3077 let Inst{20} = 0; 3078 let Inst{25} = 1; 3079 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3080} 3081 3082def : InstAlias<"mov${p} $Rd, $imm", 3083 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>, 3084 Requires<[IsARM]>; 3085 3086def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3087 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3088 Sched<[WriteALU]>; 3089 3090let Constraints = "$src = $Rd" in { 3091def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd), 3092 (ins GPR:$src, imm0_65535_expr:$imm), 3093 DPFrm, IIC_iMOVi, 3094 "movt", "\t$Rd, $imm", 3095 [(set GPRnopc:$Rd, 3096 (or (and GPR:$src, 0xffff), 3097 lo16AllZero:$imm))]>, UnaryDP, 3098 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> { 3099 bits<4> Rd; 3100 bits<16> imm; 3101 let Inst{15-12} = Rd; 3102 let Inst{11-0} = imm{11-0}; 3103 let Inst{19-16} = imm{15-12}; 3104 let Inst{20} = 0; 3105 let Inst{25} = 1; 3106 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3107} 3108 3109def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3110 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3111 Sched<[WriteALU]>; 3112 3113} // Constraints 3114 3115def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>, 3116 Requires<[IsARM, HasV6T2]>; 3117 3118let Uses = [CPSR] in 3119def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, 3120 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP, 3121 Requires<[IsARM]>, Sched<[WriteALU]>; 3122 3123// These aren't really mov instructions, but we have to define them this way 3124// due to flag operands. 3125 3126let Defs = [CPSR] in { 3127def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3128 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP, 3129 Sched<[WriteALU]>, Requires<[IsARM]>; 3130def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3131 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP, 3132 Sched<[WriteALU]>, Requires<[IsARM]>; 3133} 3134 3135//===----------------------------------------------------------------------===// 3136// Extend Instructions. 3137// 3138 3139// Sign extenders 3140 3141def SXTB : AI_ext_rrot<0b01101010, 3142 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 3143def SXTH : AI_ext_rrot<0b01101011, 3144 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 3145 3146def SXTAB : AI_exta_rrot<0b01101010, 3147 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 3148def SXTAH : AI_exta_rrot<0b01101011, 3149 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 3150 3151def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; 3152 3153def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; 3154 3155// Zero extenders 3156 3157let AddedComplexity = 16 in { 3158def UXTB : AI_ext_rrot<0b01101110, 3159 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 3160def UXTH : AI_ext_rrot<0b01101111, 3161 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 3162def UXTB16 : AI_ext_rrot<0b01101100, 3163 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 3164 3165// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 3166// The transformation should probably be done as a combiner action 3167// instead so we can include a check for masking back in the upper 3168// eight bits of the source into the lower eight bits of the result. 3169//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 3170// (UXTB16r_rot GPR:$Src, 3)>; 3171def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 3172 (UXTB16 GPR:$Src, 1)>; 3173 3174def UXTAB : AI_exta_rrot<0b01101110, "uxtab", 3175 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 3176def UXTAH : AI_exta_rrot<0b01101111, "uxtah", 3177 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 3178} 3179 3180// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 3181def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; 3182 3183 3184def SBFX : I<(outs GPRnopc:$Rd), 3185 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3186 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3187 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3188 Requires<[IsARM, HasV6T2]> { 3189 bits<4> Rd; 3190 bits<4> Rn; 3191 bits<5> lsb; 3192 bits<5> width; 3193 let Inst{27-21} = 0b0111101; 3194 let Inst{6-4} = 0b101; 3195 let Inst{20-16} = width; 3196 let Inst{15-12} = Rd; 3197 let Inst{11-7} = lsb; 3198 let Inst{3-0} = Rn; 3199} 3200 3201def UBFX : I<(outs GPR:$Rd), 3202 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width), 3203 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3204 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3205 Requires<[IsARM, HasV6T2]> { 3206 bits<4> Rd; 3207 bits<4> Rn; 3208 bits<5> lsb; 3209 bits<5> width; 3210 let Inst{27-21} = 0b0111111; 3211 let Inst{6-4} = 0b101; 3212 let Inst{20-16} = width; 3213 let Inst{15-12} = Rd; 3214 let Inst{11-7} = lsb; 3215 let Inst{3-0} = Rn; 3216} 3217 3218//===----------------------------------------------------------------------===// 3219// Arithmetic Instructions. 3220// 3221 3222defm ADD : AsI1_bin_irs<0b0100, "add", 3223 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3224 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; 3225defm SUB : AsI1_bin_irs<0b0010, "sub", 3226 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3227 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 3228 3229// ADD and SUB with 's' bit set. 3230// 3231// Currently, ADDS/SUBS are pseudo opcodes that exist only in the 3232// selection DAG. They are "lowered" to real ADD/SUB opcodes by 3233// AdjustInstrPostInstrSelection where we determine whether or not to 3234// set the "s" bit based on CPSR liveness. 3235// 3236// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen 3237// support for an optional CPSR definition that corresponds to the DAG 3238// node's second value. We can then eliminate the implicit def of CPSR. 3239defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3240 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>; 3241defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3242 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; 3243 3244defm ADC : AI1_adde_sube_irs<0b0101, "adc", 3245 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>; 3246defm SBC : AI1_adde_sube_irs<0b0110, "sbc", 3247 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>; 3248 3249defm RSB : AsI1_rbin_irs<0b0011, "rsb", 3250 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3251 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 3252 3253// FIXME: Eliminate them if we can write def : Pat patterns which defines 3254// CPSR and the implicit def of CPSR is not needed. 3255defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3256 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; 3257 3258defm RSC : AI1_rsc_irs<0b0111, "rsc", 3259 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>; 3260 3261// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 3262// The assume-no-carry-in form uses the negation of the input since add/sub 3263// assume opposite meanings of the carry flag (i.e., carry == !borrow). 3264// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 3265// details. 3266def : ARMPat<(add GPR:$src, so_imm_neg:$imm), 3267 (SUBri GPR:$src, so_imm_neg:$imm)>; 3268def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm), 3269 (SUBSri GPR:$src, so_imm_neg:$imm)>; 3270 3271def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm), 3272 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3273 Requires<[IsARM, HasV6T2]>; 3274def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm), 3275 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3276 Requires<[IsARM, HasV6T2]>; 3277 3278// The with-carry-in form matches bitwise not instead of the negation. 3279// Effectively, the inverse interpretation of the carry flag already accounts 3280// for part of the negation. 3281def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR), 3282 (SBCri GPR:$src, so_imm_not:$imm)>; 3283def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR), 3284 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>; 3285 3286// Note: These are implemented in C++ code, because they have to generate 3287// ADD/SUBrs instructions, which use a complex pattern that a xform function 3288// cannot produce. 3289// (mul X, 2^n+1) -> (add (X << n), X) 3290// (mul X, 2^n-1) -> (rsb X, (X << n)) 3291 3292// ARM Arithmetic Instruction 3293// GPR:$dst = GPR:$a op GPR:$b 3294class AAI<bits<8> op27_20, bits<8> op11_4, string opc, 3295 list<dag> pattern = [], 3296 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm), 3297 string asm = "\t$Rd, $Rn, $Rm"> 3298 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>, 3299 Sched<[WriteALU, ReadALU, ReadALU]> { 3300 bits<4> Rn; 3301 bits<4> Rd; 3302 bits<4> Rm; 3303 let Inst{27-20} = op27_20; 3304 let Inst{11-4} = op11_4; 3305 let Inst{19-16} = Rn; 3306 let Inst{15-12} = Rd; 3307 let Inst{3-0} = Rm; 3308 3309 let Unpredictable{11-8} = 0b1111; 3310} 3311 3312// Saturating add/subtract 3313 3314let DecoderMethod = "DecodeQADDInstruction" in 3315def QADD : AAI<0b00010000, 0b00000101, "qadd", 3316 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))], 3317 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">; 3318 3319def QSUB : AAI<0b00010010, 0b00000101, "qsub", 3320 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))], 3321 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">; 3322def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], 3323 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3324 "\t$Rd, $Rm, $Rn">; 3325def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], 3326 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3327 "\t$Rd, $Rm, $Rn">; 3328 3329def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">; 3330def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">; 3331def QASX : AAI<0b01100010, 0b11110011, "qasx">; 3332def QSAX : AAI<0b01100010, 0b11110101, "qsax">; 3333def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">; 3334def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">; 3335def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">; 3336def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">; 3337def UQASX : AAI<0b01100110, 0b11110011, "uqasx">; 3338def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">; 3339def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">; 3340def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">; 3341 3342// Signed/Unsigned add/subtract 3343 3344def SASX : AAI<0b01100001, 0b11110011, "sasx">; 3345def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">; 3346def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">; 3347def SSAX : AAI<0b01100001, 0b11110101, "ssax">; 3348def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">; 3349def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">; 3350def UASX : AAI<0b01100101, 0b11110011, "uasx">; 3351def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">; 3352def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">; 3353def USAX : AAI<0b01100101, 0b11110101, "usax">; 3354def USUB16 : AAI<0b01100101, 0b11110111, "usub16">; 3355def USUB8 : AAI<0b01100101, 0b11111111, "usub8">; 3356 3357// Signed/Unsigned halving add/subtract 3358 3359def SHASX : AAI<0b01100011, 0b11110011, "shasx">; 3360def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">; 3361def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">; 3362def SHSAX : AAI<0b01100011, 0b11110101, "shsax">; 3363def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">; 3364def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">; 3365def UHASX : AAI<0b01100111, 0b11110011, "uhasx">; 3366def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">; 3367def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">; 3368def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">; 3369def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">; 3370def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">; 3371 3372// Unsigned Sum of Absolute Differences [and Accumulate]. 3373 3374def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3375 MulFrm /* for convenience */, NoItinerary, "usad8", 3376 "\t$Rd, $Rn, $Rm", []>, 3377 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> { 3378 bits<4> Rd; 3379 bits<4> Rn; 3380 bits<4> Rm; 3381 let Inst{27-20} = 0b01111000; 3382 let Inst{15-12} = 0b1111; 3383 let Inst{7-4} = 0b0001; 3384 let Inst{19-16} = Rd; 3385 let Inst{11-8} = Rm; 3386 let Inst{3-0} = Rn; 3387} 3388def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3389 MulFrm /* for convenience */, NoItinerary, "usada8", 3390 "\t$Rd, $Rn, $Rm, $Ra", []>, 3391 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{ 3392 bits<4> Rd; 3393 bits<4> Rn; 3394 bits<4> Rm; 3395 bits<4> Ra; 3396 let Inst{27-20} = 0b01111000; 3397 let Inst{7-4} = 0b0001; 3398 let Inst{19-16} = Rd; 3399 let Inst{15-12} = Ra; 3400 let Inst{11-8} = Rm; 3401 let Inst{3-0} = Rn; 3402} 3403 3404// Signed/Unsigned saturate 3405 3406def SSAT : AI<(outs GPRnopc:$Rd), 3407 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3408 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> { 3409 bits<4> Rd; 3410 bits<5> sat_imm; 3411 bits<4> Rn; 3412 bits<8> sh; 3413 let Inst{27-21} = 0b0110101; 3414 let Inst{5-4} = 0b01; 3415 let Inst{20-16} = sat_imm; 3416 let Inst{15-12} = Rd; 3417 let Inst{11-7} = sh{4-0}; 3418 let Inst{6} = sh{5}; 3419 let Inst{3-0} = Rn; 3420} 3421 3422def SSAT16 : AI<(outs GPRnopc:$Rd), 3423 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm, 3424 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> { 3425 bits<4> Rd; 3426 bits<4> sat_imm; 3427 bits<4> Rn; 3428 let Inst{27-20} = 0b01101010; 3429 let Inst{11-4} = 0b11110011; 3430 let Inst{15-12} = Rd; 3431 let Inst{19-16} = sat_imm; 3432 let Inst{3-0} = Rn; 3433} 3434 3435def USAT : AI<(outs GPRnopc:$Rd), 3436 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3437 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> { 3438 bits<4> Rd; 3439 bits<5> sat_imm; 3440 bits<4> Rn; 3441 bits<8> sh; 3442 let Inst{27-21} = 0b0110111; 3443 let Inst{5-4} = 0b01; 3444 let Inst{15-12} = Rd; 3445 let Inst{11-7} = sh{4-0}; 3446 let Inst{6} = sh{5}; 3447 let Inst{20-16} = sat_imm; 3448 let Inst{3-0} = Rn; 3449} 3450 3451def USAT16 : AI<(outs GPRnopc:$Rd), 3452 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm, 3453 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> { 3454 bits<4> Rd; 3455 bits<4> sat_imm; 3456 bits<4> Rn; 3457 let Inst{27-20} = 0b01101110; 3458 let Inst{11-4} = 0b11110011; 3459 let Inst{15-12} = Rd; 3460 let Inst{19-16} = sat_imm; 3461 let Inst{3-0} = Rn; 3462} 3463 3464def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos), 3465 (SSAT imm:$pos, GPRnopc:$a, 0)>; 3466def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos), 3467 (USAT imm:$pos, GPRnopc:$a, 0)>; 3468 3469//===----------------------------------------------------------------------===// 3470// Bitwise Instructions. 3471// 3472 3473defm AND : AsI1_bin_irs<0b0000, "and", 3474 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3475 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; 3476defm ORR : AsI1_bin_irs<0b1100, "orr", 3477 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3478 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; 3479defm EOR : AsI1_bin_irs<0b0001, "eor", 3480 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3481 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; 3482defm BIC : AsI1_bin_irs<0b1110, "bic", 3483 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3484 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 3485 3486// FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just 3487// like in the actual instruction encoding. The complexity of mapping the mask 3488// to the lsb/msb pair should be handled by ISel, not encapsulated in the 3489// instruction description. 3490def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), 3491 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3492 "bfc", "\t$Rd, $imm", "$src = $Rd", 3493 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>, 3494 Requires<[IsARM, HasV6T2]> { 3495 bits<4> Rd; 3496 bits<10> imm; 3497 let Inst{27-21} = 0b0111110; 3498 let Inst{6-0} = 0b0011111; 3499 let Inst{15-12} = Rd; 3500 let Inst{11-7} = imm{4-0}; // lsb 3501 let Inst{20-16} = imm{9-5}; // msb 3502} 3503 3504// A8.6.18 BFI - Bitfield insert (Encoding A1) 3505def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm), 3506 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3507 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd", 3508 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn, 3509 bf_inv_mask_imm:$imm))]>, 3510 Requires<[IsARM, HasV6T2]> { 3511 bits<4> Rd; 3512 bits<4> Rn; 3513 bits<10> imm; 3514 let Inst{27-21} = 0b0111110; 3515 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 3516 let Inst{15-12} = Rd; 3517 let Inst{11-7} = imm{4-0}; // lsb 3518 let Inst{20-16} = imm{9-5}; // width 3519 let Inst{3-0} = Rn; 3520} 3521 3522def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr, 3523 "mvn", "\t$Rd, $Rm", 3524 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> { 3525 bits<4> Rd; 3526 bits<4> Rm; 3527 let Inst{25} = 0; 3528 let Inst{19-16} = 0b0000; 3529 let Inst{11-4} = 0b00000000; 3530 let Inst{15-12} = Rd; 3531 let Inst{3-0} = Rm; 3532} 3533def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift), 3534 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3535 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP, 3536 Sched<[WriteALU]> { 3537 bits<4> Rd; 3538 bits<12> shift; 3539 let Inst{25} = 0; 3540 let Inst{19-16} = 0b0000; 3541 let Inst{15-12} = Rd; 3542 let Inst{11-5} = shift{11-5}; 3543 let Inst{4} = 0; 3544 let Inst{3-0} = shift{3-0}; 3545} 3546def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift), 3547 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3548 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP, 3549 Sched<[WriteALU]> { 3550 bits<4> Rd; 3551 bits<12> shift; 3552 let Inst{25} = 0; 3553 let Inst{19-16} = 0b0000; 3554 let Inst{15-12} = Rd; 3555 let Inst{11-8} = shift{11-8}; 3556 let Inst{7} = 0; 3557 let Inst{6-5} = shift{6-5}; 3558 let Inst{4} = 1; 3559 let Inst{3-0} = shift{3-0}; 3560} 3561let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3562def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, 3563 IIC_iMVNi, "mvn", "\t$Rd, $imm", 3564 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> { 3565 bits<4> Rd; 3566 bits<12> imm; 3567 let Inst{25} = 1; 3568 let Inst{19-16} = 0b0000; 3569 let Inst{15-12} = Rd; 3570 let Inst{11-0} = imm; 3571} 3572 3573def : ARMPat<(and GPR:$src, so_imm_not:$imm), 3574 (BICri GPR:$src, so_imm_not:$imm)>; 3575 3576//===----------------------------------------------------------------------===// 3577// Multiply Instructions. 3578// 3579class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3580 string opc, string asm, list<dag> pattern> 3581 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3582 bits<4> Rd; 3583 bits<4> Rm; 3584 bits<4> Rn; 3585 let Inst{19-16} = Rd; 3586 let Inst{11-8} = Rm; 3587 let Inst{3-0} = Rn; 3588} 3589class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3590 string opc, string asm, list<dag> pattern> 3591 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3592 bits<4> RdLo; 3593 bits<4> RdHi; 3594 bits<4> Rm; 3595 bits<4> Rn; 3596 let Inst{19-16} = RdHi; 3597 let Inst{15-12} = RdLo; 3598 let Inst{11-8} = Rm; 3599 let Inst{3-0} = Rn; 3600} 3601class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3602 string opc, string asm, list<dag> pattern> 3603 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3604 bits<4> RdLo; 3605 bits<4> RdHi; 3606 bits<4> Rm; 3607 bits<4> Rn; 3608 let Inst{19-16} = RdHi; 3609 let Inst{15-12} = RdLo; 3610 let Inst{11-8} = Rm; 3611 let Inst{3-0} = Rn; 3612} 3613 3614// FIXME: The v5 pseudos are only necessary for the additional Constraint 3615// property. Remove them when it's possible to add those properties 3616// on an individual MachineInstr, not just an instruction description. 3617let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in { 3618def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), 3619 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3620 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", 3621 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>, 3622 Requires<[IsARM, HasV6]> { 3623 let Inst{15-12} = 0b0000; 3624 let Unpredictable{15-12} = 0b1111; 3625} 3626 3627let Constraints = "@earlyclobber $Rd" in 3628def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, 3629 pred:$p, cc_out:$s), 3630 4, IIC_iMUL32, 3631 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))], 3632 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 3633 Requires<[IsARM, NoV6, UseMulOps]>; 3634} 3635 3636def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd), 3637 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra), 3638 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra", 3639 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>, 3640 Requires<[IsARM, HasV6, UseMulOps]> { 3641 bits<4> Ra; 3642 let Inst{15-12} = Ra; 3643} 3644 3645let Constraints = "@earlyclobber $Rd" in 3646def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd), 3647 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 3648 pred:$p, cc_out:$s), 4, IIC_iMAC32, 3649 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))], 3650 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>, 3651 Requires<[IsARM, NoV6]>; 3652 3653def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3654 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra", 3655 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>, 3656 Requires<[IsARM, HasV6T2, UseMulOps]> { 3657 bits<4> Rd; 3658 bits<4> Rm; 3659 bits<4> Rn; 3660 bits<4> Ra; 3661 let Inst{19-16} = Rd; 3662 let Inst{15-12} = Ra; 3663 let Inst{11-8} = Rm; 3664 let Inst{3-0} = Rn; 3665} 3666 3667// Extra precision multiplies with low / high results 3668let neverHasSideEffects = 1 in { 3669let isCommutable = 1 in { 3670def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi), 3671 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 3672 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3673 Requires<[IsARM, HasV6]>; 3674 3675def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), 3676 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 3677 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3678 Requires<[IsARM, HasV6]>; 3679 3680let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { 3681def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3682 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 3683 4, IIC_iMUL64, [], 3684 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 3685 Requires<[IsARM, NoV6]>; 3686 3687def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3688 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 3689 4, IIC_iMUL64, [], 3690 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 3691 Requires<[IsARM, NoV6]>; 3692} 3693} 3694 3695// Multiply + accumulate 3696def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi), 3697 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 3698 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3699 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>; 3700def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi), 3701 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 3702 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3703 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>; 3704 3705def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi), 3706 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64, 3707 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3708 Requires<[IsARM, HasV6]> { 3709 bits<4> RdLo; 3710 bits<4> RdHi; 3711 bits<4> Rm; 3712 bits<4> Rn; 3713 let Inst{19-16} = RdHi; 3714 let Inst{15-12} = RdLo; 3715 let Inst{11-8} = Rm; 3716 let Inst{3-0} = Rn; 3717} 3718 3719let Constraints = 3720 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in { 3721def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3722 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 3723 4, IIC_iMAC64, [], 3724 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 3725 pred:$p, cc_out:$s)>, 3726 Requires<[IsARM, NoV6]>; 3727def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3728 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 3729 4, IIC_iMAC64, [], 3730 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 3731 pred:$p, cc_out:$s)>, 3732 Requires<[IsARM, NoV6]>; 3733} 3734 3735} // neverHasSideEffects 3736 3737// Most significant word multiply 3738def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3739 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm", 3740 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>, 3741 Requires<[IsARM, HasV6]> { 3742 let Inst{15-12} = 0b1111; 3743} 3744 3745def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3746 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>, 3747 Requires<[IsARM, HasV6]> { 3748 let Inst{15-12} = 0b1111; 3749} 3750 3751def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd), 3752 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3753 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra", 3754 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, 3755 Requires<[IsARM, HasV6, UseMulOps]>; 3756 3757def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd), 3758 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3759 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>, 3760 Requires<[IsARM, HasV6]>; 3761 3762def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd), 3763 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3764 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>, 3765 Requires<[IsARM, HasV6, UseMulOps]>; 3766 3767def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd), 3768 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3769 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>, 3770 Requires<[IsARM, HasV6]>; 3771 3772multiclass AI_smul<string opc, PatFrag opnode> { 3773 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3774 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 3775 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16), 3776 (sext_inreg GPR:$Rm, i16)))]>, 3777 Requires<[IsARM, HasV5TE]>; 3778 3779 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3780 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 3781 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16), 3782 (sra GPR:$Rm, (i32 16))))]>, 3783 Requires<[IsARM, HasV5TE]>; 3784 3785 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3786 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 3787 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)), 3788 (sext_inreg GPR:$Rm, i16)))]>, 3789 Requires<[IsARM, HasV5TE]>; 3790 3791 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3792 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 3793 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)), 3794 (sra GPR:$Rm, (i32 16))))]>, 3795 Requires<[IsARM, HasV5TE]>; 3796 3797 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3798 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 3799 [(set GPR:$Rd, (sra (opnode GPR:$Rn, 3800 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>, 3801 Requires<[IsARM, HasV5TE]>; 3802 3803 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3804 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 3805 [(set GPR:$Rd, (sra (opnode GPR:$Rn, 3806 (sra GPR:$Rm, (i32 16))), (i32 16)))]>, 3807 Requires<[IsARM, HasV5TE]>; 3808} 3809 3810 3811multiclass AI_smla<string opc, PatFrag opnode> { 3812 let DecoderMethod = "DecodeSMLAInstruction" in { 3813 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd), 3814 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3815 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 3816 [(set GPRnopc:$Rd, (add GPR:$Ra, 3817 (opnode (sext_inreg GPRnopc:$Rn, i16), 3818 (sext_inreg GPRnopc:$Rm, i16))))]>, 3819 Requires<[IsARM, HasV5TE, UseMulOps]>; 3820 3821 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd), 3822 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3823 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 3824 [(set GPRnopc:$Rd, 3825 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16), 3826 (sra GPRnopc:$Rm, (i32 16)))))]>, 3827 Requires<[IsARM, HasV5TE, UseMulOps]>; 3828 3829 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd), 3830 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3831 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 3832 [(set GPRnopc:$Rd, 3833 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)), 3834 (sext_inreg GPRnopc:$Rm, i16))))]>, 3835 Requires<[IsARM, HasV5TE, UseMulOps]>; 3836 3837 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd), 3838 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3839 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 3840 [(set GPRnopc:$Rd, 3841 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)), 3842 (sra GPRnopc:$Rm, (i32 16)))))]>, 3843 Requires<[IsARM, HasV5TE, UseMulOps]>; 3844 3845 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd), 3846 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3847 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 3848 [(set GPRnopc:$Rd, 3849 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn, 3850 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>, 3851 Requires<[IsARM, HasV5TE, UseMulOps]>; 3852 3853 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd), 3854 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3855 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 3856 [(set GPRnopc:$Rd, 3857 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn, 3858 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>, 3859 Requires<[IsARM, HasV5TE, UseMulOps]>; 3860 } 3861} 3862 3863defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 3864defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 3865 3866// Halfword multiply accumulate long: SMLAL<x><y>. 3867def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3868 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3869 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3870 Requires<[IsARM, HasV5TE]>; 3871 3872def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3873 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3874 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3875 Requires<[IsARM, HasV5TE]>; 3876 3877def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3878 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3879 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3880 Requires<[IsARM, HasV5TE]>; 3881 3882def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3883 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3884 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3885 Requires<[IsARM, HasV5TE]>; 3886 3887// Helper class for AI_smld. 3888class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops, 3889 InstrItinClass itin, string opc, string asm> 3890 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> { 3891 bits<4> Rn; 3892 bits<4> Rm; 3893 let Inst{27-23} = 0b01110; 3894 let Inst{22} = long; 3895 let Inst{21-20} = 0b00; 3896 let Inst{11-8} = Rm; 3897 let Inst{7} = 0; 3898 let Inst{6} = sub; 3899 let Inst{5} = swap; 3900 let Inst{4} = 1; 3901 let Inst{3-0} = Rn; 3902} 3903class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops, 3904 InstrItinClass itin, string opc, string asm> 3905 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 3906 bits<4> Rd; 3907 let Inst{15-12} = 0b1111; 3908 let Inst{19-16} = Rd; 3909} 3910class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops, 3911 InstrItinClass itin, string opc, string asm> 3912 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 3913 bits<4> Ra; 3914 bits<4> Rd; 3915 let Inst{19-16} = Rd; 3916 let Inst{15-12} = Ra; 3917} 3918class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops, 3919 InstrItinClass itin, string opc, string asm> 3920 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 3921 bits<4> RdLo; 3922 bits<4> RdHi; 3923 let Inst{19-16} = RdHi; 3924 let Inst{15-12} = RdLo; 3925} 3926 3927multiclass AI_smld<bit sub, string opc> { 3928 3929 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd), 3930 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3931 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">; 3932 3933 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd), 3934 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3935 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">; 3936 3937 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3938 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary, 3939 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">; 3940 3941 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3942 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary, 3943 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">; 3944 3945} 3946 3947defm SMLA : AI_smld<0, "smla">; 3948defm SMLS : AI_smld<1, "smls">; 3949 3950multiclass AI_sdml<bit sub, string opc> { 3951 3952 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), 3953 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">; 3954 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm), 3955 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">; 3956} 3957 3958defm SMUA : AI_sdml<0, "smua">; 3959defm SMUS : AI_sdml<1, "smus">; 3960 3961//===----------------------------------------------------------------------===// 3962// Division Instructions (ARMv7-A with virtualization extension) 3963// 3964def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 3965 "sdiv", "\t$Rd, $Rn, $Rm", 3966 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>, 3967 Requires<[IsARM, HasDivideInARM]>; 3968 3969def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 3970 "udiv", "\t$Rd, $Rn, $Rm", 3971 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>, 3972 Requires<[IsARM, HasDivideInARM]>; 3973 3974//===----------------------------------------------------------------------===// 3975// Misc. Arithmetic Instructions. 3976// 3977 3978def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm), 3979 IIC_iUNAr, "clz", "\t$Rd, $Rm", 3980 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>, 3981 Sched<[WriteALU]>; 3982 3983def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 3984 IIC_iUNAr, "rbit", "\t$Rd, $Rm", 3985 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>, 3986 Requires<[IsARM, HasV6T2]>, 3987 Sched<[WriteALU]>; 3988 3989def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 3990 IIC_iUNAr, "rev", "\t$Rd, $Rm", 3991 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>, 3992 Sched<[WriteALU]>; 3993 3994let AddedComplexity = 5 in 3995def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 3996 IIC_iUNAr, "rev16", "\t$Rd, $Rm", 3997 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>, 3998 Requires<[IsARM, HasV6]>, 3999 Sched<[WriteALU]>; 4000 4001let AddedComplexity = 5 in 4002def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4003 IIC_iUNAr, "revsh", "\t$Rd, $Rm", 4004 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>, 4005 Requires<[IsARM, HasV6]>, 4006 Sched<[WriteALU]>; 4007 4008def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)), 4009 (and (srl GPR:$Rm, (i32 8)), 0xFF)), 4010 (REVSH GPR:$Rm)>; 4011 4012def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd), 4013 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh), 4014 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 4015 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF), 4016 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh), 4017 0xFFFF0000)))]>, 4018 Requires<[IsARM, HasV6]>, 4019 Sched<[WriteALUsi, ReadALU]>; 4020 4021// Alternate cases for PKHBT where identities eliminate some nodes. 4022def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)), 4023 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>; 4024def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)), 4025 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>; 4026 4027// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 4028// will match the pattern below. 4029def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd), 4030 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh), 4031 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 4032 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000), 4033 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh), 4034 0xFFFF)))]>, 4035 Requires<[IsARM, HasV6]>, 4036 Sched<[WriteALUsi, ReadALU]>; 4037 4038// Alternate cases for PKHTB where identities eliminate some nodes. Note that 4039// a shift amount of 0 is *not legal* here, it is PKHBT instead. 4040// We also can not replace a srl (17..31) by an arithmetic shift we would use in 4041// pkhtb src1, src2, asr (17..31). 4042def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4043 (srl GPRnopc:$src2, imm16:$sh)), 4044 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>; 4045def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4046 (sra GPRnopc:$src2, imm16_31:$sh)), 4047 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>; 4048def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4049 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)), 4050 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>; 4051 4052//===----------------------------------------------------------------------===// 4053// CRC Instructions 4054// 4055// Polynomials: 4056// + CRC32{B,H,W} 0x04C11DB7 4057// + CRC32C{B,H,W} 0x1EDC6F41 4058// 4059 4060class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin> 4061 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary, 4062 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm", 4063 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>, 4064 Requires<[IsARM, HasV8, HasCRC]> { 4065 bits<4> Rd; 4066 bits<4> Rn; 4067 bits<4> Rm; 4068 4069 let Inst{31-28} = 0b1110; 4070 let Inst{27-23} = 0b00010; 4071 let Inst{22-21} = sz; 4072 let Inst{20} = 0; 4073 let Inst{19-16} = Rn; 4074 let Inst{15-12} = Rd; 4075 let Inst{11-10} = 0b00; 4076 let Inst{9} = C; 4077 let Inst{8} = 0; 4078 let Inst{7-4} = 0b0100; 4079 let Inst{3-0} = Rm; 4080 4081 let Unpredictable{11-8} = 0b1101; 4082} 4083 4084def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>; 4085def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>; 4086def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>; 4087def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>; 4088def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>; 4089def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>; 4090 4091//===----------------------------------------------------------------------===// 4092// Comparison Instructions... 4093// 4094 4095defm CMP : AI1_cmp_irs<0b1010, "cmp", 4096 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, 4097 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; 4098 4099// ARMcmpZ can re-use the above instruction definitions. 4100def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm), 4101 (CMPri GPR:$src, so_imm:$imm)>; 4102def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs), 4103 (CMPrr GPR:$src, GPR:$rhs)>; 4104def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs), 4105 (CMPrsi GPR:$src, so_reg_imm:$rhs)>; 4106def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs), 4107 (CMPrsr GPR:$src, so_reg_reg:$rhs)>; 4108 4109// CMN register-integer 4110let isCompare = 1, Defs = [CPSR] in { 4111def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi, 4112 "cmn", "\t$Rn, $imm", 4113 [(ARMcmn GPR:$Rn, so_imm:$imm)]>, 4114 Sched<[WriteCMP, ReadALU]> { 4115 bits<4> Rn; 4116 bits<12> imm; 4117 let Inst{25} = 1; 4118 let Inst{20} = 1; 4119 let Inst{19-16} = Rn; 4120 let Inst{15-12} = 0b0000; 4121 let Inst{11-0} = imm; 4122 4123 let Unpredictable{15-12} = 0b1111; 4124} 4125 4126// CMN register-register/shift 4127def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr, 4128 "cmn", "\t$Rn, $Rm", 4129 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4130 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> { 4131 bits<4> Rn; 4132 bits<4> Rm; 4133 let isCommutable = 1; 4134 let Inst{25} = 0; 4135 let Inst{20} = 1; 4136 let Inst{19-16} = Rn; 4137 let Inst{15-12} = 0b0000; 4138 let Inst{11-4} = 0b00000000; 4139 let Inst{3-0} = Rm; 4140 4141 let Unpredictable{15-12} = 0b1111; 4142} 4143 4144def CMNzrsi : AI1<0b1011, (outs), 4145 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr, 4146 "cmn", "\t$Rn, $shift", 4147 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4148 GPR:$Rn, so_reg_imm:$shift)]>, 4149 Sched<[WriteCMPsi, ReadALU]> { 4150 bits<4> Rn; 4151 bits<12> shift; 4152 let Inst{25} = 0; 4153 let Inst{20} = 1; 4154 let Inst{19-16} = Rn; 4155 let Inst{15-12} = 0b0000; 4156 let Inst{11-5} = shift{11-5}; 4157 let Inst{4} = 0; 4158 let Inst{3-0} = shift{3-0}; 4159 4160 let Unpredictable{15-12} = 0b1111; 4161} 4162 4163def CMNzrsr : AI1<0b1011, (outs), 4164 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr, 4165 "cmn", "\t$Rn, $shift", 4166 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4167 GPRnopc:$Rn, so_reg_reg:$shift)]>, 4168 Sched<[WriteCMPsr, ReadALU]> { 4169 bits<4> Rn; 4170 bits<12> shift; 4171 let Inst{25} = 0; 4172 let Inst{20} = 1; 4173 let Inst{19-16} = Rn; 4174 let Inst{15-12} = 0b0000; 4175 let Inst{11-8} = shift{11-8}; 4176 let Inst{7} = 0; 4177 let Inst{6-5} = shift{6-5}; 4178 let Inst{4} = 1; 4179 let Inst{3-0} = shift{3-0}; 4180 4181 let Unpredictable{15-12} = 0b1111; 4182} 4183 4184} 4185 4186def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm), 4187 (CMNri GPR:$src, so_imm_neg:$imm)>; 4188 4189def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm), 4190 (CMNri GPR:$src, so_imm_neg:$imm)>; 4191 4192// Note that TST/TEQ don't set all the same flags that CMP does! 4193defm TST : AI1_cmp_irs<0b1000, "tst", 4194 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4195 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>; 4196defm TEQ : AI1_cmp_irs<0b1001, "teq", 4197 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4198 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>; 4199 4200// Pseudo i64 compares for some floating point compares. 4201let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, 4202 Defs = [CPSR] in { 4203def BCCi64 : PseudoInst<(outs), 4204 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst), 4205 IIC_Br, 4206 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>, 4207 Sched<[WriteBr]>; 4208 4209def BCCZi64 : PseudoInst<(outs), 4210 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, 4211 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>, 4212 Sched<[WriteBr]>; 4213} // usesCustomInserter 4214 4215 4216// Conditional moves 4217let neverHasSideEffects = 1 in { 4218 4219let isCommutable = 1, isSelect = 1 in 4220def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), 4221 (ins GPR:$false, GPR:$Rm, cmovpred:$p), 4222 4, IIC_iCMOVr, 4223 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, 4224 cmovpred:$p))]>, 4225 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4226 4227def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd), 4228 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p), 4229 4, IIC_iCMOVsr, 4230 [(set GPR:$Rd, 4231 (ARMcmov GPR:$false, so_reg_imm:$shift, 4232 cmovpred:$p))]>, 4233 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4234def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd), 4235 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p), 4236 4, IIC_iCMOVsr, 4237 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift, 4238 cmovpred:$p))]>, 4239 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4240 4241 4242let isMoveImm = 1 in 4243def MOVCCi16 4244 : ARMPseudoInst<(outs GPR:$Rd), 4245 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p), 4246 4, IIC_iMOVi, 4247 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm, 4248 cmovpred:$p))]>, 4249 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>, 4250 Sched<[WriteALU]>; 4251 4252let isMoveImm = 1 in 4253def MOVCCi : ARMPseudoInst<(outs GPR:$Rd), 4254 (ins GPR:$false, so_imm:$imm, cmovpred:$p), 4255 4, IIC_iCMOVi, 4256 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, 4257 cmovpred:$p))]>, 4258 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4259 4260// Two instruction predicate mov immediate. 4261let isMoveImm = 1 in 4262def MOVCCi32imm 4263 : ARMPseudoInst<(outs GPR:$Rd), 4264 (ins GPR:$false, i32imm:$src, cmovpred:$p), 4265 8, IIC_iCMOVix2, 4266 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src, 4267 cmovpred:$p))]>, 4268 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>; 4269 4270let isMoveImm = 1 in 4271def MVNCCi : ARMPseudoInst<(outs GPR:$Rd), 4272 (ins GPR:$false, so_imm:$imm, cmovpred:$p), 4273 4, IIC_iCMOVi, 4274 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, 4275 cmovpred:$p))]>, 4276 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4277 4278} // neverHasSideEffects 4279 4280 4281//===----------------------------------------------------------------------===// 4282// Atomic operations intrinsics 4283// 4284 4285def MemBarrierOptOperand : AsmOperandClass { 4286 let Name = "MemBarrierOpt"; 4287 let ParserMethod = "parseMemBarrierOptOperand"; 4288} 4289def memb_opt : Operand<i32> { 4290 let PrintMethod = "printMemBOption"; 4291 let ParserMatchClass = MemBarrierOptOperand; 4292 let DecoderMethod = "DecodeMemBarrierOption"; 4293} 4294 4295def InstSyncBarrierOptOperand : AsmOperandClass { 4296 let Name = "InstSyncBarrierOpt"; 4297 let ParserMethod = "parseInstSyncBarrierOptOperand"; 4298} 4299def instsyncb_opt : Operand<i32> { 4300 let PrintMethod = "printInstSyncBOption"; 4301 let ParserMatchClass = InstSyncBarrierOptOperand; 4302 let DecoderMethod = "DecodeInstSyncBarrierOption"; 4303} 4304 4305// memory barriers protect the atomic sequences 4306let hasSideEffects = 1 in { 4307def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4308 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>, 4309 Requires<[IsARM, HasDB]> { 4310 bits<4> opt; 4311 let Inst{31-4} = 0xf57ff05; 4312 let Inst{3-0} = opt; 4313} 4314} 4315 4316def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4317 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>, 4318 Requires<[IsARM, HasDB]> { 4319 bits<4> opt; 4320 let Inst{31-4} = 0xf57ff04; 4321 let Inst{3-0} = opt; 4322} 4323 4324// ISB has only full system option 4325def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary, 4326 "isb", "\t$opt", []>, 4327 Requires<[IsARM, HasDB]> { 4328 bits<4> opt; 4329 let Inst{31-4} = 0xf57ff06; 4330 let Inst{3-0} = opt; 4331} 4332 4333let usesCustomInserter = 1, Defs = [CPSR] in { 4334 4335// Pseudo instruction that combines movs + predicated rsbmi 4336// to implement integer ABS 4337 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>; 4338 4339// Atomic pseudo-insts which will be lowered to ldrex/strex loops. 4340// (64-bit pseudos use a hand-written selection code). 4341 let mayLoad = 1, mayStore = 1 in { 4342 def ATOMIC_LOAD_ADD_I8 : PseudoInst< 4343 (outs GPR:$dst), 4344 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4345 NoItinerary, []>; 4346 def ATOMIC_LOAD_SUB_I8 : PseudoInst< 4347 (outs GPR:$dst), 4348 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4349 NoItinerary, []>; 4350 def ATOMIC_LOAD_AND_I8 : PseudoInst< 4351 (outs GPR:$dst), 4352 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4353 NoItinerary, []>; 4354 def ATOMIC_LOAD_OR_I8 : PseudoInst< 4355 (outs GPR:$dst), 4356 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4357 NoItinerary, []>; 4358 def ATOMIC_LOAD_XOR_I8 : PseudoInst< 4359 (outs GPR:$dst), 4360 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4361 NoItinerary, []>; 4362 def ATOMIC_LOAD_NAND_I8 : PseudoInst< 4363 (outs GPR:$dst), 4364 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4365 NoItinerary, []>; 4366 def ATOMIC_LOAD_MIN_I8 : PseudoInst< 4367 (outs GPR:$dst), 4368 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4369 NoItinerary, []>; 4370 def ATOMIC_LOAD_MAX_I8 : PseudoInst< 4371 (outs GPR:$dst), 4372 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4373 NoItinerary, []>; 4374 def ATOMIC_LOAD_UMIN_I8 : PseudoInst< 4375 (outs GPR:$dst), 4376 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4377 NoItinerary, []>; 4378 def ATOMIC_LOAD_UMAX_I8 : PseudoInst< 4379 (outs GPR:$dst), 4380 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4381 NoItinerary, []>; 4382 def ATOMIC_SWAP_I8 : PseudoInst< 4383 (outs GPR:$dst), 4384 (ins GPR:$ptr, GPR:$new, i32imm:$ordering), 4385 NoItinerary, []>; 4386 def ATOMIC_CMP_SWAP_I8 : PseudoInst< 4387 (outs GPR:$dst), 4388 (ins GPR:$ptr, GPR:$old, GPR:$new, i32imm:$ordering), 4389 NoItinerary, []>; 4390 def ATOMIC_LOAD_ADD_I16 : PseudoInst< 4391 (outs GPR:$dst), 4392 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4393 NoItinerary, []>; 4394 def ATOMIC_LOAD_SUB_I16 : PseudoInst< 4395 (outs GPR:$dst), 4396 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4397 NoItinerary, []>; 4398 def ATOMIC_LOAD_AND_I16 : PseudoInst< 4399 (outs GPR:$dst), 4400 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4401 NoItinerary, []>; 4402 def ATOMIC_LOAD_OR_I16 : PseudoInst< 4403 (outs GPR:$dst), 4404 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4405 NoItinerary, []>; 4406 def ATOMIC_LOAD_XOR_I16 : PseudoInst< 4407 (outs GPR:$dst), 4408 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4409 NoItinerary, []>; 4410 def ATOMIC_LOAD_NAND_I16 : PseudoInst< 4411 (outs GPR:$dst), 4412 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4413 NoItinerary, []>; 4414 def ATOMIC_LOAD_MIN_I16 : PseudoInst< 4415 (outs GPR:$dst), 4416 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4417 NoItinerary, []>; 4418 def ATOMIC_LOAD_MAX_I16 : PseudoInst< 4419 (outs GPR:$dst), 4420 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4421 NoItinerary, []>; 4422 def ATOMIC_LOAD_UMIN_I16 : PseudoInst< 4423 (outs GPR:$dst), 4424 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4425 NoItinerary, []>; 4426 def ATOMIC_LOAD_UMAX_I16 : PseudoInst< 4427 (outs GPR:$dst), 4428 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4429 NoItinerary, []>; 4430 def ATOMIC_SWAP_I16 : PseudoInst< 4431 (outs GPR:$dst), 4432 (ins GPR:$ptr, GPR:$new, i32imm:$ordering), 4433 NoItinerary, []>; 4434 def ATOMIC_CMP_SWAP_I16 : PseudoInst< 4435 (outs GPR:$dst), 4436 (ins GPR:$ptr, GPR:$old, GPR:$new, i32imm:$ordering), 4437 NoItinerary, []>; 4438 def ATOMIC_LOAD_ADD_I32 : PseudoInst< 4439 (outs GPR:$dst), 4440 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4441 NoItinerary, []>; 4442 def ATOMIC_LOAD_SUB_I32 : PseudoInst< 4443 (outs GPR:$dst), 4444 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4445 NoItinerary, []>; 4446 def ATOMIC_LOAD_AND_I32 : PseudoInst< 4447 (outs GPR:$dst), 4448 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4449 NoItinerary, []>; 4450 def ATOMIC_LOAD_OR_I32 : PseudoInst< 4451 (outs GPR:$dst), 4452 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4453 NoItinerary, []>; 4454 def ATOMIC_LOAD_XOR_I32 : PseudoInst< 4455 (outs GPR:$dst), 4456 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4457 NoItinerary, []>; 4458 def ATOMIC_LOAD_NAND_I32 : PseudoInst< 4459 (outs GPR:$dst), 4460 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4461 NoItinerary, []>; 4462 def ATOMIC_LOAD_MIN_I32 : PseudoInst< 4463 (outs GPR:$dst), 4464 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4465 NoItinerary, []>; 4466 def ATOMIC_LOAD_MAX_I32 : PseudoInst< 4467 (outs GPR:$dst), 4468 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4469 NoItinerary, []>; 4470 def ATOMIC_LOAD_UMIN_I32 : PseudoInst< 4471 (outs GPR:$dst), 4472 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4473 NoItinerary, []>; 4474 def ATOMIC_LOAD_UMAX_I32 : PseudoInst< 4475 (outs GPR:$dst), 4476 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4477 NoItinerary, []>; 4478 def ATOMIC_SWAP_I32 : PseudoInst< 4479 (outs GPR:$dst), 4480 (ins GPR:$ptr, GPR:$new, i32imm:$ordering), 4481 NoItinerary, []>; 4482 def ATOMIC_CMP_SWAP_I32 : PseudoInst< 4483 (outs GPR:$dst), 4484 (ins GPR:$ptr, GPR:$old, GPR:$new, i32imm:$ordering), 4485 NoItinerary, []>; 4486 def ATOMIC_LOAD_ADD_I64 : PseudoInst< 4487 (outs GPR:$dst1, GPR:$dst2), 4488 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4489 NoItinerary, []>; 4490 def ATOMIC_LOAD_SUB_I64 : PseudoInst< 4491 (outs GPR:$dst1, GPR:$dst2), 4492 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4493 NoItinerary, []>; 4494 def ATOMIC_LOAD_AND_I64 : PseudoInst< 4495 (outs GPR:$dst1, GPR:$dst2), 4496 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4497 NoItinerary, []>; 4498 def ATOMIC_LOAD_OR_I64 : PseudoInst< 4499 (outs GPR:$dst1, GPR:$dst2), 4500 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4501 NoItinerary, []>; 4502 def ATOMIC_LOAD_XOR_I64 : PseudoInst< 4503 (outs GPR:$dst1, GPR:$dst2), 4504 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4505 NoItinerary, []>; 4506 def ATOMIC_LOAD_NAND_I64 : PseudoInst< 4507 (outs GPR:$dst1, GPR:$dst2), 4508 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4509 NoItinerary, []>; 4510 def ATOMIC_LOAD_MIN_I64 : PseudoInst< 4511 (outs GPR:$dst1, GPR:$dst2), 4512 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4513 NoItinerary, []>; 4514 def ATOMIC_LOAD_MAX_I64 : PseudoInst< 4515 (outs GPR:$dst1, GPR:$dst2), 4516 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4517 NoItinerary, []>; 4518 def ATOMIC_LOAD_UMIN_I64 : PseudoInst< 4519 (outs GPR:$dst1, GPR:$dst2), 4520 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4521 NoItinerary, []>; 4522 def ATOMIC_LOAD_UMAX_I64 : PseudoInst< 4523 (outs GPR:$dst1, GPR:$dst2), 4524 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4525 NoItinerary, []>; 4526 def ATOMIC_SWAP_I64 : PseudoInst< 4527 (outs GPR:$dst1, GPR:$dst2), 4528 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4529 NoItinerary, []>; 4530 def ATOMIC_CMP_SWAP_I64 : PseudoInst< 4531 (outs GPR:$dst1, GPR:$dst2), 4532 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2, 4533 GPR:$set1, GPR:$set2, i32imm:$ordering), 4534 NoItinerary, []>; 4535 } 4536 let mayLoad = 1 in 4537 def ATOMIC_LOAD_I64 : PseudoInst< 4538 (outs GPR:$dst1, GPR:$dst2), 4539 (ins GPR:$addr, i32imm:$ordering), 4540 NoItinerary, []>; 4541 let mayStore = 1 in 4542 def ATOMIC_STORE_I64 : PseudoInst< 4543 (outs GPR:$dst1, GPR:$dst2), 4544 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4545 NoItinerary, []>; 4546} 4547 4548let usesCustomInserter = 1 in { 4549 def COPY_STRUCT_BYVAL_I32 : PseudoInst< 4550 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment), 4551 NoItinerary, 4552 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>; 4553} 4554 4555def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4556 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4557}]>; 4558 4559def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4560 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4561}]>; 4562 4563def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4564 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4565}]>; 4566 4567def strex_1 : PatFrag<(ops node:$val, node:$ptr), 4568 (int_arm_strex node:$val, node:$ptr), [{ 4569 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4570}]>; 4571 4572def strex_2 : PatFrag<(ops node:$val, node:$ptr), 4573 (int_arm_strex node:$val, node:$ptr), [{ 4574 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4575}]>; 4576 4577def strex_4 : PatFrag<(ops node:$val, node:$ptr), 4578 (int_arm_strex node:$val, node:$ptr), [{ 4579 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4580}]>; 4581 4582let mayLoad = 1 in { 4583def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4584 NoItinerary, "ldrexb", "\t$Rt, $addr", 4585 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>; 4586def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4587 NoItinerary, "ldrexh", "\t$Rt, $addr", 4588 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>; 4589def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4590 NoItinerary, "ldrex", "\t$Rt, $addr", 4591 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>; 4592let hasExtraDefRegAllocReq = 1 in 4593def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 4594 NoItinerary, "ldrexd", "\t$Rt, $addr", []> { 4595 let DecoderMethod = "DecodeDoubleRegLoad"; 4596} 4597 4598def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4599 NoItinerary, "ldaexb", "\t$Rt, $addr", []>; 4600def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4601 NoItinerary, "ldaexh", "\t$Rt, $addr", []>; 4602def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4603 NoItinerary, "ldaex", "\t$Rt, $addr", []>; 4604let hasExtraDefRegAllocReq = 1 in 4605def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 4606 NoItinerary, "ldaexd", "\t$Rt, $addr", []> { 4607 let DecoderMethod = "DecodeDoubleRegLoad"; 4608} 4609} 4610 4611let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 4612def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4613 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", 4614 [(set GPR:$Rd, (strex_1 GPR:$Rt, addr_offset_none:$addr))]>; 4615def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4616 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", 4617 [(set GPR:$Rd, (strex_2 GPR:$Rt, addr_offset_none:$addr))]>; 4618def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4619 NoItinerary, "strex", "\t$Rd, $Rt, $addr", 4620 [(set GPR:$Rd, (strex_4 GPR:$Rt, addr_offset_none:$addr))]>; 4621let hasExtraSrcRegAllocReq = 1 in 4622def STREXD : AIstrex<0b01, (outs GPR:$Rd), 4623 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 4624 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> { 4625 let DecoderMethod = "DecodeDoubleRegStore"; 4626} 4627def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4628 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr", 4629 []>; 4630def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4631 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr", 4632 []>; 4633def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4634 NoItinerary, "stlex", "\t$Rd, $Rt, $addr", 4635 []>; 4636let hasExtraSrcRegAllocReq = 1 in 4637def STLEXD : AIstlex<0b01, (outs GPR:$Rd), 4638 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 4639 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> { 4640 let DecoderMethod = "DecodeDoubleRegStore"; 4641} 4642} 4643 4644def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", 4645 [(int_arm_clrex)]>, 4646 Requires<[IsARM, HasV7]> { 4647 let Inst{31-0} = 0b11110101011111111111000000011111; 4648} 4649 4650def : ARMPat<(and (ldrex_1 addr_offset_none:$addr), 0xff), 4651 (LDREXB addr_offset_none:$addr)>; 4652def : ARMPat<(and (ldrex_2 addr_offset_none:$addr), 0xffff), 4653 (LDREXH addr_offset_none:$addr)>; 4654def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 4655 (STREXB GPR:$Rt, addr_offset_none:$addr)>; 4656def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 4657 (STREXH GPR:$Rt, addr_offset_none:$addr)>; 4658 4659class acquiring_load<PatFrag base> 4660 : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 4661 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 4662 return Ordering == Acquire || Ordering == SequentiallyConsistent; 4663}]>; 4664 4665def atomic_load_acquire_8 : acquiring_load<atomic_load_8>; 4666def atomic_load_acquire_16 : acquiring_load<atomic_load_16>; 4667def atomic_load_acquire_32 : acquiring_load<atomic_load_32>; 4668 4669class releasing_store<PatFrag base> 4670 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 4671 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 4672 return Ordering == Release || Ordering == SequentiallyConsistent; 4673}]>; 4674 4675def atomic_store_release_8 : releasing_store<atomic_store_8>; 4676def atomic_store_release_16 : releasing_store<atomic_store_16>; 4677def atomic_store_release_32 : releasing_store<atomic_store_32>; 4678 4679let AddedComplexity = 8 in { 4680 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>; 4681 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>; 4682 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>; 4683 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>; 4684 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>; 4685 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>; 4686} 4687 4688// SWP/SWPB are deprecated in V6/V7. 4689let mayLoad = 1, mayStore = 1 in { 4690def SWP : AIswp<0, (outs GPRnopc:$Rt), 4691 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>, 4692 Requires<[PreV8]>; 4693def SWPB: AIswp<1, (outs GPRnopc:$Rt), 4694 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>, 4695 Requires<[PreV8]>; 4696} 4697 4698//===----------------------------------------------------------------------===// 4699// Coprocessor Instructions. 4700// 4701 4702def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4703 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4704 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4705 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4706 imm:$CRm, imm:$opc2)]>, 4707 Requires<[PreV8]> { 4708 bits<4> opc1; 4709 bits<4> CRn; 4710 bits<4> CRd; 4711 bits<4> cop; 4712 bits<3> opc2; 4713 bits<4> CRm; 4714 4715 let Inst{3-0} = CRm; 4716 let Inst{4} = 0; 4717 let Inst{7-5} = opc2; 4718 let Inst{11-8} = cop; 4719 let Inst{15-12} = CRd; 4720 let Inst{19-16} = CRn; 4721 let Inst{23-20} = opc1; 4722} 4723 4724def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4725 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4726 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4727 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4728 imm:$CRm, imm:$opc2)]>, 4729 Requires<[PreV8]> { 4730 let Inst{31-28} = 0b1111; 4731 bits<4> opc1; 4732 bits<4> CRn; 4733 bits<4> CRd; 4734 bits<4> cop; 4735 bits<3> opc2; 4736 bits<4> CRm; 4737 4738 let Inst{3-0} = CRm; 4739 let Inst{4} = 0; 4740 let Inst{7-5} = opc2; 4741 let Inst{11-8} = cop; 4742 let Inst{15-12} = CRd; 4743 let Inst{19-16} = CRn; 4744 let Inst{23-20} = opc1; 4745} 4746 4747class ACI<dag oops, dag iops, string opc, string asm, 4748 IndexMode im = IndexModeNone> 4749 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 4750 opc, asm, "", []> { 4751 let Inst{27-25} = 0b110; 4752} 4753class ACInoP<dag oops, dag iops, string opc, string asm, 4754 IndexMode im = IndexModeNone> 4755 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 4756 opc, asm, "", []> { 4757 let Inst{31-28} = 0b1111; 4758 let Inst{27-25} = 0b110; 4759} 4760multiclass LdStCop<bit load, bit Dbit, string asm> { 4761 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 4762 asm, "\t$cop, $CRd, $addr"> { 4763 bits<13> addr; 4764 bits<4> cop; 4765 bits<4> CRd; 4766 let Inst{24} = 1; // P = 1 4767 let Inst{23} = addr{8}; 4768 let Inst{22} = Dbit; 4769 let Inst{21} = 0; // W = 0 4770 let Inst{20} = load; 4771 let Inst{19-16} = addr{12-9}; 4772 let Inst{15-12} = CRd; 4773 let Inst{11-8} = cop; 4774 let Inst{7-0} = addr{7-0}; 4775 let DecoderMethod = "DecodeCopMemInstruction"; 4776 } 4777 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 4778 asm, "\t$cop, $CRd, $addr!", IndexModePre> { 4779 bits<13> addr; 4780 bits<4> cop; 4781 bits<4> CRd; 4782 let Inst{24} = 1; // P = 1 4783 let Inst{23} = addr{8}; 4784 let Inst{22} = Dbit; 4785 let Inst{21} = 1; // W = 1 4786 let Inst{20} = load; 4787 let Inst{19-16} = addr{12-9}; 4788 let Inst{15-12} = CRd; 4789 let Inst{11-8} = cop; 4790 let Inst{7-0} = addr{7-0}; 4791 let DecoderMethod = "DecodeCopMemInstruction"; 4792 } 4793 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4794 postidx_imm8s4:$offset), 4795 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> { 4796 bits<9> offset; 4797 bits<4> addr; 4798 bits<4> cop; 4799 bits<4> CRd; 4800 let Inst{24} = 0; // P = 0 4801 let Inst{23} = offset{8}; 4802 let Inst{22} = Dbit; 4803 let Inst{21} = 1; // W = 1 4804 let Inst{20} = load; 4805 let Inst{19-16} = addr; 4806 let Inst{15-12} = CRd; 4807 let Inst{11-8} = cop; 4808 let Inst{7-0} = offset{7-0}; 4809 let DecoderMethod = "DecodeCopMemInstruction"; 4810 } 4811 def _OPTION : ACI<(outs), 4812 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4813 coproc_option_imm:$option), 4814 asm, "\t$cop, $CRd, $addr, $option"> { 4815 bits<8> option; 4816 bits<4> addr; 4817 bits<4> cop; 4818 bits<4> CRd; 4819 let Inst{24} = 0; // P = 0 4820 let Inst{23} = 1; // U = 1 4821 let Inst{22} = Dbit; 4822 let Inst{21} = 0; // W = 0 4823 let Inst{20} = load; 4824 let Inst{19-16} = addr; 4825 let Inst{15-12} = CRd; 4826 let Inst{11-8} = cop; 4827 let Inst{7-0} = option; 4828 let DecoderMethod = "DecodeCopMemInstruction"; 4829 } 4830} 4831multiclass LdSt2Cop<bit load, bit Dbit, string asm> { 4832 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 4833 asm, "\t$cop, $CRd, $addr"> { 4834 bits<13> addr; 4835 bits<4> cop; 4836 bits<4> CRd; 4837 let Inst{24} = 1; // P = 1 4838 let Inst{23} = addr{8}; 4839 let Inst{22} = Dbit; 4840 let Inst{21} = 0; // W = 0 4841 let Inst{20} = load; 4842 let Inst{19-16} = addr{12-9}; 4843 let Inst{15-12} = CRd; 4844 let Inst{11-8} = cop; 4845 let Inst{7-0} = addr{7-0}; 4846 let DecoderMethod = "DecodeCopMemInstruction"; 4847 } 4848 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 4849 asm, "\t$cop, $CRd, $addr!", IndexModePre> { 4850 bits<13> addr; 4851 bits<4> cop; 4852 bits<4> CRd; 4853 let Inst{24} = 1; // P = 1 4854 let Inst{23} = addr{8}; 4855 let Inst{22} = Dbit; 4856 let Inst{21} = 1; // W = 1 4857 let Inst{20} = load; 4858 let Inst{19-16} = addr{12-9}; 4859 let Inst{15-12} = CRd; 4860 let Inst{11-8} = cop; 4861 let Inst{7-0} = addr{7-0}; 4862 let DecoderMethod = "DecodeCopMemInstruction"; 4863 } 4864 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4865 postidx_imm8s4:$offset), 4866 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> { 4867 bits<9> offset; 4868 bits<4> addr; 4869 bits<4> cop; 4870 bits<4> CRd; 4871 let Inst{24} = 0; // P = 0 4872 let Inst{23} = offset{8}; 4873 let Inst{22} = Dbit; 4874 let Inst{21} = 1; // W = 1 4875 let Inst{20} = load; 4876 let Inst{19-16} = addr; 4877 let Inst{15-12} = CRd; 4878 let Inst{11-8} = cop; 4879 let Inst{7-0} = offset{7-0}; 4880 let DecoderMethod = "DecodeCopMemInstruction"; 4881 } 4882 def _OPTION : ACInoP<(outs), 4883 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4884 coproc_option_imm:$option), 4885 asm, "\t$cop, $CRd, $addr, $option"> { 4886 bits<8> option; 4887 bits<4> addr; 4888 bits<4> cop; 4889 bits<4> CRd; 4890 let Inst{24} = 0; // P = 0 4891 let Inst{23} = 1; // U = 1 4892 let Inst{22} = Dbit; 4893 let Inst{21} = 0; // W = 0 4894 let Inst{20} = load; 4895 let Inst{19-16} = addr; 4896 let Inst{15-12} = CRd; 4897 let Inst{11-8} = cop; 4898 let Inst{7-0} = option; 4899 let DecoderMethod = "DecodeCopMemInstruction"; 4900 } 4901} 4902 4903defm LDC : LdStCop <1, 0, "ldc">; 4904defm LDCL : LdStCop <1, 1, "ldcl">; 4905defm STC : LdStCop <0, 0, "stc">; 4906defm STCL : LdStCop <0, 1, "stcl">; 4907defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>; 4908defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>; 4909defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>; 4910defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>; 4911 4912//===----------------------------------------------------------------------===// 4913// Move between coprocessor and ARM core register. 4914// 4915 4916class MovRCopro<string opc, bit direction, dag oops, dag iops, 4917 list<dag> pattern> 4918 : ABI<0b1110, oops, iops, NoItinerary, opc, 4919 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> { 4920 let Inst{20} = direction; 4921 let Inst{4} = 1; 4922 4923 bits<4> Rt; 4924 bits<4> cop; 4925 bits<3> opc1; 4926 bits<3> opc2; 4927 bits<4> CRm; 4928 bits<4> CRn; 4929 4930 let Inst{15-12} = Rt; 4931 let Inst{11-8} = cop; 4932 let Inst{23-21} = opc1; 4933 let Inst{7-5} = opc2; 4934 let Inst{3-0} = CRm; 4935 let Inst{19-16} = CRn; 4936} 4937 4938def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */, 4939 (outs), 4940 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4941 c_imm:$CRm, imm0_7:$opc2), 4942 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 4943 imm:$CRm, imm:$opc2)]>, 4944 ComplexDeprecationPredicate<"MCR">; 4945def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 4946 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4947 c_imm:$CRm, 0, pred:$p)>; 4948def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, 4949 (outs GPRwithAPSR:$Rt), 4950 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 4951 imm0_7:$opc2), []>; 4952def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", 4953 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4954 c_imm:$CRm, 0, pred:$p)>; 4955 4956def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 4957 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 4958 4959class MovRCopro2<string opc, bit direction, dag oops, dag iops, 4960 list<dag> pattern> 4961 : ABXI<0b1110, oops, iops, NoItinerary, 4962 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> { 4963 let Inst{31-24} = 0b11111110; 4964 let Inst{20} = direction; 4965 let Inst{4} = 1; 4966 4967 bits<4> Rt; 4968 bits<4> cop; 4969 bits<3> opc1; 4970 bits<3> opc2; 4971 bits<4> CRm; 4972 bits<4> CRn; 4973 4974 let Inst{15-12} = Rt; 4975 let Inst{11-8} = cop; 4976 let Inst{23-21} = opc1; 4977 let Inst{7-5} = opc2; 4978 let Inst{3-0} = CRm; 4979 let Inst{19-16} = CRn; 4980} 4981 4982def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */, 4983 (outs), 4984 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4985 c_imm:$CRm, imm0_7:$opc2), 4986 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 4987 imm:$CRm, imm:$opc2)]>, 4988 Requires<[PreV8]>; 4989def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm", 4990 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4991 c_imm:$CRm, 0)>; 4992def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, 4993 (outs GPRwithAPSR:$Rt), 4994 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 4995 imm0_7:$opc2), []>, 4996 Requires<[PreV8]>; 4997def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm", 4998 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4999 c_imm:$CRm, 0)>; 5000 5001def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, 5002 imm:$CRm, imm:$opc2), 5003 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 5004 5005class MovRRCopro<string opc, bit direction, list<dag> pattern = []> 5006 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5007 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), 5008 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> { 5009 let Inst{23-21} = 0b010; 5010 let Inst{20} = direction; 5011 5012 bits<4> Rt; 5013 bits<4> Rt2; 5014 bits<4> cop; 5015 bits<4> opc1; 5016 bits<4> CRm; 5017 5018 let Inst{15-12} = Rt; 5019 let Inst{19-16} = Rt2; 5020 let Inst{11-8} = cop; 5021 let Inst{7-4} = opc1; 5022 let Inst{3-0} = CRm; 5023} 5024 5025def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */, 5026 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt, 5027 GPRnopc:$Rt2, imm:$CRm)]>; 5028def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>; 5029 5030class MovRRCopro2<string opc, bit direction, list<dag> pattern = []> 5031 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5032 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary, 5033 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>, 5034 Requires<[PreV8]> { 5035 let Inst{31-28} = 0b1111; 5036 let Inst{23-21} = 0b010; 5037 let Inst{20} = direction; 5038 5039 bits<4> Rt; 5040 bits<4> Rt2; 5041 bits<4> cop; 5042 bits<4> opc1; 5043 bits<4> CRm; 5044 5045 let Inst{15-12} = Rt; 5046 let Inst{19-16} = Rt2; 5047 let Inst{11-8} = cop; 5048 let Inst{7-4} = opc1; 5049 let Inst{3-0} = CRm; 5050 5051 let DecoderMethod = "DecodeMRRC2"; 5052} 5053 5054def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */, 5055 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt, 5056 GPRnopc:$Rt2, imm:$CRm)]>; 5057def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>; 5058 5059//===----------------------------------------------------------------------===// 5060// Move between special register and ARM core register 5061// 5062 5063// Move to ARM core register from Special Register 5064def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5065 "mrs", "\t$Rd, apsr", []> { 5066 bits<4> Rd; 5067 let Inst{23-16} = 0b00001111; 5068 let Unpredictable{19-17} = 0b111; 5069 5070 let Inst{15-12} = Rd; 5071 5072 let Inst{11-0} = 0b000000000000; 5073 let Unpredictable{11-0} = 0b110100001111; 5074} 5075 5076def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>, 5077 Requires<[IsARM]>; 5078 5079// The MRSsys instruction is the MRS instruction from the ARM ARM, 5080// section B9.3.9, with the R bit set to 1. 5081def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5082 "mrs", "\t$Rd, spsr", []> { 5083 bits<4> Rd; 5084 let Inst{23-16} = 0b01001111; 5085 let Unpredictable{19-16} = 0b1111; 5086 5087 let Inst{15-12} = Rd; 5088 5089 let Inst{11-0} = 0b000000000000; 5090 let Unpredictable{11-0} = 0b110100001111; 5091} 5092 5093// Move from ARM core register to Special Register 5094// 5095// No need to have both system and application versions, the encodings are the 5096// same and the assembly parser has no way to distinguish between them. The mask 5097// operand contains the special register (R Bit) in bit 4 and bits 3-0 contains 5098// the mask with the fields to be accessed in the special register. 5099def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, 5100 "msr", "\t$mask, $Rn", []> { 5101 bits<5> mask; 5102 bits<4> Rn; 5103 5104 let Inst{23} = 0; 5105 let Inst{22} = mask{4}; // R bit 5106 let Inst{21-20} = 0b10; 5107 let Inst{19-16} = mask{3-0}; 5108 let Inst{15-12} = 0b1111; 5109 let Inst{11-4} = 0b00000000; 5110 let Inst{3-0} = Rn; 5111} 5112 5113def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary, 5114 "msr", "\t$mask, $a", []> { 5115 bits<5> mask; 5116 bits<12> a; 5117 5118 let Inst{23} = 0; 5119 let Inst{22} = mask{4}; // R bit 5120 let Inst{21-20} = 0b10; 5121 let Inst{19-16} = mask{3-0}; 5122 let Inst{15-12} = 0b1111; 5123 let Inst{11-0} = a; 5124} 5125 5126//===----------------------------------------------------------------------===// 5127// TLS Instructions 5128// 5129 5130// __aeabi_read_tp preserves the registers r1-r3. 5131// This is a pseudo inst so that we can get the encoding right, 5132// complete with fixup for the aeabi_read_tp function. 5133let isCall = 1, 5134 Defs = [R0, R12, LR, CPSR], Uses = [SP] in { 5135 def TPsoft : PseudoInst<(outs), (ins), IIC_Br, 5136 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>; 5137} 5138 5139//===----------------------------------------------------------------------===// 5140// SJLJ Exception handling intrinsics 5141// eh_sjlj_setjmp() is an instruction sequence to store the return 5142// address and save #0 in R0 for the non-longjmp case. 5143// Since by its nature we may be coming from some other function to get 5144// here, and we're using the stack frame for the containing function to 5145// save/restore registers, we can't keep anything live in regs across 5146// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 5147// when we get here from a longjmp(). We force everything out of registers 5148// except for our own input by listing the relevant registers in Defs. By 5149// doing so, we also cause the prologue/epilogue code to actively preserve 5150// all of the callee-saved resgisters, which is exactly what we want. 5151// A constant value is passed in $val, and we use the location as a scratch. 5152// 5153// These are pseudo-instructions and are lowered to individual MC-insts, so 5154// no encoding information is necessary. 5155let Defs = 5156 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 5157 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ], 5158 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5159 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5160 NoItinerary, 5161 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5162 Requires<[IsARM, HasVFP2]>; 5163} 5164 5165let Defs = 5166 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 5167 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5168 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5169 NoItinerary, 5170 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5171 Requires<[IsARM, NoVFP]>; 5172} 5173 5174// FIXME: Non-IOS version(s) 5175let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, 5176 Defs = [ R7, LR, SP ] in { 5177def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch), 5178 NoItinerary, 5179 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 5180 Requires<[IsARM, IsIOS]>; 5181} 5182 5183// eh.sjlj.dispatchsetup pseudo-instruction. 5184// This pseudo is used for both ARM and Thumb. Any differences are handled when 5185// the pseudo is expanded (which happens before any passes that need the 5186// instruction size). 5187let isBarrier = 1 in 5188def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>; 5189 5190 5191//===----------------------------------------------------------------------===// 5192// Non-Instruction Patterns 5193// 5194 5195// ARMv4 indirect branch using (MOVr PC, dst) 5196let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in 5197 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst), 5198 4, IIC_Br, [(brind GPR:$dst)], 5199 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5200 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5201 5202// Large immediate handling. 5203 5204// 32-bit immediate using two piece so_imms or movw + movt. 5205// This is a single pseudo instruction, the benefit is that it can be remat'd 5206// as a single unit instead of having to handle reg inputs. 5207// FIXME: Remove this when we can do generalized remat. 5208let isReMaterializable = 1, isMoveImm = 1 in 5209def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 5210 [(set GPR:$dst, (arm_i32imm:$src))]>, 5211 Requires<[IsARM]>; 5212 5213def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i, 5214 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>, 5215 Requires<[IsARM, DontUseMovt]>; 5216 5217// Pseudo instruction that combines movw + movt + add pc (if PIC). 5218// It also makes it possible to rematerialize the instructions. 5219// FIXME: Remove this when we can do generalized remat and when machine licm 5220// can properly the instructions. 5221let isReMaterializable = 1 in { 5222def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5223 IIC_iMOVix2addpc, 5224 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 5225 Requires<[IsARM, UseMovt]>; 5226 5227def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5228 IIC_iLoadiALU, 5229 [(set GPR:$dst, 5230 (ARMWrapperPIC tglobaladdr:$addr))]>, 5231 Requires<[IsARM, DontUseMovt]>; 5232 5233def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5234 NoItinerary, 5235 [(set GPR:$dst, 5236 (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5237 Requires<[IsARM, DontUseMovt]>; 5238 5239let AddedComplexity = 10 in 5240def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5241 IIC_iMOVix2ld, 5242 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5243 Requires<[IsARM, UseMovt]>; 5244} // isReMaterializable 5245 5246// ConstantPool, GlobalAddress, and JumpTable 5247def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 5248def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>, 5249 Requires<[IsARM, UseMovt]>; 5250def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id), 5251 (LEApcrelJT tjumptable:$dst, imm:$id)>; 5252 5253// TODO: add,sub,and, 3-instr forms? 5254 5255// Tail calls. These patterns also apply to Thumb mode. 5256def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>; 5257def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>; 5258def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>; 5259 5260// Direct calls 5261def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; 5262def : ARMPat<(ARMcall_nolink texternalsym:$func), 5263 (BMOVPCB_CALL texternalsym:$func)>; 5264 5265// zextload i1 -> zextload i8 5266def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5267def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5268 5269// extload -> zextload 5270def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5271def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5272def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5273def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5274 5275def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 5276 5277def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; 5278def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; 5279 5280// smul* and smla* 5281def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5282 (sra (shl GPR:$b, (i32 16)), (i32 16))), 5283 (SMULBB GPR:$a, GPR:$b)>; 5284def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 5285 (SMULBB GPR:$a, GPR:$b)>; 5286def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5287 (sra GPR:$b, (i32 16))), 5288 (SMULBT GPR:$a, GPR:$b)>; 5289def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))), 5290 (SMULBT GPR:$a, GPR:$b)>; 5291def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), 5292 (sra (shl GPR:$b, (i32 16)), (i32 16))), 5293 (SMULTB GPR:$a, GPR:$b)>; 5294def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b), 5295 (SMULTB GPR:$a, GPR:$b)>; 5296def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))), 5297 (i32 16)), 5298 (SMULWB GPR:$a, GPR:$b)>; 5299def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)), 5300 (SMULWB GPR:$a, GPR:$b)>; 5301 5302def : ARMV5MOPat<(add GPR:$acc, 5303 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5304 (sra (shl GPR:$b, (i32 16)), (i32 16)))), 5305 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5306def : ARMV5MOPat<(add GPR:$acc, 5307 (mul sext_16_node:$a, sext_16_node:$b)), 5308 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5309def : ARMV5MOPat<(add GPR:$acc, 5310 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5311 (sra GPR:$b, (i32 16)))), 5312 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5313def : ARMV5MOPat<(add GPR:$acc, 5314 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))), 5315 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5316def : ARMV5MOPat<(add GPR:$acc, 5317 (mul (sra GPR:$a, (i32 16)), 5318 (sra (shl GPR:$b, (i32 16)), (i32 16)))), 5319 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5320def : ARMV5MOPat<(add GPR:$acc, 5321 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)), 5322 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5323def : ARMV5MOPat<(add GPR:$acc, 5324 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))), 5325 (i32 16))), 5326 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 5327def : ARMV5MOPat<(add GPR:$acc, 5328 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))), 5329 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 5330 5331 5332// Pre-v7 uses MCR for synchronization barriers. 5333def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>, 5334 Requires<[IsARM, HasV6]>; 5335 5336// SXT/UXT with no rotate 5337let AddedComplexity = 16 in { 5338def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>; 5339def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>; 5340def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>; 5341def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)), 5342 (UXTAB GPR:$Rn, GPR:$Rm, 0)>; 5343def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)), 5344 (UXTAH GPR:$Rn, GPR:$Rm, 0)>; 5345} 5346 5347def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>; 5348def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; 5349 5350def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)), 5351 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>; 5352def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)), 5353 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>; 5354 5355// Atomic load/store patterns 5356def : ARMPat<(atomic_load_8 ldst_so_reg:$src), 5357 (LDRBrs ldst_so_reg:$src)>; 5358def : ARMPat<(atomic_load_8 addrmode_imm12:$src), 5359 (LDRBi12 addrmode_imm12:$src)>; 5360def : ARMPat<(atomic_load_16 addrmode3:$src), 5361 (LDRH addrmode3:$src)>; 5362def : ARMPat<(atomic_load_32 ldst_so_reg:$src), 5363 (LDRrs ldst_so_reg:$src)>; 5364def : ARMPat<(atomic_load_32 addrmode_imm12:$src), 5365 (LDRi12 addrmode_imm12:$src)>; 5366def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val), 5367 (STRBrs GPR:$val, ldst_so_reg:$ptr)>; 5368def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val), 5369 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>; 5370def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val), 5371 (STRH GPR:$val, addrmode3:$ptr)>; 5372def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val), 5373 (STRrs GPR:$val, ldst_so_reg:$ptr)>; 5374def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val), 5375 (STRi12 GPR:$val, addrmode_imm12:$ptr)>; 5376 5377 5378//===----------------------------------------------------------------------===// 5379// Thumb Support 5380// 5381 5382include "ARMInstrThumb.td" 5383 5384//===----------------------------------------------------------------------===// 5385// Thumb2 Support 5386// 5387 5388include "ARMInstrThumb2.td" 5389 5390//===----------------------------------------------------------------------===// 5391// Floating Point Support 5392// 5393 5394include "ARMInstrVFP.td" 5395 5396//===----------------------------------------------------------------------===// 5397// Advanced SIMD (NEON) Support 5398// 5399 5400include "ARMInstrNEON.td" 5401 5402//===----------------------------------------------------------------------===// 5403// Assembler aliases 5404// 5405 5406// Memory barriers 5407def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>; 5408def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>; 5409def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>; 5410 5411// System instructions 5412def : MnemonicAlias<"swi", "svc">; 5413 5414// Load / Store Multiple 5415def : MnemonicAlias<"ldmfd", "ldm">; 5416def : MnemonicAlias<"ldmia", "ldm">; 5417def : MnemonicAlias<"ldmea", "ldmdb">; 5418def : MnemonicAlias<"stmfd", "stmdb">; 5419def : MnemonicAlias<"stmia", "stm">; 5420def : MnemonicAlias<"stmea", "stm">; 5421 5422// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the 5423// shift amount is zero (i.e., unspecified). 5424def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 5425 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>, 5426 Requires<[IsARM, HasV6]>; 5427def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 5428 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>, 5429 Requires<[IsARM, HasV6]>; 5430 5431// PUSH/POP aliases for STM/LDM 5432def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>; 5433def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>; 5434 5435// SSAT/USAT optional shift operand. 5436def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 5437 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5438def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn", 5439 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5440 5441 5442// Extend instruction optional rotate operand. 5443def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm", 5444 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5445def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm", 5446 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5447def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 5448 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5449def : ARMInstAlias<"sxtb${p} $Rd, $Rm", 5450 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5451def : ARMInstAlias<"sxtb16${p} $Rd, $Rm", 5452 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5453def : ARMInstAlias<"sxth${p} $Rd, $Rm", 5454 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5455 5456def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm", 5457 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5458def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm", 5459 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5460def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 5461 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5462def : ARMInstAlias<"uxtb${p} $Rd, $Rm", 5463 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5464def : ARMInstAlias<"uxtb16${p} $Rd, $Rm", 5465 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5466def : ARMInstAlias<"uxth${p} $Rd, $Rm", 5467 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5468 5469 5470// RFE aliases 5471def : MnemonicAlias<"rfefa", "rfeda">; 5472def : MnemonicAlias<"rfeea", "rfedb">; 5473def : MnemonicAlias<"rfefd", "rfeia">; 5474def : MnemonicAlias<"rfeed", "rfeib">; 5475def : MnemonicAlias<"rfe", "rfeia">; 5476 5477// SRS aliases 5478def : MnemonicAlias<"srsfa", "srsib">; 5479def : MnemonicAlias<"srsea", "srsia">; 5480def : MnemonicAlias<"srsfd", "srsdb">; 5481def : MnemonicAlias<"srsed", "srsda">; 5482def : MnemonicAlias<"srs", "srsia">; 5483 5484// QSAX == QSUBADDX 5485def : MnemonicAlias<"qsubaddx", "qsax">; 5486// SASX == SADDSUBX 5487def : MnemonicAlias<"saddsubx", "sasx">; 5488// SHASX == SHADDSUBX 5489def : MnemonicAlias<"shaddsubx", "shasx">; 5490// SHSAX == SHSUBADDX 5491def : MnemonicAlias<"shsubaddx", "shsax">; 5492// SSAX == SSUBADDX 5493def : MnemonicAlias<"ssubaddx", "ssax">; 5494// UASX == UADDSUBX 5495def : MnemonicAlias<"uaddsubx", "uasx">; 5496// UHASX == UHADDSUBX 5497def : MnemonicAlias<"uhaddsubx", "uhasx">; 5498// UHSAX == UHSUBADDX 5499def : MnemonicAlias<"uhsubaddx", "uhsax">; 5500// UQASX == UQADDSUBX 5501def : MnemonicAlias<"uqaddsubx", "uqasx">; 5502// UQSAX == UQSUBADDX 5503def : MnemonicAlias<"uqsubaddx", "uqsax">; 5504// USAX == USUBADDX 5505def : MnemonicAlias<"usubaddx", "usax">; 5506 5507// "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like 5508// for isel. 5509def : ARMInstAlias<"mov${s}${p} $Rd, $imm", 5510 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>; 5511def : ARMInstAlias<"mvn${s}${p} $Rd, $imm", 5512 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>; 5513// Same for AND <--> BIC 5514def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm", 5515 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm, 5516 pred:$p, cc_out:$s)>; 5517def : ARMInstAlias<"bic${s}${p} $Rdn, $imm", 5518 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm, 5519 pred:$p, cc_out:$s)>; 5520def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm", 5521 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm, 5522 pred:$p, cc_out:$s)>; 5523def : ARMInstAlias<"and${s}${p} $Rdn, $imm", 5524 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm, 5525 pred:$p, cc_out:$s)>; 5526 5527// Likewise, "add Rd, so_imm_neg" -> sub 5528def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm", 5529 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>; 5530def : ARMInstAlias<"add${s}${p} $Rd, $imm", 5531 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>; 5532// Same for CMP <--> CMN via so_imm_neg 5533def : ARMInstAlias<"cmp${p} $Rd, $imm", 5534 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>; 5535def : ARMInstAlias<"cmn${p} $Rd, $imm", 5536 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>; 5537 5538// The shifter forms of the MOV instruction are aliased to the ASR, LSL, 5539// LSR, ROR, and RRX instructions. 5540// FIXME: We need C++ parser hooks to map the alias to the MOV 5541// encoding. It seems we should be able to do that sort of thing 5542// in tblgen, but it could get ugly. 5543let TwoOperandAliasConstraint = "$Rm = $Rd" in { 5544def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm", 5545 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 5546 cc_out:$s)>; 5547def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm", 5548 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 5549 cc_out:$s)>; 5550def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm", 5551 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 5552 cc_out:$s)>; 5553def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm", 5554 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 5555 cc_out:$s)>; 5556} 5557def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm", 5558 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>; 5559let TwoOperandAliasConstraint = "$Rn = $Rd" in { 5560def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm", 5561 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5562 cc_out:$s)>; 5563def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm", 5564 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5565 cc_out:$s)>; 5566def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm", 5567 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5568 cc_out:$s)>; 5569def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm", 5570 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5571 cc_out:$s)>; 5572} 5573 5574// "neg" is and alias for "rsb rd, rn, #0" 5575def : ARMInstAlias<"neg${s}${p} $Rd, $Rm", 5576 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>; 5577 5578// Pre-v6, 'mov r0, r0' was used as a NOP encoding. 5579def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>, 5580 Requires<[IsARM, NoV6]>; 5581 5582// MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but 5583// the instruction definitions need difference constraints pre-v6. 5584// Use these aliases for the assembly parsing on pre-v6. 5585def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm", 5586 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 5587 Requires<[IsARM, NoV6]>; 5588def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra", 5589 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 5590 pred:$p, cc_out:$s)>, 5591 Requires<[IsARM, NoV6]>; 5592def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5593 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5594 Requires<[IsARM, NoV6]>; 5595def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5596 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5597 Requires<[IsARM, NoV6]>; 5598def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5599 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5600 Requires<[IsARM, NoV6]>; 5601def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5602 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5603 Requires<[IsARM, NoV6]>; 5604 5605// 'it' blocks in ARM mode just validate the predicates. The IT itself 5606// is discarded. 5607def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>, 5608 ComplexDeprecationPredicate<"IT">; 5609