1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the ARM instructions in TableGen format. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// ARM specific DAG Nodes. 15// 16 17// Type profiles. 18def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 19 SDTCisVT<1, i32> ]>; 20def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 21def SDT_ARMStructByVal : SDTypeProfile<0, 4, 22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 24 25def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 26 27def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 28 29def SDT_ARMCMov : SDTypeProfile<1, 3, 30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 31 SDTCisVT<3, i32>]>; 32 33def SDT_ARMBrcond : SDTypeProfile<0, 2, 34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 35 36def SDT_ARMBrJT : SDTypeProfile<0, 2, 37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 38 39def SDT_ARMBr2JT : SDTypeProfile<0, 3, 40 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 41 SDTCisVT<2, i32>]>; 42 43def SDT_ARMBCC_i64 : SDTypeProfile<0, 6, 44 [SDTCisVT<0, i32>, 45 SDTCisVT<1, i32>, SDTCisVT<2, i32>, 46 SDTCisVT<3, i32>, SDTCisVT<4, i32>, 47 SDTCisVT<5, OtherVT>]>; 48 49def SDT_ARMAnd : SDTypeProfile<1, 2, 50 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 51 SDTCisVT<2, i32>]>; 52 53def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 54 55def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 56 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 57 58def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 59def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, 60 SDTCisInt<2>]>; 61def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 62def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>; 63 64def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 65 66def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, 67 SDTCisInt<1>]>; 68 69def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 70 71def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 73 74def SDT_WIN__DBZCHK : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 75 76def SDT_ARMMEMCPY : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 77 SDTCisVT<2, i32>, SDTCisVT<3, i32>, 78 SDTCisVT<4, i32>]>; 79 80def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 81 [SDTCisSameAs<0, 2>, 82 SDTCisSameAs<0, 3>, 83 SDTCisInt<0>, SDTCisVT<1, i32>]>; 84 85// SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR 86def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 87 [SDTCisSameAs<0, 2>, 88 SDTCisSameAs<0, 3>, 89 SDTCisInt<0>, 90 SDTCisVT<1, i32>, 91 SDTCisVT<4, i32>]>; 92 93def SDT_LongMac : SDTypeProfile<2, 4, [SDTCisVT<0, i32>, 94 SDTCisSameAs<0, 1>, 95 SDTCisSameAs<0, 2>, 96 SDTCisSameAs<0, 3>, 97 SDTCisSameAs<0, 4>, 98 SDTCisSameAs<0, 5>]>; 99 100// ARMlsll, ARMlsrl, ARMasrl 101def SDT_ARMIntShiftParts : SDTypeProfile<2, 3, [SDTCisSameAs<0, 1>, 102 SDTCisSameAs<0, 2>, 103 SDTCisSameAs<0, 3>, 104 SDTCisInt<0>, 105 SDTCisInt<4>]>; 106 107// TODO Add another operand for 'Size' so that we can re-use this node when we 108// start supporting *TP versions. 109def SDT_ARMLoLoop : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, 110 SDTCisVT<1, OtherVT>]>; 111 112def ARMSmlald : SDNode<"ARMISD::SMLALD", SDT_LongMac>; 113def ARMSmlaldx : SDNode<"ARMISD::SMLALDX", SDT_LongMac>; 114def ARMSmlsld : SDNode<"ARMISD::SMLSLD", SDT_LongMac>; 115def ARMSmlsldx : SDNode<"ARMISD::SMLSLDX", SDT_LongMac>; 116 117def SDT_ARMCSel : SDTypeProfile<1, 3, 118 [SDTCisSameAs<0, 1>, 119 SDTCisSameAs<0, 2>, 120 SDTCisInt<3>, 121 SDTCisVT<3, i32>]>; 122 123def ARMcsinv : SDNode<"ARMISD::CSINV", SDT_ARMCSel, [SDNPOptInGlue]>; 124def ARMcsneg : SDNode<"ARMISD::CSNEG", SDT_ARMCSel, [SDNPOptInGlue]>; 125def ARMcsinc : SDNode<"ARMISD::CSINC", SDT_ARMCSel, [SDNPOptInGlue]>; 126 127def SDT_MulHSR : SDTypeProfile<1, 3, [SDTCisVT<0,i32>, 128 SDTCisSameAs<0, 1>, 129 SDTCisSameAs<0, 2>, 130 SDTCisSameAs<0, 3>]>; 131 132def ARMsmmlar : SDNode<"ARMISD::SMMLAR", SDT_MulHSR>; 133def ARMsmmlsr : SDNode<"ARMISD::SMMLSR", SDT_MulHSR>; 134 135// Node definitions. 136def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 137def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>; 138def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>; 139 140def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 141 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 142def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 143 [SDNPHasChain, SDNPSideEffect, 144 SDNPOptInGlue, SDNPOutGlue]>; 145def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" , 146 SDT_ARMStructByVal, 147 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 148 SDNPMayStore, SDNPMayLoad]>; 149 150def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 151 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 152 SDNPVariadic]>; 153def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 154 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 155 SDNPVariadic]>; 156def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 157 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 158 SDNPVariadic]>; 159 160def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, 161 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 162def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall, 163 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 164def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 165 [SDNPInGlue]>; 166def ARMsubs : SDNode<"ARMISD::SUBS", SDTIntBinOp, [SDNPOutGlue]>; 167 168def ARMssatnoshift : SDNode<"ARMISD::SSAT", SDTIntSatNoShOp, []>; 169 170def ARMusatnoshift : SDNode<"ARMISD::USAT", SDTIntSatNoShOp, []>; 171 172def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 173 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 174 175def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 176 [SDNPHasChain]>; 177def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, 178 [SDNPHasChain]>; 179 180def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64, 181 [SDNPHasChain]>; 182 183def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 184 [SDNPOutGlue]>; 185 186def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp, 187 [SDNPOutGlue]>; 188 189def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, 190 [SDNPOutGlue, SDNPCommutative]>; 191 192def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 193 194def ARMasrl : SDNode<"ARMISD::ASRL", SDT_ARMIntShiftParts, []>; 195def ARMlsrl : SDNode<"ARMISD::LSRL", SDT_ARMIntShiftParts, []>; 196def ARMlsll : SDNode<"ARMISD::LSLL", SDT_ARMIntShiftParts, []>; 197 198def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 199def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 200def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>; 201 202def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags, 203 [SDNPCommutative]>; 204def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>; 205def ARMlsls : SDNode<"ARMISD::LSLS", SDTBinaryArithWithFlags>; 206def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>; 207def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>; 208 209def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 210def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", 211 SDT_ARMEH_SJLJ_Setjmp, 212 [SDNPHasChain, SDNPSideEffect]>; 213def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP", 214 SDT_ARMEH_SJLJ_Longjmp, 215 [SDNPHasChain, SDNPSideEffect]>; 216def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH", 217 SDT_ARMEH_SJLJ_SetupDispatch, 218 [SDNPHasChain, SDNPSideEffect]>; 219 220def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER, 221 [SDNPHasChain, SDNPSideEffect]>; 222def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH, 223 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 224 225def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET, 226 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 227 228def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; 229 230def ARMmemcopy : SDNode<"ARMISD::MEMCPY", SDT_ARMMEMCPY, 231 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 232 SDNPMayStore, SDNPMayLoad]>; 233 234def ARMsmulwb : SDNode<"ARMISD::SMULWB", SDTIntBinOp, []>; 235def ARMsmulwt : SDNode<"ARMISD::SMULWT", SDTIntBinOp, []>; 236def ARMsmlalbb : SDNode<"ARMISD::SMLALBB", SDT_LongMac, []>; 237def ARMsmlalbt : SDNode<"ARMISD::SMLALBT", SDT_LongMac, []>; 238def ARMsmlaltb : SDNode<"ARMISD::SMLALTB", SDT_LongMac, []>; 239def ARMsmlaltt : SDNode<"ARMISD::SMLALTT", SDT_LongMac, []>; 240 241def ARMqadd8b : SDNode<"ARMISD::QADD8b", SDT_ARMAnd, []>; 242def ARMqsub8b : SDNode<"ARMISD::QSUB8b", SDT_ARMAnd, []>; 243def ARMqadd16b : SDNode<"ARMISD::QADD16b", SDT_ARMAnd, []>; 244def ARMqsub16b : SDNode<"ARMISD::QSUB16b", SDT_ARMAnd, []>; 245 246def SDT_ARMldrd : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>; 247def ARMldrd : SDNode<"ARMISD::LDRD", SDT_ARMldrd, [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 248 249def SDT_ARMstrd : SDTypeProfile<0, 3, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>; 250def ARMstrd : SDNode<"ARMISD::STRD", SDT_ARMstrd, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 251 252// Vector operations shared between NEON and MVE 253 254def ARMvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>; 255 256// VDUPLANE can produce a quad-register result from a double-register source, 257// so the result is not constrained to match the source. 258def ARMvduplane : SDNode<"ARMISD::VDUPLANE", 259 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 260 SDTCisVT<2, i32>]>>; 261 262def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>; 263def ARMvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>; 264def ARMvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>; 265def ARMvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>; 266 267def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>, 268 SDTCisVT<2, i32>]>; 269def ARMvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>; 270def ARMvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>; 271 272def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>; 273def ARMvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>; 274def ARMvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>; 275def ARMvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>; 276 277def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, 278 SDTCisVT<2, i32>]>; 279def ARMvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>; 280def ARMvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>; 281 282def SDTARMVSHIMM : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 283 SDTCisVT<2, i32>]>; 284def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 285 SDTCisSameAs<0, 2>,]>; 286def ARMvshlImm : SDNode<"ARMISD::VSHLIMM", SDTARMVSHIMM>; 287def ARMvshrsImm : SDNode<"ARMISD::VSHRsIMM", SDTARMVSHIMM>; 288def ARMvshruImm : SDNode<"ARMISD::VSHRuIMM", SDTARMVSHIMM>; 289def ARMvshls : SDNode<"ARMISD::VSHLs", SDTARMVSH>; 290def ARMvshlu : SDNode<"ARMISD::VSHLu", SDTARMVSH>; 291 292def SDTARMVCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, 293 SDTCisInt<3>]>; 294def SDTARMVCMPZ : SDTypeProfile<1, 2, [SDTCisInt<2>]>; 295 296def ARMvcmp : SDNode<"ARMISD::VCMP", SDTARMVCMP>; 297def ARMvcmpz : SDNode<"ARMISD::VCMPZ", SDTARMVCMPZ>; 298 299def ARMWLS : SDNode<"ARMISD::WLS", SDT_ARMLoLoop, [SDNPHasChain]>; 300def ARMLE : SDNode<"ARMISD::LE", SDT_ARMLoLoop, [SDNPHasChain]>; 301def ARMLoopDec : SDNode<"ARMISD::LOOP_DEC", SDTIntBinOp, [SDNPHasChain]>; 302 303//===----------------------------------------------------------------------===// 304// ARM Flag Definitions. 305 306class RegConstraint<string C> { 307 string Constraints = C; 308} 309 310// ARMCC condition codes. See ARMCC::CondCodes 311def ARMCCeq : PatLeaf<(i32 0)>; 312def ARMCCne : PatLeaf<(i32 1)>; 313def ARMCChs : PatLeaf<(i32 2)>; 314def ARMCClo : PatLeaf<(i32 3)>; 315def ARMCCmi : PatLeaf<(i32 4)>; 316def ARMCCpl : PatLeaf<(i32 5)>; 317def ARMCCvs : PatLeaf<(i32 6)>; 318def ARMCCvc : PatLeaf<(i32 7)>; 319def ARMCChi : PatLeaf<(i32 8)>; 320def ARMCCls : PatLeaf<(i32 9)>; 321def ARMCCge : PatLeaf<(i32 10)>; 322def ARMCClt : PatLeaf<(i32 11)>; 323def ARMCCgt : PatLeaf<(i32 12)>; 324def ARMCCle : PatLeaf<(i32 13)>; 325def ARMCCal : PatLeaf<(i32 14)>; 326 327// VCC predicates. See ARMVCC::VPTCodes 328def ARMVCCNone : PatLeaf<(i32 0)>; 329def ARMVCCThen : PatLeaf<(i32 1)>; 330def ARMVCCElse : PatLeaf<(i32 2)>; 331 332//===----------------------------------------------------------------------===// 333// ARM specific transformation functions and pattern fragments. 334// 335 336// imm_neg_XFORM - Return the negation of an i32 immediate value. 337def imm_neg_XFORM : SDNodeXForm<imm, [{ 338 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32); 339}]>; 340 341// imm_not_XFORM - Return the complement of a i32 immediate value. 342def imm_not_XFORM : SDNodeXForm<imm, [{ 343 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32); 344}]>; 345 346/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 347def imm16_31 : ImmLeaf<i32, [{ 348 return (int32_t)Imm >= 16 && (int32_t)Imm < 32; 349}]>; 350 351// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 352def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 353 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; 354}]>; 355 356def sext_bottom_16 : PatFrag<(ops node:$a), 357 (sext_inreg node:$a, i16)>; 358def sext_top_16 : PatFrag<(ops node:$a), 359 (i32 (sra node:$a, (i32 16)))>; 360 361def bb_mul : PatFrag<(ops node:$a, node:$b), 362 (mul (sext_bottom_16 node:$a), (sext_bottom_16 node:$b))>; 363def bt_mul : PatFrag<(ops node:$a, node:$b), 364 (mul (sext_bottom_16 node:$a), (sra node:$b, (i32 16)))>; 365def tb_mul : PatFrag<(ops node:$a, node:$b), 366 (mul (sra node:$a, (i32 16)), (sext_bottom_16 node:$b))>; 367def tt_mul : PatFrag<(ops node:$a, node:$b), 368 (mul (sra node:$a, (i32 16)), (sra node:$b, (i32 16)))>; 369 370/// Split a 32-bit immediate into two 16 bit parts. 371def hi16 : SDNodeXForm<imm, [{ 372 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N), 373 MVT::i32); 374}]>; 375 376def lo16AllZero : PatLeaf<(i32 imm), [{ 377 // Returns true if all low 16-bits are 0. 378 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 379}], hi16>; 380 381class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 382class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 383 384// An 'and' node with a single use. 385def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 386 return N->hasOneUse(); 387}]>; 388 389// An 'xor' node with a single use. 390def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{ 391 return N->hasOneUse(); 392}]>; 393 394// An 'fmul' node with a single use. 395def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{ 396 return N->hasOneUse(); 397}]>; 398 399// An 'fadd' node which checks for single non-hazardous use. 400def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{ 401 return hasNoVMLxHazardUse(N); 402}]>; 403 404// An 'fsub' node which checks for single non-hazardous use. 405def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{ 406 return hasNoVMLxHazardUse(N); 407}]>; 408 409//===----------------------------------------------------------------------===// 410// Operand Definitions. 411// 412 413// Immediate operands with a shared generic asm render method. 414class ImmAsmOperand<int Low, int High> : AsmOperandClass { 415 let RenderMethod = "addImmOperands"; 416 let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; 417 let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]"; 418} 419 420class ImmAsmOperandMinusOne<int Low, int High> : AsmOperandClass { 421 let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; 422 let DiagnosticType = "ImmRange" # Low # "_" # High; 423 let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]"; 424} 425 426// Operands that are part of a memory addressing mode. 427class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; } 428 429// Branch target. 430// FIXME: rename brtarget to t2_brtarget 431def brtarget : Operand<OtherVT> { 432 let EncoderMethod = "getBranchTargetOpValue"; 433 let OperandType = "OPERAND_PCREL"; 434 let DecoderMethod = "DecodeT2BROperand"; 435} 436 437// Branches targeting ARM-mode must be divisible by 4 if they're a raw 438// immediate. 439def ARMBranchTarget : AsmOperandClass { 440 let Name = "ARMBranchTarget"; 441} 442 443// Branches targeting Thumb-mode must be divisible by 2 if they're a raw 444// immediate. 445def ThumbBranchTarget : AsmOperandClass { 446 let Name = "ThumbBranchTarget"; 447} 448 449def arm_br_target : Operand<OtherVT> { 450 let ParserMatchClass = ARMBranchTarget; 451 let EncoderMethod = "getARMBranchTargetOpValue"; 452 let OperandType = "OPERAND_PCREL"; 453} 454 455// Call target for ARM. Handles conditional/unconditional 456// FIXME: rename bl_target to t2_bltarget? 457def arm_bl_target : Operand<i32> { 458 let ParserMatchClass = ARMBranchTarget; 459 let EncoderMethod = "getARMBLTargetOpValue"; 460 let OperandType = "OPERAND_PCREL"; 461} 462 463// Target for BLX *from* ARM mode. 464def arm_blx_target : Operand<i32> { 465 let ParserMatchClass = ThumbBranchTarget; 466 let EncoderMethod = "getARMBLXTargetOpValue"; 467 let OperandType = "OPERAND_PCREL"; 468} 469 470// A list of registers separated by comma. Used by load/store multiple. 471def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; } 472def reglist : Operand<i32> { 473 let EncoderMethod = "getRegisterListOpValue"; 474 let ParserMatchClass = RegListAsmOperand; 475 let PrintMethod = "printRegisterList"; 476 let DecoderMethod = "DecodeRegListOperand"; 477} 478 479// A list of general purpose registers and APSR separated by comma. 480// Used by CLRM 481def RegListWithAPSRAsmOperand : AsmOperandClass { let Name = "RegListWithAPSR"; } 482def reglist_with_apsr : Operand<i32> { 483 let EncoderMethod = "getRegisterListOpValue"; 484 let ParserMatchClass = RegListWithAPSRAsmOperand; 485 let PrintMethod = "printRegisterList"; 486 let DecoderMethod = "DecodeRegListOperand"; 487} 488 489def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">; 490 491def DPRRegListAsmOperand : AsmOperandClass { 492 let Name = "DPRRegList"; 493 let DiagnosticType = "DPR_RegList"; 494} 495def dpr_reglist : Operand<i32> { 496 let EncoderMethod = "getRegisterListOpValue"; 497 let ParserMatchClass = DPRRegListAsmOperand; 498 let PrintMethod = "printRegisterList"; 499 let DecoderMethod = "DecodeDPRRegListOperand"; 500} 501 502def SPRRegListAsmOperand : AsmOperandClass { 503 let Name = "SPRRegList"; 504 let DiagnosticString = "operand must be a list of registers in range [s0, s31]"; 505} 506def spr_reglist : Operand<i32> { 507 let EncoderMethod = "getRegisterListOpValue"; 508 let ParserMatchClass = SPRRegListAsmOperand; 509 let PrintMethod = "printRegisterList"; 510 let DecoderMethod = "DecodeSPRRegListOperand"; 511} 512 513def FPSRegListWithVPRAsmOperand : AsmOperandClass { let Name = 514 "FPSRegListWithVPR"; } 515def fp_sreglist_with_vpr : Operand<i32> { 516 let EncoderMethod = "getRegisterListOpValue"; 517 let ParserMatchClass = FPSRegListWithVPRAsmOperand; 518 let PrintMethod = "printRegisterList"; 519} 520def FPDRegListWithVPRAsmOperand : AsmOperandClass { let Name = 521 "FPDRegListWithVPR"; } 522def fp_dreglist_with_vpr : Operand<i32> { 523 let EncoderMethod = "getRegisterListOpValue"; 524 let ParserMatchClass = FPDRegListWithVPRAsmOperand; 525 let PrintMethod = "printRegisterList"; 526} 527 528// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 529def cpinst_operand : Operand<i32> { 530 let PrintMethod = "printCPInstOperand"; 531} 532 533// Local PC labels. 534def pclabel : Operand<i32> { 535 let PrintMethod = "printPCLabel"; 536} 537 538// ADR instruction labels. 539def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; } 540def adrlabel : Operand<i32> { 541 let EncoderMethod = "getAdrLabelOpValue"; 542 let ParserMatchClass = AdrLabelAsmOperand; 543 let PrintMethod = "printAdrLabelOperand<0>"; 544} 545 546def neon_vcvt_imm32 : Operand<i32> { 547 let EncoderMethod = "getNEONVcvtImm32OpValue"; 548 let DecoderMethod = "DecodeVCVTImmOperand"; 549} 550 551// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. 552def rot_imm_XFORM: SDNodeXForm<imm, [{ 553 switch (N->getZExtValue()){ 554 default: llvm_unreachable(nullptr); 555 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); 556 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32); 557 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32); 558 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32); 559 } 560}]>; 561def RotImmAsmOperand : AsmOperandClass { 562 let Name = "RotImm"; 563 let ParserMethod = "parseRotImm"; 564} 565def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{ 566 int32_t v = N->getZExtValue(); 567 return v == 8 || v == 16 || v == 24; }], 568 rot_imm_XFORM> { 569 let PrintMethod = "printRotImmOperand"; 570 let ParserMatchClass = RotImmAsmOperand; 571} 572 573// Power-of-two operand for MVE VIDUP and friends, which encode 574// {1,2,4,8} as its log to base 2, i.e. as {0,1,2,3} respectively 575def MVE_VIDUP_imm_asmoperand : AsmOperandClass { 576 let Name = "VIDUP_imm"; 577 let PredicateMethod = "isPowerTwoInRange<1,8>"; 578 let RenderMethod = "addPowerTwoOperands"; 579 let DiagnosticString = "vector increment immediate must be 1, 2, 4 or 8"; 580} 581def MVE_VIDUP_imm : Operand<i32> { 582 let EncoderMethod = "getPowerTwoOpValue"; 583 let DecoderMethod = "DecodePowerTwoOperand<0,3>"; 584 let ParserMatchClass = MVE_VIDUP_imm_asmoperand; 585} 586 587// Pair vector indexing 588class MVEPairVectorIndexOperand<string start, string end> : AsmOperandClass { 589 let Name = "MVEPairVectorIndex"#start; 590 let RenderMethod = "addMVEPairVectorIndexOperands"; 591 let PredicateMethod = "isMVEPairVectorIndex<"#start#", "#end#">"; 592} 593 594class MVEPairVectorIndex<string opval> : Operand<i32> { 595 let PrintMethod = "printVectorIndex"; 596 let EncoderMethod = "getMVEPairVectorIndexOpValue<"#opval#">"; 597 let DecoderMethod = "DecodeMVEPairVectorIndexOperand<"#opval#">"; 598 let MIOperandInfo = (ops i32imm); 599} 600 601def MVEPairVectorIndex0 : MVEPairVectorIndex<"0"> { 602 let ParserMatchClass = MVEPairVectorIndexOperand<"0", "1">; 603} 604 605def MVEPairVectorIndex2 : MVEPairVectorIndex<"2"> { 606 let ParserMatchClass = MVEPairVectorIndexOperand<"2", "3">; 607} 608 609// Vector indexing 610class MVEVectorIndexOperand<int NumLanes> : AsmOperandClass { 611 let Name = "MVEVectorIndex"#NumLanes; 612 let RenderMethod = "addMVEVectorIndexOperands"; 613 let PredicateMethod = "isVectorIndexInRange<"#NumLanes#">"; 614} 615 616class MVEVectorIndex<int NumLanes> : Operand<i32> { 617 let PrintMethod = "printVectorIndex"; 618 let ParserMatchClass = MVEVectorIndexOperand<NumLanes>; 619 let MIOperandInfo = (ops i32imm); 620} 621 622// shift_imm: An integer that encodes a shift amount and the type of shift 623// (asr or lsl). The 6-bit immediate encodes as: 624// {5} 0 ==> lsl 625// 1 asr 626// {4-0} imm5 shift amount. 627// asr #32 encoded as imm5 == 0. 628def ShifterImmAsmOperand : AsmOperandClass { 629 let Name = "ShifterImm"; 630 let ParserMethod = "parseShifterImm"; 631} 632def shift_imm : Operand<i32> { 633 let PrintMethod = "printShiftImmOperand"; 634 let ParserMatchClass = ShifterImmAsmOperand; 635} 636 637// shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm. 638def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; } 639def so_reg_reg : Operand<i32>, // reg reg imm 640 ComplexPattern<i32, 3, "SelectRegShifterOperand", 641 [shl, srl, sra, rotr]> { 642 let EncoderMethod = "getSORegRegOpValue"; 643 let PrintMethod = "printSORegRegOperand"; 644 let DecoderMethod = "DecodeSORegRegOperand"; 645 let ParserMatchClass = ShiftedRegAsmOperand; 646 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm); 647} 648 649def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; } 650def so_reg_imm : Operand<i32>, // reg imm 651 ComplexPattern<i32, 2, "SelectImmShifterOperand", 652 [shl, srl, sra, rotr]> { 653 let EncoderMethod = "getSORegImmOpValue"; 654 let PrintMethod = "printSORegImmOperand"; 655 let DecoderMethod = "DecodeSORegImmOperand"; 656 let ParserMatchClass = ShiftedImmAsmOperand; 657 let MIOperandInfo = (ops GPR, i32imm); 658} 659 660// FIXME: Does this need to be distinct from so_reg? 661def shift_so_reg_reg : Operand<i32>, // reg reg imm 662 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand", 663 [shl,srl,sra,rotr]> { 664 let EncoderMethod = "getSORegRegOpValue"; 665 let PrintMethod = "printSORegRegOperand"; 666 let DecoderMethod = "DecodeSORegRegOperand"; 667 let ParserMatchClass = ShiftedRegAsmOperand; 668 let MIOperandInfo = (ops GPR, GPR, i32imm); 669} 670 671// FIXME: Does this need to be distinct from so_reg? 672def shift_so_reg_imm : Operand<i32>, // reg reg imm 673 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand", 674 [shl,srl,sra,rotr]> { 675 let EncoderMethod = "getSORegImmOpValue"; 676 let PrintMethod = "printSORegImmOperand"; 677 let DecoderMethod = "DecodeSORegImmOperand"; 678 let ParserMatchClass = ShiftedImmAsmOperand; 679 let MIOperandInfo = (ops GPR, i32imm); 680} 681 682// mod_imm: match a 32-bit immediate operand, which can be encoded into 683// a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM 684// - "Modified Immediate Constants"). Within the MC layer we keep this 685// immediate in its encoded form. 686def ModImmAsmOperand: AsmOperandClass { 687 let Name = "ModImm"; 688 let ParserMethod = "parseModImm"; 689} 690def mod_imm : Operand<i32>, ImmLeaf<i32, [{ 691 return ARM_AM::getSOImmVal(Imm) != -1; 692 }]> { 693 let EncoderMethod = "getModImmOpValue"; 694 let PrintMethod = "printModImmOperand"; 695 let ParserMatchClass = ModImmAsmOperand; 696} 697 698// Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder 699// method and such, as they are only used on aliases (Pat<> and InstAlias<>). 700// The actual parsing, encoding, decoding are handled by the destination 701// instructions, which use mod_imm. 702 703def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; } 704def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{ 705 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1; 706 }], imm_not_XFORM> { 707 let ParserMatchClass = ModImmNotAsmOperand; 708} 709 710def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; } 711def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{ 712 unsigned Value = -(unsigned)N->getZExtValue(); 713 return Value && ARM_AM::getSOImmVal(Value) != -1; 714 }], imm_neg_XFORM> { 715 let ParserMatchClass = ModImmNegAsmOperand; 716} 717 718/// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal() 719def arm_i32imm : IntImmLeaf<i32, [{ 720 if (Subtarget->useMovt()) 721 return true; 722 return ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue()); 723}]>; 724 725/// imm0_1 predicate - Immediate in the range [0,1]. 726def Imm0_1AsmOperand: ImmAsmOperand<0,1> { let Name = "Imm0_1"; } 727def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; } 728 729/// imm0_3 predicate - Immediate in the range [0,3]. 730def Imm0_3AsmOperand: ImmAsmOperand<0,3> { let Name = "Imm0_3"; } 731def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; } 732 733/// imm0_7 predicate - Immediate in the range [0,7]. 734def Imm0_7AsmOperand: ImmAsmOperand<0,7> { 735 let Name = "Imm0_7"; 736} 737def imm0_7 : Operand<i32>, ImmLeaf<i32, [{ 738 return Imm >= 0 && Imm < 8; 739}]> { 740 let ParserMatchClass = Imm0_7AsmOperand; 741} 742 743/// imm8_255 predicate - Immediate in the range [8,255]. 744def Imm8_255AsmOperand: ImmAsmOperand<8,255> { let Name = "Imm8_255"; } 745def imm8_255 : Operand<i32>, ImmLeaf<i32, [{ 746 return Imm >= 8 && Imm < 256; 747}]> { 748 let ParserMatchClass = Imm8_255AsmOperand; 749} 750 751/// imm8 predicate - Immediate is exactly 8. 752def Imm8AsmOperand: ImmAsmOperand<8,8> { let Name = "Imm8"; } 753def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> { 754 let ParserMatchClass = Imm8AsmOperand; 755} 756 757/// imm16 predicate - Immediate is exactly 16. 758def Imm16AsmOperand: ImmAsmOperand<16,16> { let Name = "Imm16"; } 759def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> { 760 let ParserMatchClass = Imm16AsmOperand; 761} 762 763/// imm32 predicate - Immediate is exactly 32. 764def Imm32AsmOperand: ImmAsmOperand<32,32> { let Name = "Imm32"; } 765def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> { 766 let ParserMatchClass = Imm32AsmOperand; 767} 768 769def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>; 770 771/// imm1_7 predicate - Immediate in the range [1,7]. 772def Imm1_7AsmOperand: ImmAsmOperand<1,7> { let Name = "Imm1_7"; } 773def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> { 774 let ParserMatchClass = Imm1_7AsmOperand; 775} 776 777/// imm1_15 predicate - Immediate in the range [1,15]. 778def Imm1_15AsmOperand: ImmAsmOperand<1,15> { let Name = "Imm1_15"; } 779def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> { 780 let ParserMatchClass = Imm1_15AsmOperand; 781} 782 783/// imm1_31 predicate - Immediate in the range [1,31]. 784def Imm1_31AsmOperand: ImmAsmOperand<1,31> { let Name = "Imm1_31"; } 785def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> { 786 let ParserMatchClass = Imm1_31AsmOperand; 787} 788 789/// imm0_15 predicate - Immediate in the range [0,15]. 790def Imm0_15AsmOperand: ImmAsmOperand<0,15> { 791 let Name = "Imm0_15"; 792} 793def imm0_15 : Operand<i32>, ImmLeaf<i32, [{ 794 return Imm >= 0 && Imm < 16; 795}]> { 796 let ParserMatchClass = Imm0_15AsmOperand; 797} 798 799/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31]. 800def Imm0_31AsmOperand: ImmAsmOperand<0,31> { let Name = "Imm0_31"; } 801def imm0_31 : Operand<i32>, ImmLeaf<i32, [{ 802 return Imm >= 0 && Imm < 32; 803}]> { 804 let ParserMatchClass = Imm0_31AsmOperand; 805} 806 807/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32]. 808def Imm0_32AsmOperand: ImmAsmOperand<0,32> { let Name = "Imm0_32"; } 809def imm0_32 : Operand<i32>, ImmLeaf<i32, [{ 810 return Imm >= 0 && Imm < 33; 811}]> { 812 let ParserMatchClass = Imm0_32AsmOperand; 813} 814 815/// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63]. 816def Imm0_63AsmOperand: ImmAsmOperand<0,63> { let Name = "Imm0_63"; } 817def imm0_63 : Operand<i32>, ImmLeaf<i32, [{ 818 return Imm >= 0 && Imm < 64; 819}]> { 820 let ParserMatchClass = Imm0_63AsmOperand; 821} 822 823/// imm0_239 predicate - Immediate in the range [0,239]. 824def Imm0_239AsmOperand : ImmAsmOperand<0,239> { 825 let Name = "Imm0_239"; 826} 827def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> { 828 let ParserMatchClass = Imm0_239AsmOperand; 829} 830 831/// imm0_255 predicate - Immediate in the range [0,255]. 832def Imm0_255AsmOperand : ImmAsmOperand<0,255> { let Name = "Imm0_255"; } 833def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> { 834 let ParserMatchClass = Imm0_255AsmOperand; 835} 836 837/// imm0_65535 - An immediate is in the range [0,65535]. 838def Imm0_65535AsmOperand: ImmAsmOperand<0,65535> { let Name = "Imm0_65535"; } 839def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{ 840 return Imm >= 0 && Imm < 65536; 841}]> { 842 let ParserMatchClass = Imm0_65535AsmOperand; 843} 844 845// imm0_65535_neg - An immediate whose negative value is in the range [0.65535]. 846def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{ 847 return -Imm >= 0 && -Imm < 65536; 848}]>; 849 850// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference 851// a relocatable expression. 852// 853// FIXME: This really needs a Thumb version separate from the ARM version. 854// While the range is the same, and can thus use the same match class, 855// the encoding is different so it should have a different encoder method. 856def Imm0_65535ExprAsmOperand: AsmOperandClass { 857 let Name = "Imm0_65535Expr"; 858 let RenderMethod = "addImmOperands"; 859 let DiagnosticString = "operand must be an immediate in the range [0,0xffff] or a relocatable expression"; 860} 861 862def imm0_65535_expr : Operand<i32> { 863 let EncoderMethod = "getHiLo16ImmOpValue"; 864 let ParserMatchClass = Imm0_65535ExprAsmOperand; 865} 866 867def Imm256_65535ExprAsmOperand: ImmAsmOperand<256,65535> { let Name = "Imm256_65535Expr"; } 868def imm256_65535_expr : Operand<i32> { 869 let ParserMatchClass = Imm256_65535ExprAsmOperand; 870} 871 872/// imm24b - True if the 32-bit immediate is encodable in 24 bits. 873def Imm24bitAsmOperand: ImmAsmOperand<0,0xffffff> { 874 let Name = "Imm24bit"; 875 let DiagnosticString = "operand must be an immediate in the range [0,0xffffff]"; 876} 877def imm24b : Operand<i32>, ImmLeaf<i32, [{ 878 return Imm >= 0 && Imm <= 0xffffff; 879}]> { 880 let ParserMatchClass = Imm24bitAsmOperand; 881} 882 883 884/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield 885/// e.g., 0xf000ffff 886def BitfieldAsmOperand : AsmOperandClass { 887 let Name = "Bitfield"; 888 let ParserMethod = "parseBitfield"; 889} 890 891def bf_inv_mask_imm : Operand<i32>, 892 PatLeaf<(imm), [{ 893 return ARM::isBitFieldInvertedMask(N->getZExtValue()); 894}] > { 895 let EncoderMethod = "getBitfieldInvertedMaskOpValue"; 896 let PrintMethod = "printBitfieldInvMaskImmOperand"; 897 let DecoderMethod = "DecodeBitfieldMaskOperand"; 898 let ParserMatchClass = BitfieldAsmOperand; 899 let GISelPredicateCode = [{ 900 // There's better methods of implementing this check. IntImmLeaf<> would be 901 // equivalent and have less boilerplate but we need a test for C++ 902 // predicates and this one causes new rules to be imported into GlobalISel 903 // without requiring additional features first. 904 const auto &MO = MI.getOperand(1); 905 if (!MO.isCImm()) 906 return false; 907 return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue()); 908 }]; 909} 910 911def imm1_32_XFORM: SDNodeXForm<imm, [{ 912 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 913 MVT::i32); 914}]>; 915def Imm1_32AsmOperand: ImmAsmOperandMinusOne<1,32> { 916 let Name = "Imm1_32"; 917} 918def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ 919 uint64_t Imm = N->getZExtValue(); 920 return Imm > 0 && Imm <= 32; 921 }], 922 imm1_32_XFORM> { 923 let PrintMethod = "printImmPlusOneOperand"; 924 let ParserMatchClass = Imm1_32AsmOperand; 925} 926 927def imm1_16_XFORM: SDNodeXForm<imm, [{ 928 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 929 MVT::i32); 930}]>; 931def Imm1_16AsmOperand: ImmAsmOperandMinusOne<1,16> { let Name = "Imm1_16"; } 932def imm1_16 : Operand<i32>, ImmLeaf<i32, [{ 933 return Imm > 0 && Imm <= 16; 934 }], 935 imm1_16_XFORM> { 936 let PrintMethod = "printImmPlusOneOperand"; 937 let ParserMatchClass = Imm1_16AsmOperand; 938} 939 940def MVEShiftImm1_7AsmOperand: ImmAsmOperand<1,7> { 941 let Name = "MVEShiftImm1_7"; 942 // Reason we're doing this is because instruction vshll.s8 t1 encoding 943 // accepts 1,7 but the t2 encoding accepts 8. By doing this we can get a 944 // better diagnostic message if someone uses bigger immediate than the t1/t2 945 // encodings allow. 946 let DiagnosticString = "operand must be an immediate in the range [1,8]"; 947} 948def mve_shift_imm1_7 : Operand<i32>, 949 // SelectImmediateInRange / isScaledConstantInRange uses a 950 // half-open interval, so the parameters <1,8> mean 1-7 inclusive 951 ComplexPattern<i32, 1, "SelectImmediateInRange<1,8>", [], []> { 952 let ParserMatchClass = MVEShiftImm1_7AsmOperand; 953 let EncoderMethod = "getMVEShiftImmOpValue"; 954} 955 956def MVEShiftImm1_15AsmOperand: ImmAsmOperand<1,15> { 957 let Name = "MVEShiftImm1_15"; 958 // Reason we're doing this is because instruction vshll.s16 t1 encoding 959 // accepts 1,15 but the t2 encoding accepts 16. By doing this we can get a 960 // better diagnostic message if someone uses bigger immediate than the t1/t2 961 // encodings allow. 962 let DiagnosticString = "operand must be an immediate in the range [1,16]"; 963} 964def mve_shift_imm1_15 : Operand<i32>, 965 // SelectImmediateInRange / isScaledConstantInRange uses a 966 // half-open interval, so the parameters <1,16> mean 1-15 inclusive 967 ComplexPattern<i32, 1, "SelectImmediateInRange<1,16>", [], []> { 968 let ParserMatchClass = MVEShiftImm1_15AsmOperand; 969 let EncoderMethod = "getMVEShiftImmOpValue"; 970} 971 972// Define ARM specific addressing modes. 973// addrmode_imm12 := reg +/- imm12 974// 975def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; } 976class AddrMode_Imm12 : MemOperand, 977 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> { 978 // 12-bit immediate operand. Note that instructions using this encode 979 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other 980 // immediate values are as normal. 981 982 let EncoderMethod = "getAddrModeImm12OpValue"; 983 let DecoderMethod = "DecodeAddrModeImm12Operand"; 984 let ParserMatchClass = MemImm12OffsetAsmOperand; 985 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 986} 987 988def addrmode_imm12 : AddrMode_Imm12 { 989 let PrintMethod = "printAddrModeImm12Operand<false>"; 990} 991 992def addrmode_imm12_pre : AddrMode_Imm12 { 993 let PrintMethod = "printAddrModeImm12Operand<true>"; 994} 995 996// ldst_so_reg := reg +/- reg shop imm 997// 998def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; } 999def ldst_so_reg : MemOperand, 1000 ComplexPattern<i32, 3, "SelectLdStSOReg", []> { 1001 let EncoderMethod = "getLdStSORegOpValue"; 1002 // FIXME: Simplify the printer 1003 let PrintMethod = "printAddrMode2Operand"; 1004 let DecoderMethod = "DecodeSORegMemOperand"; 1005 let ParserMatchClass = MemRegOffsetAsmOperand; 1006 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift); 1007} 1008 1009// postidx_imm8 := +/- [0,255] 1010// 1011// 9 bit value: 1012// {8} 1 is imm8 is non-negative. 0 otherwise. 1013// {7-0} [0,255] imm8 value. 1014def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; } 1015def postidx_imm8 : MemOperand { 1016 let PrintMethod = "printPostIdxImm8Operand"; 1017 let ParserMatchClass = PostIdxImm8AsmOperand; 1018 let MIOperandInfo = (ops i32imm); 1019} 1020 1021// postidx_imm8s4 := +/- [0,1020] 1022// 1023// 9 bit value: 1024// {8} 1 is imm8 is non-negative. 0 otherwise. 1025// {7-0} [0,255] imm8 value, scaled by 4. 1026def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; } 1027def postidx_imm8s4 : MemOperand { 1028 let PrintMethod = "printPostIdxImm8s4Operand"; 1029 let ParserMatchClass = PostIdxImm8s4AsmOperand; 1030 let MIOperandInfo = (ops i32imm); 1031} 1032 1033 1034// postidx_reg := +/- reg 1035// 1036def PostIdxRegAsmOperand : AsmOperandClass { 1037 let Name = "PostIdxReg"; 1038 let ParserMethod = "parsePostIdxReg"; 1039} 1040def postidx_reg : MemOperand { 1041 let EncoderMethod = "getPostIdxRegOpValue"; 1042 let DecoderMethod = "DecodePostIdxReg"; 1043 let PrintMethod = "printPostIdxRegOperand"; 1044 let ParserMatchClass = PostIdxRegAsmOperand; 1045 let MIOperandInfo = (ops GPRnopc, i32imm); 1046} 1047 1048def PostIdxRegShiftedAsmOperand : AsmOperandClass { 1049 let Name = "PostIdxRegShifted"; 1050 let ParserMethod = "parsePostIdxReg"; 1051} 1052def am2offset_reg : MemOperand, 1053 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg", 1054 [], [SDNPWantRoot]> { 1055 let EncoderMethod = "getAddrMode2OffsetOpValue"; 1056 let PrintMethod = "printAddrMode2OffsetOperand"; 1057 // When using this for assembly, it's always as a post-index offset. 1058 let ParserMatchClass = PostIdxRegShiftedAsmOperand; 1059 let MIOperandInfo = (ops GPRnopc, i32imm); 1060} 1061 1062// FIXME: am2offset_imm should only need the immediate, not the GPR. Having 1063// the GPR is purely vestigal at this point. 1064def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; } 1065def am2offset_imm : MemOperand, 1066 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm", 1067 [], [SDNPWantRoot]> { 1068 let EncoderMethod = "getAddrMode2OffsetOpValue"; 1069 let PrintMethod = "printAddrMode2OffsetOperand"; 1070 let ParserMatchClass = AM2OffsetImmAsmOperand; 1071 let MIOperandInfo = (ops GPRnopc, i32imm); 1072} 1073 1074 1075// addrmode3 := reg +/- reg 1076// addrmode3 := reg +/- imm8 1077// 1078// FIXME: split into imm vs. reg versions. 1079def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; } 1080class AddrMode3 : MemOperand, 1081 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 1082 let EncoderMethod = "getAddrMode3OpValue"; 1083 let ParserMatchClass = AddrMode3AsmOperand; 1084 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 1085} 1086 1087def addrmode3 : AddrMode3 1088{ 1089 let PrintMethod = "printAddrMode3Operand<false>"; 1090} 1091 1092def addrmode3_pre : AddrMode3 1093{ 1094 let PrintMethod = "printAddrMode3Operand<true>"; 1095} 1096 1097// FIXME: split into imm vs. reg versions. 1098// FIXME: parser method to handle +/- register. 1099def AM3OffsetAsmOperand : AsmOperandClass { 1100 let Name = "AM3Offset"; 1101 let ParserMethod = "parseAM3Offset"; 1102} 1103def am3offset : MemOperand, 1104 ComplexPattern<i32, 2, "SelectAddrMode3Offset", 1105 [], [SDNPWantRoot]> { 1106 let EncoderMethod = "getAddrMode3OffsetOpValue"; 1107 let PrintMethod = "printAddrMode3OffsetOperand"; 1108 let ParserMatchClass = AM3OffsetAsmOperand; 1109 let MIOperandInfo = (ops GPR, i32imm); 1110} 1111 1112// ldstm_mode := {ia, ib, da, db} 1113// 1114def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> { 1115 let EncoderMethod = "getLdStmModeOpValue"; 1116 let PrintMethod = "printLdStmModeOperand"; 1117} 1118 1119// addrmode5 := reg +/- imm8*4 1120// 1121def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; } 1122class AddrMode5 : MemOperand, 1123 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 1124 let EncoderMethod = "getAddrMode5OpValue"; 1125 let DecoderMethod = "DecodeAddrMode5Operand"; 1126 let ParserMatchClass = AddrMode5AsmOperand; 1127 let MIOperandInfo = (ops GPR:$base, i32imm); 1128} 1129 1130def addrmode5 : AddrMode5 { 1131 let PrintMethod = "printAddrMode5Operand<false>"; 1132} 1133 1134def addrmode5_pre : AddrMode5 { 1135 let PrintMethod = "printAddrMode5Operand<true>"; 1136} 1137 1138// addrmode5fp16 := reg +/- imm8*2 1139// 1140def AddrMode5FP16AsmOperand : AsmOperandClass { let Name = "AddrMode5FP16"; } 1141class AddrMode5FP16 : Operand<i32>, 1142 ComplexPattern<i32, 2, "SelectAddrMode5FP16", []> { 1143 let EncoderMethod = "getAddrMode5FP16OpValue"; 1144 let DecoderMethod = "DecodeAddrMode5FP16Operand"; 1145 let ParserMatchClass = AddrMode5FP16AsmOperand; 1146 let MIOperandInfo = (ops GPR:$base, i32imm); 1147} 1148 1149def addrmode5fp16 : AddrMode5FP16 { 1150 let PrintMethod = "printAddrMode5FP16Operand<false>"; 1151} 1152 1153// addrmode6 := reg with optional alignment 1154// 1155def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; } 1156def addrmode6 : MemOperand, 1157 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1158 let PrintMethod = "printAddrMode6Operand"; 1159 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1160 let EncoderMethod = "getAddrMode6AddressOpValue"; 1161 let DecoderMethod = "DecodeAddrMode6Operand"; 1162 let ParserMatchClass = AddrMode6AsmOperand; 1163} 1164 1165def am6offset : MemOperand, 1166 ComplexPattern<i32, 1, "SelectAddrMode6Offset", 1167 [], [SDNPWantRoot]> { 1168 let PrintMethod = "printAddrMode6OffsetOperand"; 1169 let MIOperandInfo = (ops GPR); 1170 let EncoderMethod = "getAddrMode6OffsetOpValue"; 1171 let DecoderMethod = "DecodeGPRRegisterClass"; 1172} 1173 1174// Special version of addrmode6 to handle alignment encoding for VST1/VLD1 1175// (single element from one lane) for size 32. 1176def addrmode6oneL32 : MemOperand, 1177 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1178 let PrintMethod = "printAddrMode6Operand"; 1179 let MIOperandInfo = (ops GPR:$addr, i32imm); 1180 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue"; 1181} 1182 1183// Base class for addrmode6 with specific alignment restrictions. 1184class AddrMode6Align : MemOperand, 1185 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1186 let PrintMethod = "printAddrMode6Operand"; 1187 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1188 let EncoderMethod = "getAddrMode6AddressOpValue"; 1189 let DecoderMethod = "DecodeAddrMode6Operand"; 1190} 1191 1192// Special version of addrmode6 to handle no allowed alignment encoding for 1193// VLD/VST instructions and checking the alignment is not specified. 1194def AddrMode6AlignNoneAsmOperand : AsmOperandClass { 1195 let Name = "AlignedMemoryNone"; 1196 let DiagnosticString = "alignment must be omitted"; 1197} 1198def addrmode6alignNone : AddrMode6Align { 1199 // The alignment specifier can only be omitted. 1200 let ParserMatchClass = AddrMode6AlignNoneAsmOperand; 1201} 1202 1203// Special version of addrmode6 to handle 16-bit alignment encoding for 1204// VLD/VST instructions and checking the alignment value. 1205def AddrMode6Align16AsmOperand : AsmOperandClass { 1206 let Name = "AlignedMemory16"; 1207 let DiagnosticString = "alignment must be 16 or omitted"; 1208} 1209def addrmode6align16 : AddrMode6Align { 1210 // The alignment specifier can only be 16 or omitted. 1211 let ParserMatchClass = AddrMode6Align16AsmOperand; 1212} 1213 1214// Special version of addrmode6 to handle 32-bit alignment encoding for 1215// VLD/VST instructions and checking the alignment value. 1216def AddrMode6Align32AsmOperand : AsmOperandClass { 1217 let Name = "AlignedMemory32"; 1218 let DiagnosticString = "alignment must be 32 or omitted"; 1219} 1220def addrmode6align32 : AddrMode6Align { 1221 // The alignment specifier can only be 32 or omitted. 1222 let ParserMatchClass = AddrMode6Align32AsmOperand; 1223} 1224 1225// Special version of addrmode6 to handle 64-bit alignment encoding for 1226// VLD/VST instructions and checking the alignment value. 1227def AddrMode6Align64AsmOperand : AsmOperandClass { 1228 let Name = "AlignedMemory64"; 1229 let DiagnosticString = "alignment must be 64 or omitted"; 1230} 1231def addrmode6align64 : AddrMode6Align { 1232 // The alignment specifier can only be 64 or omitted. 1233 let ParserMatchClass = AddrMode6Align64AsmOperand; 1234} 1235 1236// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1237// for VLD/VST instructions and checking the alignment value. 1238def AddrMode6Align64or128AsmOperand : AsmOperandClass { 1239 let Name = "AlignedMemory64or128"; 1240 let DiagnosticString = "alignment must be 64, 128 or omitted"; 1241} 1242def addrmode6align64or128 : AddrMode6Align { 1243 // The alignment specifier can only be 64, 128 or omitted. 1244 let ParserMatchClass = AddrMode6Align64or128AsmOperand; 1245} 1246 1247// Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment 1248// encoding for VLD/VST instructions and checking the alignment value. 1249def AddrMode6Align64or128or256AsmOperand : AsmOperandClass { 1250 let Name = "AlignedMemory64or128or256"; 1251 let DiagnosticString = "alignment must be 64, 128, 256 or omitted"; 1252} 1253def addrmode6align64or128or256 : AddrMode6Align { 1254 // The alignment specifier can only be 64, 128, 256 or omitted. 1255 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand; 1256} 1257 1258// Special version of addrmode6 to handle alignment encoding for VLD-dup 1259// instructions, specifically VLD4-dup. 1260def addrmode6dup : MemOperand, 1261 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1262 let PrintMethod = "printAddrMode6Operand"; 1263 let MIOperandInfo = (ops GPR:$addr, i32imm); 1264 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1265 // FIXME: This is close, but not quite right. The alignment specifier is 1266 // different. 1267 let ParserMatchClass = AddrMode6AsmOperand; 1268} 1269 1270// Base class for addrmode6dup with specific alignment restrictions. 1271class AddrMode6DupAlign : MemOperand, 1272 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1273 let PrintMethod = "printAddrMode6Operand"; 1274 let MIOperandInfo = (ops GPR:$addr, i32imm); 1275 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1276} 1277 1278// Special version of addrmode6 to handle no allowed alignment encoding for 1279// VLD-dup instruction and checking the alignment is not specified. 1280def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass { 1281 let Name = "DupAlignedMemoryNone"; 1282 let DiagnosticString = "alignment must be omitted"; 1283} 1284def addrmode6dupalignNone : AddrMode6DupAlign { 1285 // The alignment specifier can only be omitted. 1286 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand; 1287} 1288 1289// Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup 1290// instruction and checking the alignment value. 1291def AddrMode6dupAlign16AsmOperand : AsmOperandClass { 1292 let Name = "DupAlignedMemory16"; 1293 let DiagnosticString = "alignment must be 16 or omitted"; 1294} 1295def addrmode6dupalign16 : AddrMode6DupAlign { 1296 // The alignment specifier can only be 16 or omitted. 1297 let ParserMatchClass = AddrMode6dupAlign16AsmOperand; 1298} 1299 1300// Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup 1301// instruction and checking the alignment value. 1302def AddrMode6dupAlign32AsmOperand : AsmOperandClass { 1303 let Name = "DupAlignedMemory32"; 1304 let DiagnosticString = "alignment must be 32 or omitted"; 1305} 1306def addrmode6dupalign32 : AddrMode6DupAlign { 1307 // The alignment specifier can only be 32 or omitted. 1308 let ParserMatchClass = AddrMode6dupAlign32AsmOperand; 1309} 1310 1311// Special version of addrmode6 to handle 64-bit alignment encoding for VLD 1312// instructions and checking the alignment value. 1313def AddrMode6dupAlign64AsmOperand : AsmOperandClass { 1314 let Name = "DupAlignedMemory64"; 1315 let DiagnosticString = "alignment must be 64 or omitted"; 1316} 1317def addrmode6dupalign64 : AddrMode6DupAlign { 1318 // The alignment specifier can only be 64 or omitted. 1319 let ParserMatchClass = AddrMode6dupAlign64AsmOperand; 1320} 1321 1322// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1323// for VLD instructions and checking the alignment value. 1324def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass { 1325 let Name = "DupAlignedMemory64or128"; 1326 let DiagnosticString = "alignment must be 64, 128 or omitted"; 1327} 1328def addrmode6dupalign64or128 : AddrMode6DupAlign { 1329 // The alignment specifier can only be 64, 128 or omitted. 1330 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand; 1331} 1332 1333// addrmodepc := pc + reg 1334// 1335def addrmodepc : MemOperand, 1336 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 1337 let PrintMethod = "printAddrModePCOperand"; 1338 let MIOperandInfo = (ops GPR, i32imm); 1339} 1340 1341// addr_offset_none := reg 1342// 1343def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; } 1344def addr_offset_none : MemOperand, 1345 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> { 1346 let PrintMethod = "printAddrMode7Operand"; 1347 let DecoderMethod = "DecodeAddrMode7Operand"; 1348 let ParserMatchClass = MemNoOffsetAsmOperand; 1349 let MIOperandInfo = (ops GPR:$base); 1350} 1351 1352// t_addr_offset_none := reg [r0-r7] 1353def MemNoOffsetTAsmOperand : AsmOperandClass { let Name = "MemNoOffsetT"; } 1354def t_addr_offset_none : MemOperand { 1355 let PrintMethod = "printAddrMode7Operand"; 1356 let DecoderMethod = "DecodetGPRRegisterClass"; 1357 let ParserMatchClass = MemNoOffsetTAsmOperand; 1358 let MIOperandInfo = (ops tGPR:$base); 1359} 1360 1361def nohash_imm : Operand<i32> { 1362 let PrintMethod = "printNoHashImmediate"; 1363} 1364 1365def CoprocNumAsmOperand : AsmOperandClass { 1366 let Name = "CoprocNum"; 1367 let ParserMethod = "parseCoprocNumOperand"; 1368} 1369def p_imm : Operand<i32> { 1370 let PrintMethod = "printPImmediate"; 1371 let ParserMatchClass = CoprocNumAsmOperand; 1372 let DecoderMethod = "DecodeCoprocessor"; 1373} 1374 1375def CoprocRegAsmOperand : AsmOperandClass { 1376 let Name = "CoprocReg"; 1377 let ParserMethod = "parseCoprocRegOperand"; 1378} 1379def c_imm : Operand<i32> { 1380 let PrintMethod = "printCImmediate"; 1381 let ParserMatchClass = CoprocRegAsmOperand; 1382} 1383def CoprocOptionAsmOperand : AsmOperandClass { 1384 let Name = "CoprocOption"; 1385 let ParserMethod = "parseCoprocOptionOperand"; 1386} 1387def coproc_option_imm : Operand<i32> { 1388 let PrintMethod = "printCoprocOptionImm"; 1389 let ParserMatchClass = CoprocOptionAsmOperand; 1390} 1391 1392//===----------------------------------------------------------------------===// 1393 1394include "ARMInstrFormats.td" 1395 1396//===----------------------------------------------------------------------===// 1397// Multiclass helpers... 1398// 1399 1400/// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a 1401/// binop that produces a value. 1402let TwoOperandAliasConstraint = "$Rn = $Rd" in 1403multiclass AsI1_bin_irs<bits<4> opcod, string opc, 1404 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1405 SDPatternOperator opnode, bit Commutable = 0> { 1406 // The register-immediate version is re-materializable. This is useful 1407 // in particular for taking the address of a local. 1408 let isReMaterializable = 1 in { 1409 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1410 iii, opc, "\t$Rd, $Rn, $imm", 1411 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>, 1412 Sched<[WriteALU, ReadALU]> { 1413 bits<4> Rd; 1414 bits<4> Rn; 1415 bits<12> imm; 1416 let Inst{25} = 1; 1417 let Inst{19-16} = Rn; 1418 let Inst{15-12} = Rd; 1419 let Inst{11-0} = imm; 1420 } 1421 } 1422 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1423 iir, opc, "\t$Rd, $Rn, $Rm", 1424 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, 1425 Sched<[WriteALU, ReadALU, ReadALU]> { 1426 bits<4> Rd; 1427 bits<4> Rn; 1428 bits<4> Rm; 1429 let Inst{25} = 0; 1430 let isCommutable = Commutable; 1431 let Inst{19-16} = Rn; 1432 let Inst{15-12} = Rd; 1433 let Inst{11-4} = 0b00000000; 1434 let Inst{3-0} = Rm; 1435 } 1436 1437 def rsi : AsI1<opcod, (outs GPR:$Rd), 1438 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1439 iis, opc, "\t$Rd, $Rn, $shift", 1440 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>, 1441 Sched<[WriteALUsi, ReadALU]> { 1442 bits<4> Rd; 1443 bits<4> Rn; 1444 bits<12> shift; 1445 let Inst{25} = 0; 1446 let Inst{19-16} = Rn; 1447 let Inst{15-12} = Rd; 1448 let Inst{11-5} = shift{11-5}; 1449 let Inst{4} = 0; 1450 let Inst{3-0} = shift{3-0}; 1451 } 1452 1453 def rsr : AsI1<opcod, (outs GPR:$Rd), 1454 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1455 iis, opc, "\t$Rd, $Rn, $shift", 1456 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>, 1457 Sched<[WriteALUsr, ReadALUsr]> { 1458 bits<4> Rd; 1459 bits<4> Rn; 1460 bits<12> shift; 1461 let Inst{25} = 0; 1462 let Inst{19-16} = Rn; 1463 let Inst{15-12} = Rd; 1464 let Inst{11-8} = shift{11-8}; 1465 let Inst{7} = 0; 1466 let Inst{6-5} = shift{6-5}; 1467 let Inst{4} = 1; 1468 let Inst{3-0} = shift{3-0}; 1469 } 1470} 1471 1472/// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are 1473/// reversed. The 'rr' form is only defined for the disassembler; for codegen 1474/// it is equivalent to the AsI1_bin_irs counterpart. 1475let TwoOperandAliasConstraint = "$Rn = $Rd" in 1476multiclass AsI1_rbin_irs<bits<4> opcod, string opc, 1477 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1478 SDNode opnode, bit Commutable = 0> { 1479 // The register-immediate version is re-materializable. This is useful 1480 // in particular for taking the address of a local. 1481 let isReMaterializable = 1 in { 1482 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1483 iii, opc, "\t$Rd, $Rn, $imm", 1484 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>, 1485 Sched<[WriteALU, ReadALU]> { 1486 bits<4> Rd; 1487 bits<4> Rn; 1488 bits<12> imm; 1489 let Inst{25} = 1; 1490 let Inst{19-16} = Rn; 1491 let Inst{15-12} = Rd; 1492 let Inst{11-0} = imm; 1493 } 1494 } 1495 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1496 iir, opc, "\t$Rd, $Rn, $Rm", 1497 [/* pattern left blank */]>, 1498 Sched<[WriteALU, ReadALU, ReadALU]> { 1499 bits<4> Rd; 1500 bits<4> Rn; 1501 bits<4> Rm; 1502 let Inst{11-4} = 0b00000000; 1503 let Inst{25} = 0; 1504 let Inst{3-0} = Rm; 1505 let Inst{15-12} = Rd; 1506 let Inst{19-16} = Rn; 1507 } 1508 1509 def rsi : AsI1<opcod, (outs GPR:$Rd), 1510 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1511 iis, opc, "\t$Rd, $Rn, $shift", 1512 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>, 1513 Sched<[WriteALUsi, ReadALU]> { 1514 bits<4> Rd; 1515 bits<4> Rn; 1516 bits<12> shift; 1517 let Inst{25} = 0; 1518 let Inst{19-16} = Rn; 1519 let Inst{15-12} = Rd; 1520 let Inst{11-5} = shift{11-5}; 1521 let Inst{4} = 0; 1522 let Inst{3-0} = shift{3-0}; 1523 } 1524 1525 def rsr : AsI1<opcod, (outs GPR:$Rd), 1526 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1527 iis, opc, "\t$Rd, $Rn, $shift", 1528 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>, 1529 Sched<[WriteALUsr, ReadALUsr]> { 1530 bits<4> Rd; 1531 bits<4> Rn; 1532 bits<12> shift; 1533 let Inst{25} = 0; 1534 let Inst{19-16} = Rn; 1535 let Inst{15-12} = Rd; 1536 let Inst{11-8} = shift{11-8}; 1537 let Inst{7} = 0; 1538 let Inst{6-5} = shift{6-5}; 1539 let Inst{4} = 1; 1540 let Inst{3-0} = shift{3-0}; 1541 } 1542} 1543 1544/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default. 1545/// 1546/// These opcodes will be converted to the real non-S opcodes by 1547/// AdjustInstrPostInstrSelection after giving them an optional CPSR operand. 1548let hasPostISelHook = 1, Defs = [CPSR] in { 1549multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir, 1550 InstrItinClass iis, SDNode opnode, 1551 bit Commutable = 0> { 1552 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1553 4, iii, 1554 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>, 1555 Sched<[WriteALU, ReadALU]>; 1556 1557 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p), 1558 4, iir, 1559 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>, 1560 Sched<[WriteALU, ReadALU, ReadALU]> { 1561 let isCommutable = Commutable; 1562 } 1563 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1564 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1565 4, iis, 1566 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1567 so_reg_imm:$shift))]>, 1568 Sched<[WriteALUsi, ReadALU]>; 1569 1570 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1571 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1572 4, iis, 1573 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1574 so_reg_reg:$shift))]>, 1575 Sched<[WriteALUSsr, ReadALUsr]>; 1576} 1577} 1578 1579/// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG 1580/// operands are reversed. 1581let hasPostISelHook = 1, Defs = [CPSR] in { 1582multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir, 1583 InstrItinClass iis, SDNode opnode, 1584 bit Commutable = 0> { 1585 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1586 4, iii, 1587 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>, 1588 Sched<[WriteALU, ReadALU]>; 1589 1590 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1591 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1592 4, iis, 1593 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, 1594 GPR:$Rn))]>, 1595 Sched<[WriteALUsi, ReadALU]>; 1596 1597 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1598 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1599 4, iis, 1600 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, 1601 GPR:$Rn))]>, 1602 Sched<[WriteALUSsr, ReadALUsr]>; 1603} 1604} 1605 1606/// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test 1607/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 1608/// a explicit result, only implicitly set CPSR. 1609let isCompare = 1, Defs = [CPSR] in { 1610multiclass AI1_cmp_irs<bits<4> opcod, string opc, 1611 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1612 SDPatternOperator opnode, bit Commutable = 0, 1613 string rrDecoderMethod = ""> { 1614 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii, 1615 opc, "\t$Rn, $imm", 1616 [(opnode GPR:$Rn, mod_imm:$imm)]>, 1617 Sched<[WriteCMP, ReadALU]> { 1618 bits<4> Rn; 1619 bits<12> imm; 1620 let Inst{25} = 1; 1621 let Inst{20} = 1; 1622 let Inst{19-16} = Rn; 1623 let Inst{15-12} = 0b0000; 1624 let Inst{11-0} = imm; 1625 1626 let Unpredictable{15-12} = 0b1111; 1627 } 1628 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir, 1629 opc, "\t$Rn, $Rm", 1630 [(opnode GPR:$Rn, GPR:$Rm)]>, 1631 Sched<[WriteCMP, ReadALU, ReadALU]> { 1632 bits<4> Rn; 1633 bits<4> Rm; 1634 let isCommutable = Commutable; 1635 let Inst{25} = 0; 1636 let Inst{20} = 1; 1637 let Inst{19-16} = Rn; 1638 let Inst{15-12} = 0b0000; 1639 let Inst{11-4} = 0b00000000; 1640 let Inst{3-0} = Rm; 1641 let DecoderMethod = rrDecoderMethod; 1642 1643 let Unpredictable{15-12} = 0b1111; 1644 } 1645 def rsi : AI1<opcod, (outs), 1646 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis, 1647 opc, "\t$Rn, $shift", 1648 [(opnode GPR:$Rn, so_reg_imm:$shift)]>, 1649 Sched<[WriteCMPsi, ReadALU]> { 1650 bits<4> Rn; 1651 bits<12> shift; 1652 let Inst{25} = 0; 1653 let Inst{20} = 1; 1654 let Inst{19-16} = Rn; 1655 let Inst{15-12} = 0b0000; 1656 let Inst{11-5} = shift{11-5}; 1657 let Inst{4} = 0; 1658 let Inst{3-0} = shift{3-0}; 1659 1660 let Unpredictable{15-12} = 0b1111; 1661 } 1662 def rsr : AI1<opcod, (outs), 1663 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis, 1664 opc, "\t$Rn, $shift", 1665 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>, 1666 Sched<[WriteCMPsr, ReadALU]> { 1667 bits<4> Rn; 1668 bits<12> shift; 1669 let Inst{25} = 0; 1670 let Inst{20} = 1; 1671 let Inst{19-16} = Rn; 1672 let Inst{15-12} = 0b0000; 1673 let Inst{11-8} = shift{11-8}; 1674 let Inst{7} = 0; 1675 let Inst{6-5} = shift{6-5}; 1676 let Inst{4} = 1; 1677 let Inst{3-0} = shift{3-0}; 1678 1679 let Unpredictable{15-12} = 0b1111; 1680 } 1681 1682} 1683} 1684 1685/// AI_ext_rrot - A unary operation with two forms: one whose operand is a 1686/// register and one whose operand is a register rotated by 8/16/24. 1687/// FIXME: Remove the 'r' variant. Its rot_imm is zero. 1688class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> 1689 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1690 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", 1691 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1692 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1693 bits<4> Rd; 1694 bits<4> Rm; 1695 bits<2> rot; 1696 let Inst{19-16} = 0b1111; 1697 let Inst{15-12} = Rd; 1698 let Inst{11-10} = rot; 1699 let Inst{3-0} = Rm; 1700} 1701 1702class AI_ext_rrot_np<bits<8> opcod, string opc> 1703 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1704 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>, 1705 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1706 bits<2> rot; 1707 let Inst{19-16} = 0b1111; 1708 let Inst{11-10} = rot; 1709 } 1710 1711/// AI_exta_rrot - A binary operation with two forms: one whose operand is a 1712/// register and one whose operand is a register rotated by 8/16/24. 1713class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> 1714 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1715 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", 1716 [(set GPRnopc:$Rd, (opnode GPR:$Rn, 1717 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1718 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1719 bits<4> Rd; 1720 bits<4> Rm; 1721 bits<4> Rn; 1722 bits<2> rot; 1723 let Inst{19-16} = Rn; 1724 let Inst{15-12} = Rd; 1725 let Inst{11-10} = rot; 1726 let Inst{9-4} = 0b000111; 1727 let Inst{3-0} = Rm; 1728} 1729 1730class AI_exta_rrot_np<bits<8> opcod, string opc> 1731 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1732 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>, 1733 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1734 bits<4> Rn; 1735 bits<2> rot; 1736 let Inst{19-16} = Rn; 1737 let Inst{11-10} = rot; 1738} 1739 1740/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. 1741let TwoOperandAliasConstraint = "$Rn = $Rd" in 1742multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode, 1743 bit Commutable = 0> { 1744 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1745 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1746 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1747 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>, 1748 Requires<[IsARM]>, 1749 Sched<[WriteALU, ReadALU]> { 1750 bits<4> Rd; 1751 bits<4> Rn; 1752 bits<12> imm; 1753 let Inst{25} = 1; 1754 let Inst{15-12} = Rd; 1755 let Inst{19-16} = Rn; 1756 let Inst{11-0} = imm; 1757 } 1758 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1759 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1760 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>, 1761 Requires<[IsARM]>, 1762 Sched<[WriteALU, ReadALU, ReadALU]> { 1763 bits<4> Rd; 1764 bits<4> Rn; 1765 bits<4> Rm; 1766 let Inst{11-4} = 0b00000000; 1767 let Inst{25} = 0; 1768 let isCommutable = Commutable; 1769 let Inst{3-0} = Rm; 1770 let Inst{15-12} = Rd; 1771 let Inst{19-16} = Rn; 1772 } 1773 def rsi : AsI1<opcod, (outs GPR:$Rd), 1774 (ins GPR:$Rn, so_reg_imm:$shift), 1775 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1776 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>, 1777 Requires<[IsARM]>, 1778 Sched<[WriteALUsi, ReadALU]> { 1779 bits<4> Rd; 1780 bits<4> Rn; 1781 bits<12> shift; 1782 let Inst{25} = 0; 1783 let Inst{19-16} = Rn; 1784 let Inst{15-12} = Rd; 1785 let Inst{11-5} = shift{11-5}; 1786 let Inst{4} = 0; 1787 let Inst{3-0} = shift{3-0}; 1788 } 1789 def rsr : AsI1<opcod, (outs GPRnopc:$Rd), 1790 (ins GPRnopc:$Rn, so_reg_reg:$shift), 1791 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1792 [(set GPRnopc:$Rd, CPSR, 1793 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>, 1794 Requires<[IsARM]>, 1795 Sched<[WriteALUsr, ReadALUsr]> { 1796 bits<4> Rd; 1797 bits<4> Rn; 1798 bits<12> shift; 1799 let Inst{25} = 0; 1800 let Inst{19-16} = Rn; 1801 let Inst{15-12} = Rd; 1802 let Inst{11-8} = shift{11-8}; 1803 let Inst{7} = 0; 1804 let Inst{6-5} = shift{6-5}; 1805 let Inst{4} = 1; 1806 let Inst{3-0} = shift{3-0}; 1807 } 1808 } 1809} 1810 1811/// AI1_rsc_irs - Define instructions and patterns for rsc 1812let TwoOperandAliasConstraint = "$Rn = $Rd" in 1813multiclass AI1_rsc_irs<bits<4> opcod, string opc, SDNode opnode> { 1814 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1815 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1816 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1817 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>, 1818 Requires<[IsARM]>, 1819 Sched<[WriteALU, ReadALU]> { 1820 bits<4> Rd; 1821 bits<4> Rn; 1822 bits<12> imm; 1823 let Inst{25} = 1; 1824 let Inst{15-12} = Rd; 1825 let Inst{19-16} = Rn; 1826 let Inst{11-0} = imm; 1827 } 1828 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1829 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1830 [/* pattern left blank */]>, 1831 Sched<[WriteALU, ReadALU, ReadALU]> { 1832 bits<4> Rd; 1833 bits<4> Rn; 1834 bits<4> Rm; 1835 let Inst{11-4} = 0b00000000; 1836 let Inst{25} = 0; 1837 let Inst{3-0} = Rm; 1838 let Inst{15-12} = Rd; 1839 let Inst{19-16} = Rn; 1840 } 1841 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), 1842 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1843 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>, 1844 Requires<[IsARM]>, 1845 Sched<[WriteALUsi, ReadALU]> { 1846 bits<4> Rd; 1847 bits<4> Rn; 1848 bits<12> shift; 1849 let Inst{25} = 0; 1850 let Inst{19-16} = Rn; 1851 let Inst{15-12} = Rd; 1852 let Inst{11-5} = shift{11-5}; 1853 let Inst{4} = 0; 1854 let Inst{3-0} = shift{3-0}; 1855 } 1856 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), 1857 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1858 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>, 1859 Requires<[IsARM]>, 1860 Sched<[WriteALUsr, ReadALUsr]> { 1861 bits<4> Rd; 1862 bits<4> Rn; 1863 bits<12> shift; 1864 let Inst{25} = 0; 1865 let Inst{19-16} = Rn; 1866 let Inst{15-12} = Rd; 1867 let Inst{11-8} = shift{11-8}; 1868 let Inst{7} = 0; 1869 let Inst{6-5} = shift{6-5}; 1870 let Inst{4} = 1; 1871 let Inst{3-0} = shift{3-0}; 1872 } 1873 } 1874} 1875 1876let canFoldAsLoad = 1, isReMaterializable = 1 in { 1877multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii, 1878 InstrItinClass iir, PatFrag opnode> { 1879 // Note: We use the complex addrmode_imm12 rather than just an input 1880 // GPR and a constrained immediate so that we can use this to match 1881 // frame index references and avoid matching constant pool references. 1882 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 1883 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1884 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { 1885 bits<4> Rt; 1886 bits<17> addr; 1887 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1888 let Inst{19-16} = addr{16-13}; // Rn 1889 let Inst{15-12} = Rt; 1890 let Inst{11-0} = addr{11-0}; // imm12 1891 } 1892 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift), 1893 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1894 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { 1895 bits<4> Rt; 1896 bits<17> shift; 1897 let shift{4} = 0; // Inst{4} = 0 1898 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1899 let Inst{19-16} = shift{16-13}; // Rn 1900 let Inst{15-12} = Rt; 1901 let Inst{11-0} = shift{11-0}; 1902 } 1903} 1904} 1905 1906let canFoldAsLoad = 1, isReMaterializable = 1 in { 1907multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii, 1908 InstrItinClass iir, PatFrag opnode> { 1909 // Note: We use the complex addrmode_imm12 rather than just an input 1910 // GPR and a constrained immediate so that we can use this to match 1911 // frame index references and avoid matching constant pool references. 1912 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), 1913 (ins addrmode_imm12:$addr), 1914 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1915 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> { 1916 bits<4> Rt; 1917 bits<17> addr; 1918 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1919 let Inst{19-16} = addr{16-13}; // Rn 1920 let Inst{15-12} = Rt; 1921 let Inst{11-0} = addr{11-0}; // imm12 1922 } 1923 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), 1924 (ins ldst_so_reg:$shift), 1925 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1926 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> { 1927 bits<4> Rt; 1928 bits<17> shift; 1929 let shift{4} = 0; // Inst{4} = 0 1930 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1931 let Inst{19-16} = shift{16-13}; // Rn 1932 let Inst{15-12} = Rt; 1933 let Inst{11-0} = shift{11-0}; 1934 } 1935} 1936} 1937 1938 1939multiclass AI_str1<bit isByte, string opc, InstrItinClass iii, 1940 InstrItinClass iir, PatFrag opnode> { 1941 // Note: We use the complex addrmode_imm12 rather than just an input 1942 // GPR and a constrained immediate so that we can use this to match 1943 // frame index references and avoid matching constant pool references. 1944 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1945 (ins GPR:$Rt, addrmode_imm12:$addr), 1946 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1947 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> { 1948 bits<4> Rt; 1949 bits<17> addr; 1950 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1951 let Inst{19-16} = addr{16-13}; // Rn 1952 let Inst{15-12} = Rt; 1953 let Inst{11-0} = addr{11-0}; // imm12 1954 } 1955 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift), 1956 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1957 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> { 1958 bits<4> Rt; 1959 bits<17> shift; 1960 let shift{4} = 0; // Inst{4} = 0 1961 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1962 let Inst{19-16} = shift{16-13}; // Rn 1963 let Inst{15-12} = Rt; 1964 let Inst{11-0} = shift{11-0}; 1965 } 1966} 1967 1968multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii, 1969 InstrItinClass iir, PatFrag opnode> { 1970 // Note: We use the complex addrmode_imm12 rather than just an input 1971 // GPR and a constrained immediate so that we can use this to match 1972 // frame index references and avoid matching constant pool references. 1973 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1974 (ins GPRnopc:$Rt, addrmode_imm12:$addr), 1975 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1976 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> { 1977 bits<4> Rt; 1978 bits<17> addr; 1979 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1980 let Inst{19-16} = addr{16-13}; // Rn 1981 let Inst{15-12} = Rt; 1982 let Inst{11-0} = addr{11-0}; // imm12 1983 } 1984 def rs : AI2ldst<0b011, 0, isByte, (outs), 1985 (ins GPRnopc:$Rt, ldst_so_reg:$shift), 1986 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1987 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> { 1988 bits<4> Rt; 1989 bits<17> shift; 1990 let shift{4} = 0; // Inst{4} = 0 1991 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1992 let Inst{19-16} = shift{16-13}; // Rn 1993 let Inst{15-12} = Rt; 1994 let Inst{11-0} = shift{11-0}; 1995 } 1996} 1997 1998 1999//===----------------------------------------------------------------------===// 2000// Instructions 2001//===----------------------------------------------------------------------===// 2002 2003//===----------------------------------------------------------------------===// 2004// Miscellaneous Instructions. 2005// 2006 2007/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 2008/// the function. The first operand is the ID# for this instruction, the second 2009/// is the index into the MachineConstantPool that this is, the third is the 2010/// size in bytes of this constant pool entry. 2011let hasSideEffects = 0, isNotDuplicable = 1, hasNoSchedulingInfo = 1 in 2012def CONSTPOOL_ENTRY : 2013PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2014 i32imm:$size), NoItinerary, []>; 2015 2016/// A jumptable consisting of direct 32-bit addresses of the destination basic 2017/// blocks (either absolute, or relative to the start of the jump-table in PIC 2018/// mode). Used mostly in ARM and Thumb-1 modes. 2019def JUMPTABLE_ADDRS : 2020PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2021 i32imm:$size), NoItinerary, []>; 2022 2023/// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables 2024/// that cannot be optimised to use TBB or TBH. 2025def JUMPTABLE_INSTS : 2026PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2027 i32imm:$size), NoItinerary, []>; 2028 2029/// A jumptable consisting of 8-bit unsigned integers representing offsets from 2030/// a TBB instruction. 2031def JUMPTABLE_TBB : 2032PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2033 i32imm:$size), NoItinerary, []>; 2034 2035/// A jumptable consisting of 16-bit unsigned integers representing offsets from 2036/// a TBH instruction. 2037def JUMPTABLE_TBH : 2038PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2039 i32imm:$size), NoItinerary, []>; 2040 2041 2042// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 2043// from removing one half of the matched pairs. That breaks PEI, which assumes 2044// these will always be in pairs, and asserts if it finds otherwise. Better way? 2045let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 2046def ADJCALLSTACKUP : 2047PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, 2048 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; 2049 2050def ADJCALLSTACKDOWN : 2051PseudoInst<(outs), (ins i32imm:$amt, i32imm:$amt2, pred:$p), NoItinerary, 2052 [(ARMcallseq_start timm:$amt, timm:$amt2)]>; 2053} 2054 2055def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary, 2056 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>, 2057 Requires<[IsARM, HasV6]> { 2058 bits<8> imm; 2059 let Inst{27-8} = 0b00110010000011110000; 2060 let Inst{7-0} = imm; 2061 let DecoderMethod = "DecodeHINTInstruction"; 2062} 2063 2064def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>; 2065def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>; 2066def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>; 2067def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>; 2068def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>; 2069def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>; 2070def : InstAlias<"esb$p", (HINT 16, pred:$p)>, Requires<[IsARM, HasRAS]>; 2071def : InstAlias<"csdb$p", (HINT 20, pred:$p)>, Requires<[IsARM, HasV6K]>; 2072 2073def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel", 2074 "\t$Rd, $Rn, $Rm", 2075 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>, 2076 Requires<[IsARM, HasV6]> { 2077 bits<4> Rd; 2078 bits<4> Rn; 2079 bits<4> Rm; 2080 let Inst{3-0} = Rm; 2081 let Inst{15-12} = Rd; 2082 let Inst{19-16} = Rn; 2083 let Inst{27-20} = 0b01101000; 2084 let Inst{7-4} = 0b1011; 2085 let Inst{11-8} = 0b1111; 2086 let Unpredictable{11-8} = 0b1111; 2087} 2088 2089// The 16-bit operand $val can be used by a debugger to store more information 2090// about the breakpoint. 2091def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 2092 "bkpt", "\t$val", []>, Requires<[IsARM]> { 2093 bits<16> val; 2094 let Inst{3-0} = val{3-0}; 2095 let Inst{19-8} = val{15-4}; 2096 let Inst{27-20} = 0b00010010; 2097 let Inst{31-28} = 0xe; // AL 2098 let Inst{7-4} = 0b0111; 2099} 2100// default immediate for breakpoint mnemonic 2101def : InstAlias<"bkpt", (BKPT 0), 0>, Requires<[IsARM]>; 2102 2103def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 2104 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> { 2105 bits<16> val; 2106 let Inst{3-0} = val{3-0}; 2107 let Inst{19-8} = val{15-4}; 2108 let Inst{27-20} = 0b00010000; 2109 let Inst{31-28} = 0xe; // AL 2110 let Inst{7-4} = 0b0111; 2111} 2112 2113// Change Processor State 2114// FIXME: We should use InstAlias to handle the optional operands. 2115class CPS<dag iops, string asm_ops> 2116 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops), 2117 []>, Requires<[IsARM]> { 2118 bits<2> imod; 2119 bits<3> iflags; 2120 bits<5> mode; 2121 bit M; 2122 2123 let Inst{31-28} = 0b1111; 2124 let Inst{27-20} = 0b00010000; 2125 let Inst{19-18} = imod; 2126 let Inst{17} = M; // Enabled if mode is set; 2127 let Inst{16-9} = 0b00000000; 2128 let Inst{8-6} = iflags; 2129 let Inst{5} = 0; 2130 let Inst{4-0} = mode; 2131} 2132 2133let DecoderMethod = "DecodeCPSInstruction" in { 2134let M = 1 in 2135 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode), 2136 "$imod\t$iflags, $mode">; 2137let mode = 0, M = 0 in 2138 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">; 2139 2140let imod = 0, iflags = 0, M = 1 in 2141 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">; 2142} 2143 2144// Preload signals the memory system of possible future data/instruction access. 2145multiclass APreLoad<bits<1> read, bits<1> data, string opc> { 2146 2147 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm, 2148 IIC_Preload, !strconcat(opc, "\t$addr"), 2149 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>, 2150 Sched<[WritePreLd]> { 2151 bits<4> Rt; 2152 bits<17> addr; 2153 let Inst{31-26} = 0b111101; 2154 let Inst{25} = 0; // 0 for immediate form 2155 let Inst{24} = data; 2156 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2157 let Inst{22} = read; 2158 let Inst{21-20} = 0b01; 2159 let Inst{19-16} = addr{16-13}; // Rn 2160 let Inst{15-12} = 0b1111; 2161 let Inst{11-0} = addr{11-0}; // imm12 2162 } 2163 2164 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, 2165 !strconcat(opc, "\t$shift"), 2166 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>, 2167 Sched<[WritePreLd]> { 2168 bits<17> shift; 2169 let Inst{31-26} = 0b111101; 2170 let Inst{25} = 1; // 1 for register form 2171 let Inst{24} = data; 2172 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2173 let Inst{22} = read; 2174 let Inst{21-20} = 0b01; 2175 let Inst{19-16} = shift{16-13}; // Rn 2176 let Inst{15-12} = 0b1111; 2177 let Inst{11-0} = shift{11-0}; 2178 let Inst{4} = 0; 2179 } 2180} 2181 2182defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>; 2183defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>; 2184defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>; 2185 2186def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary, 2187 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> { 2188 bits<1> end; 2189 let Inst{31-10} = 0b1111000100000001000000; 2190 let Inst{9} = end; 2191 let Inst{8-0} = 0; 2192} 2193 2194def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", 2195 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> { 2196 bits<4> opt; 2197 let Inst{27-4} = 0b001100100000111100001111; 2198 let Inst{3-0} = opt; 2199} 2200 2201// A8.8.247 UDF - Undefined (Encoding A1) 2202def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary, 2203 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> { 2204 bits<16> imm16; 2205 let Inst{31-28} = 0b1110; // AL 2206 let Inst{27-25} = 0b011; 2207 let Inst{24-20} = 0b11111; 2208 let Inst{19-8} = imm16{15-4}; 2209 let Inst{7-4} = 0b1111; 2210 let Inst{3-0} = imm16{3-0}; 2211} 2212 2213/* 2214 * A5.4 Permanently UNDEFINED instructions. 2215 * 2216 * For most targets use UDF #65006, for which the OS will generate SIGTRAP. 2217 * Other UDF encodings generate SIGILL. 2218 * 2219 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb. 2220 * Encoding A1: 2221 * 1110 0111 1111 iiii iiii iiii 1111 iiii 2222 * Encoding T1: 2223 * 1101 1110 iiii iiii 2224 * It uses the following encoding: 2225 * 1110 0111 1111 1110 1101 1110 1111 0000 2226 * - In ARM: UDF #60896; 2227 * - In Thumb: UDF #254 followed by a branch-to-self. 2228 */ 2229let isBarrier = 1, isTerminator = 1 in 2230def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary, 2231 "trap", [(trap)]>, 2232 Requires<[IsARM,UseNaClTrap]> { 2233 let Inst = 0xe7fedef0; 2234} 2235let isBarrier = 1, isTerminator = 1 in 2236def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, 2237 "trap", [(trap)]>, 2238 Requires<[IsARM,DontUseNaClTrap]> { 2239 let Inst = 0xe7ffdefe; 2240} 2241 2242def : Pat<(debugtrap), (BKPT 0)>, Requires<[IsARM, HasV5T]>; 2243def : Pat<(debugtrap), (UDF 254)>, Requires<[IsARM, NoV5T]>; 2244 2245// Address computation and loads and stores in PIC mode. 2246let isNotDuplicable = 1 in { 2247def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 2248 4, IIC_iALUr, 2249 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>, 2250 Sched<[WriteALU, ReadALU]>; 2251 2252let AddedComplexity = 10 in { 2253def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 2254 4, IIC_iLoad_r, 2255 [(set GPR:$dst, (load addrmodepc:$addr))]>; 2256 2257def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2258 4, IIC_iLoad_bh_r, 2259 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>; 2260 2261def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2262 4, IIC_iLoad_bh_r, 2263 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>; 2264 2265def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2266 4, IIC_iLoad_bh_r, 2267 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>; 2268 2269def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2270 4, IIC_iLoad_bh_r, 2271 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>; 2272} 2273let AddedComplexity = 10 in { 2274def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2275 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>; 2276 2277def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2278 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, 2279 addrmodepc:$addr)]>; 2280 2281def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2282 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 2283} 2284} // isNotDuplicable = 1 2285 2286 2287// LEApcrel - Load a pc-relative address into a register without offending the 2288// assembler. 2289let hasSideEffects = 0, isReMaterializable = 1 in 2290// The 'adr' mnemonic encodes differently if the label is before or after 2291// the instruction. The {24-21} opcode bits are set by the fixup, as we don't 2292// know until then which form of the instruction will be used. 2293def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), 2294 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>, 2295 Sched<[WriteALU, ReadALU]> { 2296 bits<4> Rd; 2297 bits<14> label; 2298 let Inst{27-25} = 0b001; 2299 let Inst{24} = 0; 2300 let Inst{23-22} = label{13-12}; 2301 let Inst{21} = 0; 2302 let Inst{20} = 0; 2303 let Inst{19-16} = 0b1111; 2304 let Inst{15-12} = Rd; 2305 let Inst{11-0} = label{11-0}; 2306} 2307 2308let hasSideEffects = 1 in { 2309def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 2310 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2311 2312def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd), 2313 (ins i32imm:$label, pred:$p), 2314 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2315} 2316 2317//===----------------------------------------------------------------------===// 2318// Control Flow Instructions. 2319// 2320 2321let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 2322 // ARMV4T and above 2323 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2324 "bx", "\tlr", [(ARMretflag)]>, 2325 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2326 let Inst{27-0} = 0b0001001011111111111100011110; 2327 } 2328 2329 // ARMV4 only 2330 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2331 "mov", "\tpc, lr", [(ARMretflag)]>, 2332 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> { 2333 let Inst{27-0} = 0b0001101000001111000000001110; 2334 } 2335 2336 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets 2337 // the user-space one). 2338 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p), 2339 4, IIC_Br, 2340 [(ARMintretflag imm:$offset)]>; 2341} 2342 2343// Indirect branches 2344let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 2345 // ARMV4T and above 2346 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst", 2347 [(brind GPR:$dst)]>, 2348 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2349 bits<4> dst; 2350 let Inst{31-4} = 0b1110000100101111111111110001; 2351 let Inst{3-0} = dst; 2352 } 2353 2354 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, 2355 "bx", "\t$dst", [/* pattern left blank */]>, 2356 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2357 bits<4> dst; 2358 let Inst{27-4} = 0b000100101111111111110001; 2359 let Inst{3-0} = dst; 2360 } 2361} 2362 2363// SP is marked as a use to prevent stack-pointer assignments that appear 2364// immediately before calls from potentially appearing dead. 2365let isCall = 1, 2366 // FIXME: Do we really need a non-predicated version? If so, it should 2367 // at least be a pseudo instruction expanding to the predicated version 2368 // at MC lowering time. 2369 Defs = [LR], Uses = [SP] in { 2370 def BL : ABXI<0b1011, (outs), (ins arm_bl_target:$func), 2371 IIC_Br, "bl\t$func", 2372 [(ARMcall tglobaladdr:$func)]>, 2373 Requires<[IsARM]>, Sched<[WriteBrL]> { 2374 let Inst{31-28} = 0b1110; 2375 bits<24> func; 2376 let Inst{23-0} = func; 2377 let DecoderMethod = "DecodeBranchImmInstruction"; 2378 } 2379 2380 def BL_pred : ABI<0b1011, (outs), (ins arm_bl_target:$func), 2381 IIC_Br, "bl", "\t$func", 2382 [(ARMcall_pred tglobaladdr:$func)]>, 2383 Requires<[IsARM]>, Sched<[WriteBrL]> { 2384 bits<24> func; 2385 let Inst{23-0} = func; 2386 let DecoderMethod = "DecodeBranchImmInstruction"; 2387 } 2388 2389 // ARMv5T and above 2390 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm, 2391 IIC_Br, "blx\t$func", 2392 [(ARMcall GPR:$func)]>, 2393 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2394 bits<4> func; 2395 let Inst{31-4} = 0b1110000100101111111111110011; 2396 let Inst{3-0} = func; 2397 } 2398 2399 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm, 2400 IIC_Br, "blx", "\t$func", 2401 [(ARMcall_pred GPR:$func)]>, 2402 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2403 bits<4> func; 2404 let Inst{27-4} = 0b000100101111111111110011; 2405 let Inst{3-0} = func; 2406 } 2407 2408 // ARMv4T 2409 // Note: Restrict $func to the tGPR regclass to prevent it being in LR. 2410 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2411 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2412 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>; 2413 2414 // ARMv4 2415 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2416 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2417 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 2418 2419 // mov lr, pc; b if callee is marked noreturn to avoid confusing the 2420 // return stack predictor. 2421 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins arm_bl_target:$func), 2422 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>, 2423 Requires<[IsARM]>, Sched<[WriteBr]>; 2424 2425 // push lr before the call 2426 def BL_PUSHLR : ARMPseudoInst<(outs), (ins GPRlr:$ra, arm_bl_target:$func), 2427 4, IIC_Br, 2428 []>, 2429 Requires<[IsARM]>, Sched<[WriteBr]>; 2430} 2431 2432let isBranch = 1, isTerminator = 1 in { 2433 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 2434 // a two-value operand where a dag node expects two operands. :( 2435 def Bcc : ABI<0b1010, (outs), (ins arm_br_target:$target), 2436 IIC_Br, "b", "\t$target", 2437 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>, 2438 Sched<[WriteBr]> { 2439 bits<24> target; 2440 let Inst{23-0} = target; 2441 let DecoderMethod = "DecodeBranchImmInstruction"; 2442 } 2443 2444 let isBarrier = 1 in { 2445 // B is "predicable" since it's just a Bcc with an 'always' condition. 2446 let isPredicable = 1 in 2447 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly 2448 // should be sufficient. 2449 // FIXME: Is B really a Barrier? That doesn't seem right. 2450 def B : ARMPseudoExpand<(outs), (ins arm_br_target:$target), 4, IIC_Br, 2451 [(br bb:$target)], (Bcc arm_br_target:$target, 2452 (ops 14, zero_reg))>, 2453 Sched<[WriteBr]>; 2454 2455 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in { 2456 def BR_JTr : ARMPseudoInst<(outs), 2457 (ins GPR:$target, i32imm:$jt), 2458 0, IIC_Br, 2459 [(ARMbrjt GPR:$target, tjumptable:$jt)]>, 2460 Sched<[WriteBr]>; 2461 def BR_JTm_i12 : ARMPseudoInst<(outs), 2462 (ins addrmode_imm12:$target, i32imm:$jt), 2463 0, IIC_Br, 2464 [(ARMbrjt (i32 (load addrmode_imm12:$target)), 2465 tjumptable:$jt)]>, Sched<[WriteBrTbl]>; 2466 def BR_JTm_rs : ARMPseudoInst<(outs), 2467 (ins ldst_so_reg:$target, i32imm:$jt), 2468 0, IIC_Br, 2469 [(ARMbrjt (i32 (load ldst_so_reg:$target)), 2470 tjumptable:$jt)]>, Sched<[WriteBrTbl]>; 2471 def BR_JTadd : ARMPseudoInst<(outs), 2472 (ins GPR:$target, GPR:$idx, i32imm:$jt), 2473 0, IIC_Br, 2474 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>, 2475 Sched<[WriteBrTbl]>; 2476 } // isNotDuplicable = 1, isIndirectBranch = 1 2477 } // isBarrier = 1 2478 2479} 2480 2481// BLX (immediate) 2482def BLXi : AXI<(outs), (ins arm_blx_target:$target), BrMiscFrm, NoItinerary, 2483 "blx\t$target", []>, 2484 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2485 let Inst{31-25} = 0b1111101; 2486 bits<25> target; 2487 let Inst{23-0} = target{24-1}; 2488 let Inst{24} = target{0}; 2489 let isCall = 1; 2490} 2491 2492// Branch and Exchange Jazelle 2493def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", 2494 [/* pattern left blank */]>, Sched<[WriteBr]> { 2495 bits<4> func; 2496 let Inst{23-20} = 0b0010; 2497 let Inst{19-8} = 0xfff; 2498 let Inst{7-4} = 0b0010; 2499 let Inst{3-0} = func; 2500 let isBranch = 1; 2501} 2502 2503// Tail calls. 2504 2505let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { 2506 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>, 2507 Sched<[WriteBr]>; 2508 2509 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>, 2510 Sched<[WriteBr]>; 2511 2512 def TAILJMPd : ARMPseudoExpand<(outs), (ins arm_br_target:$dst), 2513 4, IIC_Br, [], 2514 (Bcc arm_br_target:$dst, (ops 14, zero_reg))>, 2515 Requires<[IsARM]>, Sched<[WriteBr]>; 2516 2517 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst), 2518 4, IIC_Br, [], 2519 (BX GPR:$dst)>, Sched<[WriteBr]>, 2520 Requires<[IsARM, HasV4T]>; 2521} 2522 2523// Secure Monitor Call is a system instruction. 2524def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", 2525 []>, Requires<[IsARM, HasTrustZone]> { 2526 bits<4> opt; 2527 let Inst{23-4} = 0b01100000000000000111; 2528 let Inst{3-0} = opt; 2529} 2530def : MnemonicAlias<"smi", "smc">; 2531 2532// Supervisor Call (Software Interrupt) 2533let isCall = 1, Uses = [SP] in { 2534def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>, 2535 Sched<[WriteBr]> { 2536 bits<24> svc; 2537 let Inst{23-0} = svc; 2538} 2539} 2540 2541// Store Return State 2542class SRSI<bit wb, string asm> 2543 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm, 2544 NoItinerary, asm, "", []> { 2545 bits<5> mode; 2546 let Inst{31-28} = 0b1111; 2547 let Inst{27-25} = 0b100; 2548 let Inst{22} = 1; 2549 let Inst{21} = wb; 2550 let Inst{20} = 0; 2551 let Inst{19-16} = 0b1101; // SP 2552 let Inst{15-5} = 0b00000101000; 2553 let Inst{4-0} = mode; 2554} 2555 2556def SRSDA : SRSI<0, "srsda\tsp, $mode"> { 2557 let Inst{24-23} = 0; 2558} 2559def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> { 2560 let Inst{24-23} = 0; 2561} 2562def SRSDB : SRSI<0, "srsdb\tsp, $mode"> { 2563 let Inst{24-23} = 0b10; 2564} 2565def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> { 2566 let Inst{24-23} = 0b10; 2567} 2568def SRSIA : SRSI<0, "srsia\tsp, $mode"> { 2569 let Inst{24-23} = 0b01; 2570} 2571def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> { 2572 let Inst{24-23} = 0b01; 2573} 2574def SRSIB : SRSI<0, "srsib\tsp, $mode"> { 2575 let Inst{24-23} = 0b11; 2576} 2577def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> { 2578 let Inst{24-23} = 0b11; 2579} 2580 2581def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>; 2582def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>; 2583 2584def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>; 2585def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>; 2586 2587def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>; 2588def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>; 2589 2590def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>; 2591def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>; 2592 2593// Return From Exception 2594class RFEI<bit wb, string asm> 2595 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm, 2596 NoItinerary, asm, "", []> { 2597 bits<4> Rn; 2598 let Inst{31-28} = 0b1111; 2599 let Inst{27-25} = 0b100; 2600 let Inst{22} = 0; 2601 let Inst{21} = wb; 2602 let Inst{20} = 1; 2603 let Inst{19-16} = Rn; 2604 let Inst{15-0} = 0xa00; 2605} 2606 2607def RFEDA : RFEI<0, "rfeda\t$Rn"> { 2608 let Inst{24-23} = 0; 2609} 2610def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> { 2611 let Inst{24-23} = 0; 2612} 2613def RFEDB : RFEI<0, "rfedb\t$Rn"> { 2614 let Inst{24-23} = 0b10; 2615} 2616def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> { 2617 let Inst{24-23} = 0b10; 2618} 2619def RFEIA : RFEI<0, "rfeia\t$Rn"> { 2620 let Inst{24-23} = 0b01; 2621} 2622def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> { 2623 let Inst{24-23} = 0b01; 2624} 2625def RFEIB : RFEI<0, "rfeib\t$Rn"> { 2626 let Inst{24-23} = 0b11; 2627} 2628def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> { 2629 let Inst{24-23} = 0b11; 2630} 2631 2632// Hypervisor Call is a system instruction 2633let isCall = 1 in { 2634def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary, 2635 "hvc", "\t$imm", []>, 2636 Requires<[IsARM, HasVirtualization]> { 2637 bits<16> imm; 2638 2639 // Even though HVC isn't predicable, it's encoding includes a condition field. 2640 // The instruction is undefined if the condition field is 0xf otherwise it is 2641 // unpredictable if it isn't condition AL (0xe). 2642 let Inst{31-28} = 0b1110; 2643 let Unpredictable{31-28} = 0b1111; 2644 let Inst{27-24} = 0b0001; 2645 let Inst{23-20} = 0b0100; 2646 let Inst{19-8} = imm{15-4}; 2647 let Inst{7-4} = 0b0111; 2648 let Inst{3-0} = imm{3-0}; 2649} 2650} 2651 2652// Return from exception in Hypervisor mode. 2653let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in 2654def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>, 2655 Requires<[IsARM, HasVirtualization]> { 2656 let Inst{23-0} = 0b011000000000000001101110; 2657} 2658 2659//===----------------------------------------------------------------------===// 2660// Load / Store Instructions. 2661// 2662 2663// Load 2664 2665 2666defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si, load>; 2667defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si, 2668 zextloadi8>; 2669defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si, store>; 2670defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si, 2671 truncstorei8>; 2672 2673// Special LDR for loads from non-pc-relative constpools. 2674let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0, 2675 isReMaterializable = 1, isCodeGenOnly = 1 in 2676def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 2677 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", 2678 []> { 2679 bits<4> Rt; 2680 bits<17> addr; 2681 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2682 let Inst{19-16} = 0b1111; 2683 let Inst{15-12} = Rt; 2684 let Inst{11-0} = addr{11-0}; // imm12 2685} 2686 2687// Loads with zero extension 2688def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2689 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr", 2690 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>; 2691 2692// Loads with sign extension 2693def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2694 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr", 2695 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>; 2696 2697def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2698 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr", 2699 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>; 2700 2701let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in { 2702 // Load doubleword 2703 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr), 2704 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>, 2705 Requires<[IsARM, HasV5TE]>; 2706} 2707 2708let mayLoad = 1, hasSideEffects = 0, hasNoSchedulingInfo = 1 in { 2709def LOADDUAL : ARMPseudoInst<(outs GPRPairOp:$Rt), (ins addrmode3:$addr), 2710 64, IIC_iLoad_d_r, []>, 2711 Requires<[IsARM, HasV5TE]> { 2712 let AM = AddrMode3; 2713} 2714} 2715 2716def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2717 NoItinerary, "lda", "\t$Rt, $addr", []>; 2718def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2719 NoItinerary, "ldab", "\t$Rt, $addr", []>; 2720def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2721 NoItinerary, "ldah", "\t$Rt, $addr", []>; 2722 2723// Indexed loads 2724multiclass AI2_ldridx<bit isByte, string opc, 2725 InstrItinClass iii, InstrItinClass iir> { 2726 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2727 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii, 2728 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2729 bits<17> addr; 2730 let Inst{25} = 0; 2731 let Inst{23} = addr{12}; 2732 let Inst{19-16} = addr{16-13}; 2733 let Inst{11-0} = addr{11-0}; 2734 let DecoderMethod = "DecodeLDRPreImm"; 2735 } 2736 2737 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2738 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir, 2739 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2740 bits<17> addr; 2741 let Inst{25} = 1; 2742 let Inst{23} = addr{12}; 2743 let Inst{19-16} = addr{16-13}; 2744 let Inst{11-0} = addr{11-0}; 2745 let Inst{4} = 0; 2746 let DecoderMethod = "DecodeLDRPreReg"; 2747 } 2748 2749 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2750 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2751 IndexModePost, LdFrm, iir, 2752 opc, "\t$Rt, $addr, $offset", 2753 "$addr.base = $Rn_wb", []> { 2754 // {12} isAdd 2755 // {11-0} imm12/Rm 2756 bits<14> offset; 2757 bits<4> addr; 2758 let Inst{25} = 1; 2759 let Inst{23} = offset{12}; 2760 let Inst{19-16} = addr; 2761 let Inst{11-0} = offset{11-0}; 2762 let Inst{4} = 0; 2763 2764 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2765 } 2766 2767 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2768 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2769 IndexModePost, LdFrm, iii, 2770 opc, "\t$Rt, $addr, $offset", 2771 "$addr.base = $Rn_wb", []> { 2772 // {12} isAdd 2773 // {11-0} imm12/Rm 2774 bits<14> offset; 2775 bits<4> addr; 2776 let Inst{25} = 0; 2777 let Inst{23} = offset{12}; 2778 let Inst{19-16} = addr; 2779 let Inst{11-0} = offset{11-0}; 2780 2781 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2782 } 2783 2784} 2785 2786let mayLoad = 1, hasSideEffects = 0 in { 2787// FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or 2788// IIC_iLoad_siu depending on whether it the offset register is shifted. 2789defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>; 2790defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>; 2791} 2792 2793multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> { 2794 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2795 (ins addrmode3_pre:$addr), IndexModePre, 2796 LdMiscFrm, itin, 2797 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2798 bits<14> addr; 2799 let Inst{23} = addr{8}; // U bit 2800 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2801 let Inst{19-16} = addr{12-9}; // Rn 2802 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2803 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2804 let DecoderMethod = "DecodeAddrMode3Instruction"; 2805 } 2806 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2807 (ins addr_offset_none:$addr, am3offset:$offset), 2808 IndexModePost, LdMiscFrm, itin, 2809 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2810 []> { 2811 bits<10> offset; 2812 bits<4> addr; 2813 let Inst{23} = offset{8}; // U bit 2814 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2815 let Inst{19-16} = addr; 2816 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2817 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2818 let DecoderMethod = "DecodeAddrMode3Instruction"; 2819 } 2820} 2821 2822let mayLoad = 1, hasSideEffects = 0 in { 2823defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>; 2824defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>; 2825defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>; 2826let hasExtraDefRegAllocReq = 1 in { 2827def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2828 (ins addrmode3_pre:$addr), IndexModePre, 2829 LdMiscFrm, IIC_iLoad_d_ru, 2830 "ldrd", "\t$Rt, $Rt2, $addr!", 2831 "$addr.base = $Rn_wb", []> { 2832 bits<14> addr; 2833 let Inst{23} = addr{8}; // U bit 2834 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2835 let Inst{19-16} = addr{12-9}; // Rn 2836 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2837 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2838 let DecoderMethod = "DecodeAddrMode3Instruction"; 2839} 2840def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2841 (ins addr_offset_none:$addr, am3offset:$offset), 2842 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru, 2843 "ldrd", "\t$Rt, $Rt2, $addr, $offset", 2844 "$addr.base = $Rn_wb", []> { 2845 bits<10> offset; 2846 bits<4> addr; 2847 let Inst{23} = offset{8}; // U bit 2848 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2849 let Inst{19-16} = addr; 2850 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2851 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2852 let DecoderMethod = "DecodeAddrMode3Instruction"; 2853} 2854} // hasExtraDefRegAllocReq = 1 2855} // mayLoad = 1, hasSideEffects = 0 2856 2857// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT. 2858let mayLoad = 1, hasSideEffects = 0 in { 2859def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2860 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2861 IndexModePost, LdFrm, IIC_iLoad_ru, 2862 "ldrt", "\t$Rt, $addr, $offset", 2863 "$addr.base = $Rn_wb", []> { 2864 // {12} isAdd 2865 // {11-0} imm12/Rm 2866 bits<14> offset; 2867 bits<4> addr; 2868 let Inst{25} = 1; 2869 let Inst{23} = offset{12}; 2870 let Inst{21} = 1; // overwrite 2871 let Inst{19-16} = addr; 2872 let Inst{11-5} = offset{11-5}; 2873 let Inst{4} = 0; 2874 let Inst{3-0} = offset{3-0}; 2875 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2876} 2877 2878def LDRT_POST_IMM 2879 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2880 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2881 IndexModePost, LdFrm, IIC_iLoad_ru, 2882 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2883 // {12} isAdd 2884 // {11-0} imm12/Rm 2885 bits<14> offset; 2886 bits<4> addr; 2887 let Inst{25} = 0; 2888 let Inst{23} = offset{12}; 2889 let Inst{21} = 1; // overwrite 2890 let Inst{19-16} = addr; 2891 let Inst{11-0} = offset{11-0}; 2892 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2893} 2894 2895def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2896 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2897 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2898 "ldrbt", "\t$Rt, $addr, $offset", 2899 "$addr.base = $Rn_wb", []> { 2900 // {12} isAdd 2901 // {11-0} imm12/Rm 2902 bits<14> offset; 2903 bits<4> addr; 2904 let Inst{25} = 1; 2905 let Inst{23} = offset{12}; 2906 let Inst{21} = 1; // overwrite 2907 let Inst{19-16} = addr; 2908 let Inst{11-5} = offset{11-5}; 2909 let Inst{4} = 0; 2910 let Inst{3-0} = offset{3-0}; 2911 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2912} 2913 2914def LDRBT_POST_IMM 2915 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2916 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2917 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2918 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2919 // {12} isAdd 2920 // {11-0} imm12/Rm 2921 bits<14> offset; 2922 bits<4> addr; 2923 let Inst{25} = 0; 2924 let Inst{23} = offset{12}; 2925 let Inst{21} = 1; // overwrite 2926 let Inst{19-16} = addr; 2927 let Inst{11-0} = offset{11-0}; 2928 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2929} 2930 2931multiclass AI3ldrT<bits<4> op, string opc> { 2932 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb), 2933 (ins addr_offset_none:$addr, postidx_imm8:$offset), 2934 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2935 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 2936 bits<9> offset; 2937 let Inst{23} = offset{8}; 2938 let Inst{22} = 1; 2939 let Inst{11-8} = offset{7-4}; 2940 let Inst{3-0} = offset{3-0}; 2941 } 2942 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb), 2943 (ins addr_offset_none:$addr, postidx_reg:$Rm), 2944 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2945 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 2946 bits<5> Rm; 2947 let Inst{23} = Rm{4}; 2948 let Inst{22} = 0; 2949 let Inst{11-8} = 0; 2950 let Unpredictable{11-8} = 0b1111; 2951 let Inst{3-0} = Rm{3-0}; 2952 let DecoderMethod = "DecodeLDR"; 2953 } 2954} 2955 2956defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">; 2957defm LDRHT : AI3ldrT<0b1011, "ldrht">; 2958defm LDRSHT : AI3ldrT<0b1111, "ldrsht">; 2959} 2960 2961def LDRT_POST 2962 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2963 (outs GPR:$Rt)>; 2964 2965def LDRBT_POST 2966 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2967 (outs GPR:$Rt)>; 2968 2969// Pseudo instruction ldr Rt, =immediate 2970def LDRConstPool 2971 : ARMAsmPseudo<"ldr${q} $Rt, $immediate", 2972 (ins const_pool_asm_imm:$immediate, pred:$q), 2973 (outs GPR:$Rt)>; 2974 2975// Store 2976 2977// Stores with truncate 2978def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, 2979 IIC_iStore_bh_r, "strh", "\t$Rt, $addr", 2980 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>; 2981 2982// Store doubleword 2983let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 2984 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr), 2985 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>, 2986 Requires<[IsARM, HasV5TE]> { 2987 let Inst{21} = 0; 2988 } 2989} 2990 2991let mayStore = 1, hasSideEffects = 0, hasNoSchedulingInfo = 1 in { 2992def STOREDUAL : ARMPseudoInst<(outs), (ins GPRPairOp:$Rt, addrmode3:$addr), 2993 64, IIC_iStore_d_r, []>, 2994 Requires<[IsARM, HasV5TE]> { 2995 let AM = AddrMode3; 2996} 2997} 2998 2999let Predicates = [IsARM, HasV5TE] in { 3000def : Pat<(ARMstrd GPR:$Rt, GPR:$Rt2, addrmode3:$addr), 3001 (STOREDUAL (REG_SEQUENCE GPRPair, GPR:$Rt, gsub_0, GPR:$Rt2, gsub_1), addrmode3:$addr)>; 3002} 3003 3004// Indexed stores 3005multiclass AI2_stridx<bit isByte, string opc, 3006 InstrItinClass iii, InstrItinClass iir> { 3007 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 3008 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre, 3009 StFrm, iii, 3010 opc, "\t$Rt, $addr!", 3011 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3012 bits<17> addr; 3013 let Inst{25} = 0; 3014 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 3015 let Inst{19-16} = addr{16-13}; // Rn 3016 let Inst{11-0} = addr{11-0}; // imm12 3017 let DecoderMethod = "DecodeSTRPreImm"; 3018 } 3019 3020 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 3021 (ins GPR:$Rt, ldst_so_reg:$addr), 3022 IndexModePre, StFrm, iir, 3023 opc, "\t$Rt, $addr!", 3024 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3025 bits<17> addr; 3026 let Inst{25} = 1; 3027 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 3028 let Inst{19-16} = addr{16-13}; // Rn 3029 let Inst{11-0} = addr{11-0}; 3030 let Inst{4} = 0; // Inst{4} = 0 3031 let DecoderMethod = "DecodeSTRPreReg"; 3032 } 3033 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 3034 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3035 IndexModePost, StFrm, iir, 3036 opc, "\t$Rt, $addr, $offset", 3037 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3038 // {12} isAdd 3039 // {11-0} imm12/Rm 3040 bits<14> offset; 3041 bits<4> addr; 3042 let Inst{25} = 1; 3043 let Inst{23} = offset{12}; 3044 let Inst{19-16} = addr; 3045 let Inst{11-0} = offset{11-0}; 3046 let Inst{4} = 0; 3047 3048 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3049 } 3050 3051 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 3052 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3053 IndexModePost, StFrm, iii, 3054 opc, "\t$Rt, $addr, $offset", 3055 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3056 // {12} isAdd 3057 // {11-0} imm12/Rm 3058 bits<14> offset; 3059 bits<4> addr; 3060 let Inst{25} = 0; 3061 let Inst{23} = offset{12}; 3062 let Inst{19-16} = addr; 3063 let Inst{11-0} = offset{11-0}; 3064 3065 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3066 } 3067} 3068 3069let mayStore = 1, hasSideEffects = 0 in { 3070// FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or 3071// IIC_iStore_siu depending on whether it the offset register is shifted. 3072defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>; 3073defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>; 3074} 3075 3076def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 3077 am2offset_reg:$offset), 3078 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr, 3079 am2offset_reg:$offset)>; 3080def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 3081 am2offset_imm:$offset), 3082 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr, 3083 am2offset_imm:$offset)>; 3084def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 3085 am2offset_reg:$offset), 3086 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr, 3087 am2offset_reg:$offset)>; 3088def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 3089 am2offset_imm:$offset), 3090 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr, 3091 am2offset_imm:$offset)>; 3092 3093// Pseudo-instructions for pattern matching the pre-indexed stores. We can't 3094// put the patterns on the instruction definitions directly as ISel wants 3095// the address base and offset to be separate operands, not a single 3096// complex operand like we represent the instructions themselves. The 3097// pseudos map between the two. 3098let usesCustomInserter = 1, 3099 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 3100def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3101 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 3102 4, IIC_iStore_ru, 3103 [(set GPR:$Rn_wb, 3104 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 3105def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3106 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 3107 4, IIC_iStore_ru, 3108 [(set GPR:$Rn_wb, 3109 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 3110def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3111 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 3112 4, IIC_iStore_ru, 3113 [(set GPR:$Rn_wb, 3114 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 3115def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3116 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 3117 4, IIC_iStore_ru, 3118 [(set GPR:$Rn_wb, 3119 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 3120def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3121 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p), 3122 4, IIC_iStore_ru, 3123 [(set GPR:$Rn_wb, 3124 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>; 3125} 3126 3127 3128 3129def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb), 3130 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre, 3131 StMiscFrm, IIC_iStore_bh_ru, 3132 "strh", "\t$Rt, $addr!", 3133 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3134 bits<14> addr; 3135 let Inst{23} = addr{8}; // U bit 3136 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 3137 let Inst{19-16} = addr{12-9}; // Rn 3138 let Inst{11-8} = addr{7-4}; // imm7_4/zero 3139 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 3140 let DecoderMethod = "DecodeAddrMode3Instruction"; 3141} 3142 3143def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb), 3144 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset), 3145 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, 3146 "strh", "\t$Rt, $addr, $offset", 3147 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", 3148 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt, 3149 addr_offset_none:$addr, 3150 am3offset:$offset))]> { 3151 bits<10> offset; 3152 bits<4> addr; 3153 let Inst{23} = offset{8}; // U bit 3154 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 3155 let Inst{19-16} = addr; 3156 let Inst{11-8} = offset{7-4}; // imm7_4/zero 3157 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 3158 let DecoderMethod = "DecodeAddrMode3Instruction"; 3159} 3160 3161let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 3162def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb), 3163 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr), 3164 IndexModePre, StMiscFrm, IIC_iStore_d_ru, 3165 "strd", "\t$Rt, $Rt2, $addr!", 3166 "$addr.base = $Rn_wb", []> { 3167 bits<14> addr; 3168 let Inst{23} = addr{8}; // U bit 3169 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 3170 let Inst{19-16} = addr{12-9}; // Rn 3171 let Inst{11-8} = addr{7-4}; // imm7_4/zero 3172 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 3173 let DecoderMethod = "DecodeAddrMode3Instruction"; 3174} 3175 3176def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb), 3177 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr, 3178 am3offset:$offset), 3179 IndexModePost, StMiscFrm, IIC_iStore_d_ru, 3180 "strd", "\t$Rt, $Rt2, $addr, $offset", 3181 "$addr.base = $Rn_wb", []> { 3182 bits<10> offset; 3183 bits<4> addr; 3184 let Inst{23} = offset{8}; // U bit 3185 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 3186 let Inst{19-16} = addr; 3187 let Inst{11-8} = offset{7-4}; // imm7_4/zero 3188 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 3189 let DecoderMethod = "DecodeAddrMode3Instruction"; 3190} 3191} // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 3192 3193// STRT, STRBT, and STRHT 3194 3195def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3196 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3197 IndexModePost, StFrm, IIC_iStore_bh_ru, 3198 "strbt", "\t$Rt, $addr, $offset", 3199 "$addr.base = $Rn_wb", []> { 3200 // {12} isAdd 3201 // {11-0} imm12/Rm 3202 bits<14> offset; 3203 bits<4> addr; 3204 let Inst{25} = 1; 3205 let Inst{23} = offset{12}; 3206 let Inst{21} = 1; // overwrite 3207 let Inst{19-16} = addr; 3208 let Inst{11-5} = offset{11-5}; 3209 let Inst{4} = 0; 3210 let Inst{3-0} = offset{3-0}; 3211 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3212} 3213 3214def STRBT_POST_IMM 3215 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3216 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3217 IndexModePost, StFrm, IIC_iStore_bh_ru, 3218 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3219 // {12} isAdd 3220 // {11-0} imm12/Rm 3221 bits<14> offset; 3222 bits<4> addr; 3223 let Inst{25} = 0; 3224 let Inst{23} = offset{12}; 3225 let Inst{21} = 1; // overwrite 3226 let Inst{19-16} = addr; 3227 let Inst{11-0} = offset{11-0}; 3228 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3229} 3230 3231def STRBT_POST 3232 : ARMAsmPseudo<"strbt${q} $Rt, $addr", 3233 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3234 3235let mayStore = 1, hasSideEffects = 0 in { 3236def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3237 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3238 IndexModePost, StFrm, IIC_iStore_ru, 3239 "strt", "\t$Rt, $addr, $offset", 3240 "$addr.base = $Rn_wb", []> { 3241 // {12} isAdd 3242 // {11-0} imm12/Rm 3243 bits<14> offset; 3244 bits<4> addr; 3245 let Inst{25} = 1; 3246 let Inst{23} = offset{12}; 3247 let Inst{21} = 1; // overwrite 3248 let Inst{19-16} = addr; 3249 let Inst{11-5} = offset{11-5}; 3250 let Inst{4} = 0; 3251 let Inst{3-0} = offset{3-0}; 3252 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3253} 3254 3255def STRT_POST_IMM 3256 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3257 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3258 IndexModePost, StFrm, IIC_iStore_ru, 3259 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3260 // {12} isAdd 3261 // {11-0} imm12/Rm 3262 bits<14> offset; 3263 bits<4> addr; 3264 let Inst{25} = 0; 3265 let Inst{23} = offset{12}; 3266 let Inst{21} = 1; // overwrite 3267 let Inst{19-16} = addr; 3268 let Inst{11-0} = offset{11-0}; 3269 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3270} 3271} 3272 3273def STRT_POST 3274 : ARMAsmPseudo<"strt${q} $Rt, $addr", 3275 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3276 3277multiclass AI3strT<bits<4> op, string opc> { 3278 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3279 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset), 3280 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3281 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 3282 bits<9> offset; 3283 let Inst{23} = offset{8}; 3284 let Inst{22} = 1; 3285 let Inst{11-8} = offset{7-4}; 3286 let Inst{3-0} = offset{3-0}; 3287 } 3288 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3289 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm), 3290 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3291 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 3292 bits<5> Rm; 3293 let Inst{23} = Rm{4}; 3294 let Inst{22} = 0; 3295 let Inst{11-8} = 0; 3296 let Inst{3-0} = Rm{3-0}; 3297 } 3298} 3299 3300 3301defm STRHT : AI3strT<0b1011, "strht">; 3302 3303def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3304 NoItinerary, "stl", "\t$Rt, $addr", []>; 3305def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3306 NoItinerary, "stlb", "\t$Rt, $addr", []>; 3307def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3308 NoItinerary, "stlh", "\t$Rt, $addr", []>; 3309 3310//===----------------------------------------------------------------------===// 3311// Load / store multiple Instructions. 3312// 3313 3314multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f, 3315 InstrItinClass itin, InstrItinClass itin_upd> { 3316 // IA is the default, so no need for an explicit suffix on the 3317 // mnemonic here. Without it is the canonical spelling. 3318 def IA : 3319 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3320 IndexModeNone, f, itin, 3321 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> { 3322 let Inst{24-23} = 0b01; // Increment After 3323 let Inst{22} = P_bit; 3324 let Inst{21} = 0; // No writeback 3325 let Inst{20} = L_bit; 3326 } 3327 def IA_UPD : 3328 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3329 IndexModeUpd, f, itin_upd, 3330 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3331 let Inst{24-23} = 0b01; // Increment After 3332 let Inst{22} = P_bit; 3333 let Inst{21} = 1; // Writeback 3334 let Inst{20} = L_bit; 3335 3336 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3337 } 3338 def DA : 3339 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3340 IndexModeNone, f, itin, 3341 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> { 3342 let Inst{24-23} = 0b00; // Decrement After 3343 let Inst{22} = P_bit; 3344 let Inst{21} = 0; // No writeback 3345 let Inst{20} = L_bit; 3346 } 3347 def DA_UPD : 3348 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3349 IndexModeUpd, f, itin_upd, 3350 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3351 let Inst{24-23} = 0b00; // Decrement After 3352 let Inst{22} = P_bit; 3353 let Inst{21} = 1; // Writeback 3354 let Inst{20} = L_bit; 3355 3356 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3357 } 3358 def DB : 3359 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3360 IndexModeNone, f, itin, 3361 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> { 3362 let Inst{24-23} = 0b10; // Decrement Before 3363 let Inst{22} = P_bit; 3364 let Inst{21} = 0; // No writeback 3365 let Inst{20} = L_bit; 3366 } 3367 def DB_UPD : 3368 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3369 IndexModeUpd, f, itin_upd, 3370 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3371 let Inst{24-23} = 0b10; // Decrement Before 3372 let Inst{22} = P_bit; 3373 let Inst{21} = 1; // Writeback 3374 let Inst{20} = L_bit; 3375 3376 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3377 } 3378 def IB : 3379 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3380 IndexModeNone, f, itin, 3381 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> { 3382 let Inst{24-23} = 0b11; // Increment Before 3383 let Inst{22} = P_bit; 3384 let Inst{21} = 0; // No writeback 3385 let Inst{20} = L_bit; 3386 } 3387 def IB_UPD : 3388 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3389 IndexModeUpd, f, itin_upd, 3390 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3391 let Inst{24-23} = 0b11; // Increment Before 3392 let Inst{22} = P_bit; 3393 let Inst{21} = 1; // Writeback 3394 let Inst{20} = L_bit; 3395 3396 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3397 } 3398} 3399 3400let hasSideEffects = 0 in { 3401 3402let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in 3403defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m, 3404 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">; 3405 3406let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3407defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m, 3408 IIC_iStore_mu>, 3409 ComplexDeprecationPredicate<"ARMStore">; 3410 3411} // hasSideEffects 3412 3413// FIXME: remove when we have a way to marking a MI with these properties. 3414// FIXME: Should pc be an implicit operand like PICADD, etc? 3415let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 3416 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 3417def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 3418 reglist:$regs, variable_ops), 3419 4, IIC_iLoad_mBr, [], 3420 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 3421 RegConstraint<"$Rn = $wb">; 3422 3423let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 3424defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m, 3425 IIC_iLoad_mu>; 3426 3427let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3428defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m, 3429 IIC_iStore_mu>; 3430 3431 3432 3433//===----------------------------------------------------------------------===// 3434// Move Instructions. 3435// 3436 3437let hasSideEffects = 0, isMoveReg = 1 in 3438def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr, 3439 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3440 bits<4> Rd; 3441 bits<4> Rm; 3442 3443 let Inst{19-16} = 0b0000; 3444 let Inst{11-4} = 0b00000000; 3445 let Inst{25} = 0; 3446 let Inst{3-0} = Rm; 3447 let Inst{15-12} = Rd; 3448} 3449 3450// A version for the smaller set of tail call registers. 3451let hasSideEffects = 0 in 3452def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, 3453 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3454 bits<4> Rd; 3455 bits<4> Rm; 3456 3457 let Inst{11-4} = 0b00000000; 3458 let Inst{25} = 0; 3459 let Inst{3-0} = Rm; 3460 let Inst{15-12} = Rd; 3461} 3462 3463def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src), 3464 DPSoRegRegFrm, IIC_iMOVsr, 3465 "mov", "\t$Rd, $src", 3466 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP, 3467 Sched<[WriteALU]> { 3468 bits<4> Rd; 3469 bits<12> src; 3470 let Inst{15-12} = Rd; 3471 let Inst{19-16} = 0b0000; 3472 let Inst{11-8} = src{11-8}; 3473 let Inst{7} = 0; 3474 let Inst{6-5} = src{6-5}; 3475 let Inst{4} = 1; 3476 let Inst{3-0} = src{3-0}; 3477 let Inst{25} = 0; 3478} 3479 3480def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src), 3481 DPSoRegImmFrm, IIC_iMOVsr, 3482 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>, 3483 UnaryDP, Sched<[WriteALU]> { 3484 bits<4> Rd; 3485 bits<12> src; 3486 let Inst{15-12} = Rd; 3487 let Inst{19-16} = 0b0000; 3488 let Inst{11-5} = src{11-5}; 3489 let Inst{4} = 0; 3490 let Inst{3-0} = src{3-0}; 3491 let Inst{25} = 0; 3492} 3493 3494let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3495def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi, 3496 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP, 3497 Sched<[WriteALU]> { 3498 bits<4> Rd; 3499 bits<12> imm; 3500 let Inst{25} = 1; 3501 let Inst{15-12} = Rd; 3502 let Inst{19-16} = 0b0000; 3503 let Inst{11-0} = imm; 3504} 3505 3506let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3507def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm), 3508 DPFrm, IIC_iMOVi, 3509 "movw", "\t$Rd, $imm", 3510 [(set GPR:$Rd, imm0_65535:$imm)]>, 3511 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> { 3512 bits<4> Rd; 3513 bits<16> imm; 3514 let Inst{15-12} = Rd; 3515 let Inst{11-0} = imm{11-0}; 3516 let Inst{19-16} = imm{15-12}; 3517 let Inst{20} = 0; 3518 let Inst{25} = 1; 3519 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3520} 3521 3522def : InstAlias<"mov${p} $Rd, $imm", 3523 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p), 0>, 3524 Requires<[IsARM, HasV6T2]>; 3525 3526def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3527 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3528 Sched<[WriteALU]>; 3529 3530let Constraints = "$src = $Rd" in { 3531def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd), 3532 (ins GPR:$src, imm0_65535_expr:$imm), 3533 DPFrm, IIC_iMOVi, 3534 "movt", "\t$Rd, $imm", 3535 [(set GPRnopc:$Rd, 3536 (or (and GPR:$src, 0xffff), 3537 lo16AllZero:$imm))]>, UnaryDP, 3538 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> { 3539 bits<4> Rd; 3540 bits<16> imm; 3541 let Inst{15-12} = Rd; 3542 let Inst{11-0} = imm{11-0}; 3543 let Inst{19-16} = imm{15-12}; 3544 let Inst{20} = 0; 3545 let Inst{25} = 1; 3546 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3547} 3548 3549def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3550 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3551 Sched<[WriteALU]>; 3552 3553} // Constraints 3554 3555def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>, 3556 Requires<[IsARM, HasV6T2]>; 3557 3558let Uses = [CPSR] in 3559def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, 3560 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP, 3561 Requires<[IsARM]>, Sched<[WriteALU]>; 3562 3563// These aren't really mov instructions, but we have to define them this way 3564// due to flag operands. 3565 3566let Defs = [CPSR] in { 3567def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3568 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP, 3569 Sched<[WriteALU]>, Requires<[IsARM]>; 3570def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3571 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP, 3572 Sched<[WriteALU]>, Requires<[IsARM]>; 3573} 3574 3575//===----------------------------------------------------------------------===// 3576// Extend Instructions. 3577// 3578 3579// Sign extenders 3580 3581def SXTB : AI_ext_rrot<0b01101010, 3582 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 3583def SXTH : AI_ext_rrot<0b01101011, 3584 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 3585 3586def SXTAB : AI_exta_rrot<0b01101010, 3587 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 3588def SXTAH : AI_exta_rrot<0b01101011, 3589 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 3590 3591def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8)), 3592 (SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3593def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot), 3594 i16)), 3595 (SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3596 3597def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; 3598def : ARMV6Pat<(int_arm_sxtb16 GPR:$Src), 3599 (SXTB16 GPR:$Src, 0)>; 3600def : ARMV6Pat<(int_arm_sxtb16 (rotr GPR:$Src, rot_imm:$rot)), 3601 (SXTB16 GPR:$Src, rot_imm:$rot)>; 3602 3603def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; 3604def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, GPR:$RHS), 3605 (SXTAB16 GPR:$LHS, GPR:$RHS, 0)>; 3606def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)), 3607 (SXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>; 3608 3609// Zero extenders 3610 3611let AddedComplexity = 16 in { 3612def UXTB : AI_ext_rrot<0b01101110, 3613 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 3614def UXTH : AI_ext_rrot<0b01101111, 3615 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 3616def UXTB16 : AI_ext_rrot<0b01101100, 3617 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 3618 3619// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 3620// The transformation should probably be done as a combiner action 3621// instead so we can include a check for masking back in the upper 3622// eight bits of the source into the lower eight bits of the result. 3623//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 3624// (UXTB16r_rot GPR:$Src, 3)>; 3625def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 3626 (UXTB16 GPR:$Src, 1)>; 3627def : ARMV6Pat<(int_arm_uxtb16 GPR:$Src), 3628 (UXTB16 GPR:$Src, 0)>; 3629def : ARMV6Pat<(int_arm_uxtb16 (rotr GPR:$Src, rot_imm:$rot)), 3630 (UXTB16 GPR:$Src, rot_imm:$rot)>; 3631 3632def UXTAB : AI_exta_rrot<0b01101110, "uxtab", 3633 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 3634def UXTAH : AI_exta_rrot<0b01101111, "uxtah", 3635 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 3636 3637def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 0xFF)), 3638 (UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3639def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 0xFFFF)), 3640 (UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3641} 3642 3643// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 3644def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; 3645def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, GPR:$RHS), 3646 (UXTAB16 GPR:$LHS, GPR:$RHS, 0)>; 3647def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)), 3648 (UXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>; 3649 3650 3651def SBFX : I<(outs GPRnopc:$Rd), 3652 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3653 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3654 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3655 Requires<[IsARM, HasV6T2]> { 3656 bits<4> Rd; 3657 bits<4> Rn; 3658 bits<5> lsb; 3659 bits<5> width; 3660 let Inst{27-21} = 0b0111101; 3661 let Inst{6-4} = 0b101; 3662 let Inst{20-16} = width; 3663 let Inst{15-12} = Rd; 3664 let Inst{11-7} = lsb; 3665 let Inst{3-0} = Rn; 3666} 3667 3668def UBFX : I<(outs GPRnopc:$Rd), 3669 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3670 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3671 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3672 Requires<[IsARM, HasV6T2]> { 3673 bits<4> Rd; 3674 bits<4> Rn; 3675 bits<5> lsb; 3676 bits<5> width; 3677 let Inst{27-21} = 0b0111111; 3678 let Inst{6-4} = 0b101; 3679 let Inst{20-16} = width; 3680 let Inst{15-12} = Rd; 3681 let Inst{11-7} = lsb; 3682 let Inst{3-0} = Rn; 3683} 3684 3685//===----------------------------------------------------------------------===// 3686// Arithmetic Instructions. 3687// 3688 3689let isAdd = 1 in 3690defm ADD : AsI1_bin_irs<0b0100, "add", 3691 IIC_iALUi, IIC_iALUr, IIC_iALUsr, add, 1>; 3692defm SUB : AsI1_bin_irs<0b0010, "sub", 3693 IIC_iALUi, IIC_iALUr, IIC_iALUsr, sub>; 3694 3695// ADD and SUB with 's' bit set. 3696// 3697// Currently, ADDS/SUBS are pseudo opcodes that exist only in the 3698// selection DAG. They are "lowered" to real ADD/SUB opcodes by 3699// AdjustInstrPostInstrSelection where we determine whether or not to 3700// set the "s" bit based on CPSR liveness. 3701// 3702// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen 3703// support for an optional CPSR definition that corresponds to the DAG 3704// node's second value. We can then eliminate the implicit def of CPSR. 3705let isAdd = 1 in 3706defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMaddc, 1>; 3707defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>; 3708 3709def : ARMPat<(ARMsubs GPR:$Rn, mod_imm:$imm), (SUBSri $Rn, mod_imm:$imm)>; 3710def : ARMPat<(ARMsubs GPR:$Rn, GPR:$Rm), (SUBSrr $Rn, $Rm)>; 3711def : ARMPat<(ARMsubs GPR:$Rn, so_reg_imm:$shift), 3712 (SUBSrsi $Rn, so_reg_imm:$shift)>; 3713def : ARMPat<(ARMsubs GPR:$Rn, so_reg_reg:$shift), 3714 (SUBSrsr $Rn, so_reg_reg:$shift)>; 3715 3716 3717let isAdd = 1 in 3718defm ADC : AI1_adde_sube_irs<0b0101, "adc", ARMadde, 1>; 3719defm SBC : AI1_adde_sube_irs<0b0110, "sbc", ARMsube>; 3720 3721defm RSB : AsI1_rbin_irs<0b0011, "rsb", 3722 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3723 sub>; 3724 3725// FIXME: Eliminate them if we can write def : Pat patterns which defines 3726// CPSR and the implicit def of CPSR is not needed. 3727defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>; 3728 3729defm RSC : AI1_rsc_irs<0b0111, "rsc", ARMsube>; 3730 3731// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 3732// The assume-no-carry-in form uses the negation of the input since add/sub 3733// assume opposite meanings of the carry flag (i.e., carry == !borrow). 3734// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 3735// details. 3736def : ARMPat<(add GPR:$src, mod_imm_neg:$imm), 3737 (SUBri GPR:$src, mod_imm_neg:$imm)>; 3738def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm), 3739 (SUBSri GPR:$src, mod_imm_neg:$imm)>; 3740 3741def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm), 3742 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3743 Requires<[IsARM, HasV6T2]>; 3744def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm), 3745 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3746 Requires<[IsARM, HasV6T2]>; 3747 3748// The with-carry-in form matches bitwise not instead of the negation. 3749// Effectively, the inverse interpretation of the carry flag already accounts 3750// for part of the negation. 3751def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR), 3752 (SBCri GPR:$src, mod_imm_not:$imm)>; 3753def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR), 3754 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>, 3755 Requires<[IsARM, HasV6T2]>; 3756 3757// Note: These are implemented in C++ code, because they have to generate 3758// ADD/SUBrs instructions, which use a complex pattern that a xform function 3759// cannot produce. 3760// (mul X, 2^n+1) -> (add (X << n), X) 3761// (mul X, 2^n-1) -> (rsb X, (X << n)) 3762 3763// ARM Arithmetic Instruction 3764// GPR:$dst = GPR:$a op GPR:$b 3765class AAI<bits<8> op27_20, bits<8> op11_4, string opc, 3766 list<dag> pattern = [], 3767 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm), 3768 string asm = "\t$Rd, $Rn, $Rm"> 3769 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>, 3770 Sched<[WriteALU, ReadALU, ReadALU]> { 3771 bits<4> Rn; 3772 bits<4> Rd; 3773 bits<4> Rm; 3774 let Inst{27-20} = op27_20; 3775 let Inst{11-4} = op11_4; 3776 let Inst{19-16} = Rn; 3777 let Inst{15-12} = Rd; 3778 let Inst{3-0} = Rm; 3779 3780 let Unpredictable{11-8} = 0b1111; 3781} 3782 3783// Wrappers around the AAI class 3784class AAIRevOpr<bits<8> op27_20, bits<8> op11_4, string opc, 3785 list<dag> pattern = []> 3786 : AAI<op27_20, op11_4, opc, 3787 pattern, 3788 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3789 "\t$Rd, $Rm, $Rn">; 3790 3791class AAIIntrinsic<bits<8> op27_20, bits<8> op11_4, string opc, 3792 Intrinsic intrinsic> 3793 : AAI<op27_20, op11_4, opc, 3794 [(set GPRnopc:$Rd, (intrinsic GPRnopc:$Rn, GPRnopc:$Rm))]>; 3795 3796// Saturating add/subtract 3797let hasSideEffects = 1 in { 3798def QADD8 : AAIIntrinsic<0b01100010, 0b11111001, "qadd8", int_arm_qadd8>; 3799def QADD16 : AAIIntrinsic<0b01100010, 0b11110001, "qadd16", int_arm_qadd16>; 3800def QSUB16 : AAIIntrinsic<0b01100010, 0b11110111, "qsub16", int_arm_qsub16>; 3801def QSUB8 : AAIIntrinsic<0b01100010, 0b11111111, "qsub8", int_arm_qsub8>; 3802 3803def QDADD : AAIRevOpr<0b00010100, 0b00000101, "qdadd", 3804 [(set GPRnopc:$Rd, (int_arm_qadd (int_arm_qadd GPRnopc:$Rm, 3805 GPRnopc:$Rm), 3806 GPRnopc:$Rn))]>; 3807def QDSUB : AAIRevOpr<0b00010110, 0b00000101, "qdsub", 3808 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, 3809 (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>; 3810def QSUB : AAIRevOpr<0b00010010, 0b00000101, "qsub", 3811 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))]>; 3812let DecoderMethod = "DecodeQADDInstruction" in 3813 def QADD : AAIRevOpr<0b00010000, 0b00000101, "qadd", 3814 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))]>; 3815} 3816 3817def : ARMV5TEPat<(saddsat GPR:$a, GPR:$b), 3818 (QADD GPR:$a, GPR:$b)>; 3819def : ARMV5TEPat<(ssubsat GPR:$a, GPR:$b), 3820 (QSUB GPR:$a, GPR:$b)>; 3821def : ARMV5TEPat<(saddsat(saddsat rGPR:$Rm, rGPR:$Rm), rGPR:$Rn), 3822 (QDADD rGPR:$Rm, rGPR:$Rn)>; 3823def : ARMV5TEPat<(ssubsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)), 3824 (QDSUB rGPR:$Rm, rGPR:$Rn)>; 3825def : ARMV6Pat<(ARMqadd8b rGPR:$Rm, rGPR:$Rn), 3826 (QADD8 rGPR:$Rm, rGPR:$Rn)>; 3827def : ARMV6Pat<(ARMqsub8b rGPR:$Rm, rGPR:$Rn), 3828 (QSUB8 rGPR:$Rm, rGPR:$Rn)>; 3829def : ARMV6Pat<(ARMqadd16b rGPR:$Rm, rGPR:$Rn), 3830 (QADD16 rGPR:$Rm, rGPR:$Rn)>; 3831def : ARMV6Pat<(ARMqsub16b rGPR:$Rm, rGPR:$Rn), 3832 (QSUB16 rGPR:$Rm, rGPR:$Rn)>; 3833 3834def UQADD16 : AAIIntrinsic<0b01100110, 0b11110001, "uqadd16", int_arm_uqadd16>; 3835def UQADD8 : AAIIntrinsic<0b01100110, 0b11111001, "uqadd8", int_arm_uqadd8>; 3836def UQSUB16 : AAIIntrinsic<0b01100110, 0b11110111, "uqsub16", int_arm_uqsub16>; 3837def UQSUB8 : AAIIntrinsic<0b01100110, 0b11111111, "uqsub8", int_arm_uqsub8>; 3838def QASX : AAIIntrinsic<0b01100010, 0b11110011, "qasx", int_arm_qasx>; 3839def QSAX : AAIIntrinsic<0b01100010, 0b11110101, "qsax", int_arm_qsax>; 3840def UQASX : AAIIntrinsic<0b01100110, 0b11110011, "uqasx", int_arm_uqasx>; 3841def UQSAX : AAIIntrinsic<0b01100110, 0b11110101, "uqsax", int_arm_uqsax>; 3842 3843// Signed/Unsigned add/subtract 3844 3845def SASX : AAIIntrinsic<0b01100001, 0b11110011, "sasx", int_arm_sasx>; 3846def SADD16 : AAIIntrinsic<0b01100001, 0b11110001, "sadd16", int_arm_sadd16>; 3847def SADD8 : AAIIntrinsic<0b01100001, 0b11111001, "sadd8", int_arm_sadd8>; 3848def SSAX : AAIIntrinsic<0b01100001, 0b11110101, "ssax", int_arm_ssax>; 3849def SSUB16 : AAIIntrinsic<0b01100001, 0b11110111, "ssub16", int_arm_ssub16>; 3850def SSUB8 : AAIIntrinsic<0b01100001, 0b11111111, "ssub8", int_arm_ssub8>; 3851def UASX : AAIIntrinsic<0b01100101, 0b11110011, "uasx", int_arm_uasx>; 3852def UADD16 : AAIIntrinsic<0b01100101, 0b11110001, "uadd16", int_arm_uadd16>; 3853def UADD8 : AAIIntrinsic<0b01100101, 0b11111001, "uadd8", int_arm_uadd8>; 3854def USAX : AAIIntrinsic<0b01100101, 0b11110101, "usax", int_arm_usax>; 3855def USUB16 : AAIIntrinsic<0b01100101, 0b11110111, "usub16", int_arm_usub16>; 3856def USUB8 : AAIIntrinsic<0b01100101, 0b11111111, "usub8", int_arm_usub8>; 3857 3858// Signed/Unsigned halving add/subtract 3859 3860def SHASX : AAIIntrinsic<0b01100011, 0b11110011, "shasx", int_arm_shasx>; 3861def SHADD16 : AAIIntrinsic<0b01100011, 0b11110001, "shadd16", int_arm_shadd16>; 3862def SHADD8 : AAIIntrinsic<0b01100011, 0b11111001, "shadd8", int_arm_shadd8>; 3863def SHSAX : AAIIntrinsic<0b01100011, 0b11110101, "shsax", int_arm_shsax>; 3864def SHSUB16 : AAIIntrinsic<0b01100011, 0b11110111, "shsub16", int_arm_shsub16>; 3865def SHSUB8 : AAIIntrinsic<0b01100011, 0b11111111, "shsub8", int_arm_shsub8>; 3866def UHASX : AAIIntrinsic<0b01100111, 0b11110011, "uhasx", int_arm_uhasx>; 3867def UHADD16 : AAIIntrinsic<0b01100111, 0b11110001, "uhadd16", int_arm_uhadd16>; 3868def UHADD8 : AAIIntrinsic<0b01100111, 0b11111001, "uhadd8", int_arm_uhadd8>; 3869def UHSAX : AAIIntrinsic<0b01100111, 0b11110101, "uhsax", int_arm_uhsax>; 3870def UHSUB16 : AAIIntrinsic<0b01100111, 0b11110111, "uhsub16", int_arm_uhsub16>; 3871def UHSUB8 : AAIIntrinsic<0b01100111, 0b11111111, "uhsub8", int_arm_uhsub8>; 3872 3873// Unsigned Sum of Absolute Differences [and Accumulate]. 3874 3875def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3876 MulFrm /* for convenience */, NoItinerary, "usad8", 3877 "\t$Rd, $Rn, $Rm", 3878 [(set GPR:$Rd, (int_arm_usad8 GPR:$Rn, GPR:$Rm))]>, 3879 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> { 3880 bits<4> Rd; 3881 bits<4> Rn; 3882 bits<4> Rm; 3883 let Inst{27-20} = 0b01111000; 3884 let Inst{15-12} = 0b1111; 3885 let Inst{7-4} = 0b0001; 3886 let Inst{19-16} = Rd; 3887 let Inst{11-8} = Rm; 3888 let Inst{3-0} = Rn; 3889} 3890def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3891 MulFrm /* for convenience */, NoItinerary, "usada8", 3892 "\t$Rd, $Rn, $Rm, $Ra", 3893 [(set GPR:$Rd, (int_arm_usada8 GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 3894 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{ 3895 bits<4> Rd; 3896 bits<4> Rn; 3897 bits<4> Rm; 3898 bits<4> Ra; 3899 let Inst{27-20} = 0b01111000; 3900 let Inst{7-4} = 0b0001; 3901 let Inst{19-16} = Rd; 3902 let Inst{15-12} = Ra; 3903 let Inst{11-8} = Rm; 3904 let Inst{3-0} = Rn; 3905} 3906 3907// Signed/Unsigned saturate 3908def SSAT : AI<(outs GPRnopc:$Rd), 3909 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3910 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>, 3911 Requires<[IsARM,HasV6]>{ 3912 bits<4> Rd; 3913 bits<5> sat_imm; 3914 bits<4> Rn; 3915 bits<8> sh; 3916 let Inst{27-21} = 0b0110101; 3917 let Inst{5-4} = 0b01; 3918 let Inst{20-16} = sat_imm; 3919 let Inst{15-12} = Rd; 3920 let Inst{11-7} = sh{4-0}; 3921 let Inst{6} = sh{5}; 3922 let Inst{3-0} = Rn; 3923} 3924 3925def SSAT16 : AI<(outs GPRnopc:$Rd), 3926 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm, 3927 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []>, 3928 Requires<[IsARM,HasV6]>{ 3929 bits<4> Rd; 3930 bits<4> sat_imm; 3931 bits<4> Rn; 3932 let Inst{27-20} = 0b01101010; 3933 let Inst{11-4} = 0b11110011; 3934 let Inst{15-12} = Rd; 3935 let Inst{19-16} = sat_imm; 3936 let Inst{3-0} = Rn; 3937} 3938 3939def USAT : AI<(outs GPRnopc:$Rd), 3940 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3941 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>, 3942 Requires<[IsARM,HasV6]> { 3943 bits<4> Rd; 3944 bits<5> sat_imm; 3945 bits<4> Rn; 3946 bits<8> sh; 3947 let Inst{27-21} = 0b0110111; 3948 let Inst{5-4} = 0b01; 3949 let Inst{15-12} = Rd; 3950 let Inst{11-7} = sh{4-0}; 3951 let Inst{6} = sh{5}; 3952 let Inst{20-16} = sat_imm; 3953 let Inst{3-0} = Rn; 3954} 3955 3956def USAT16 : AI<(outs GPRnopc:$Rd), 3957 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm, 3958 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []>, 3959 Requires<[IsARM,HasV6]>{ 3960 bits<4> Rd; 3961 bits<4> sat_imm; 3962 bits<4> Rn; 3963 let Inst{27-20} = 0b01101110; 3964 let Inst{11-4} = 0b11110011; 3965 let Inst{15-12} = Rd; 3966 let Inst{19-16} = sat_imm; 3967 let Inst{3-0} = Rn; 3968} 3969 3970def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos), 3971 (SSAT imm1_32:$pos, GPRnopc:$a, 0)>; 3972def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos), 3973 (USAT imm0_31:$pos, GPRnopc:$a, 0)>; 3974def : ARMPat<(ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm), 3975 (SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 3976def : ARMPat<(ARMusatnoshift GPRnopc:$Rn, imm0_31:$imm), 3977 (USAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 3978def : ARMV6Pat<(int_arm_ssat16 GPRnopc:$a, imm1_16:$pos), 3979 (SSAT16 imm1_16:$pos, GPRnopc:$a)>; 3980def : ARMV6Pat<(int_arm_usat16 GPRnopc:$a, imm0_15:$pos), 3981 (USAT16 imm0_15:$pos, GPRnopc:$a)>; 3982 3983//===----------------------------------------------------------------------===// 3984// Bitwise Instructions. 3985// 3986 3987defm AND : AsI1_bin_irs<0b0000, "and", 3988 IIC_iBITi, IIC_iBITr, IIC_iBITsr, and, 1>; 3989defm ORR : AsI1_bin_irs<0b1100, "orr", 3990 IIC_iBITi, IIC_iBITr, IIC_iBITsr, or, 1>; 3991defm EOR : AsI1_bin_irs<0b0001, "eor", 3992 IIC_iBITi, IIC_iBITr, IIC_iBITsr, xor, 1>; 3993defm BIC : AsI1_bin_irs<0b1110, "bic", 3994 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3995 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 3996 3997// FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just 3998// like in the actual instruction encoding. The complexity of mapping the mask 3999// to the lsb/msb pair should be handled by ISel, not encapsulated in the 4000// instruction description. 4001def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), 4002 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 4003 "bfc", "\t$Rd, $imm", "$src = $Rd", 4004 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>, 4005 Requires<[IsARM, HasV6T2]> { 4006 bits<4> Rd; 4007 bits<10> imm; 4008 let Inst{27-21} = 0b0111110; 4009 let Inst{6-0} = 0b0011111; 4010 let Inst{15-12} = Rd; 4011 let Inst{11-7} = imm{4-0}; // lsb 4012 let Inst{20-16} = imm{9-5}; // msb 4013} 4014 4015// A8.6.18 BFI - Bitfield insert (Encoding A1) 4016def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm), 4017 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 4018 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd", 4019 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn, 4020 bf_inv_mask_imm:$imm))]>, 4021 Requires<[IsARM, HasV6T2]> { 4022 bits<4> Rd; 4023 bits<4> Rn; 4024 bits<10> imm; 4025 let Inst{27-21} = 0b0111110; 4026 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 4027 let Inst{15-12} = Rd; 4028 let Inst{11-7} = imm{4-0}; // lsb 4029 let Inst{20-16} = imm{9-5}; // width 4030 let Inst{3-0} = Rn; 4031} 4032 4033def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr, 4034 "mvn", "\t$Rd, $Rm", 4035 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> { 4036 bits<4> Rd; 4037 bits<4> Rm; 4038 let Inst{25} = 0; 4039 let Inst{19-16} = 0b0000; 4040 let Inst{11-4} = 0b00000000; 4041 let Inst{15-12} = Rd; 4042 let Inst{3-0} = Rm; 4043 4044 let Unpredictable{19-16} = 0b1111; 4045} 4046def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift), 4047 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 4048 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP, 4049 Sched<[WriteALU]> { 4050 bits<4> Rd; 4051 bits<12> shift; 4052 let Inst{25} = 0; 4053 let Inst{19-16} = 0b0000; 4054 let Inst{15-12} = Rd; 4055 let Inst{11-5} = shift{11-5}; 4056 let Inst{4} = 0; 4057 let Inst{3-0} = shift{3-0}; 4058 4059 let Unpredictable{19-16} = 0b1111; 4060} 4061def MVNsr : AsI1<0b1111, (outs GPRnopc:$Rd), (ins so_reg_reg:$shift), 4062 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 4063 [(set GPRnopc:$Rd, (not so_reg_reg:$shift))]>, UnaryDP, 4064 Sched<[WriteALU]> { 4065 bits<4> Rd; 4066 bits<12> shift; 4067 let Inst{25} = 0; 4068 let Inst{19-16} = 0b0000; 4069 let Inst{15-12} = Rd; 4070 let Inst{11-8} = shift{11-8}; 4071 let Inst{7} = 0; 4072 let Inst{6-5} = shift{6-5}; 4073 let Inst{4} = 1; 4074 let Inst{3-0} = shift{3-0}; 4075 4076 let Unpredictable{19-16} = 0b1111; 4077} 4078let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 4079def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, 4080 IIC_iMVNi, "mvn", "\t$Rd, $imm", 4081 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> { 4082 bits<4> Rd; 4083 bits<12> imm; 4084 let Inst{25} = 1; 4085 let Inst{19-16} = 0b0000; 4086 let Inst{15-12} = Rd; 4087 let Inst{11-0} = imm; 4088} 4089 4090let AddedComplexity = 1 in 4091def : ARMPat<(and GPR:$src, mod_imm_not:$imm), 4092 (BICri GPR:$src, mod_imm_not:$imm)>; 4093 4094//===----------------------------------------------------------------------===// 4095// Multiply Instructions. 4096// 4097class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4098 string opc, string asm, list<dag> pattern> 4099 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4100 bits<4> Rd; 4101 bits<4> Rm; 4102 bits<4> Rn; 4103 let Inst{19-16} = Rd; 4104 let Inst{11-8} = Rm; 4105 let Inst{3-0} = Rn; 4106} 4107class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4108 string opc, string asm, list<dag> pattern> 4109 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4110 bits<4> RdLo; 4111 bits<4> RdHi; 4112 bits<4> Rm; 4113 bits<4> Rn; 4114 let Inst{19-16} = RdHi; 4115 let Inst{15-12} = RdLo; 4116 let Inst{11-8} = Rm; 4117 let Inst{3-0} = Rn; 4118} 4119class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4120 string opc, string asm, list<dag> pattern> 4121 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4122 bits<4> RdLo; 4123 bits<4> RdHi; 4124 bits<4> Rm; 4125 bits<4> Rn; 4126 let Inst{19-16} = RdHi; 4127 let Inst{15-12} = RdLo; 4128 let Inst{11-8} = Rm; 4129 let Inst{3-0} = Rn; 4130} 4131 4132// FIXME: The v5 pseudos are only necessary for the additional Constraint 4133// property. Remove them when it's possible to add those properties 4134// on an individual MachineInstr, not just an instruction description. 4135let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in { 4136def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), 4137 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4138 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", 4139 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>, 4140 Requires<[IsARM, HasV6]>, 4141 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4142 let Inst{15-12} = 0b0000; 4143 let Unpredictable{15-12} = 0b1111; 4144} 4145 4146let Constraints = "@earlyclobber $Rd" in 4147def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, 4148 pred:$p, cc_out:$s), 4149 4, IIC_iMUL32, 4150 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))], 4151 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 4152 Requires<[IsARM, NoV6, UseMulOps]>, 4153 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4154} 4155 4156def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd), 4157 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra), 4158 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra", 4159 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>, 4160 Requires<[IsARM, HasV6, UseMulOps]>, 4161 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 4162 bits<4> Ra; 4163 let Inst{15-12} = Ra; 4164} 4165 4166let Constraints = "@earlyclobber $Rd" in 4167def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd), 4168 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 4169 pred:$p, cc_out:$s), 4, IIC_iMAC32, 4170 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))], 4171 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>, 4172 Requires<[IsARM, NoV6]>, 4173 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4174 4175def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4176 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra", 4177 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>, 4178 Requires<[IsARM, HasV6T2, UseMulOps]>, 4179 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 4180 bits<4> Rd; 4181 bits<4> Rm; 4182 bits<4> Rn; 4183 bits<4> Ra; 4184 let Inst{19-16} = Rd; 4185 let Inst{15-12} = Ra; 4186 let Inst{11-8} = Rm; 4187 let Inst{3-0} = Rn; 4188} 4189 4190// Extra precision multiplies with low / high results 4191let hasSideEffects = 0 in { 4192let isCommutable = 1 in { 4193def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi), 4194 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 4195 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", 4196 [(set GPR:$RdLo, GPR:$RdHi, 4197 (smullohi GPR:$Rn, GPR:$Rm))]>, 4198 Requires<[IsARM, HasV6]>, 4199 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4200 4201def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), 4202 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 4203 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", 4204 [(set GPR:$RdLo, GPR:$RdHi, 4205 (umullohi GPR:$Rn, GPR:$Rm))]>, 4206 Requires<[IsARM, HasV6]>, 4207 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL]>; 4208 4209let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { 4210def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4211 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 4212 4, IIC_iMUL64, 4213 [(set GPR:$RdLo, GPR:$RdHi, 4214 (smullohi GPR:$Rn, GPR:$Rm))], 4215 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 4216 Requires<[IsARM, NoV6]>, 4217 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4218 4219def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4220 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 4221 4, IIC_iMUL64, 4222 [(set GPR:$RdLo, GPR:$RdHi, 4223 (umullohi GPR:$Rn, GPR:$Rm))], 4224 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 4225 Requires<[IsARM, NoV6]>, 4226 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4227} 4228} 4229 4230// Multiply + accumulate 4231def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi), 4232 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4233 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4234 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4235 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4236def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi), 4237 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4238 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4239 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4240 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4241 4242def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi), 4243 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4244 IIC_iMAC64, 4245 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4246 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4247 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> { 4248 bits<4> RdLo; 4249 bits<4> RdHi; 4250 bits<4> Rm; 4251 bits<4> Rn; 4252 let Inst{19-16} = RdHi; 4253 let Inst{15-12} = RdLo; 4254 let Inst{11-8} = Rm; 4255 let Inst{3-0} = Rn; 4256} 4257 4258let Constraints = 4259 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in { 4260def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4261 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4262 4, IIC_iMAC64, [], 4263 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4264 pred:$p, cc_out:$s)>, 4265 Requires<[IsARM, NoV6]>, 4266 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4267def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4268 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4269 4, IIC_iMAC64, [], 4270 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4271 pred:$p, cc_out:$s)>, 4272 Requires<[IsARM, NoV6]>, 4273 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4274} 4275 4276} // hasSideEffects 4277 4278// Most significant word multiply 4279def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4280 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm", 4281 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>, 4282 Requires<[IsARM, HasV6]>, 4283 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4284 let Inst{15-12} = 0b1111; 4285} 4286 4287def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4288 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", 4289 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, (i32 0)))]>, 4290 Requires<[IsARM, HasV6]>, 4291 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4292 let Inst{15-12} = 0b1111; 4293} 4294 4295def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd), 4296 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4297 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra", 4298 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, 4299 Requires<[IsARM, HasV6, UseMulOps]>, 4300 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4301 4302def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd), 4303 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4304 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", 4305 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 4306 Requires<[IsARM, HasV6]>, 4307 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4308 4309def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd), 4310 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4311 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>, 4312 Requires<[IsARM, HasV6, UseMulOps]>, 4313 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4314 4315def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd), 4316 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4317 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", 4318 [(set GPR:$Rd, (ARMsmmlsr GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 4319 Requires<[IsARM, HasV6]>, 4320 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4321 4322multiclass AI_smul<string opc> { 4323 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4324 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 4325 [(set GPR:$Rd, (bb_mul GPR:$Rn, GPR:$Rm))]>, 4326 Requires<[IsARM, HasV5TE]>, 4327 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4328 4329 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4330 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 4331 [(set GPR:$Rd, (bt_mul GPR:$Rn, GPR:$Rm))]>, 4332 Requires<[IsARM, HasV5TE]>, 4333 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4334 4335 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4336 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 4337 [(set GPR:$Rd, (tb_mul GPR:$Rn, GPR:$Rm))]>, 4338 Requires<[IsARM, HasV5TE]>, 4339 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4340 4341 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4342 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 4343 [(set GPR:$Rd, (tt_mul GPR:$Rn, GPR:$Rm))]>, 4344 Requires<[IsARM, HasV5TE]>, 4345 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4346 4347 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4348 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 4349 [(set GPR:$Rd, (ARMsmulwb GPR:$Rn, GPR:$Rm))]>, 4350 Requires<[IsARM, HasV5TE]>, 4351 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4352 4353 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4354 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 4355 [(set GPR:$Rd, (ARMsmulwt GPR:$Rn, GPR:$Rm))]>, 4356 Requires<[IsARM, HasV5TE]>, 4357 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4358} 4359 4360 4361multiclass AI_smla<string opc> { 4362 let DecoderMethod = "DecodeSMLAInstruction" in { 4363 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd), 4364 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4365 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 4366 [(set GPRnopc:$Rd, (add GPR:$Ra, 4367 (bb_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4368 Requires<[IsARM, HasV5TE, UseMulOps]>, 4369 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4370 4371 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd), 4372 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4373 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 4374 [(set GPRnopc:$Rd, (add GPR:$Ra, 4375 (bt_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4376 Requires<[IsARM, HasV5TE, UseMulOps]>, 4377 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4378 4379 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd), 4380 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4381 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 4382 [(set GPRnopc:$Rd, (add GPR:$Ra, 4383 (tb_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4384 Requires<[IsARM, HasV5TE, UseMulOps]>, 4385 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4386 4387 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd), 4388 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4389 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 4390 [(set GPRnopc:$Rd, (add GPR:$Ra, 4391 (tt_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4392 Requires<[IsARM, HasV5TE, UseMulOps]>, 4393 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4394 4395 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd), 4396 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4397 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 4398 [(set GPRnopc:$Rd, 4399 (add GPR:$Ra, (ARMsmulwb GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4400 Requires<[IsARM, HasV5TE, UseMulOps]>, 4401 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4402 4403 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd), 4404 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4405 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 4406 [(set GPRnopc:$Rd, 4407 (add GPR:$Ra, (ARMsmulwt GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4408 Requires<[IsARM, HasV5TE, UseMulOps]>, 4409 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4410 } 4411} 4412 4413defm SMUL : AI_smul<"smul">; 4414defm SMLA : AI_smla<"smla">; 4415 4416// Halfword multiply accumulate long: SMLAL<x><y>. 4417class SMLAL<bits<2> opc1, string asm> 4418 : AMulxyI64<0b0001010, opc1, 4419 (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4420 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4421 IIC_iMAC64, asm, "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4422 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4423 Requires<[IsARM, HasV5TE]>, 4424 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4425 4426def SMLALBB : SMLAL<0b00, "smlalbb">; 4427def SMLALBT : SMLAL<0b10, "smlalbt">; 4428def SMLALTB : SMLAL<0b01, "smlaltb">; 4429def SMLALTT : SMLAL<0b11, "smlaltt">; 4430 4431def : ARMV5TEPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4432 (SMLALBB $Rn, $Rm, $RLo, $RHi)>; 4433def : ARMV5TEPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4434 (SMLALBT $Rn, $Rm, $RLo, $RHi)>; 4435def : ARMV5TEPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4436 (SMLALTB $Rn, $Rm, $RLo, $RHi)>; 4437def : ARMV5TEPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4438 (SMLALTT $Rn, $Rm, $RLo, $RHi)>; 4439 4440// Helper class for AI_smld. 4441class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops, 4442 InstrItinClass itin, string opc, string asm> 4443 : AI<oops, iops, MulFrm, itin, opc, asm, []>, 4444 Requires<[IsARM, HasV6]> { 4445 bits<4> Rn; 4446 bits<4> Rm; 4447 let Inst{27-23} = 0b01110; 4448 let Inst{22} = long; 4449 let Inst{21-20} = 0b00; 4450 let Inst{11-8} = Rm; 4451 let Inst{7} = 0; 4452 let Inst{6} = sub; 4453 let Inst{5} = swap; 4454 let Inst{4} = 1; 4455 let Inst{3-0} = Rn; 4456} 4457class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops, 4458 InstrItinClass itin, string opc, string asm> 4459 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4460 bits<4> Rd; 4461 let Inst{15-12} = 0b1111; 4462 let Inst{19-16} = Rd; 4463} 4464class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops, 4465 InstrItinClass itin, string opc, string asm> 4466 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4467 bits<4> Ra; 4468 bits<4> Rd; 4469 let Inst{19-16} = Rd; 4470 let Inst{15-12} = Ra; 4471} 4472class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops, 4473 InstrItinClass itin, string opc, string asm> 4474 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4475 bits<4> RdLo; 4476 bits<4> RdHi; 4477 let Inst{19-16} = RdHi; 4478 let Inst{15-12} = RdLo; 4479} 4480 4481multiclass AI_smld<bit sub, string opc> { 4482 4483 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd), 4484 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4485 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">, 4486 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4487 4488 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd), 4489 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4490 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">, 4491 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4492 4493 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4494 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4495 NoItinerary, 4496 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">, 4497 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4498 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4499 4500 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4501 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4502 NoItinerary, 4503 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">, 4504 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4505 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4506} 4507 4508defm SMLA : AI_smld<0, "smla">; 4509defm SMLS : AI_smld<1, "smls">; 4510 4511def : ARMV6Pat<(int_arm_smlad GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4512 (SMLAD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4513def : ARMV6Pat<(int_arm_smladx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4514 (SMLADX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4515def : ARMV6Pat<(int_arm_smlsd GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4516 (SMLSD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4517def : ARMV6Pat<(int_arm_smlsdx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4518 (SMLSDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4519def : ARMV6Pat<(ARMSmlald GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4520 (SMLALD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4521def : ARMV6Pat<(ARMSmlaldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4522 (SMLALDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4523def : ARMV6Pat<(ARMSmlsld GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4524 (SMLSLD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4525def : ARMV6Pat<(ARMSmlsldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4526 (SMLSLDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4527 4528multiclass AI_sdml<bit sub, string opc> { 4529 4530 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), 4531 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">, 4532 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4533 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm), 4534 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">, 4535 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4536} 4537 4538defm SMUA : AI_sdml<0, "smua">; 4539defm SMUS : AI_sdml<1, "smus">; 4540 4541def : ARMV6Pat<(int_arm_smuad GPRnopc:$Rn, GPRnopc:$Rm), 4542 (SMUAD GPRnopc:$Rn, GPRnopc:$Rm)>; 4543def : ARMV6Pat<(int_arm_smuadx GPRnopc:$Rn, GPRnopc:$Rm), 4544 (SMUADX GPRnopc:$Rn, GPRnopc:$Rm)>; 4545def : ARMV6Pat<(int_arm_smusd GPRnopc:$Rn, GPRnopc:$Rm), 4546 (SMUSD GPRnopc:$Rn, GPRnopc:$Rm)>; 4547def : ARMV6Pat<(int_arm_smusdx GPRnopc:$Rn, GPRnopc:$Rm), 4548 (SMUSDX GPRnopc:$Rn, GPRnopc:$Rm)>; 4549 4550//===----------------------------------------------------------------------===// 4551// Division Instructions (ARMv7-A with virtualization extension) 4552// 4553def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4554 "sdiv", "\t$Rd, $Rn, $Rm", 4555 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>, 4556 Requires<[IsARM, HasDivideInARM]>, 4557 Sched<[WriteDIV]>; 4558 4559def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4560 "udiv", "\t$Rd, $Rn, $Rm", 4561 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>, 4562 Requires<[IsARM, HasDivideInARM]>, 4563 Sched<[WriteDIV]>; 4564 4565//===----------------------------------------------------------------------===// 4566// Misc. Arithmetic Instructions. 4567// 4568 4569def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm), 4570 IIC_iUNAr, "clz", "\t$Rd, $Rm", 4571 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>, 4572 Sched<[WriteALU]>; 4573 4574def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4575 IIC_iUNAr, "rbit", "\t$Rd, $Rm", 4576 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>, 4577 Requires<[IsARM, HasV6T2]>, 4578 Sched<[WriteALU]>; 4579 4580def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4581 IIC_iUNAr, "rev", "\t$Rd, $Rm", 4582 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>, 4583 Sched<[WriteALU]>; 4584 4585let AddedComplexity = 5 in 4586def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4587 IIC_iUNAr, "rev16", "\t$Rd, $Rm", 4588 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>, 4589 Requires<[IsARM, HasV6]>, 4590 Sched<[WriteALU]>; 4591 4592def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)), 4593 (REV16 (LDRH addrmode3:$addr))>; 4594def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr), 4595 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>; 4596 4597let AddedComplexity = 5 in 4598def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4599 IIC_iUNAr, "revsh", "\t$Rd, $Rm", 4600 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>, 4601 Requires<[IsARM, HasV6]>, 4602 Sched<[WriteALU]>; 4603 4604def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)), 4605 (and (srl GPR:$Rm, (i32 8)), 0xFF)), 4606 (REVSH GPR:$Rm)>; 4607 4608def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd), 4609 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh), 4610 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 4611 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF), 4612 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh), 4613 0xFFFF0000)))]>, 4614 Requires<[IsARM, HasV6]>, 4615 Sched<[WriteALUsi, ReadALU]>; 4616 4617// Alternate cases for PKHBT where identities eliminate some nodes. 4618def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)), 4619 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>; 4620def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)), 4621 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>; 4622 4623// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 4624// will match the pattern below. 4625def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd), 4626 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh), 4627 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 4628 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000), 4629 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh), 4630 0xFFFF)))]>, 4631 Requires<[IsARM, HasV6]>, 4632 Sched<[WriteALUsi, ReadALU]>; 4633 4634// Alternate cases for PKHTB where identities eliminate some nodes. Note that 4635// a shift amount of 0 is *not legal* here, it is PKHBT instead. 4636// We also can not replace a srl (17..31) by an arithmetic shift we would use in 4637// pkhtb src1, src2, asr (17..31). 4638def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4639 (srl GPRnopc:$src2, imm16:$sh)), 4640 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>; 4641def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4642 (sra GPRnopc:$src2, imm16_31:$sh)), 4643 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>; 4644def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4645 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)), 4646 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>; 4647 4648//===----------------------------------------------------------------------===// 4649// CRC Instructions 4650// 4651// Polynomials: 4652// + CRC32{B,H,W} 0x04C11DB7 4653// + CRC32C{B,H,W} 0x1EDC6F41 4654// 4655 4656class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin> 4657 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary, 4658 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm", 4659 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>, 4660 Requires<[IsARM, HasV8, HasCRC]> { 4661 bits<4> Rd; 4662 bits<4> Rn; 4663 bits<4> Rm; 4664 4665 let Inst{31-28} = 0b1110; 4666 let Inst{27-23} = 0b00010; 4667 let Inst{22-21} = sz; 4668 let Inst{20} = 0; 4669 let Inst{19-16} = Rn; 4670 let Inst{15-12} = Rd; 4671 let Inst{11-10} = 0b00; 4672 let Inst{9} = C; 4673 let Inst{8} = 0; 4674 let Inst{7-4} = 0b0100; 4675 let Inst{3-0} = Rm; 4676 4677 let Unpredictable{11-8} = 0b1101; 4678} 4679 4680def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>; 4681def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>; 4682def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>; 4683def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>; 4684def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>; 4685def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>; 4686 4687//===----------------------------------------------------------------------===// 4688// ARMv8.1a Privilege Access Never extension 4689// 4690// SETPAN #imm1 4691 4692def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan", 4693 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> { 4694 bits<1> imm; 4695 4696 let Inst{31-28} = 0b1111; 4697 let Inst{27-20} = 0b00010001; 4698 let Inst{19-16} = 0b0000; 4699 let Inst{15-10} = 0b000000; 4700 let Inst{9} = imm; 4701 let Inst{8} = 0b0; 4702 let Inst{7-4} = 0b0000; 4703 let Inst{3-0} = 0b0000; 4704 4705 let Unpredictable{19-16} = 0b1111; 4706 let Unpredictable{15-10} = 0b111111; 4707 let Unpredictable{8} = 0b1; 4708 let Unpredictable{3-0} = 0b1111; 4709} 4710 4711//===----------------------------------------------------------------------===// 4712// Comparison Instructions... 4713// 4714 4715defm CMP : AI1_cmp_irs<0b1010, "cmp", 4716 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, ARMcmp>; 4717 4718// ARMcmpZ can re-use the above instruction definitions. 4719def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm), 4720 (CMPri GPR:$src, mod_imm:$imm)>; 4721def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs), 4722 (CMPrr GPR:$src, GPR:$rhs)>; 4723def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs), 4724 (CMPrsi GPR:$src, so_reg_imm:$rhs)>; 4725def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs), 4726 (CMPrsr GPR:$src, so_reg_reg:$rhs)>; 4727 4728// CMN register-integer 4729let isCompare = 1, Defs = [CPSR] in { 4730def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi, 4731 "cmn", "\t$Rn, $imm", 4732 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>, 4733 Sched<[WriteCMP, ReadALU]> { 4734 bits<4> Rn; 4735 bits<12> imm; 4736 let Inst{25} = 1; 4737 let Inst{20} = 1; 4738 let Inst{19-16} = Rn; 4739 let Inst{15-12} = 0b0000; 4740 let Inst{11-0} = imm; 4741 4742 let Unpredictable{15-12} = 0b1111; 4743} 4744 4745// CMN register-register/shift 4746def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr, 4747 "cmn", "\t$Rn, $Rm", 4748 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4749 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> { 4750 bits<4> Rn; 4751 bits<4> Rm; 4752 let isCommutable = 1; 4753 let Inst{25} = 0; 4754 let Inst{20} = 1; 4755 let Inst{19-16} = Rn; 4756 let Inst{15-12} = 0b0000; 4757 let Inst{11-4} = 0b00000000; 4758 let Inst{3-0} = Rm; 4759 4760 let Unpredictable{15-12} = 0b1111; 4761} 4762 4763def CMNzrsi : AI1<0b1011, (outs), 4764 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr, 4765 "cmn", "\t$Rn, $shift", 4766 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4767 GPR:$Rn, so_reg_imm:$shift)]>, 4768 Sched<[WriteCMPsi, ReadALU]> { 4769 bits<4> Rn; 4770 bits<12> shift; 4771 let Inst{25} = 0; 4772 let Inst{20} = 1; 4773 let Inst{19-16} = Rn; 4774 let Inst{15-12} = 0b0000; 4775 let Inst{11-5} = shift{11-5}; 4776 let Inst{4} = 0; 4777 let Inst{3-0} = shift{3-0}; 4778 4779 let Unpredictable{15-12} = 0b1111; 4780} 4781 4782def CMNzrsr : AI1<0b1011, (outs), 4783 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr, 4784 "cmn", "\t$Rn, $shift", 4785 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4786 GPRnopc:$Rn, so_reg_reg:$shift)]>, 4787 Sched<[WriteCMPsr, ReadALU]> { 4788 bits<4> Rn; 4789 bits<12> shift; 4790 let Inst{25} = 0; 4791 let Inst{20} = 1; 4792 let Inst{19-16} = Rn; 4793 let Inst{15-12} = 0b0000; 4794 let Inst{11-8} = shift{11-8}; 4795 let Inst{7} = 0; 4796 let Inst{6-5} = shift{6-5}; 4797 let Inst{4} = 1; 4798 let Inst{3-0} = shift{3-0}; 4799 4800 let Unpredictable{15-12} = 0b1111; 4801} 4802 4803} 4804 4805def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm), 4806 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4807 4808def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm), 4809 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4810 4811// Note that TST/TEQ don't set all the same flags that CMP does! 4812defm TST : AI1_cmp_irs<0b1000, "tst", 4813 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4814 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1, 4815 "DecodeTSTInstruction">; 4816defm TEQ : AI1_cmp_irs<0b1001, "teq", 4817 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4818 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>; 4819 4820// Pseudo i64 compares for some floating point compares. 4821let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, 4822 Defs = [CPSR] in { 4823def BCCi64 : PseudoInst<(outs), 4824 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst), 4825 IIC_Br, 4826 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>, 4827 Sched<[WriteBr]>; 4828 4829def BCCZi64 : PseudoInst<(outs), 4830 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, 4831 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>, 4832 Sched<[WriteBr]>; 4833} // usesCustomInserter 4834 4835 4836// Conditional moves 4837let hasSideEffects = 0 in { 4838 4839let isCommutable = 1, isSelect = 1 in 4840def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), 4841 (ins GPR:$false, GPR:$Rm, cmovpred:$p), 4842 4, IIC_iCMOVr, 4843 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, 4844 cmovpred:$p))]>, 4845 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4846 4847def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd), 4848 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p), 4849 4, IIC_iCMOVsr, 4850 [(set GPR:$Rd, 4851 (ARMcmov GPR:$false, so_reg_imm:$shift, 4852 cmovpred:$p))]>, 4853 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4854def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd), 4855 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p), 4856 4, IIC_iCMOVsr, 4857 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift, 4858 cmovpred:$p))]>, 4859 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4860 4861 4862let isMoveImm = 1 in 4863def MOVCCi16 4864 : ARMPseudoInst<(outs GPR:$Rd), 4865 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p), 4866 4, IIC_iMOVi, 4867 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm, 4868 cmovpred:$p))]>, 4869 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>, 4870 Sched<[WriteALU]>; 4871 4872let isMoveImm = 1 in 4873def MOVCCi : ARMPseudoInst<(outs GPR:$Rd), 4874 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 4875 4, IIC_iCMOVi, 4876 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm, 4877 cmovpred:$p))]>, 4878 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4879 4880// Two instruction predicate mov immediate. 4881let isMoveImm = 1 in 4882def MOVCCi32imm 4883 : ARMPseudoInst<(outs GPR:$Rd), 4884 (ins GPR:$false, i32imm:$src, cmovpred:$p), 4885 8, IIC_iCMOVix2, 4886 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src, 4887 cmovpred:$p))]>, 4888 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>; 4889 4890let isMoveImm = 1 in 4891def MVNCCi : ARMPseudoInst<(outs GPR:$Rd), 4892 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 4893 4, IIC_iCMOVi, 4894 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm, 4895 cmovpred:$p))]>, 4896 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4897 4898} // hasSideEffects 4899 4900 4901//===----------------------------------------------------------------------===// 4902// Atomic operations intrinsics 4903// 4904 4905def MemBarrierOptOperand : AsmOperandClass { 4906 let Name = "MemBarrierOpt"; 4907 let ParserMethod = "parseMemBarrierOptOperand"; 4908} 4909def memb_opt : Operand<i32> { 4910 let PrintMethod = "printMemBOption"; 4911 let ParserMatchClass = MemBarrierOptOperand; 4912 let DecoderMethod = "DecodeMemBarrierOption"; 4913} 4914 4915def InstSyncBarrierOptOperand : AsmOperandClass { 4916 let Name = "InstSyncBarrierOpt"; 4917 let ParserMethod = "parseInstSyncBarrierOptOperand"; 4918} 4919def instsyncb_opt : Operand<i32> { 4920 let PrintMethod = "printInstSyncBOption"; 4921 let ParserMatchClass = InstSyncBarrierOptOperand; 4922 let DecoderMethod = "DecodeInstSyncBarrierOption"; 4923} 4924 4925def TraceSyncBarrierOptOperand : AsmOperandClass { 4926 let Name = "TraceSyncBarrierOpt"; 4927 let ParserMethod = "parseTraceSyncBarrierOptOperand"; 4928} 4929def tsb_opt : Operand<i32> { 4930 let PrintMethod = "printTraceSyncBOption"; 4931 let ParserMatchClass = TraceSyncBarrierOptOperand; 4932} 4933 4934// Memory barriers protect the atomic sequences 4935let hasSideEffects = 1 in { 4936def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4937 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>, 4938 Requires<[IsARM, HasDB]> { 4939 bits<4> opt; 4940 let Inst{31-4} = 0xf57ff05; 4941 let Inst{3-0} = opt; 4942} 4943 4944def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4945 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>, 4946 Requires<[IsARM, HasDB]> { 4947 bits<4> opt; 4948 let Inst{31-4} = 0xf57ff04; 4949 let Inst{3-0} = opt; 4950} 4951 4952// ISB has only full system option 4953def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary, 4954 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>, 4955 Requires<[IsARM, HasDB]> { 4956 bits<4> opt; 4957 let Inst{31-4} = 0xf57ff06; 4958 let Inst{3-0} = opt; 4959} 4960 4961let hasNoSchedulingInfo = 1 in 4962def TSB : AInoP<(outs), (ins tsb_opt:$opt), MiscFrm, NoItinerary, 4963 "tsb", "\t$opt", []>, Requires<[IsARM, HasV8_4a]> { 4964 let Inst{31-0} = 0xe320f012; 4965} 4966 4967} 4968 4969// Armv8.5-A speculation barrier 4970def SB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "sb", "", []>, 4971 Requires<[IsARM, HasSB]>, Sched<[]> { 4972 let Inst{31-0} = 0xf57ff070; 4973 let Unpredictable = 0x000fff0f; 4974 let hasSideEffects = 1; 4975} 4976 4977let usesCustomInserter = 1, Defs = [CPSR], hasNoSchedulingInfo = 1 in { 4978 // Pseudo instruction that combines movs + predicated rsbmi 4979 // to implement integer ABS 4980 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>; 4981} 4982 4983let usesCustomInserter = 1, Defs = [CPSR], hasNoSchedulingInfo = 1 in { 4984 def COPY_STRUCT_BYVAL_I32 : PseudoInst< 4985 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment), 4986 NoItinerary, 4987 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>; 4988} 4989 4990let hasPostISelHook = 1, Constraints = "$newdst = $dst, $newsrc = $src" in { 4991 // %newsrc, %newdst = MEMCPY %dst, %src, N, ...N scratch regs... 4992 // Copies N registers worth of memory from address %src to address %dst 4993 // and returns the incremented addresses. N scratch register will 4994 // be attached for the copy to use. 4995 def MEMCPY : PseudoInst< 4996 (outs GPR:$newdst, GPR:$newsrc), 4997 (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops), 4998 NoItinerary, 4999 [(set GPR:$newdst, GPR:$newsrc, 5000 (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>; 5001} 5002 5003def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 5004 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 5005}]>; 5006 5007def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 5008 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 5009}]>; 5010 5011def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 5012 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 5013}]>; 5014 5015def strex_1 : PatFrag<(ops node:$val, node:$ptr), 5016 (int_arm_strex node:$val, node:$ptr), [{ 5017 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 5018}]>; 5019 5020def strex_2 : PatFrag<(ops node:$val, node:$ptr), 5021 (int_arm_strex node:$val, node:$ptr), [{ 5022 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 5023}]>; 5024 5025def strex_4 : PatFrag<(ops node:$val, node:$ptr), 5026 (int_arm_strex node:$val, node:$ptr), [{ 5027 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 5028}]>; 5029 5030def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 5031 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 5032}]>; 5033 5034def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 5035 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 5036}]>; 5037 5038def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 5039 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 5040}]>; 5041 5042def stlex_1 : PatFrag<(ops node:$val, node:$ptr), 5043 (int_arm_stlex node:$val, node:$ptr), [{ 5044 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 5045}]>; 5046 5047def stlex_2 : PatFrag<(ops node:$val, node:$ptr), 5048 (int_arm_stlex node:$val, node:$ptr), [{ 5049 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 5050}]>; 5051 5052def stlex_4 : PatFrag<(ops node:$val, node:$ptr), 5053 (int_arm_stlex node:$val, node:$ptr), [{ 5054 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 5055}]>; 5056 5057let mayLoad = 1 in { 5058def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5059 NoItinerary, "ldrexb", "\t$Rt, $addr", 5060 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>; 5061def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5062 NoItinerary, "ldrexh", "\t$Rt, $addr", 5063 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>; 5064def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5065 NoItinerary, "ldrex", "\t$Rt, $addr", 5066 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>; 5067let hasExtraDefRegAllocReq = 1 in 5068def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 5069 NoItinerary, "ldrexd", "\t$Rt, $addr", []> { 5070 let DecoderMethod = "DecodeDoubleRegLoad"; 5071} 5072 5073def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5074 NoItinerary, "ldaexb", "\t$Rt, $addr", 5075 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>; 5076def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5077 NoItinerary, "ldaexh", "\t$Rt, $addr", 5078 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>; 5079def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5080 NoItinerary, "ldaex", "\t$Rt, $addr", 5081 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>; 5082let hasExtraDefRegAllocReq = 1 in 5083def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 5084 NoItinerary, "ldaexd", "\t$Rt, $addr", []> { 5085 let DecoderMethod = "DecodeDoubleRegLoad"; 5086} 5087} 5088 5089let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 5090def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5091 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", 5092 [(set GPR:$Rd, (strex_1 GPR:$Rt, 5093 addr_offset_none:$addr))]>; 5094def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5095 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", 5096 [(set GPR:$Rd, (strex_2 GPR:$Rt, 5097 addr_offset_none:$addr))]>; 5098def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5099 NoItinerary, "strex", "\t$Rd, $Rt, $addr", 5100 [(set GPR:$Rd, (strex_4 GPR:$Rt, 5101 addr_offset_none:$addr))]>; 5102let hasExtraSrcRegAllocReq = 1 in 5103def STREXD : AIstrex<0b01, (outs GPR:$Rd), 5104 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 5105 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> { 5106 let DecoderMethod = "DecodeDoubleRegStore"; 5107} 5108def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5109 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr", 5110 [(set GPR:$Rd, 5111 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>; 5112def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5113 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr", 5114 [(set GPR:$Rd, 5115 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>; 5116def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5117 NoItinerary, "stlex", "\t$Rd, $Rt, $addr", 5118 [(set GPR:$Rd, 5119 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>; 5120let hasExtraSrcRegAllocReq = 1 in 5121def STLEXD : AIstlex<0b01, (outs GPR:$Rd), 5122 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 5123 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> { 5124 let DecoderMethod = "DecodeDoubleRegStore"; 5125} 5126} 5127 5128def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", 5129 [(int_arm_clrex)]>, 5130 Requires<[IsARM, HasV6K]> { 5131 let Inst{31-0} = 0b11110101011111111111000000011111; 5132} 5133 5134def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 5135 (STREXB GPR:$Rt, addr_offset_none:$addr)>; 5136def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 5137 (STREXH GPR:$Rt, addr_offset_none:$addr)>; 5138 5139def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 5140 (STLEXB GPR:$Rt, addr_offset_none:$addr)>; 5141def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 5142 (STLEXH GPR:$Rt, addr_offset_none:$addr)>; 5143 5144class acquiring_load<PatFrag base> 5145 : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 5146 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 5147 return isAcquireOrStronger(Ordering); 5148}]>; 5149 5150def atomic_load_acquire_8 : acquiring_load<atomic_load_8>; 5151def atomic_load_acquire_16 : acquiring_load<atomic_load_16>; 5152def atomic_load_acquire_32 : acquiring_load<atomic_load_32>; 5153 5154class releasing_store<PatFrag base> 5155 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 5156 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 5157 return isReleaseOrStronger(Ordering); 5158}]>; 5159 5160def atomic_store_release_8 : releasing_store<atomic_store_8>; 5161def atomic_store_release_16 : releasing_store<atomic_store_16>; 5162def atomic_store_release_32 : releasing_store<atomic_store_32>; 5163 5164let AddedComplexity = 8 in { 5165 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>; 5166 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>; 5167 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>; 5168 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>; 5169 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>; 5170 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>; 5171} 5172 5173// SWP/SWPB are deprecated in V6/V7 and optional in v7VE. 5174// FIXME Use InstAlias to generate LDREX/STREX pairs instead. 5175let mayLoad = 1, mayStore = 1 in { 5176def SWP : AIswp<0, (outs GPRnopc:$Rt), 5177 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>, 5178 Requires<[IsARM,PreV8]>; 5179def SWPB: AIswp<1, (outs GPRnopc:$Rt), 5180 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>, 5181 Requires<[IsARM,PreV8]>; 5182} 5183 5184//===----------------------------------------------------------------------===// 5185// Coprocessor Instructions. 5186// 5187 5188def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5189 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5190 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5191 [(int_arm_cdp timm:$cop, timm:$opc1, timm:$CRd, timm:$CRn, 5192 timm:$CRm, timm:$opc2)]>, 5193 Requires<[IsARM,PreV8]> { 5194 bits<4> opc1; 5195 bits<4> CRn; 5196 bits<4> CRd; 5197 bits<4> cop; 5198 bits<3> opc2; 5199 bits<4> CRm; 5200 5201 let Inst{3-0} = CRm; 5202 let Inst{4} = 0; 5203 let Inst{7-5} = opc2; 5204 let Inst{11-8} = cop; 5205 let Inst{15-12} = CRd; 5206 let Inst{19-16} = CRn; 5207 let Inst{23-20} = opc1; 5208 5209 let DecoderNamespace = "CoProc"; 5210} 5211 5212def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5213 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5214 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5215 [(int_arm_cdp2 timm:$cop, timm:$opc1, timm:$CRd, timm:$CRn, 5216 timm:$CRm, timm:$opc2)]>, 5217 Requires<[IsARM,PreV8]> { 5218 let Inst{31-28} = 0b1111; 5219 bits<4> opc1; 5220 bits<4> CRn; 5221 bits<4> CRd; 5222 bits<4> cop; 5223 bits<3> opc2; 5224 bits<4> CRm; 5225 5226 let Inst{3-0} = CRm; 5227 let Inst{4} = 0; 5228 let Inst{7-5} = opc2; 5229 let Inst{11-8} = cop; 5230 let Inst{15-12} = CRd; 5231 let Inst{19-16} = CRn; 5232 let Inst{23-20} = opc1; 5233 5234 let DecoderNamespace = "CoProc"; 5235} 5236 5237class ACI<dag oops, dag iops, string opc, string asm, 5238 list<dag> pattern, IndexMode im = IndexModeNone> 5239 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 5240 opc, asm, "", pattern> { 5241 let Inst{27-25} = 0b110; 5242} 5243class ACInoP<dag oops, dag iops, string opc, string asm, 5244 list<dag> pattern, IndexMode im = IndexModeNone> 5245 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 5246 opc, asm, "", pattern> { 5247 let Inst{31-28} = 0b1111; 5248 let Inst{27-25} = 0b110; 5249} 5250 5251let DecoderNamespace = "CoProc" in { 5252multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> { 5253 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 5254 asm, "\t$cop, $CRd, $addr", pattern> { 5255 bits<13> addr; 5256 bits<4> cop; 5257 bits<4> CRd; 5258 let Inst{24} = 1; // P = 1 5259 let Inst{23} = addr{8}; 5260 let Inst{22} = Dbit; 5261 let Inst{21} = 0; // W = 0 5262 let Inst{20} = load; 5263 let Inst{19-16} = addr{12-9}; 5264 let Inst{15-12} = CRd; 5265 let Inst{11-8} = cop; 5266 let Inst{7-0} = addr{7-0}; 5267 let DecoderMethod = "DecodeCopMemInstruction"; 5268 } 5269 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 5270 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { 5271 bits<13> addr; 5272 bits<4> cop; 5273 bits<4> CRd; 5274 let Inst{24} = 1; // P = 1 5275 let Inst{23} = addr{8}; 5276 let Inst{22} = Dbit; 5277 let Inst{21} = 1; // W = 1 5278 let Inst{20} = load; 5279 let Inst{19-16} = addr{12-9}; 5280 let Inst{15-12} = CRd; 5281 let Inst{11-8} = cop; 5282 let Inst{7-0} = addr{7-0}; 5283 let DecoderMethod = "DecodeCopMemInstruction"; 5284 } 5285 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5286 postidx_imm8s4:$offset), 5287 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { 5288 bits<9> offset; 5289 bits<4> addr; 5290 bits<4> cop; 5291 bits<4> CRd; 5292 let Inst{24} = 0; // P = 0 5293 let Inst{23} = offset{8}; 5294 let Inst{22} = Dbit; 5295 let Inst{21} = 1; // W = 1 5296 let Inst{20} = load; 5297 let Inst{19-16} = addr; 5298 let Inst{15-12} = CRd; 5299 let Inst{11-8} = cop; 5300 let Inst{7-0} = offset{7-0}; 5301 let DecoderMethod = "DecodeCopMemInstruction"; 5302 } 5303 def _OPTION : ACI<(outs), 5304 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5305 coproc_option_imm:$option), 5306 asm, "\t$cop, $CRd, $addr, $option", []> { 5307 bits<8> option; 5308 bits<4> addr; 5309 bits<4> cop; 5310 bits<4> CRd; 5311 let Inst{24} = 0; // P = 0 5312 let Inst{23} = 1; // U = 1 5313 let Inst{22} = Dbit; 5314 let Inst{21} = 0; // W = 0 5315 let Inst{20} = load; 5316 let Inst{19-16} = addr; 5317 let Inst{15-12} = CRd; 5318 let Inst{11-8} = cop; 5319 let Inst{7-0} = option; 5320 let DecoderMethod = "DecodeCopMemInstruction"; 5321 } 5322} 5323multiclass LdSt2Cop<bit load, bit Dbit, string asm, list<dag> pattern> { 5324 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 5325 asm, "\t$cop, $CRd, $addr", pattern> { 5326 bits<13> addr; 5327 bits<4> cop; 5328 bits<4> CRd; 5329 let Inst{24} = 1; // P = 1 5330 let Inst{23} = addr{8}; 5331 let Inst{22} = Dbit; 5332 let Inst{21} = 0; // W = 0 5333 let Inst{20} = load; 5334 let Inst{19-16} = addr{12-9}; 5335 let Inst{15-12} = CRd; 5336 let Inst{11-8} = cop; 5337 let Inst{7-0} = addr{7-0}; 5338 let DecoderMethod = "DecodeCopMemInstruction"; 5339 } 5340 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 5341 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { 5342 bits<13> addr; 5343 bits<4> cop; 5344 bits<4> CRd; 5345 let Inst{24} = 1; // P = 1 5346 let Inst{23} = addr{8}; 5347 let Inst{22} = Dbit; 5348 let Inst{21} = 1; // W = 1 5349 let Inst{20} = load; 5350 let Inst{19-16} = addr{12-9}; 5351 let Inst{15-12} = CRd; 5352 let Inst{11-8} = cop; 5353 let Inst{7-0} = addr{7-0}; 5354 let DecoderMethod = "DecodeCopMemInstruction"; 5355 } 5356 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5357 postidx_imm8s4:$offset), 5358 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { 5359 bits<9> offset; 5360 bits<4> addr; 5361 bits<4> cop; 5362 bits<4> CRd; 5363 let Inst{24} = 0; // P = 0 5364 let Inst{23} = offset{8}; 5365 let Inst{22} = Dbit; 5366 let Inst{21} = 1; // W = 1 5367 let Inst{20} = load; 5368 let Inst{19-16} = addr; 5369 let Inst{15-12} = CRd; 5370 let Inst{11-8} = cop; 5371 let Inst{7-0} = offset{7-0}; 5372 let DecoderMethod = "DecodeCopMemInstruction"; 5373 } 5374 def _OPTION : ACInoP<(outs), 5375 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5376 coproc_option_imm:$option), 5377 asm, "\t$cop, $CRd, $addr, $option", []> { 5378 bits<8> option; 5379 bits<4> addr; 5380 bits<4> cop; 5381 bits<4> CRd; 5382 let Inst{24} = 0; // P = 0 5383 let Inst{23} = 1; // U = 1 5384 let Inst{22} = Dbit; 5385 let Inst{21} = 0; // W = 0 5386 let Inst{20} = load; 5387 let Inst{19-16} = addr; 5388 let Inst{15-12} = CRd; 5389 let Inst{11-8} = cop; 5390 let Inst{7-0} = option; 5391 let DecoderMethod = "DecodeCopMemInstruction"; 5392 } 5393} 5394 5395defm LDC : LdStCop <1, 0, "ldc", [(int_arm_ldc timm:$cop, timm:$CRd, addrmode5:$addr)]>; 5396defm LDCL : LdStCop <1, 1, "ldcl", [(int_arm_ldcl timm:$cop, timm:$CRd, addrmode5:$addr)]>; 5397defm LDC2 : LdSt2Cop<1, 0, "ldc2", [(int_arm_ldc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5398defm LDC2L : LdSt2Cop<1, 1, "ldc2l", [(int_arm_ldc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5399 5400defm STC : LdStCop <0, 0, "stc", [(int_arm_stc timm:$cop, timm:$CRd, addrmode5:$addr)]>; 5401defm STCL : LdStCop <0, 1, "stcl", [(int_arm_stcl timm:$cop, timm:$CRd, addrmode5:$addr)]>; 5402defm STC2 : LdSt2Cop<0, 0, "stc2", [(int_arm_stc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5403defm STC2L : LdSt2Cop<0, 1, "stc2l", [(int_arm_stc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5404 5405} // DecoderNamespace = "CoProc" 5406 5407//===----------------------------------------------------------------------===// 5408// Move between coprocessor and ARM core register. 5409// 5410 5411class MovRCopro<string opc, bit direction, dag oops, dag iops, 5412 list<dag> pattern> 5413 : ABI<0b1110, oops, iops, NoItinerary, opc, 5414 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> { 5415 let Inst{20} = direction; 5416 let Inst{4} = 1; 5417 5418 bits<4> Rt; 5419 bits<4> cop; 5420 bits<3> opc1; 5421 bits<3> opc2; 5422 bits<4> CRm; 5423 bits<4> CRn; 5424 5425 let Inst{15-12} = Rt; 5426 let Inst{11-8} = cop; 5427 let Inst{23-21} = opc1; 5428 let Inst{7-5} = opc2; 5429 let Inst{3-0} = CRm; 5430 let Inst{19-16} = CRn; 5431 5432 let DecoderNamespace = "CoProc"; 5433} 5434 5435def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */, 5436 (outs), 5437 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5438 c_imm:$CRm, imm0_7:$opc2), 5439 [(int_arm_mcr timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn, 5440 timm:$CRm, timm:$opc2)]>, 5441 ComplexDeprecationPredicate<"MCR">; 5442def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 5443 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5444 c_imm:$CRm, 0, pred:$p)>; 5445def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, 5446 (outs GPRwithAPSR:$Rt), 5447 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5448 imm0_7:$opc2), []>; 5449def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", 5450 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5451 c_imm:$CRm, 0, pred:$p)>; 5452 5453def : ARMPat<(int_arm_mrc timm:$cop, timm:$opc1, timm:$CRn, timm:$CRm, timm:$opc2), 5454 (MRC p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2)>; 5455 5456class MovRCopro2<string opc, bit direction, dag oops, dag iops, 5457 list<dag> pattern> 5458 : ABXI<0b1110, oops, iops, NoItinerary, 5459 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> { 5460 let Inst{31-24} = 0b11111110; 5461 let Inst{20} = direction; 5462 let Inst{4} = 1; 5463 5464 bits<4> Rt; 5465 bits<4> cop; 5466 bits<3> opc1; 5467 bits<3> opc2; 5468 bits<4> CRm; 5469 bits<4> CRn; 5470 5471 let Inst{15-12} = Rt; 5472 let Inst{11-8} = cop; 5473 let Inst{23-21} = opc1; 5474 let Inst{7-5} = opc2; 5475 let Inst{3-0} = CRm; 5476 let Inst{19-16} = CRn; 5477 5478 let DecoderNamespace = "CoProc"; 5479} 5480 5481def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */, 5482 (outs), 5483 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5484 c_imm:$CRm, imm0_7:$opc2), 5485 [(int_arm_mcr2 timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn, 5486 timm:$CRm, timm:$opc2)]>, 5487 Requires<[IsARM,PreV8]>; 5488def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm", 5489 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5490 c_imm:$CRm, 0)>; 5491def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, 5492 (outs GPRwithAPSR:$Rt), 5493 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5494 imm0_7:$opc2), []>, 5495 Requires<[IsARM,PreV8]>; 5496def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm", 5497 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5498 c_imm:$CRm, 0)>; 5499 5500def : ARMV5TPat<(int_arm_mrc2 timm:$cop, timm:$opc1, timm:$CRn, 5501 timm:$CRm, timm:$opc2), 5502 (MRC2 p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2)>; 5503 5504class MovRRCopro<string opc, bit direction, dag oops, dag iops, list<dag> 5505 pattern = []> 5506 : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", 5507 pattern> { 5508 5509 let Inst{23-21} = 0b010; 5510 let Inst{20} = direction; 5511 5512 bits<4> Rt; 5513 bits<4> Rt2; 5514 bits<4> cop; 5515 bits<4> opc1; 5516 bits<4> CRm; 5517 5518 let Inst{15-12} = Rt; 5519 let Inst{19-16} = Rt2; 5520 let Inst{11-8} = cop; 5521 let Inst{7-4} = opc1; 5522 let Inst{3-0} = CRm; 5523} 5524 5525def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */, 5526 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5527 GPRnopc:$Rt2, c_imm:$CRm), 5528 [(int_arm_mcrr timm:$cop, timm:$opc1, GPRnopc:$Rt, 5529 GPRnopc:$Rt2, timm:$CRm)]>; 5530def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */, 5531 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5532 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5533 5534class MovRRCopro2<string opc, bit direction, dag oops, dag iops, 5535 list<dag> pattern = []> 5536 : ABXI<0b1100, oops, iops, NoItinerary, 5537 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>, 5538 Requires<[IsARM,PreV8]> { 5539 let Inst{31-28} = 0b1111; 5540 let Inst{23-21} = 0b010; 5541 let Inst{20} = direction; 5542 5543 bits<4> Rt; 5544 bits<4> Rt2; 5545 bits<4> cop; 5546 bits<4> opc1; 5547 bits<4> CRm; 5548 5549 let Inst{15-12} = Rt; 5550 let Inst{19-16} = Rt2; 5551 let Inst{11-8} = cop; 5552 let Inst{7-4} = opc1; 5553 let Inst{3-0} = CRm; 5554 5555 let DecoderMethod = "DecoderForMRRC2AndMCRR2"; 5556} 5557 5558def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */, 5559 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5560 GPRnopc:$Rt2, c_imm:$CRm), 5561 [(int_arm_mcrr2 timm:$cop, timm:$opc1, GPRnopc:$Rt, 5562 GPRnopc:$Rt2, timm:$CRm)]>; 5563 5564def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */, 5565 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5566 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5567 5568//===----------------------------------------------------------------------===// 5569// Move between special register and ARM core register 5570// 5571 5572// Move to ARM core register from Special Register 5573def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5574 "mrs", "\t$Rd, apsr", []> { 5575 bits<4> Rd; 5576 let Inst{23-16} = 0b00001111; 5577 let Unpredictable{19-17} = 0b111; 5578 5579 let Inst{15-12} = Rd; 5580 5581 let Inst{11-0} = 0b000000000000; 5582 let Unpredictable{11-0} = 0b110100001111; 5583} 5584 5585def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p), 0>, 5586 Requires<[IsARM]>; 5587 5588// The MRSsys instruction is the MRS instruction from the ARM ARM, 5589// section B9.3.9, with the R bit set to 1. 5590def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5591 "mrs", "\t$Rd, spsr", []> { 5592 bits<4> Rd; 5593 let Inst{23-16} = 0b01001111; 5594 let Unpredictable{19-16} = 0b1111; 5595 5596 let Inst{15-12} = Rd; 5597 5598 let Inst{11-0} = 0b000000000000; 5599 let Unpredictable{11-0} = 0b110100001111; 5600} 5601 5602// However, the MRS (banked register) system instruction (ARMv7VE) *does* have a 5603// separate encoding (distinguished by bit 5. 5604def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked), 5605 NoItinerary, "mrs", "\t$Rd, $banked", []>, 5606 Requires<[IsARM, HasVirtualization]> { 5607 bits<6> banked; 5608 bits<4> Rd; 5609 5610 let Inst{23} = 0; 5611 let Inst{22} = banked{5}; // R bit 5612 let Inst{21-20} = 0b00; 5613 let Inst{19-16} = banked{3-0}; 5614 let Inst{15-12} = Rd; 5615 let Inst{11-9} = 0b001; 5616 let Inst{8} = banked{4}; 5617 let Inst{7-0} = 0b00000000; 5618} 5619 5620// Move from ARM core register to Special Register 5621// 5622// No need to have both system and application versions of MSR (immediate) or 5623// MSR (register), the encodings are the same and the assembly parser has no way 5624// to distinguish between them. The mask operand contains the special register 5625// (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be 5626// accessed in the special register. 5627let Defs = [CPSR] in 5628def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, 5629 "msr", "\t$mask, $Rn", []> { 5630 bits<5> mask; 5631 bits<4> Rn; 5632 5633 let Inst{23} = 0; 5634 let Inst{22} = mask{4}; // R bit 5635 let Inst{21-20} = 0b10; 5636 let Inst{19-16} = mask{3-0}; 5637 let Inst{15-12} = 0b1111; 5638 let Inst{11-4} = 0b00000000; 5639 let Inst{3-0} = Rn; 5640} 5641 5642let Defs = [CPSR] in 5643def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary, 5644 "msr", "\t$mask, $imm", []> { 5645 bits<5> mask; 5646 bits<12> imm; 5647 5648 let Inst{23} = 0; 5649 let Inst{22} = mask{4}; // R bit 5650 let Inst{21-20} = 0b10; 5651 let Inst{19-16} = mask{3-0}; 5652 let Inst{15-12} = 0b1111; 5653 let Inst{11-0} = imm; 5654} 5655 5656// However, the MSR (banked register) system instruction (ARMv7VE) *does* have a 5657// separate encoding (distinguished by bit 5. 5658def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn), 5659 NoItinerary, "msr", "\t$banked, $Rn", []>, 5660 Requires<[IsARM, HasVirtualization]> { 5661 bits<6> banked; 5662 bits<4> Rn; 5663 5664 let Inst{23} = 0; 5665 let Inst{22} = banked{5}; // R bit 5666 let Inst{21-20} = 0b10; 5667 let Inst{19-16} = banked{3-0}; 5668 let Inst{15-12} = 0b1111; 5669 let Inst{11-9} = 0b001; 5670 let Inst{8} = banked{4}; 5671 let Inst{7-4} = 0b0000; 5672 let Inst{3-0} = Rn; 5673} 5674 5675// Dynamic stack allocation yields a _chkstk for Windows targets. These calls 5676// are needed to probe the stack when allocating more than 5677// 4k bytes in one go. Touching the stack at 4K increments is necessary to 5678// ensure that the guard pages used by the OS virtual memory manager are 5679// allocated in correct sequence. 5680// The main point of having separate instruction are extra unmodelled effects 5681// (compared to ordinary calls) like stack pointer change. 5682 5683def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone, 5684 [SDNPHasChain, SDNPSideEffect]>; 5685let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP], hasNoSchedulingInfo = 1 in 5686 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>; 5687 5688def win__dbzchk : SDNode<"ARMISD::WIN__DBZCHK", SDT_WIN__DBZCHK, 5689 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 5690let usesCustomInserter = 1, Defs = [CPSR], hasNoSchedulingInfo = 1 in 5691 def WIN__DBZCHK : PseudoInst<(outs), (ins tGPR:$divisor), NoItinerary, 5692 [(win__dbzchk tGPR:$divisor)]>; 5693 5694//===----------------------------------------------------------------------===// 5695// TLS Instructions 5696// 5697 5698// __aeabi_read_tp preserves the registers r1-r3. 5699// This is a pseudo inst so that we can get the encoding right, 5700// complete with fixup for the aeabi_read_tp function. 5701// TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern 5702// is defined in "ARMInstrThumb.td". 5703let isCall = 1, 5704 Defs = [R0, R12, LR, CPSR], Uses = [SP] in { 5705 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br, 5706 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>, 5707 Requires<[IsARM, IsReadTPSoft]>; 5708} 5709 5710// Reading thread pointer from coprocessor register 5711def : ARMPat<(ARMthread_pointer), (MRC 15, 0, 13, 0, 3)>, 5712 Requires<[IsARM, IsReadTPHard]>; 5713 5714//===----------------------------------------------------------------------===// 5715// SJLJ Exception handling intrinsics 5716// eh_sjlj_setjmp() is an instruction sequence to store the return 5717// address and save #0 in R0 for the non-longjmp case. 5718// Since by its nature we may be coming from some other function to get 5719// here, and we're using the stack frame for the containing function to 5720// save/restore registers, we can't keep anything live in regs across 5721// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 5722// when we get here from a longjmp(). We force everything out of registers 5723// except for our own input by listing the relevant registers in Defs. By 5724// doing so, we also cause the prologue/epilogue code to actively preserve 5725// all of the callee-saved resgisters, which is exactly what we want. 5726// A constant value is passed in $val, and we use the location as a scratch. 5727// 5728// These are pseudo-instructions and are lowered to individual MC-insts, so 5729// no encoding information is necessary. 5730let Defs = 5731 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 5732 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ], 5733 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5734 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5735 NoItinerary, 5736 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5737 Requires<[IsARM, HasVFP2]>; 5738} 5739 5740let Defs = 5741 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 5742 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5743 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5744 NoItinerary, 5745 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5746 Requires<[IsARM, NoVFP]>; 5747} 5748 5749// FIXME: Non-IOS version(s) 5750let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, 5751 Defs = [ R7, LR, SP ] in { 5752def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch), 5753 NoItinerary, 5754 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 5755 Requires<[IsARM]>; 5756} 5757 5758let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in 5759def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary, 5760 [(ARMeh_sjlj_setup_dispatch)]>; 5761 5762// eh.sjlj.dispatchsetup pseudo-instruction. 5763// This pseudo is used for both ARM and Thumb. Any differences are handled when 5764// the pseudo is expanded (which happens before any passes that need the 5765// instruction size). 5766let isBarrier = 1 in 5767def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>; 5768 5769 5770//===----------------------------------------------------------------------===// 5771// Non-Instruction Patterns 5772// 5773 5774// ARMv4 indirect branch using (MOVr PC, dst) 5775let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in 5776 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst), 5777 4, IIC_Br, [(brind GPR:$dst)], 5778 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5779 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5780 5781let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in 5782 def TAILJMPr4 : ARMPseudoExpand<(outs), (ins GPR:$dst), 5783 4, IIC_Br, [], 5784 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5785 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5786 5787// Large immediate handling. 5788 5789// 32-bit immediate using two piece mod_imms or movw + movt. 5790// This is a single pseudo instruction, the benefit is that it can be remat'd 5791// as a single unit instead of having to handle reg inputs. 5792// FIXME: Remove this when we can do generalized remat. 5793let isReMaterializable = 1, isMoveImm = 1 in 5794def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 5795 [(set GPR:$dst, (arm_i32imm:$src))]>, 5796 Requires<[IsARM]>; 5797 5798def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i, 5799 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>, 5800 Requires<[IsARM, DontUseMovt]>; 5801 5802// Pseudo instruction that combines movw + movt + add pc (if PIC). 5803// It also makes it possible to rematerialize the instructions. 5804// FIXME: Remove this when we can do generalized remat and when machine licm 5805// can properly the instructions. 5806let isReMaterializable = 1 in { 5807def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5808 IIC_iMOVix2addpc, 5809 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 5810 Requires<[IsARM, UseMovtInPic]>; 5811 5812def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5813 IIC_iLoadiALU, 5814 [(set GPR:$dst, 5815 (ARMWrapperPIC tglobaladdr:$addr))]>, 5816 Requires<[IsARM, DontUseMovtInPic]>; 5817 5818let AddedComplexity = 10 in 5819def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5820 NoItinerary, 5821 [(set GPR:$dst, 5822 (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5823 Requires<[IsARM, DontUseMovtInPic]>; 5824 5825let AddedComplexity = 10 in 5826def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5827 IIC_iMOVix2ld, 5828 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5829 Requires<[IsARM, UseMovtInPic]>; 5830} // isReMaterializable 5831 5832// The many different faces of TLS access. 5833def : ARMPat<(ARMWrapper tglobaltlsaddr :$dst), 5834 (MOVi32imm tglobaltlsaddr :$dst)>, 5835 Requires<[IsARM, UseMovt]>; 5836 5837def : Pat<(ARMWrapper tglobaltlsaddr:$src), 5838 (LDRLIT_ga_abs tglobaltlsaddr:$src)>, 5839 Requires<[IsARM, DontUseMovt]>; 5840 5841def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5842 (MOV_ga_pcrel tglobaltlsaddr:$addr)>, Requires<[IsARM, UseMovtInPic]>; 5843 5844def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5845 (LDRLIT_ga_pcrel tglobaltlsaddr:$addr)>, 5846 Requires<[IsARM, DontUseMovtInPic]>; 5847let AddedComplexity = 10 in 5848def : Pat<(load (ARMWrapperPIC tglobaltlsaddr:$addr)), 5849 (MOV_ga_pcrel_ldr tglobaltlsaddr:$addr)>, 5850 Requires<[IsARM, UseMovtInPic]>; 5851 5852 5853// ConstantPool, GlobalAddress, and JumpTable 5854def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 5855def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>, 5856 Requires<[IsARM, UseMovt]>; 5857def : ARMPat<(ARMWrapper texternalsym :$dst), (MOVi32imm texternalsym :$dst)>, 5858 Requires<[IsARM, UseMovt]>; 5859def : ARMPat<(ARMWrapperJT tjumptable:$dst), 5860 (LEApcrelJT tjumptable:$dst)>; 5861 5862// TODO: add,sub,and, 3-instr forms? 5863 5864// Tail calls. These patterns also apply to Thumb mode. 5865def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>; 5866def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>; 5867def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>; 5868 5869// Direct calls 5870def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; 5871def : ARMPat<(ARMcall_nolink texternalsym:$func), 5872 (BMOVPCB_CALL texternalsym:$func)>; 5873 5874// zextload i1 -> zextload i8 5875def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5876def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5877 5878// extload -> zextload 5879def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5880def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5881def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5882def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5883 5884def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 5885 5886def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; 5887def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; 5888 5889// smul* and smla* 5890def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 5891 (SMULBB GPR:$a, GPR:$b)>; 5892def : ARMV5TEPat<(mul sext_16_node:$a, (sext_bottom_16 GPR:$b)), 5893 (SMULBB GPR:$a, GPR:$b)>; 5894def : ARMV5TEPat<(mul sext_16_node:$a, (sext_top_16 GPR:$b)), 5895 (SMULBT GPR:$a, GPR:$b)>; 5896def : ARMV5TEPat<(mul (sext_top_16 GPR:$a), sext_16_node:$b), 5897 (SMULTB GPR:$a, GPR:$b)>; 5898def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, sext_16_node:$b)), 5899 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5900def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, (sext_bottom_16 GPR:$b))), 5901 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5902def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, (sext_top_16 GPR:$b))), 5903 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5904def : ARMV5MOPat<(add GPR:$acc, (mul (sext_top_16 GPR:$a), sext_16_node:$b)), 5905 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5906 5907def : ARMV5TEPat<(int_arm_smulbb GPR:$a, GPR:$b), 5908 (SMULBB GPR:$a, GPR:$b)>; 5909def : ARMV5TEPat<(int_arm_smulbt GPR:$a, GPR:$b), 5910 (SMULBT GPR:$a, GPR:$b)>; 5911def : ARMV5TEPat<(int_arm_smultb GPR:$a, GPR:$b), 5912 (SMULTB GPR:$a, GPR:$b)>; 5913def : ARMV5TEPat<(int_arm_smultt GPR:$a, GPR:$b), 5914 (SMULTT GPR:$a, GPR:$b)>; 5915def : ARMV5TEPat<(int_arm_smulwb GPR:$a, GPR:$b), 5916 (SMULWB GPR:$a, GPR:$b)>; 5917def : ARMV5TEPat<(int_arm_smulwt GPR:$a, GPR:$b), 5918 (SMULWT GPR:$a, GPR:$b)>; 5919 5920def : ARMV5TEPat<(int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc), 5921 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5922def : ARMV5TEPat<(int_arm_smlabt GPR:$a, GPR:$b, GPR:$acc), 5923 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5924def : ARMV5TEPat<(int_arm_smlatb GPR:$a, GPR:$b, GPR:$acc), 5925 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5926def : ARMV5TEPat<(int_arm_smlatt GPR:$a, GPR:$b, GPR:$acc), 5927 (SMLATT GPR:$a, GPR:$b, GPR:$acc)>; 5928def : ARMV5TEPat<(int_arm_smlawb GPR:$a, GPR:$b, GPR:$acc), 5929 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 5930def : ARMV5TEPat<(int_arm_smlawt GPR:$a, GPR:$b, GPR:$acc), 5931 (SMLAWT GPR:$a, GPR:$b, GPR:$acc)>; 5932 5933// Pre-v7 uses MCR for synchronization barriers. 5934def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>, 5935 Requires<[IsARM, HasV6]>; 5936 5937// SXT/UXT with no rotate 5938let AddedComplexity = 16 in { 5939def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>; 5940def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>; 5941def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>; 5942def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)), 5943 (UXTAB GPR:$Rn, GPR:$Rm, 0)>; 5944def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)), 5945 (UXTAH GPR:$Rn, GPR:$Rm, 0)>; 5946} 5947 5948def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>; 5949def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; 5950 5951def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)), 5952 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>; 5953def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)), 5954 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>; 5955 5956// Atomic load/store patterns 5957def : ARMPat<(atomic_load_8 ldst_so_reg:$src), 5958 (LDRBrs ldst_so_reg:$src)>; 5959def : ARMPat<(atomic_load_8 addrmode_imm12:$src), 5960 (LDRBi12 addrmode_imm12:$src)>; 5961def : ARMPat<(atomic_load_16 addrmode3:$src), 5962 (LDRH addrmode3:$src)>; 5963def : ARMPat<(atomic_load_32 ldst_so_reg:$src), 5964 (LDRrs ldst_so_reg:$src)>; 5965def : ARMPat<(atomic_load_32 addrmode_imm12:$src), 5966 (LDRi12 addrmode_imm12:$src)>; 5967def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val), 5968 (STRBrs GPR:$val, ldst_so_reg:$ptr)>; 5969def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val), 5970 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>; 5971def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val), 5972 (STRH GPR:$val, addrmode3:$ptr)>; 5973def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val), 5974 (STRrs GPR:$val, ldst_so_reg:$ptr)>; 5975def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val), 5976 (STRi12 GPR:$val, addrmode_imm12:$ptr)>; 5977 5978 5979//===----------------------------------------------------------------------===// 5980// Thumb Support 5981// 5982 5983include "ARMInstrThumb.td" 5984 5985//===----------------------------------------------------------------------===// 5986// Thumb2 Support 5987// 5988 5989include "ARMInstrThumb2.td" 5990 5991//===----------------------------------------------------------------------===// 5992// Floating Point Support 5993// 5994 5995include "ARMInstrVFP.td" 5996 5997//===----------------------------------------------------------------------===// 5998// Advanced SIMD (NEON) Support 5999// 6000 6001include "ARMInstrNEON.td" 6002 6003//===----------------------------------------------------------------------===// 6004// MVE Support 6005// 6006 6007include "ARMInstrMVE.td" 6008 6009//===----------------------------------------------------------------------===// 6010// Assembler aliases 6011// 6012 6013// Memory barriers 6014def : InstAlias<"dmb", (DMB 0xf), 0>, Requires<[IsARM, HasDB]>; 6015def : InstAlias<"dsb", (DSB 0xf), 0>, Requires<[IsARM, HasDB]>; 6016def : InstAlias<"ssbb", (DSB 0x0), 1>, Requires<[IsARM, HasDB]>; 6017def : InstAlias<"pssbb", (DSB 0x4), 1>, Requires<[IsARM, HasDB]>; 6018def : InstAlias<"isb", (ISB 0xf), 0>, Requires<[IsARM, HasDB]>; 6019// Armv8-R 'Data Full Barrier' 6020def : InstAlias<"dfb", (DSB 0xc), 1>, Requires<[IsARM, HasDFB]>; 6021 6022// System instructions 6023def : MnemonicAlias<"swi", "svc">; 6024 6025// Load / Store Multiple 6026def : MnemonicAlias<"ldmfd", "ldm">; 6027def : MnemonicAlias<"ldmia", "ldm">; 6028def : MnemonicAlias<"ldmea", "ldmdb">; 6029def : MnemonicAlias<"stmfd", "stmdb">; 6030def : MnemonicAlias<"stmia", "stm">; 6031def : MnemonicAlias<"stmea", "stm">; 6032 6033// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the 6034// input operands swapped when the shift amount is zero (i.e., unspecified). 6035def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 6036 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p), 0>, 6037 Requires<[IsARM, HasV6]>; 6038def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 6039 (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p), 0>, 6040 Requires<[IsARM, HasV6]>; 6041 6042// PUSH/POP aliases for STM/LDM 6043def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>; 6044def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>; 6045 6046// SSAT/USAT optional shift operand. 6047def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 6048 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 6049def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn", 6050 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 6051 6052 6053// Extend instruction optional rotate operand. 6054def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm", 6055 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6056def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm", 6057 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6058def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 6059 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6060def : ARMInstAlias<"sxtb${p} $Rd, $Rm", 6061 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6062def : ARMInstAlias<"sxtb16${p} $Rd, $Rm", 6063 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6064def : ARMInstAlias<"sxth${p} $Rd, $Rm", 6065 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6066 6067def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm", 6068 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6069def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm", 6070 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6071def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 6072 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6073def : ARMInstAlias<"uxtb${p} $Rd, $Rm", 6074 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6075def : ARMInstAlias<"uxtb16${p} $Rd, $Rm", 6076 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6077def : ARMInstAlias<"uxth${p} $Rd, $Rm", 6078 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6079 6080 6081// RFE aliases 6082def : MnemonicAlias<"rfefa", "rfeda">; 6083def : MnemonicAlias<"rfeea", "rfedb">; 6084def : MnemonicAlias<"rfefd", "rfeia">; 6085def : MnemonicAlias<"rfeed", "rfeib">; 6086def : MnemonicAlias<"rfe", "rfeia">; 6087 6088// SRS aliases 6089def : MnemonicAlias<"srsfa", "srsib">; 6090def : MnemonicAlias<"srsea", "srsia">; 6091def : MnemonicAlias<"srsfd", "srsdb">; 6092def : MnemonicAlias<"srsed", "srsda">; 6093def : MnemonicAlias<"srs", "srsia">; 6094 6095// QSAX == QSUBADDX 6096def : MnemonicAlias<"qsubaddx", "qsax">; 6097// SASX == SADDSUBX 6098def : MnemonicAlias<"saddsubx", "sasx">; 6099// SHASX == SHADDSUBX 6100def : MnemonicAlias<"shaddsubx", "shasx">; 6101// SHSAX == SHSUBADDX 6102def : MnemonicAlias<"shsubaddx", "shsax">; 6103// SSAX == SSUBADDX 6104def : MnemonicAlias<"ssubaddx", "ssax">; 6105// UASX == UADDSUBX 6106def : MnemonicAlias<"uaddsubx", "uasx">; 6107// UHASX == UHADDSUBX 6108def : MnemonicAlias<"uhaddsubx", "uhasx">; 6109// UHSAX == UHSUBADDX 6110def : MnemonicAlias<"uhsubaddx", "uhsax">; 6111// UQASX == UQADDSUBX 6112def : MnemonicAlias<"uqaddsubx", "uqasx">; 6113// UQSAX == UQSUBADDX 6114def : MnemonicAlias<"uqsubaddx", "uqsax">; 6115// USAX == USUBADDX 6116def : MnemonicAlias<"usubaddx", "usax">; 6117 6118// "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like 6119// for isel. 6120def : ARMInstSubst<"mov${s}${p} $Rd, $imm", 6121 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6122def : ARMInstSubst<"mvn${s}${p} $Rd, $imm", 6123 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6124// Same for AND <--> BIC 6125def : ARMInstSubst<"bic${s}${p} $Rd, $Rn, $imm", 6126 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 6127 pred:$p, cc_out:$s)>; 6128def : ARMInstSubst<"bic${s}${p} $Rdn, $imm", 6129 (ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 6130 pred:$p, cc_out:$s)>; 6131def : ARMInstSubst<"and${s}${p} $Rd, $Rn, $imm", 6132 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 6133 pred:$p, cc_out:$s)>; 6134def : ARMInstSubst<"and${s}${p} $Rdn, $imm", 6135 (BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 6136 pred:$p, cc_out:$s)>; 6137 6138// Likewise, "add Rd, mod_imm_neg" -> sub 6139def : ARMInstSubst<"add${s}${p} $Rd, $Rn, $imm", 6140 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6141def : ARMInstSubst<"add${s}${p} $Rd, $imm", 6142 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6143// Likewise, "sub Rd, mod_imm_neg" -> add 6144def : ARMInstSubst<"sub${s}${p} $Rd, $Rn, $imm", 6145 (ADDri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6146def : ARMInstSubst<"sub${s}${p} $Rd, $imm", 6147 (ADDri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6148 6149 6150def : ARMInstSubst<"adc${s}${p} $Rd, $Rn, $imm", 6151 (SBCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6152def : ARMInstSubst<"adc${s}${p} $Rdn, $imm", 6153 (SBCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6154def : ARMInstSubst<"sbc${s}${p} $Rd, $Rn, $imm", 6155 (ADCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6156def : ARMInstSubst<"sbc${s}${p} $Rdn, $imm", 6157 (ADCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6158 6159// Same for CMP <--> CMN via mod_imm_neg 6160def : ARMInstSubst<"cmp${p} $Rd, $imm", 6161 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 6162def : ARMInstSubst<"cmn${p} $Rd, $imm", 6163 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 6164 6165// The shifter forms of the MOV instruction are aliased to the ASR, LSL, 6166// LSR, ROR, and RRX instructions. 6167// FIXME: We need C++ parser hooks to map the alias to the MOV 6168// encoding. It seems we should be able to do that sort of thing 6169// in tblgen, but it could get ugly. 6170let TwoOperandAliasConstraint = "$Rm = $Rd" in { 6171def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm", 6172 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 6173 cc_out:$s)>; 6174def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm", 6175 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 6176 cc_out:$s)>; 6177def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm", 6178 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 6179 cc_out:$s)>; 6180def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm", 6181 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 6182 cc_out:$s)>; 6183} 6184def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm", 6185 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>; 6186let TwoOperandAliasConstraint = "$Rn = $Rd" in { 6187def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm", 6188 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6189 cc_out:$s)>; 6190def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm", 6191 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6192 cc_out:$s)>; 6193def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm", 6194 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6195 cc_out:$s)>; 6196def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm", 6197 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6198 cc_out:$s)>; 6199} 6200 6201// "neg" is and alias for "rsb rd, rn, #0" 6202def : ARMInstAlias<"neg${s}${p} $Rd, $Rm", 6203 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>; 6204 6205// Pre-v6, 'mov r0, r0' was used as a NOP encoding. 6206def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>, 6207 Requires<[IsARM, NoV6]>; 6208 6209// MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but 6210// the instruction definitions need difference constraints pre-v6. 6211// Use these aliases for the assembly parsing on pre-v6. 6212def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm", 6213 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s), 0>, 6214 Requires<[IsARM, NoV6]>; 6215def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra", 6216 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 6217 pred:$p, cc_out:$s), 0>, 6218 Requires<[IsARM, NoV6]>; 6219def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6220 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6221 Requires<[IsARM, NoV6]>; 6222def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6223 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6224 Requires<[IsARM, NoV6]>; 6225def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6226 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6227 Requires<[IsARM, NoV6]>; 6228def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6229 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6230 Requires<[IsARM, NoV6]>; 6231 6232// 'it' blocks in ARM mode just validate the predicates. The IT itself 6233// is discarded. 6234def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>, 6235 ComplexDeprecationPredicate<"IT">; 6236 6237let mayLoad = 1, mayStore =1, hasSideEffects = 1, hasNoSchedulingInfo = 1 in 6238def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn), 6239 NoItinerary, 6240 [(set GPR:$Rd, (int_arm_space timm:$size, GPR:$Rn))]>; 6241 6242//===---------------------------------- 6243// Atomic cmpxchg for -O0 6244//===---------------------------------- 6245 6246// The fast register allocator used during -O0 inserts spills to cover any VRegs 6247// live across basic block boundaries. When this happens between an LDXR and an 6248// STXR it can clear the exclusive monitor, causing all cmpxchg attempts to 6249// fail. 6250 6251// Unfortunately, this means we have to have an alternative (expanded 6252// post-regalloc) path for -O0 compilations. Fortunately this path can be 6253// significantly more naive than the standard expansion: we conservatively 6254// assume seq_cst, strong cmpxchg and omit clrex on failure. 6255 6256let Constraints = "@earlyclobber $Rd,@earlyclobber $temp", 6257 mayLoad = 1, mayStore = 1 in { 6258def CMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6259 (ins GPR:$addr, GPR:$desired, GPR:$new), 6260 NoItinerary, []>, Sched<[]>; 6261 6262def CMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6263 (ins GPR:$addr, GPR:$desired, GPR:$new), 6264 NoItinerary, []>, Sched<[]>; 6265 6266def CMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6267 (ins GPR:$addr, GPR:$desired, GPR:$new), 6268 NoItinerary, []>, Sched<[]>; 6269 6270def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$temp), 6271 (ins GPR:$addr, GPRPair:$desired, GPRPair:$new), 6272 NoItinerary, []>, Sched<[]>; 6273} 6274 6275def CompilerBarrier : PseudoInst<(outs), (ins i32imm:$ordering), NoItinerary, 6276 [(atomic_fence timm:$ordering, 0)]> { 6277 let hasSideEffects = 1; 6278 let Size = 0; 6279 let AsmString = "@ COMPILER BARRIER"; 6280 let hasNoSchedulingInfo = 1; 6281} 6282