1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// ARM specific DAG Nodes. 16// 17 18// Type profiles. 19def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 20 SDTCisVT<1, i32> ]>; 21def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 22def SDT_ARMStructByVal : SDTypeProfile<0, 4, 23 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 24 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 25 26def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 27 28def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 29 30def SDT_ARMCMov : SDTypeProfile<1, 3, 31 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 32 SDTCisVT<3, i32>]>; 33 34def SDT_ARMBrcond : SDTypeProfile<0, 2, 35 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 36 37def SDT_ARMBrJT : SDTypeProfile<0, 2, 38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 39 40def SDT_ARMBr2JT : SDTypeProfile<0, 3, 41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 42 SDTCisVT<2, i32>]>; 43 44def SDT_ARMBCC_i64 : SDTypeProfile<0, 6, 45 [SDTCisVT<0, i32>, 46 SDTCisVT<1, i32>, SDTCisVT<2, i32>, 47 SDTCisVT<3, i32>, SDTCisVT<4, i32>, 48 SDTCisVT<5, OtherVT>]>; 49 50def SDT_ARMAnd : SDTypeProfile<1, 2, 51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 52 SDTCisVT<2, i32>]>; 53 54def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 55def SDT_ARMFCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, 56 SDTCisVT<2, i32>]>; 57 58def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 59 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 60 61def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 62def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, 63 SDTCisInt<2>]>; 64def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 65def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>; 66 67def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 68 69def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, 70 SDTCisInt<1>]>; 71 72def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 73 74def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 75 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 76 77def SDT_WIN__DBZCHK : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 78 79def SDT_ARMMEMCPY : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 80 SDTCisVT<2, i32>, SDTCisVT<3, i32>, 81 SDTCisVT<4, i32>]>; 82 83def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 84 [SDTCisSameAs<0, 2>, 85 SDTCisSameAs<0, 3>, 86 SDTCisInt<0>, SDTCisVT<1, i32>]>; 87 88// SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR 89def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 90 [SDTCisSameAs<0, 2>, 91 SDTCisSameAs<0, 3>, 92 SDTCisInt<0>, 93 SDTCisVT<1, i32>, 94 SDTCisVT<4, i32>]>; 95 96def SDT_LongMac : SDTypeProfile<2, 4, [SDTCisVT<0, i32>, 97 SDTCisSameAs<0, 1>, 98 SDTCisSameAs<0, 2>, 99 SDTCisSameAs<0, 3>, 100 SDTCisSameAs<0, 4>, 101 SDTCisSameAs<0, 5>]>; 102 103def ARMSmlald : SDNode<"ARMISD::SMLALD", SDT_LongMac>; 104def ARMSmlaldx : SDNode<"ARMISD::SMLALDX", SDT_LongMac>; 105def ARMSmlsld : SDNode<"ARMISD::SMLSLD", SDT_LongMac>; 106def ARMSmlsldx : SDNode<"ARMISD::SMLSLDX", SDT_LongMac>; 107 108def SDT_MulHSR : SDTypeProfile<1, 3, [SDTCisVT<0,i32>, 109 SDTCisSameAs<0, 1>, 110 SDTCisSameAs<0, 2>, 111 SDTCisSameAs<0, 3>]>; 112 113def ARMsmmlar : SDNode<"ARMISD::SMMLAR", SDT_MulHSR>; 114def ARMsmmlsr : SDNode<"ARMISD::SMMLSR", SDT_MulHSR>; 115 116// Node definitions. 117def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 118def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>; 119def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>; 120 121def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 122 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 123def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 124 [SDNPHasChain, SDNPSideEffect, 125 SDNPOptInGlue, SDNPOutGlue]>; 126def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" , 127 SDT_ARMStructByVal, 128 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 129 SDNPMayStore, SDNPMayLoad]>; 130 131def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 132 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 133 SDNPVariadic]>; 134def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 135 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 136 SDNPVariadic]>; 137def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 139 SDNPVariadic]>; 140 141def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, 142 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 143def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall, 144 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 145def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 146 [SDNPInGlue]>; 147def ARMsubs : SDNode<"ARMISD::SUBS", SDTIntBinOp, [SDNPOutGlue]>; 148 149def ARMssatnoshift : SDNode<"ARMISD::SSAT", SDTIntSatNoShOp, []>; 150 151def ARMusatnoshift : SDNode<"ARMISD::USAT", SDTIntSatNoShOp, []>; 152 153def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 154 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 155 156def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 157 [SDNPHasChain]>; 158def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, 159 [SDNPHasChain]>; 160 161def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64, 162 [SDNPHasChain]>; 163 164def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 165 [SDNPOutGlue]>; 166 167def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp, 168 [SDNPOutGlue]>; 169 170def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, 171 [SDNPOutGlue, SDNPCommutative]>; 172 173def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 174 175def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 176def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 177def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>; 178 179def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags, 180 [SDNPCommutative]>; 181def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>; 182def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>; 183def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>; 184 185def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 186def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", 187 SDT_ARMEH_SJLJ_Setjmp, 188 [SDNPHasChain, SDNPSideEffect]>; 189def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP", 190 SDT_ARMEH_SJLJ_Longjmp, 191 [SDNPHasChain, SDNPSideEffect]>; 192def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH", 193 SDT_ARMEH_SJLJ_SetupDispatch, 194 [SDNPHasChain, SDNPSideEffect]>; 195 196def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER, 197 [SDNPHasChain, SDNPSideEffect]>; 198def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH, 199 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 200 201def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET, 202 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 203 204def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; 205 206def ARMmemcopy : SDNode<"ARMISD::MEMCPY", SDT_ARMMEMCPY, 207 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 208 SDNPMayStore, SDNPMayLoad]>; 209 210def ARMsmulwb : SDNode<"ARMISD::SMULWB", SDTIntBinOp, []>; 211def ARMsmulwt : SDNode<"ARMISD::SMULWT", SDTIntBinOp, []>; 212def ARMsmlalbb : SDNode<"ARMISD::SMLALBB", SDT_LongMac, []>; 213def ARMsmlalbt : SDNode<"ARMISD::SMLALBT", SDT_LongMac, []>; 214def ARMsmlaltb : SDNode<"ARMISD::SMLALTB", SDT_LongMac, []>; 215def ARMsmlaltt : SDNode<"ARMISD::SMLALTT", SDT_LongMac, []>; 216 217//===----------------------------------------------------------------------===// 218// ARM Instruction Predicate Definitions. 219// 220def HasV4T : Predicate<"Subtarget->hasV4TOps()">, 221 AssemblerPredicate<"HasV4TOps", "armv4t">; 222def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; 223def HasV5T : Predicate<"Subtarget->hasV5TOps()">, 224 AssemblerPredicate<"HasV5TOps", "armv5t">; 225def NoV5T : Predicate<"!Subtarget->hasV5TOps()">; 226def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, 227 AssemblerPredicate<"HasV5TEOps", "armv5te">; 228def HasV6 : Predicate<"Subtarget->hasV6Ops()">, 229 AssemblerPredicate<"HasV6Ops", "armv6">; 230def NoV6 : Predicate<"!Subtarget->hasV6Ops()">; 231def HasV6M : Predicate<"Subtarget->hasV6MOps()">, 232 AssemblerPredicate<"HasV6MOps", 233 "armv6m or armv6t2">; 234def HasV8MBaseline : Predicate<"Subtarget->hasV8MBaselineOps()">, 235 AssemblerPredicate<"HasV8MBaselineOps", 236 "armv8m.base">; 237def HasV8MMainline : Predicate<"Subtarget->hasV8MMainlineOps()">, 238 AssemblerPredicate<"HasV8MMainlineOps", 239 "armv8m.main">; 240def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, 241 AssemblerPredicate<"HasV6T2Ops", "armv6t2">; 242def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; 243def HasV6K : Predicate<"Subtarget->hasV6KOps()">, 244 AssemblerPredicate<"HasV6KOps", "armv6k">; 245def NoV6K : Predicate<"!Subtarget->hasV6KOps()">; 246def HasV7 : Predicate<"Subtarget->hasV7Ops()">, 247 AssemblerPredicate<"HasV7Ops", "armv7">; 248def HasV8 : Predicate<"Subtarget->hasV8Ops()">, 249 AssemblerPredicate<"HasV8Ops", "armv8">; 250def PreV8 : Predicate<"!Subtarget->hasV8Ops()">, 251 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">; 252def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">, 253 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">; 254def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">, 255 AssemblerPredicate<"HasV8_2aOps", "armv8.2a">; 256def HasV8_3a : Predicate<"Subtarget->hasV8_3aOps()">, 257 AssemblerPredicate<"HasV8_3aOps", "armv8.3a">; 258def HasV8_4a : Predicate<"Subtarget->hasV8_4aOps()">, 259 AssemblerPredicate<"HasV8_4aOps", "armv8.4a">; 260def HasV8_5a : Predicate<"Subtarget->hasV8_5aOps()">, 261 AssemblerPredicate<"HasV8_5aOps", "armv8.5a">; 262def NoVFP : Predicate<"!Subtarget->hasVFP2()">; 263def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, 264 AssemblerPredicate<"FeatureVFP2", "VFP2">; 265def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, 266 AssemblerPredicate<"FeatureVFP3", "VFP3">; 267def HasVFP4 : Predicate<"Subtarget->hasVFP4()">, 268 AssemblerPredicate<"FeatureVFP4", "VFP4">; 269def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">, 270 AssemblerPredicate<"!FeatureVFPOnlySP", 271 "double precision VFP">; 272def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, 273 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">; 274def HasNEON : Predicate<"Subtarget->hasNEON()">, 275 AssemblerPredicate<"FeatureNEON", "NEON">; 276def HasSHA2 : Predicate<"Subtarget->hasSHA2()">, 277 AssemblerPredicate<"FeatureSHA2", "sha2">; 278def HasAES : Predicate<"Subtarget->hasAES()">, 279 AssemblerPredicate<"FeatureAES", "aes">; 280def HasCrypto : Predicate<"Subtarget->hasCrypto()">, 281 AssemblerPredicate<"FeatureCrypto", "crypto">; 282def HasDotProd : Predicate<"Subtarget->hasDotProd()">, 283 AssemblerPredicate<"FeatureDotProd", "dotprod">; 284def HasCRC : Predicate<"Subtarget->hasCRC()">, 285 AssemblerPredicate<"FeatureCRC", "crc">; 286def HasRAS : Predicate<"Subtarget->hasRAS()">, 287 AssemblerPredicate<"FeatureRAS", "ras">; 288def HasFP16 : Predicate<"Subtarget->hasFP16()">, 289 AssemblerPredicate<"FeatureFP16","half-float conversions">; 290def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">, 291 AssemblerPredicate<"FeatureFullFP16","full half-float">; 292def HasFP16FML : Predicate<"Subtarget->hasFP16FML()">, 293 AssemblerPredicate<"FeatureFP16FML","full half-float fml">; 294def HasDivideInThumb : Predicate<"Subtarget->hasDivideInThumbMode()">, 295 AssemblerPredicate<"FeatureHWDivThumb", "divide in THUMB">; 296def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">, 297 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">; 298def HasDSP : Predicate<"Subtarget->hasDSP()">, 299 AssemblerPredicate<"FeatureDSP", "dsp">; 300def HasDB : Predicate<"Subtarget->hasDataBarrier()">, 301 AssemblerPredicate<"FeatureDB", 302 "data-barriers">; 303def HasDFB : Predicate<"Subtarget->hasFullDataBarrier()">, 304 AssemblerPredicate<"FeatureDFB", 305 "full-data-barrier">; 306def HasV7Clrex : Predicate<"Subtarget->hasV7Clrex()">, 307 AssemblerPredicate<"FeatureV7Clrex", 308 "v7 clrex">; 309def HasAcquireRelease : Predicate<"Subtarget->hasAcquireRelease()">, 310 AssemblerPredicate<"FeatureAcquireRelease", 311 "acquire/release">; 312def HasMP : Predicate<"Subtarget->hasMPExtension()">, 313 AssemblerPredicate<"FeatureMP", 314 "mp-extensions">; 315def HasVirtualization: Predicate<"false">, 316 AssemblerPredicate<"FeatureVirtualization", 317 "virtualization-extensions">; 318def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">, 319 AssemblerPredicate<"FeatureTrustZone", 320 "TrustZone">; 321def Has8MSecExt : Predicate<"Subtarget->has8MSecExt()">, 322 AssemblerPredicate<"Feature8MSecExt", 323 "ARMv8-M Security Extensions">; 324def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">; 325def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; 326def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; 327def IsThumb : Predicate<"Subtarget->isThumb()">, 328 AssemblerPredicate<"ModeThumb", "thumb">; 329def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; 330def IsThumb2 : Predicate<"Subtarget->isThumb2()">, 331 AssemblerPredicate<"ModeThumb,FeatureThumb2", 332 "thumb2">; 333def IsMClass : Predicate<"Subtarget->isMClass()">, 334 AssemblerPredicate<"FeatureMClass", "armv*m">; 335def IsNotMClass : Predicate<"!Subtarget->isMClass()">, 336 AssemblerPredicate<"!FeatureMClass", 337 "!armv*m">; 338def IsARM : Predicate<"!Subtarget->isThumb()">, 339 AssemblerPredicate<"!ModeThumb", "arm-mode">; 340def IsMachO : Predicate<"Subtarget->isTargetMachO()">; 341def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">; 342def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 343def IsWindows : Predicate<"Subtarget->isTargetWindows()">; 344def IsNotWindows : Predicate<"!Subtarget->isTargetWindows()">; 345def IsReadTPHard : Predicate<"Subtarget->isReadTPHard()">; 346def IsReadTPSoft : Predicate<"!Subtarget->isReadTPHard()">; 347def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">, 348 AssemblerPredicate<"FeatureNaClTrap", "NaCl">; 349def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">; 350 351def UseNegativeImmediates : 352 Predicate<"false">, 353 AssemblerPredicate<"!FeatureNoNegativeImmediates", 354 "NegativeImmediates">; 355 356// FIXME: Eventually this will be just "hasV6T2Ops". 357let RecomputePerFunction = 1 in { 358 def UseMovt : Predicate<"Subtarget->useMovt(*MF)">; 359 def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">; 360 def UseMovtInPic : Predicate<"Subtarget->useMovt(*MF) && Subtarget->allowPositionIndependentMovt()">; 361 def DontUseMovtInPic : Predicate<"!Subtarget->useMovt(*MF) || !Subtarget->allowPositionIndependentMovt()">; 362 363 def UseFPVMLx: Predicate<"((Subtarget->useFPVMLx() &&" 364 " TM.Options.AllowFPOpFusion != FPOpFusion::Fast) ||" 365 "MF->getFunction().optForMinSize())">; 366} 367def UseMulOps : Predicate<"Subtarget->useMulOps()">; 368 369// Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available. 370// But only select them if more precision in FP computation is allowed, and when 371// they are not slower than a mul + add sequence. 372// Do not use them for Darwin platforms. 373def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion ==" 374 " FPOpFusion::Fast && " 375 " Subtarget->hasVFP4()) && " 376 "!Subtarget->isTargetDarwin() &&" 377 "Subtarget->useFPVMLx()">; 378 379def HasFastVGETLNi32 : Predicate<"!Subtarget->hasSlowVGETLNi32()">; 380def HasSlowVGETLNi32 : Predicate<"Subtarget->hasSlowVGETLNi32()">; 381 382def HasFastVDUP32 : Predicate<"!Subtarget->hasSlowVDUP32()">; 383def HasSlowVDUP32 : Predicate<"Subtarget->hasSlowVDUP32()">; 384 385def UseVMOVSR : Predicate<"Subtarget->preferVMOVSR() ||" 386 "!Subtarget->useNEONForSinglePrecisionFP()">; 387def DontUseVMOVSR : Predicate<"!Subtarget->preferVMOVSR() &&" 388 "Subtarget->useNEONForSinglePrecisionFP()">; 389 390let RecomputePerFunction = 1 in { 391 def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">; 392 def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">; 393} 394 395def GenExecuteOnly : Predicate<"Subtarget->genExecuteOnly()">; 396 397// Armv8.5-A extensions 398def HasSB : Predicate<"Subtarget->hasSB()">, 399 AssemblerPredicate<"FeatureSB", "sb">; 400 401//===----------------------------------------------------------------------===// 402// ARM Flag Definitions. 403 404class RegConstraint<string C> { 405 string Constraints = C; 406} 407 408//===----------------------------------------------------------------------===// 409// ARM specific transformation functions and pattern fragments. 410// 411 412// imm_neg_XFORM - Return the negation of an i32 immediate value. 413def imm_neg_XFORM : SDNodeXForm<imm, [{ 414 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32); 415}]>; 416 417// imm_not_XFORM - Return the complement of a i32 immediate value. 418def imm_not_XFORM : SDNodeXForm<imm, [{ 419 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32); 420}]>; 421 422/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 423def imm16_31 : ImmLeaf<i32, [{ 424 return (int32_t)Imm >= 16 && (int32_t)Imm < 32; 425}]>; 426 427// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 428def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 429 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; 430}]>; 431 432def sext_bottom_16 : PatFrag<(ops node:$a), 433 (sext_inreg node:$a, i16)>; 434def sext_top_16 : PatFrag<(ops node:$a), 435 (i32 (sra node:$a, (i32 16)))>; 436 437def bb_mul : PatFrag<(ops node:$a, node:$b), 438 (mul (sext_bottom_16 node:$a), (sext_bottom_16 node:$b))>; 439def bt_mul : PatFrag<(ops node:$a, node:$b), 440 (mul (sext_bottom_16 node:$a), (sra node:$b, (i32 16)))>; 441def tb_mul : PatFrag<(ops node:$a, node:$b), 442 (mul (sra node:$a, (i32 16)), (sext_bottom_16 node:$b))>; 443def tt_mul : PatFrag<(ops node:$a, node:$b), 444 (mul (sra node:$a, (i32 16)), (sra node:$b, (i32 16)))>; 445 446/// Split a 32-bit immediate into two 16 bit parts. 447def hi16 : SDNodeXForm<imm, [{ 448 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N), 449 MVT::i32); 450}]>; 451 452def lo16AllZero : PatLeaf<(i32 imm), [{ 453 // Returns true if all low 16-bits are 0. 454 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 455}], hi16>; 456 457class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 458class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 459 460// An 'and' node with a single use. 461def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 462 return N->hasOneUse(); 463}]>; 464 465// An 'xor' node with a single use. 466def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{ 467 return N->hasOneUse(); 468}]>; 469 470// An 'fmul' node with a single use. 471def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{ 472 return N->hasOneUse(); 473}]>; 474 475// An 'fadd' node which checks for single non-hazardous use. 476def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{ 477 return hasNoVMLxHazardUse(N); 478}]>; 479 480// An 'fsub' node which checks for single non-hazardous use. 481def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{ 482 return hasNoVMLxHazardUse(N); 483}]>; 484 485//===----------------------------------------------------------------------===// 486// Operand Definitions. 487// 488 489// Immediate operands with a shared generic asm render method. 490class ImmAsmOperand<int Low, int High> : AsmOperandClass { 491 let RenderMethod = "addImmOperands"; 492 let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; 493 let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]"; 494} 495 496class ImmAsmOperandMinusOne<int Low, int High> : AsmOperandClass { 497 let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; 498 let DiagnosticType = "ImmRange" # Low # "_" # High; 499 let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]"; 500} 501 502// Operands that are part of a memory addressing mode. 503class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; } 504 505// Branch target. 506// FIXME: rename brtarget to t2_brtarget 507def brtarget : Operand<OtherVT> { 508 let EncoderMethod = "getBranchTargetOpValue"; 509 let OperandType = "OPERAND_PCREL"; 510 let DecoderMethod = "DecodeT2BROperand"; 511} 512 513// Branches targeting ARM-mode must be divisible by 4 if they're a raw 514// immediate. 515def ARMBranchTarget : AsmOperandClass { 516 let Name = "ARMBranchTarget"; 517} 518 519// Branches targeting Thumb-mode must be divisible by 2 if they're a raw 520// immediate. 521def ThumbBranchTarget : AsmOperandClass { 522 let Name = "ThumbBranchTarget"; 523} 524 525def arm_br_target : Operand<OtherVT> { 526 let ParserMatchClass = ARMBranchTarget; 527 let EncoderMethod = "getARMBranchTargetOpValue"; 528 let OperandType = "OPERAND_PCREL"; 529} 530 531// Call target for ARM. Handles conditional/unconditional 532// FIXME: rename bl_target to t2_bltarget? 533def arm_bl_target : Operand<i32> { 534 let ParserMatchClass = ARMBranchTarget; 535 let EncoderMethod = "getARMBLTargetOpValue"; 536 let OperandType = "OPERAND_PCREL"; 537} 538 539// Target for BLX *from* ARM mode. 540def arm_blx_target : Operand<i32> { 541 let ParserMatchClass = ThumbBranchTarget; 542 let EncoderMethod = "getARMBLXTargetOpValue"; 543 let OperandType = "OPERAND_PCREL"; 544} 545 546// A list of registers separated by comma. Used by load/store multiple. 547def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; } 548def reglist : Operand<i32> { 549 let EncoderMethod = "getRegisterListOpValue"; 550 let ParserMatchClass = RegListAsmOperand; 551 let PrintMethod = "printRegisterList"; 552 let DecoderMethod = "DecodeRegListOperand"; 553} 554 555def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">; 556 557def DPRRegListAsmOperand : AsmOperandClass { 558 let Name = "DPRRegList"; 559 let DiagnosticType = "DPR_RegList"; 560} 561def dpr_reglist : Operand<i32> { 562 let EncoderMethod = "getRegisterListOpValue"; 563 let ParserMatchClass = DPRRegListAsmOperand; 564 let PrintMethod = "printRegisterList"; 565 let DecoderMethod = "DecodeDPRRegListOperand"; 566} 567 568def SPRRegListAsmOperand : AsmOperandClass { 569 let Name = "SPRRegList"; 570 let DiagnosticString = "operand must be a list of registers in range [s0, s31]"; 571} 572def spr_reglist : Operand<i32> { 573 let EncoderMethod = "getRegisterListOpValue"; 574 let ParserMatchClass = SPRRegListAsmOperand; 575 let PrintMethod = "printRegisterList"; 576 let DecoderMethod = "DecodeSPRRegListOperand"; 577} 578 579// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 580def cpinst_operand : Operand<i32> { 581 let PrintMethod = "printCPInstOperand"; 582} 583 584// Local PC labels. 585def pclabel : Operand<i32> { 586 let PrintMethod = "printPCLabel"; 587} 588 589// ADR instruction labels. 590def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; } 591def adrlabel : Operand<i32> { 592 let EncoderMethod = "getAdrLabelOpValue"; 593 let ParserMatchClass = AdrLabelAsmOperand; 594 let PrintMethod = "printAdrLabelOperand<0>"; 595} 596 597def neon_vcvt_imm32 : Operand<i32> { 598 let EncoderMethod = "getNEONVcvtImm32OpValue"; 599 let DecoderMethod = "DecodeVCVTImmOperand"; 600} 601 602// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. 603def rot_imm_XFORM: SDNodeXForm<imm, [{ 604 switch (N->getZExtValue()){ 605 default: llvm_unreachable(nullptr); 606 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); 607 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32); 608 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32); 609 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32); 610 } 611}]>; 612def RotImmAsmOperand : AsmOperandClass { 613 let Name = "RotImm"; 614 let ParserMethod = "parseRotImm"; 615} 616def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{ 617 int32_t v = N->getZExtValue(); 618 return v == 8 || v == 16 || v == 24; }], 619 rot_imm_XFORM> { 620 let PrintMethod = "printRotImmOperand"; 621 let ParserMatchClass = RotImmAsmOperand; 622} 623 624// shift_imm: An integer that encodes a shift amount and the type of shift 625// (asr or lsl). The 6-bit immediate encodes as: 626// {5} 0 ==> lsl 627// 1 asr 628// {4-0} imm5 shift amount. 629// asr #32 encoded as imm5 == 0. 630def ShifterImmAsmOperand : AsmOperandClass { 631 let Name = "ShifterImm"; 632 let ParserMethod = "parseShifterImm"; 633} 634def shift_imm : Operand<i32> { 635 let PrintMethod = "printShiftImmOperand"; 636 let ParserMatchClass = ShifterImmAsmOperand; 637} 638 639// shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm. 640def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; } 641def so_reg_reg : Operand<i32>, // reg reg imm 642 ComplexPattern<i32, 3, "SelectRegShifterOperand", 643 [shl, srl, sra, rotr]> { 644 let EncoderMethod = "getSORegRegOpValue"; 645 let PrintMethod = "printSORegRegOperand"; 646 let DecoderMethod = "DecodeSORegRegOperand"; 647 let ParserMatchClass = ShiftedRegAsmOperand; 648 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm); 649} 650 651def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; } 652def so_reg_imm : Operand<i32>, // reg imm 653 ComplexPattern<i32, 2, "SelectImmShifterOperand", 654 [shl, srl, sra, rotr]> { 655 let EncoderMethod = "getSORegImmOpValue"; 656 let PrintMethod = "printSORegImmOperand"; 657 let DecoderMethod = "DecodeSORegImmOperand"; 658 let ParserMatchClass = ShiftedImmAsmOperand; 659 let MIOperandInfo = (ops GPR, i32imm); 660} 661 662// FIXME: Does this need to be distinct from so_reg? 663def shift_so_reg_reg : Operand<i32>, // reg reg imm 664 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand", 665 [shl,srl,sra,rotr]> { 666 let EncoderMethod = "getSORegRegOpValue"; 667 let PrintMethod = "printSORegRegOperand"; 668 let DecoderMethod = "DecodeSORegRegOperand"; 669 let ParserMatchClass = ShiftedRegAsmOperand; 670 let MIOperandInfo = (ops GPR, GPR, i32imm); 671} 672 673// FIXME: Does this need to be distinct from so_reg? 674def shift_so_reg_imm : Operand<i32>, // reg reg imm 675 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand", 676 [shl,srl,sra,rotr]> { 677 let EncoderMethod = "getSORegImmOpValue"; 678 let PrintMethod = "printSORegImmOperand"; 679 let DecoderMethod = "DecodeSORegImmOperand"; 680 let ParserMatchClass = ShiftedImmAsmOperand; 681 let MIOperandInfo = (ops GPR, i32imm); 682} 683 684// mod_imm: match a 32-bit immediate operand, which can be encoded into 685// a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM 686// - "Modified Immediate Constants"). Within the MC layer we keep this 687// immediate in its encoded form. 688def ModImmAsmOperand: AsmOperandClass { 689 let Name = "ModImm"; 690 let ParserMethod = "parseModImm"; 691} 692def mod_imm : Operand<i32>, ImmLeaf<i32, [{ 693 return ARM_AM::getSOImmVal(Imm) != -1; 694 }]> { 695 let EncoderMethod = "getModImmOpValue"; 696 let PrintMethod = "printModImmOperand"; 697 let ParserMatchClass = ModImmAsmOperand; 698} 699 700// Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder 701// method and such, as they are only used on aliases (Pat<> and InstAlias<>). 702// The actual parsing, encoding, decoding are handled by the destination 703// instructions, which use mod_imm. 704 705def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; } 706def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{ 707 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1; 708 }], imm_not_XFORM> { 709 let ParserMatchClass = ModImmNotAsmOperand; 710} 711 712def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; } 713def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{ 714 unsigned Value = -(unsigned)N->getZExtValue(); 715 return Value && ARM_AM::getSOImmVal(Value) != -1; 716 }], imm_neg_XFORM> { 717 let ParserMatchClass = ModImmNegAsmOperand; 718} 719 720/// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal() 721def arm_i32imm : PatLeaf<(imm), [{ 722 if (Subtarget->useMovt(*MF)) 723 return true; 724 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 725}]>; 726 727/// imm0_1 predicate - Immediate in the range [0,1]. 728def Imm0_1AsmOperand: ImmAsmOperand<0,1> { let Name = "Imm0_1"; } 729def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; } 730 731/// imm0_3 predicate - Immediate in the range [0,3]. 732def Imm0_3AsmOperand: ImmAsmOperand<0,3> { let Name = "Imm0_3"; } 733def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; } 734 735/// imm0_7 predicate - Immediate in the range [0,7]. 736def Imm0_7AsmOperand: ImmAsmOperand<0,7> { 737 let Name = "Imm0_7"; 738} 739def imm0_7 : Operand<i32>, ImmLeaf<i32, [{ 740 return Imm >= 0 && Imm < 8; 741}]> { 742 let ParserMatchClass = Imm0_7AsmOperand; 743} 744 745/// imm8_255 predicate - Immediate in the range [8,255]. 746def Imm8_255AsmOperand: ImmAsmOperand<8,255> { let Name = "Imm8_255"; } 747def imm8_255 : Operand<i32>, ImmLeaf<i32, [{ 748 return Imm >= 8 && Imm < 256; 749}]> { 750 let ParserMatchClass = Imm8_255AsmOperand; 751} 752 753/// imm8 predicate - Immediate is exactly 8. 754def Imm8AsmOperand: ImmAsmOperand<8,8> { let Name = "Imm8"; } 755def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> { 756 let ParserMatchClass = Imm8AsmOperand; 757} 758 759/// imm16 predicate - Immediate is exactly 16. 760def Imm16AsmOperand: ImmAsmOperand<16,16> { let Name = "Imm16"; } 761def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> { 762 let ParserMatchClass = Imm16AsmOperand; 763} 764 765/// imm32 predicate - Immediate is exactly 32. 766def Imm32AsmOperand: ImmAsmOperand<32,32> { let Name = "Imm32"; } 767def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> { 768 let ParserMatchClass = Imm32AsmOperand; 769} 770 771def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>; 772 773/// imm1_7 predicate - Immediate in the range [1,7]. 774def Imm1_7AsmOperand: ImmAsmOperand<1,7> { let Name = "Imm1_7"; } 775def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> { 776 let ParserMatchClass = Imm1_7AsmOperand; 777} 778 779/// imm1_15 predicate - Immediate in the range [1,15]. 780def Imm1_15AsmOperand: ImmAsmOperand<1,15> { let Name = "Imm1_15"; } 781def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> { 782 let ParserMatchClass = Imm1_15AsmOperand; 783} 784 785/// imm1_31 predicate - Immediate in the range [1,31]. 786def Imm1_31AsmOperand: ImmAsmOperand<1,31> { let Name = "Imm1_31"; } 787def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> { 788 let ParserMatchClass = Imm1_31AsmOperand; 789} 790 791/// imm0_15 predicate - Immediate in the range [0,15]. 792def Imm0_15AsmOperand: ImmAsmOperand<0,15> { 793 let Name = "Imm0_15"; 794} 795def imm0_15 : Operand<i32>, ImmLeaf<i32, [{ 796 return Imm >= 0 && Imm < 16; 797}]> { 798 let ParserMatchClass = Imm0_15AsmOperand; 799} 800 801/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31]. 802def Imm0_31AsmOperand: ImmAsmOperand<0,31> { let Name = "Imm0_31"; } 803def imm0_31 : Operand<i32>, ImmLeaf<i32, [{ 804 return Imm >= 0 && Imm < 32; 805}]> { 806 let ParserMatchClass = Imm0_31AsmOperand; 807} 808 809/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32]. 810def Imm0_32AsmOperand: ImmAsmOperand<0,32> { let Name = "Imm0_32"; } 811def imm0_32 : Operand<i32>, ImmLeaf<i32, [{ 812 return Imm >= 0 && Imm < 33; 813}]> { 814 let ParserMatchClass = Imm0_32AsmOperand; 815} 816 817/// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63]. 818def Imm0_63AsmOperand: ImmAsmOperand<0,63> { let Name = "Imm0_63"; } 819def imm0_63 : Operand<i32>, ImmLeaf<i32, [{ 820 return Imm >= 0 && Imm < 64; 821}]> { 822 let ParserMatchClass = Imm0_63AsmOperand; 823} 824 825/// imm0_239 predicate - Immediate in the range [0,239]. 826def Imm0_239AsmOperand : ImmAsmOperand<0,239> { 827 let Name = "Imm0_239"; 828} 829def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> { 830 let ParserMatchClass = Imm0_239AsmOperand; 831} 832 833/// imm0_255 predicate - Immediate in the range [0,255]. 834def Imm0_255AsmOperand : ImmAsmOperand<0,255> { let Name = "Imm0_255"; } 835def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> { 836 let ParserMatchClass = Imm0_255AsmOperand; 837} 838 839/// imm0_65535 - An immediate is in the range [0,65535]. 840def Imm0_65535AsmOperand: ImmAsmOperand<0,65535> { let Name = "Imm0_65535"; } 841def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{ 842 return Imm >= 0 && Imm < 65536; 843}]> { 844 let ParserMatchClass = Imm0_65535AsmOperand; 845} 846 847// imm0_65535_neg - An immediate whose negative value is in the range [0.65535]. 848def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{ 849 return -Imm >= 0 && -Imm < 65536; 850}]>; 851 852// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference 853// a relocatable expression. 854// 855// FIXME: This really needs a Thumb version separate from the ARM version. 856// While the range is the same, and can thus use the same match class, 857// the encoding is different so it should have a different encoder method. 858def Imm0_65535ExprAsmOperand: AsmOperandClass { 859 let Name = "Imm0_65535Expr"; 860 let RenderMethod = "addImmOperands"; 861 let DiagnosticString = "operand must be an immediate in the range [0,0xffff] or a relocatable expression"; 862} 863 864def imm0_65535_expr : Operand<i32> { 865 let EncoderMethod = "getHiLo16ImmOpValue"; 866 let ParserMatchClass = Imm0_65535ExprAsmOperand; 867} 868 869def Imm256_65535ExprAsmOperand: ImmAsmOperand<256,65535> { let Name = "Imm256_65535Expr"; } 870def imm256_65535_expr : Operand<i32> { 871 let ParserMatchClass = Imm256_65535ExprAsmOperand; 872} 873 874/// imm24b - True if the 32-bit immediate is encodable in 24 bits. 875def Imm24bitAsmOperand: ImmAsmOperand<0,0xffffff> { 876 let Name = "Imm24bit"; 877 let DiagnosticString = "operand must be an immediate in the range [0,0xffffff]"; 878} 879def imm24b : Operand<i32>, ImmLeaf<i32, [{ 880 return Imm >= 0 && Imm <= 0xffffff; 881}]> { 882 let ParserMatchClass = Imm24bitAsmOperand; 883} 884 885 886/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield 887/// e.g., 0xf000ffff 888def BitfieldAsmOperand : AsmOperandClass { 889 let Name = "Bitfield"; 890 let ParserMethod = "parseBitfield"; 891} 892 893def bf_inv_mask_imm : Operand<i32>, 894 PatLeaf<(imm), [{ 895 return ARM::isBitFieldInvertedMask(N->getZExtValue()); 896}] > { 897 let EncoderMethod = "getBitfieldInvertedMaskOpValue"; 898 let PrintMethod = "printBitfieldInvMaskImmOperand"; 899 let DecoderMethod = "DecodeBitfieldMaskOperand"; 900 let ParserMatchClass = BitfieldAsmOperand; 901 let GISelPredicateCode = [{ 902 // There's better methods of implementing this check. IntImmLeaf<> would be 903 // equivalent and have less boilerplate but we need a test for C++ 904 // predicates and this one causes new rules to be imported into GlobalISel 905 // without requiring additional features first. 906 const auto &MO = MI.getOperand(1); 907 if (!MO.isCImm()) 908 return false; 909 return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue()); 910 }]; 911} 912 913def imm1_32_XFORM: SDNodeXForm<imm, [{ 914 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 915 MVT::i32); 916}]>; 917def Imm1_32AsmOperand: ImmAsmOperandMinusOne<1,32> { 918 let Name = "Imm1_32"; 919} 920def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ 921 uint64_t Imm = N->getZExtValue(); 922 return Imm > 0 && Imm <= 32; 923 }], 924 imm1_32_XFORM> { 925 let PrintMethod = "printImmPlusOneOperand"; 926 let ParserMatchClass = Imm1_32AsmOperand; 927} 928 929def imm1_16_XFORM: SDNodeXForm<imm, [{ 930 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 931 MVT::i32); 932}]>; 933def Imm1_16AsmOperand: ImmAsmOperandMinusOne<1,16> { let Name = "Imm1_16"; } 934def imm1_16 : Operand<i32>, ImmLeaf<i32, [{ 935 return Imm > 0 && Imm <= 16; 936 }], 937 imm1_16_XFORM> { 938 let PrintMethod = "printImmPlusOneOperand"; 939 let ParserMatchClass = Imm1_16AsmOperand; 940} 941 942// Define ARM specific addressing modes. 943// addrmode_imm12 := reg +/- imm12 944// 945def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; } 946class AddrMode_Imm12 : MemOperand, 947 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> { 948 // 12-bit immediate operand. Note that instructions using this encode 949 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other 950 // immediate values are as normal. 951 952 let EncoderMethod = "getAddrModeImm12OpValue"; 953 let DecoderMethod = "DecodeAddrModeImm12Operand"; 954 let ParserMatchClass = MemImm12OffsetAsmOperand; 955 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 956} 957 958def addrmode_imm12 : AddrMode_Imm12 { 959 let PrintMethod = "printAddrModeImm12Operand<false>"; 960} 961 962def addrmode_imm12_pre : AddrMode_Imm12 { 963 let PrintMethod = "printAddrModeImm12Operand<true>"; 964} 965 966// ldst_so_reg := reg +/- reg shop imm 967// 968def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; } 969def ldst_so_reg : MemOperand, 970 ComplexPattern<i32, 3, "SelectLdStSOReg", []> { 971 let EncoderMethod = "getLdStSORegOpValue"; 972 // FIXME: Simplify the printer 973 let PrintMethod = "printAddrMode2Operand"; 974 let DecoderMethod = "DecodeSORegMemOperand"; 975 let ParserMatchClass = MemRegOffsetAsmOperand; 976 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift); 977} 978 979// postidx_imm8 := +/- [0,255] 980// 981// 9 bit value: 982// {8} 1 is imm8 is non-negative. 0 otherwise. 983// {7-0} [0,255] imm8 value. 984def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; } 985def postidx_imm8 : MemOperand { 986 let PrintMethod = "printPostIdxImm8Operand"; 987 let ParserMatchClass = PostIdxImm8AsmOperand; 988 let MIOperandInfo = (ops i32imm); 989} 990 991// postidx_imm8s4 := +/- [0,1020] 992// 993// 9 bit value: 994// {8} 1 is imm8 is non-negative. 0 otherwise. 995// {7-0} [0,255] imm8 value, scaled by 4. 996def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; } 997def postidx_imm8s4 : MemOperand { 998 let PrintMethod = "printPostIdxImm8s4Operand"; 999 let ParserMatchClass = PostIdxImm8s4AsmOperand; 1000 let MIOperandInfo = (ops i32imm); 1001} 1002 1003 1004// postidx_reg := +/- reg 1005// 1006def PostIdxRegAsmOperand : AsmOperandClass { 1007 let Name = "PostIdxReg"; 1008 let ParserMethod = "parsePostIdxReg"; 1009} 1010def postidx_reg : MemOperand { 1011 let EncoderMethod = "getPostIdxRegOpValue"; 1012 let DecoderMethod = "DecodePostIdxReg"; 1013 let PrintMethod = "printPostIdxRegOperand"; 1014 let ParserMatchClass = PostIdxRegAsmOperand; 1015 let MIOperandInfo = (ops GPRnopc, i32imm); 1016} 1017 1018def PostIdxRegShiftedAsmOperand : AsmOperandClass { 1019 let Name = "PostIdxRegShifted"; 1020 let ParserMethod = "parsePostIdxReg"; 1021} 1022def am2offset_reg : MemOperand, 1023 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg", 1024 [], [SDNPWantRoot]> { 1025 let EncoderMethod = "getAddrMode2OffsetOpValue"; 1026 let PrintMethod = "printAddrMode2OffsetOperand"; 1027 // When using this for assembly, it's always as a post-index offset. 1028 let ParserMatchClass = PostIdxRegShiftedAsmOperand; 1029 let MIOperandInfo = (ops GPRnopc, i32imm); 1030} 1031 1032// FIXME: am2offset_imm should only need the immediate, not the GPR. Having 1033// the GPR is purely vestigal at this point. 1034def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; } 1035def am2offset_imm : MemOperand, 1036 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm", 1037 [], [SDNPWantRoot]> { 1038 let EncoderMethod = "getAddrMode2OffsetOpValue"; 1039 let PrintMethod = "printAddrMode2OffsetOperand"; 1040 let ParserMatchClass = AM2OffsetImmAsmOperand; 1041 let MIOperandInfo = (ops GPRnopc, i32imm); 1042} 1043 1044 1045// addrmode3 := reg +/- reg 1046// addrmode3 := reg +/- imm8 1047// 1048// FIXME: split into imm vs. reg versions. 1049def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; } 1050class AddrMode3 : MemOperand, 1051 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 1052 let EncoderMethod = "getAddrMode3OpValue"; 1053 let ParserMatchClass = AddrMode3AsmOperand; 1054 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 1055} 1056 1057def addrmode3 : AddrMode3 1058{ 1059 let PrintMethod = "printAddrMode3Operand<false>"; 1060} 1061 1062def addrmode3_pre : AddrMode3 1063{ 1064 let PrintMethod = "printAddrMode3Operand<true>"; 1065} 1066 1067// FIXME: split into imm vs. reg versions. 1068// FIXME: parser method to handle +/- register. 1069def AM3OffsetAsmOperand : AsmOperandClass { 1070 let Name = "AM3Offset"; 1071 let ParserMethod = "parseAM3Offset"; 1072} 1073def am3offset : MemOperand, 1074 ComplexPattern<i32, 2, "SelectAddrMode3Offset", 1075 [], [SDNPWantRoot]> { 1076 let EncoderMethod = "getAddrMode3OffsetOpValue"; 1077 let PrintMethod = "printAddrMode3OffsetOperand"; 1078 let ParserMatchClass = AM3OffsetAsmOperand; 1079 let MIOperandInfo = (ops GPR, i32imm); 1080} 1081 1082// ldstm_mode := {ia, ib, da, db} 1083// 1084def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> { 1085 let EncoderMethod = "getLdStmModeOpValue"; 1086 let PrintMethod = "printLdStmModeOperand"; 1087} 1088 1089// addrmode5 := reg +/- imm8*4 1090// 1091def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; } 1092class AddrMode5 : MemOperand, 1093 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 1094 let EncoderMethod = "getAddrMode5OpValue"; 1095 let DecoderMethod = "DecodeAddrMode5Operand"; 1096 let ParserMatchClass = AddrMode5AsmOperand; 1097 let MIOperandInfo = (ops GPR:$base, i32imm); 1098} 1099 1100def addrmode5 : AddrMode5 { 1101 let PrintMethod = "printAddrMode5Operand<false>"; 1102} 1103 1104def addrmode5_pre : AddrMode5 { 1105 let PrintMethod = "printAddrMode5Operand<true>"; 1106} 1107 1108// addrmode5fp16 := reg +/- imm8*2 1109// 1110def AddrMode5FP16AsmOperand : AsmOperandClass { let Name = "AddrMode5FP16"; } 1111class AddrMode5FP16 : Operand<i32>, 1112 ComplexPattern<i32, 2, "SelectAddrMode5FP16", []> { 1113 let EncoderMethod = "getAddrMode5FP16OpValue"; 1114 let DecoderMethod = "DecodeAddrMode5FP16Operand"; 1115 let ParserMatchClass = AddrMode5FP16AsmOperand; 1116 let MIOperandInfo = (ops GPR:$base, i32imm); 1117} 1118 1119def addrmode5fp16 : AddrMode5FP16 { 1120 let PrintMethod = "printAddrMode5FP16Operand<false>"; 1121} 1122 1123// addrmode6 := reg with optional alignment 1124// 1125def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; } 1126def addrmode6 : MemOperand, 1127 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1128 let PrintMethod = "printAddrMode6Operand"; 1129 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1130 let EncoderMethod = "getAddrMode6AddressOpValue"; 1131 let DecoderMethod = "DecodeAddrMode6Operand"; 1132 let ParserMatchClass = AddrMode6AsmOperand; 1133} 1134 1135def am6offset : MemOperand, 1136 ComplexPattern<i32, 1, "SelectAddrMode6Offset", 1137 [], [SDNPWantRoot]> { 1138 let PrintMethod = "printAddrMode6OffsetOperand"; 1139 let MIOperandInfo = (ops GPR); 1140 let EncoderMethod = "getAddrMode6OffsetOpValue"; 1141 let DecoderMethod = "DecodeGPRRegisterClass"; 1142} 1143 1144// Special version of addrmode6 to handle alignment encoding for VST1/VLD1 1145// (single element from one lane) for size 32. 1146def addrmode6oneL32 : MemOperand, 1147 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1148 let PrintMethod = "printAddrMode6Operand"; 1149 let MIOperandInfo = (ops GPR:$addr, i32imm); 1150 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue"; 1151} 1152 1153// Base class for addrmode6 with specific alignment restrictions. 1154class AddrMode6Align : MemOperand, 1155 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1156 let PrintMethod = "printAddrMode6Operand"; 1157 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1158 let EncoderMethod = "getAddrMode6AddressOpValue"; 1159 let DecoderMethod = "DecodeAddrMode6Operand"; 1160} 1161 1162// Special version of addrmode6 to handle no allowed alignment encoding for 1163// VLD/VST instructions and checking the alignment is not specified. 1164def AddrMode6AlignNoneAsmOperand : AsmOperandClass { 1165 let Name = "AlignedMemoryNone"; 1166 let DiagnosticString = "alignment must be omitted"; 1167} 1168def addrmode6alignNone : AddrMode6Align { 1169 // The alignment specifier can only be omitted. 1170 let ParserMatchClass = AddrMode6AlignNoneAsmOperand; 1171} 1172 1173// Special version of addrmode6 to handle 16-bit alignment encoding for 1174// VLD/VST instructions and checking the alignment value. 1175def AddrMode6Align16AsmOperand : AsmOperandClass { 1176 let Name = "AlignedMemory16"; 1177 let DiagnosticString = "alignment must be 16 or omitted"; 1178} 1179def addrmode6align16 : AddrMode6Align { 1180 // The alignment specifier can only be 16 or omitted. 1181 let ParserMatchClass = AddrMode6Align16AsmOperand; 1182} 1183 1184// Special version of addrmode6 to handle 32-bit alignment encoding for 1185// VLD/VST instructions and checking the alignment value. 1186def AddrMode6Align32AsmOperand : AsmOperandClass { 1187 let Name = "AlignedMemory32"; 1188 let DiagnosticString = "alignment must be 32 or omitted"; 1189} 1190def addrmode6align32 : AddrMode6Align { 1191 // The alignment specifier can only be 32 or omitted. 1192 let ParserMatchClass = AddrMode6Align32AsmOperand; 1193} 1194 1195// Special version of addrmode6 to handle 64-bit alignment encoding for 1196// VLD/VST instructions and checking the alignment value. 1197def AddrMode6Align64AsmOperand : AsmOperandClass { 1198 let Name = "AlignedMemory64"; 1199 let DiagnosticString = "alignment must be 64 or omitted"; 1200} 1201def addrmode6align64 : AddrMode6Align { 1202 // The alignment specifier can only be 64 or omitted. 1203 let ParserMatchClass = AddrMode6Align64AsmOperand; 1204} 1205 1206// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1207// for VLD/VST instructions and checking the alignment value. 1208def AddrMode6Align64or128AsmOperand : AsmOperandClass { 1209 let Name = "AlignedMemory64or128"; 1210 let DiagnosticString = "alignment must be 64, 128 or omitted"; 1211} 1212def addrmode6align64or128 : AddrMode6Align { 1213 // The alignment specifier can only be 64, 128 or omitted. 1214 let ParserMatchClass = AddrMode6Align64or128AsmOperand; 1215} 1216 1217// Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment 1218// encoding for VLD/VST instructions and checking the alignment value. 1219def AddrMode6Align64or128or256AsmOperand : AsmOperandClass { 1220 let Name = "AlignedMemory64or128or256"; 1221 let DiagnosticString = "alignment must be 64, 128, 256 or omitted"; 1222} 1223def addrmode6align64or128or256 : AddrMode6Align { 1224 // The alignment specifier can only be 64, 128, 256 or omitted. 1225 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand; 1226} 1227 1228// Special version of addrmode6 to handle alignment encoding for VLD-dup 1229// instructions, specifically VLD4-dup. 1230def addrmode6dup : MemOperand, 1231 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1232 let PrintMethod = "printAddrMode6Operand"; 1233 let MIOperandInfo = (ops GPR:$addr, i32imm); 1234 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1235 // FIXME: This is close, but not quite right. The alignment specifier is 1236 // different. 1237 let ParserMatchClass = AddrMode6AsmOperand; 1238} 1239 1240// Base class for addrmode6dup with specific alignment restrictions. 1241class AddrMode6DupAlign : MemOperand, 1242 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1243 let PrintMethod = "printAddrMode6Operand"; 1244 let MIOperandInfo = (ops GPR:$addr, i32imm); 1245 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1246} 1247 1248// Special version of addrmode6 to handle no allowed alignment encoding for 1249// VLD-dup instruction and checking the alignment is not specified. 1250def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass { 1251 let Name = "DupAlignedMemoryNone"; 1252 let DiagnosticString = "alignment must be omitted"; 1253} 1254def addrmode6dupalignNone : AddrMode6DupAlign { 1255 // The alignment specifier can only be omitted. 1256 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand; 1257} 1258 1259// Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup 1260// instruction and checking the alignment value. 1261def AddrMode6dupAlign16AsmOperand : AsmOperandClass { 1262 let Name = "DupAlignedMemory16"; 1263 let DiagnosticString = "alignment must be 16 or omitted"; 1264} 1265def addrmode6dupalign16 : AddrMode6DupAlign { 1266 // The alignment specifier can only be 16 or omitted. 1267 let ParserMatchClass = AddrMode6dupAlign16AsmOperand; 1268} 1269 1270// Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup 1271// instruction and checking the alignment value. 1272def AddrMode6dupAlign32AsmOperand : AsmOperandClass { 1273 let Name = "DupAlignedMemory32"; 1274 let DiagnosticString = "alignment must be 32 or omitted"; 1275} 1276def addrmode6dupalign32 : AddrMode6DupAlign { 1277 // The alignment specifier can only be 32 or omitted. 1278 let ParserMatchClass = AddrMode6dupAlign32AsmOperand; 1279} 1280 1281// Special version of addrmode6 to handle 64-bit alignment encoding for VLD 1282// instructions and checking the alignment value. 1283def AddrMode6dupAlign64AsmOperand : AsmOperandClass { 1284 let Name = "DupAlignedMemory64"; 1285 let DiagnosticString = "alignment must be 64 or omitted"; 1286} 1287def addrmode6dupalign64 : AddrMode6DupAlign { 1288 // The alignment specifier can only be 64 or omitted. 1289 let ParserMatchClass = AddrMode6dupAlign64AsmOperand; 1290} 1291 1292// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1293// for VLD instructions and checking the alignment value. 1294def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass { 1295 let Name = "DupAlignedMemory64or128"; 1296 let DiagnosticString = "alignment must be 64, 128 or omitted"; 1297} 1298def addrmode6dupalign64or128 : AddrMode6DupAlign { 1299 // The alignment specifier can only be 64, 128 or omitted. 1300 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand; 1301} 1302 1303// addrmodepc := pc + reg 1304// 1305def addrmodepc : MemOperand, 1306 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 1307 let PrintMethod = "printAddrModePCOperand"; 1308 let MIOperandInfo = (ops GPR, i32imm); 1309} 1310 1311// addr_offset_none := reg 1312// 1313def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; } 1314def addr_offset_none : MemOperand, 1315 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> { 1316 let PrintMethod = "printAddrMode7Operand"; 1317 let DecoderMethod = "DecodeAddrMode7Operand"; 1318 let ParserMatchClass = MemNoOffsetAsmOperand; 1319 let MIOperandInfo = (ops GPR:$base); 1320} 1321 1322def nohash_imm : Operand<i32> { 1323 let PrintMethod = "printNoHashImmediate"; 1324} 1325 1326def CoprocNumAsmOperand : AsmOperandClass { 1327 let Name = "CoprocNum"; 1328 let ParserMethod = "parseCoprocNumOperand"; 1329} 1330def p_imm : Operand<i32> { 1331 let PrintMethod = "printPImmediate"; 1332 let ParserMatchClass = CoprocNumAsmOperand; 1333 let DecoderMethod = "DecodeCoprocessor"; 1334} 1335 1336def CoprocRegAsmOperand : AsmOperandClass { 1337 let Name = "CoprocReg"; 1338 let ParserMethod = "parseCoprocRegOperand"; 1339} 1340def c_imm : Operand<i32> { 1341 let PrintMethod = "printCImmediate"; 1342 let ParserMatchClass = CoprocRegAsmOperand; 1343} 1344def CoprocOptionAsmOperand : AsmOperandClass { 1345 let Name = "CoprocOption"; 1346 let ParserMethod = "parseCoprocOptionOperand"; 1347} 1348def coproc_option_imm : Operand<i32> { 1349 let PrintMethod = "printCoprocOptionImm"; 1350 let ParserMatchClass = CoprocOptionAsmOperand; 1351} 1352 1353//===----------------------------------------------------------------------===// 1354 1355include "ARMInstrFormats.td" 1356 1357//===----------------------------------------------------------------------===// 1358// Multiclass helpers... 1359// 1360 1361/// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a 1362/// binop that produces a value. 1363let TwoOperandAliasConstraint = "$Rn = $Rd" in 1364multiclass AsI1_bin_irs<bits<4> opcod, string opc, 1365 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1366 SDPatternOperator opnode, bit Commutable = 0> { 1367 // The register-immediate version is re-materializable. This is useful 1368 // in particular for taking the address of a local. 1369 let isReMaterializable = 1 in { 1370 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1371 iii, opc, "\t$Rd, $Rn, $imm", 1372 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>, 1373 Sched<[WriteALU, ReadALU]> { 1374 bits<4> Rd; 1375 bits<4> Rn; 1376 bits<12> imm; 1377 let Inst{25} = 1; 1378 let Inst{19-16} = Rn; 1379 let Inst{15-12} = Rd; 1380 let Inst{11-0} = imm; 1381 } 1382 } 1383 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1384 iir, opc, "\t$Rd, $Rn, $Rm", 1385 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, 1386 Sched<[WriteALU, ReadALU, ReadALU]> { 1387 bits<4> Rd; 1388 bits<4> Rn; 1389 bits<4> Rm; 1390 let Inst{25} = 0; 1391 let isCommutable = Commutable; 1392 let Inst{19-16} = Rn; 1393 let Inst{15-12} = Rd; 1394 let Inst{11-4} = 0b00000000; 1395 let Inst{3-0} = Rm; 1396 } 1397 1398 def rsi : AsI1<opcod, (outs GPR:$Rd), 1399 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1400 iis, opc, "\t$Rd, $Rn, $shift", 1401 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>, 1402 Sched<[WriteALUsi, ReadALU]> { 1403 bits<4> Rd; 1404 bits<4> Rn; 1405 bits<12> shift; 1406 let Inst{25} = 0; 1407 let Inst{19-16} = Rn; 1408 let Inst{15-12} = Rd; 1409 let Inst{11-5} = shift{11-5}; 1410 let Inst{4} = 0; 1411 let Inst{3-0} = shift{3-0}; 1412 } 1413 1414 def rsr : AsI1<opcod, (outs GPR:$Rd), 1415 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1416 iis, opc, "\t$Rd, $Rn, $shift", 1417 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>, 1418 Sched<[WriteALUsr, ReadALUsr]> { 1419 bits<4> Rd; 1420 bits<4> Rn; 1421 bits<12> shift; 1422 let Inst{25} = 0; 1423 let Inst{19-16} = Rn; 1424 let Inst{15-12} = Rd; 1425 let Inst{11-8} = shift{11-8}; 1426 let Inst{7} = 0; 1427 let Inst{6-5} = shift{6-5}; 1428 let Inst{4} = 1; 1429 let Inst{3-0} = shift{3-0}; 1430 } 1431} 1432 1433/// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are 1434/// reversed. The 'rr' form is only defined for the disassembler; for codegen 1435/// it is equivalent to the AsI1_bin_irs counterpart. 1436let TwoOperandAliasConstraint = "$Rn = $Rd" in 1437multiclass AsI1_rbin_irs<bits<4> opcod, string opc, 1438 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1439 SDNode opnode, bit Commutable = 0> { 1440 // The register-immediate version is re-materializable. This is useful 1441 // in particular for taking the address of a local. 1442 let isReMaterializable = 1 in { 1443 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1444 iii, opc, "\t$Rd, $Rn, $imm", 1445 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>, 1446 Sched<[WriteALU, ReadALU]> { 1447 bits<4> Rd; 1448 bits<4> Rn; 1449 bits<12> imm; 1450 let Inst{25} = 1; 1451 let Inst{19-16} = Rn; 1452 let Inst{15-12} = Rd; 1453 let Inst{11-0} = imm; 1454 } 1455 } 1456 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1457 iir, opc, "\t$Rd, $Rn, $Rm", 1458 [/* pattern left blank */]>, 1459 Sched<[WriteALU, ReadALU, ReadALU]> { 1460 bits<4> Rd; 1461 bits<4> Rn; 1462 bits<4> Rm; 1463 let Inst{11-4} = 0b00000000; 1464 let Inst{25} = 0; 1465 let Inst{3-0} = Rm; 1466 let Inst{15-12} = Rd; 1467 let Inst{19-16} = Rn; 1468 } 1469 1470 def rsi : AsI1<opcod, (outs GPR:$Rd), 1471 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1472 iis, opc, "\t$Rd, $Rn, $shift", 1473 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>, 1474 Sched<[WriteALUsi, ReadALU]> { 1475 bits<4> Rd; 1476 bits<4> Rn; 1477 bits<12> shift; 1478 let Inst{25} = 0; 1479 let Inst{19-16} = Rn; 1480 let Inst{15-12} = Rd; 1481 let Inst{11-5} = shift{11-5}; 1482 let Inst{4} = 0; 1483 let Inst{3-0} = shift{3-0}; 1484 } 1485 1486 def rsr : AsI1<opcod, (outs GPR:$Rd), 1487 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1488 iis, opc, "\t$Rd, $Rn, $shift", 1489 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>, 1490 Sched<[WriteALUsr, ReadALUsr]> { 1491 bits<4> Rd; 1492 bits<4> Rn; 1493 bits<12> shift; 1494 let Inst{25} = 0; 1495 let Inst{19-16} = Rn; 1496 let Inst{15-12} = Rd; 1497 let Inst{11-8} = shift{11-8}; 1498 let Inst{7} = 0; 1499 let Inst{6-5} = shift{6-5}; 1500 let Inst{4} = 1; 1501 let Inst{3-0} = shift{3-0}; 1502 } 1503} 1504 1505/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default. 1506/// 1507/// These opcodes will be converted to the real non-S opcodes by 1508/// AdjustInstrPostInstrSelection after giving them an optional CPSR operand. 1509let hasPostISelHook = 1, Defs = [CPSR] in { 1510multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir, 1511 InstrItinClass iis, SDNode opnode, 1512 bit Commutable = 0> { 1513 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1514 4, iii, 1515 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>, 1516 Sched<[WriteALU, ReadALU]>; 1517 1518 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p), 1519 4, iir, 1520 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>, 1521 Sched<[WriteALU, ReadALU, ReadALU]> { 1522 let isCommutable = Commutable; 1523 } 1524 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1525 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1526 4, iis, 1527 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1528 so_reg_imm:$shift))]>, 1529 Sched<[WriteALUsi, ReadALU]>; 1530 1531 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1532 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1533 4, iis, 1534 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1535 so_reg_reg:$shift))]>, 1536 Sched<[WriteALUSsr, ReadALUsr]>; 1537} 1538} 1539 1540/// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG 1541/// operands are reversed. 1542let hasPostISelHook = 1, Defs = [CPSR] in { 1543multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir, 1544 InstrItinClass iis, SDNode opnode, 1545 bit Commutable = 0> { 1546 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1547 4, iii, 1548 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>, 1549 Sched<[WriteALU, ReadALU]>; 1550 1551 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1552 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1553 4, iis, 1554 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, 1555 GPR:$Rn))]>, 1556 Sched<[WriteALUsi, ReadALU]>; 1557 1558 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1559 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1560 4, iis, 1561 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, 1562 GPR:$Rn))]>, 1563 Sched<[WriteALUSsr, ReadALUsr]>; 1564} 1565} 1566 1567/// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test 1568/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 1569/// a explicit result, only implicitly set CPSR. 1570let isCompare = 1, Defs = [CPSR] in { 1571multiclass AI1_cmp_irs<bits<4> opcod, string opc, 1572 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1573 SDPatternOperator opnode, bit Commutable = 0, 1574 string rrDecoderMethod = ""> { 1575 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii, 1576 opc, "\t$Rn, $imm", 1577 [(opnode GPR:$Rn, mod_imm:$imm)]>, 1578 Sched<[WriteCMP, ReadALU]> { 1579 bits<4> Rn; 1580 bits<12> imm; 1581 let Inst{25} = 1; 1582 let Inst{20} = 1; 1583 let Inst{19-16} = Rn; 1584 let Inst{15-12} = 0b0000; 1585 let Inst{11-0} = imm; 1586 1587 let Unpredictable{15-12} = 0b1111; 1588 } 1589 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir, 1590 opc, "\t$Rn, $Rm", 1591 [(opnode GPR:$Rn, GPR:$Rm)]>, 1592 Sched<[WriteCMP, ReadALU, ReadALU]> { 1593 bits<4> Rn; 1594 bits<4> Rm; 1595 let isCommutable = Commutable; 1596 let Inst{25} = 0; 1597 let Inst{20} = 1; 1598 let Inst{19-16} = Rn; 1599 let Inst{15-12} = 0b0000; 1600 let Inst{11-4} = 0b00000000; 1601 let Inst{3-0} = Rm; 1602 let DecoderMethod = rrDecoderMethod; 1603 1604 let Unpredictable{15-12} = 0b1111; 1605 } 1606 def rsi : AI1<opcod, (outs), 1607 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis, 1608 opc, "\t$Rn, $shift", 1609 [(opnode GPR:$Rn, so_reg_imm:$shift)]>, 1610 Sched<[WriteCMPsi, ReadALU]> { 1611 bits<4> Rn; 1612 bits<12> shift; 1613 let Inst{25} = 0; 1614 let Inst{20} = 1; 1615 let Inst{19-16} = Rn; 1616 let Inst{15-12} = 0b0000; 1617 let Inst{11-5} = shift{11-5}; 1618 let Inst{4} = 0; 1619 let Inst{3-0} = shift{3-0}; 1620 1621 let Unpredictable{15-12} = 0b1111; 1622 } 1623 def rsr : AI1<opcod, (outs), 1624 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis, 1625 opc, "\t$Rn, $shift", 1626 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>, 1627 Sched<[WriteCMPsr, ReadALU]> { 1628 bits<4> Rn; 1629 bits<12> shift; 1630 let Inst{25} = 0; 1631 let Inst{20} = 1; 1632 let Inst{19-16} = Rn; 1633 let Inst{15-12} = 0b0000; 1634 let Inst{11-8} = shift{11-8}; 1635 let Inst{7} = 0; 1636 let Inst{6-5} = shift{6-5}; 1637 let Inst{4} = 1; 1638 let Inst{3-0} = shift{3-0}; 1639 1640 let Unpredictable{15-12} = 0b1111; 1641 } 1642 1643} 1644} 1645 1646/// AI_ext_rrot - A unary operation with two forms: one whose operand is a 1647/// register and one whose operand is a register rotated by 8/16/24. 1648/// FIXME: Remove the 'r' variant. Its rot_imm is zero. 1649class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> 1650 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1651 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", 1652 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1653 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1654 bits<4> Rd; 1655 bits<4> Rm; 1656 bits<2> rot; 1657 let Inst{19-16} = 0b1111; 1658 let Inst{15-12} = Rd; 1659 let Inst{11-10} = rot; 1660 let Inst{3-0} = Rm; 1661} 1662 1663class AI_ext_rrot_np<bits<8> opcod, string opc> 1664 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1665 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>, 1666 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1667 bits<2> rot; 1668 let Inst{19-16} = 0b1111; 1669 let Inst{11-10} = rot; 1670 } 1671 1672/// AI_exta_rrot - A binary operation with two forms: one whose operand is a 1673/// register and one whose operand is a register rotated by 8/16/24. 1674class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> 1675 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1676 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", 1677 [(set GPRnopc:$Rd, (opnode GPR:$Rn, 1678 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1679 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1680 bits<4> Rd; 1681 bits<4> Rm; 1682 bits<4> Rn; 1683 bits<2> rot; 1684 let Inst{19-16} = Rn; 1685 let Inst{15-12} = Rd; 1686 let Inst{11-10} = rot; 1687 let Inst{9-4} = 0b000111; 1688 let Inst{3-0} = Rm; 1689} 1690 1691class AI_exta_rrot_np<bits<8> opcod, string opc> 1692 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1693 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>, 1694 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1695 bits<4> Rn; 1696 bits<2> rot; 1697 let Inst{19-16} = Rn; 1698 let Inst{11-10} = rot; 1699} 1700 1701/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. 1702let TwoOperandAliasConstraint = "$Rn = $Rd" in 1703multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode, 1704 bit Commutable = 0> { 1705 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1706 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1707 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1708 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>, 1709 Requires<[IsARM]>, 1710 Sched<[WriteALU, ReadALU]> { 1711 bits<4> Rd; 1712 bits<4> Rn; 1713 bits<12> imm; 1714 let Inst{25} = 1; 1715 let Inst{15-12} = Rd; 1716 let Inst{19-16} = Rn; 1717 let Inst{11-0} = imm; 1718 } 1719 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1720 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1721 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>, 1722 Requires<[IsARM]>, 1723 Sched<[WriteALU, ReadALU, ReadALU]> { 1724 bits<4> Rd; 1725 bits<4> Rn; 1726 bits<4> Rm; 1727 let Inst{11-4} = 0b00000000; 1728 let Inst{25} = 0; 1729 let isCommutable = Commutable; 1730 let Inst{3-0} = Rm; 1731 let Inst{15-12} = Rd; 1732 let Inst{19-16} = Rn; 1733 } 1734 def rsi : AsI1<opcod, (outs GPR:$Rd), 1735 (ins GPR:$Rn, so_reg_imm:$shift), 1736 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1737 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>, 1738 Requires<[IsARM]>, 1739 Sched<[WriteALUsi, ReadALU]> { 1740 bits<4> Rd; 1741 bits<4> Rn; 1742 bits<12> shift; 1743 let Inst{25} = 0; 1744 let Inst{19-16} = Rn; 1745 let Inst{15-12} = Rd; 1746 let Inst{11-5} = shift{11-5}; 1747 let Inst{4} = 0; 1748 let Inst{3-0} = shift{3-0}; 1749 } 1750 def rsr : AsI1<opcod, (outs GPRnopc:$Rd), 1751 (ins GPRnopc:$Rn, so_reg_reg:$shift), 1752 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1753 [(set GPRnopc:$Rd, CPSR, 1754 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>, 1755 Requires<[IsARM]>, 1756 Sched<[WriteALUsr, ReadALUsr]> { 1757 bits<4> Rd; 1758 bits<4> Rn; 1759 bits<12> shift; 1760 let Inst{25} = 0; 1761 let Inst{19-16} = Rn; 1762 let Inst{15-12} = Rd; 1763 let Inst{11-8} = shift{11-8}; 1764 let Inst{7} = 0; 1765 let Inst{6-5} = shift{6-5}; 1766 let Inst{4} = 1; 1767 let Inst{3-0} = shift{3-0}; 1768 } 1769 } 1770} 1771 1772/// AI1_rsc_irs - Define instructions and patterns for rsc 1773let TwoOperandAliasConstraint = "$Rn = $Rd" in 1774multiclass AI1_rsc_irs<bits<4> opcod, string opc, SDNode opnode> { 1775 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1776 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1777 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1778 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>, 1779 Requires<[IsARM]>, 1780 Sched<[WriteALU, ReadALU]> { 1781 bits<4> Rd; 1782 bits<4> Rn; 1783 bits<12> imm; 1784 let Inst{25} = 1; 1785 let Inst{15-12} = Rd; 1786 let Inst{19-16} = Rn; 1787 let Inst{11-0} = imm; 1788 } 1789 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1790 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1791 [/* pattern left blank */]>, 1792 Sched<[WriteALU, ReadALU, ReadALU]> { 1793 bits<4> Rd; 1794 bits<4> Rn; 1795 bits<4> Rm; 1796 let Inst{11-4} = 0b00000000; 1797 let Inst{25} = 0; 1798 let Inst{3-0} = Rm; 1799 let Inst{15-12} = Rd; 1800 let Inst{19-16} = Rn; 1801 } 1802 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), 1803 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1804 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>, 1805 Requires<[IsARM]>, 1806 Sched<[WriteALUsi, ReadALU]> { 1807 bits<4> Rd; 1808 bits<4> Rn; 1809 bits<12> shift; 1810 let Inst{25} = 0; 1811 let Inst{19-16} = Rn; 1812 let Inst{15-12} = Rd; 1813 let Inst{11-5} = shift{11-5}; 1814 let Inst{4} = 0; 1815 let Inst{3-0} = shift{3-0}; 1816 } 1817 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), 1818 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1819 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>, 1820 Requires<[IsARM]>, 1821 Sched<[WriteALUsr, ReadALUsr]> { 1822 bits<4> Rd; 1823 bits<4> Rn; 1824 bits<12> shift; 1825 let Inst{25} = 0; 1826 let Inst{19-16} = Rn; 1827 let Inst{15-12} = Rd; 1828 let Inst{11-8} = shift{11-8}; 1829 let Inst{7} = 0; 1830 let Inst{6-5} = shift{6-5}; 1831 let Inst{4} = 1; 1832 let Inst{3-0} = shift{3-0}; 1833 } 1834 } 1835} 1836 1837let canFoldAsLoad = 1, isReMaterializable = 1 in { 1838multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii, 1839 InstrItinClass iir, PatFrag opnode> { 1840 // Note: We use the complex addrmode_imm12 rather than just an input 1841 // GPR and a constrained immediate so that we can use this to match 1842 // frame index references and avoid matching constant pool references. 1843 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 1844 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1845 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { 1846 bits<4> Rt; 1847 bits<17> addr; 1848 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1849 let Inst{19-16} = addr{16-13}; // Rn 1850 let Inst{15-12} = Rt; 1851 let Inst{11-0} = addr{11-0}; // imm12 1852 } 1853 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift), 1854 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1855 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { 1856 bits<4> Rt; 1857 bits<17> shift; 1858 let shift{4} = 0; // Inst{4} = 0 1859 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1860 let Inst{19-16} = shift{16-13}; // Rn 1861 let Inst{15-12} = Rt; 1862 let Inst{11-0} = shift{11-0}; 1863 } 1864} 1865} 1866 1867let canFoldAsLoad = 1, isReMaterializable = 1 in { 1868multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii, 1869 InstrItinClass iir, PatFrag opnode> { 1870 // Note: We use the complex addrmode_imm12 rather than just an input 1871 // GPR and a constrained immediate so that we can use this to match 1872 // frame index references and avoid matching constant pool references. 1873 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), 1874 (ins addrmode_imm12:$addr), 1875 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1876 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> { 1877 bits<4> Rt; 1878 bits<17> addr; 1879 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1880 let Inst{19-16} = addr{16-13}; // Rn 1881 let Inst{15-12} = Rt; 1882 let Inst{11-0} = addr{11-0}; // imm12 1883 } 1884 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), 1885 (ins ldst_so_reg:$shift), 1886 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1887 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> { 1888 bits<4> Rt; 1889 bits<17> shift; 1890 let shift{4} = 0; // Inst{4} = 0 1891 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1892 let Inst{19-16} = shift{16-13}; // Rn 1893 let Inst{15-12} = Rt; 1894 let Inst{11-0} = shift{11-0}; 1895 } 1896} 1897} 1898 1899 1900multiclass AI_str1<bit isByte, string opc, InstrItinClass iii, 1901 InstrItinClass iir, PatFrag opnode> { 1902 // Note: We use the complex addrmode_imm12 rather than just an input 1903 // GPR and a constrained immediate so that we can use this to match 1904 // frame index references and avoid matching constant pool references. 1905 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1906 (ins GPR:$Rt, addrmode_imm12:$addr), 1907 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1908 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> { 1909 bits<4> Rt; 1910 bits<17> addr; 1911 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1912 let Inst{19-16} = addr{16-13}; // Rn 1913 let Inst{15-12} = Rt; 1914 let Inst{11-0} = addr{11-0}; // imm12 1915 } 1916 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift), 1917 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1918 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> { 1919 bits<4> Rt; 1920 bits<17> shift; 1921 let shift{4} = 0; // Inst{4} = 0 1922 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1923 let Inst{19-16} = shift{16-13}; // Rn 1924 let Inst{15-12} = Rt; 1925 let Inst{11-0} = shift{11-0}; 1926 } 1927} 1928 1929multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii, 1930 InstrItinClass iir, PatFrag opnode> { 1931 // Note: We use the complex addrmode_imm12 rather than just an input 1932 // GPR and a constrained immediate so that we can use this to match 1933 // frame index references and avoid matching constant pool references. 1934 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1935 (ins GPRnopc:$Rt, addrmode_imm12:$addr), 1936 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1937 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> { 1938 bits<4> Rt; 1939 bits<17> addr; 1940 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1941 let Inst{19-16} = addr{16-13}; // Rn 1942 let Inst{15-12} = Rt; 1943 let Inst{11-0} = addr{11-0}; // imm12 1944 } 1945 def rs : AI2ldst<0b011, 0, isByte, (outs), 1946 (ins GPRnopc:$Rt, ldst_so_reg:$shift), 1947 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1948 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> { 1949 bits<4> Rt; 1950 bits<17> shift; 1951 let shift{4} = 0; // Inst{4} = 0 1952 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1953 let Inst{19-16} = shift{16-13}; // Rn 1954 let Inst{15-12} = Rt; 1955 let Inst{11-0} = shift{11-0}; 1956 } 1957} 1958 1959 1960//===----------------------------------------------------------------------===// 1961// Instructions 1962//===----------------------------------------------------------------------===// 1963 1964//===----------------------------------------------------------------------===// 1965// Miscellaneous Instructions. 1966// 1967 1968/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 1969/// the function. The first operand is the ID# for this instruction, the second 1970/// is the index into the MachineConstantPool that this is, the third is the 1971/// size in bytes of this constant pool entry. 1972let hasSideEffects = 0, isNotDuplicable = 1 in 1973def CONSTPOOL_ENTRY : 1974PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1975 i32imm:$size), NoItinerary, []>; 1976 1977/// A jumptable consisting of direct 32-bit addresses of the destination basic 1978/// blocks (either absolute, or relative to the start of the jump-table in PIC 1979/// mode). Used mostly in ARM and Thumb-1 modes. 1980def JUMPTABLE_ADDRS : 1981PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1982 i32imm:$size), NoItinerary, []>; 1983 1984/// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables 1985/// that cannot be optimised to use TBB or TBH. 1986def JUMPTABLE_INSTS : 1987PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1988 i32imm:$size), NoItinerary, []>; 1989 1990/// A jumptable consisting of 8-bit unsigned integers representing offsets from 1991/// a TBB instruction. 1992def JUMPTABLE_TBB : 1993PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1994 i32imm:$size), NoItinerary, []>; 1995 1996/// A jumptable consisting of 16-bit unsigned integers representing offsets from 1997/// a TBH instruction. 1998def JUMPTABLE_TBH : 1999PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2000 i32imm:$size), NoItinerary, []>; 2001 2002 2003// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 2004// from removing one half of the matched pairs. That breaks PEI, which assumes 2005// these will always be in pairs, and asserts if it finds otherwise. Better way? 2006let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 2007def ADJCALLSTACKUP : 2008PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, 2009 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; 2010 2011def ADJCALLSTACKDOWN : 2012PseudoInst<(outs), (ins i32imm:$amt, i32imm:$amt2, pred:$p), NoItinerary, 2013 [(ARMcallseq_start timm:$amt, timm:$amt2)]>; 2014} 2015 2016def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary, 2017 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>, 2018 Requires<[IsARM, HasV6]> { 2019 bits<8> imm; 2020 let Inst{27-8} = 0b00110010000011110000; 2021 let Inst{7-0} = imm; 2022 let DecoderMethod = "DecodeHINTInstruction"; 2023} 2024 2025def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>; 2026def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>; 2027def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>; 2028def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>; 2029def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>; 2030def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>; 2031def : InstAlias<"esb$p", (HINT 16, pred:$p)>, Requires<[IsARM, HasRAS]>; 2032def : InstAlias<"csdb$p", (HINT 20, pred:$p)>, Requires<[IsARM, HasV6K]>; 2033 2034def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel", 2035 "\t$Rd, $Rn, $Rm", 2036 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>, 2037 Requires<[IsARM, HasV6]> { 2038 bits<4> Rd; 2039 bits<4> Rn; 2040 bits<4> Rm; 2041 let Inst{3-0} = Rm; 2042 let Inst{15-12} = Rd; 2043 let Inst{19-16} = Rn; 2044 let Inst{27-20} = 0b01101000; 2045 let Inst{7-4} = 0b1011; 2046 let Inst{11-8} = 0b1111; 2047 let Unpredictable{11-8} = 0b1111; 2048} 2049 2050// The 16-bit operand $val can be used by a debugger to store more information 2051// about the breakpoint. 2052def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 2053 "bkpt", "\t$val", []>, Requires<[IsARM]> { 2054 bits<16> val; 2055 let Inst{3-0} = val{3-0}; 2056 let Inst{19-8} = val{15-4}; 2057 let Inst{27-20} = 0b00010010; 2058 let Inst{31-28} = 0xe; // AL 2059 let Inst{7-4} = 0b0111; 2060} 2061// default immediate for breakpoint mnemonic 2062def : InstAlias<"bkpt", (BKPT 0), 0>, Requires<[IsARM]>; 2063 2064def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 2065 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> { 2066 bits<16> val; 2067 let Inst{3-0} = val{3-0}; 2068 let Inst{19-8} = val{15-4}; 2069 let Inst{27-20} = 0b00010000; 2070 let Inst{31-28} = 0xe; // AL 2071 let Inst{7-4} = 0b0111; 2072} 2073 2074// Change Processor State 2075// FIXME: We should use InstAlias to handle the optional operands. 2076class CPS<dag iops, string asm_ops> 2077 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops), 2078 []>, Requires<[IsARM]> { 2079 bits<2> imod; 2080 bits<3> iflags; 2081 bits<5> mode; 2082 bit M; 2083 2084 let Inst{31-28} = 0b1111; 2085 let Inst{27-20} = 0b00010000; 2086 let Inst{19-18} = imod; 2087 let Inst{17} = M; // Enabled if mode is set; 2088 let Inst{16-9} = 0b00000000; 2089 let Inst{8-6} = iflags; 2090 let Inst{5} = 0; 2091 let Inst{4-0} = mode; 2092} 2093 2094let DecoderMethod = "DecodeCPSInstruction" in { 2095let M = 1 in 2096 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode), 2097 "$imod\t$iflags, $mode">; 2098let mode = 0, M = 0 in 2099 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">; 2100 2101let imod = 0, iflags = 0, M = 1 in 2102 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">; 2103} 2104 2105// Preload signals the memory system of possible future data/instruction access. 2106multiclass APreLoad<bits<1> read, bits<1> data, string opc> { 2107 2108 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm, 2109 IIC_Preload, !strconcat(opc, "\t$addr"), 2110 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>, 2111 Sched<[WritePreLd]> { 2112 bits<4> Rt; 2113 bits<17> addr; 2114 let Inst{31-26} = 0b111101; 2115 let Inst{25} = 0; // 0 for immediate form 2116 let Inst{24} = data; 2117 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2118 let Inst{22} = read; 2119 let Inst{21-20} = 0b01; 2120 let Inst{19-16} = addr{16-13}; // Rn 2121 let Inst{15-12} = 0b1111; 2122 let Inst{11-0} = addr{11-0}; // imm12 2123 } 2124 2125 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, 2126 !strconcat(opc, "\t$shift"), 2127 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>, 2128 Sched<[WritePreLd]> { 2129 bits<17> shift; 2130 let Inst{31-26} = 0b111101; 2131 let Inst{25} = 1; // 1 for register form 2132 let Inst{24} = data; 2133 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2134 let Inst{22} = read; 2135 let Inst{21-20} = 0b01; 2136 let Inst{19-16} = shift{16-13}; // Rn 2137 let Inst{15-12} = 0b1111; 2138 let Inst{11-0} = shift{11-0}; 2139 let Inst{4} = 0; 2140 } 2141} 2142 2143defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>; 2144defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>; 2145defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>; 2146 2147def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary, 2148 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> { 2149 bits<1> end; 2150 let Inst{31-10} = 0b1111000100000001000000; 2151 let Inst{9} = end; 2152 let Inst{8-0} = 0; 2153} 2154 2155def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", 2156 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> { 2157 bits<4> opt; 2158 let Inst{27-4} = 0b001100100000111100001111; 2159 let Inst{3-0} = opt; 2160} 2161 2162// A8.8.247 UDF - Undefined (Encoding A1) 2163def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary, 2164 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> { 2165 bits<16> imm16; 2166 let Inst{31-28} = 0b1110; // AL 2167 let Inst{27-25} = 0b011; 2168 let Inst{24-20} = 0b11111; 2169 let Inst{19-8} = imm16{15-4}; 2170 let Inst{7-4} = 0b1111; 2171 let Inst{3-0} = imm16{3-0}; 2172} 2173 2174/* 2175 * A5.4 Permanently UNDEFINED instructions. 2176 * 2177 * For most targets use UDF #65006, for which the OS will generate SIGTRAP. 2178 * Other UDF encodings generate SIGILL. 2179 * 2180 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb. 2181 * Encoding A1: 2182 * 1110 0111 1111 iiii iiii iiii 1111 iiii 2183 * Encoding T1: 2184 * 1101 1110 iiii iiii 2185 * It uses the following encoding: 2186 * 1110 0111 1111 1110 1101 1110 1111 0000 2187 * - In ARM: UDF #60896; 2188 * - In Thumb: UDF #254 followed by a branch-to-self. 2189 */ 2190let isBarrier = 1, isTerminator = 1 in 2191def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary, 2192 "trap", [(trap)]>, 2193 Requires<[IsARM,UseNaClTrap]> { 2194 let Inst = 0xe7fedef0; 2195} 2196let isBarrier = 1, isTerminator = 1 in 2197def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, 2198 "trap", [(trap)]>, 2199 Requires<[IsARM,DontUseNaClTrap]> { 2200 let Inst = 0xe7ffdefe; 2201} 2202 2203def : Pat<(debugtrap), (BKPT 0)>, Requires<[IsARM, HasV5T]>; 2204def : Pat<(debugtrap), (UDF 254)>, Requires<[IsARM, NoV5T]>; 2205 2206// Address computation and loads and stores in PIC mode. 2207let isNotDuplicable = 1 in { 2208def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 2209 4, IIC_iALUr, 2210 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>, 2211 Sched<[WriteALU, ReadALU]>; 2212 2213let AddedComplexity = 10 in { 2214def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 2215 4, IIC_iLoad_r, 2216 [(set GPR:$dst, (load addrmodepc:$addr))]>; 2217 2218def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2219 4, IIC_iLoad_bh_r, 2220 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>; 2221 2222def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2223 4, IIC_iLoad_bh_r, 2224 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>; 2225 2226def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2227 4, IIC_iLoad_bh_r, 2228 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>; 2229 2230def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2231 4, IIC_iLoad_bh_r, 2232 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>; 2233} 2234let AddedComplexity = 10 in { 2235def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2236 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>; 2237 2238def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2239 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, 2240 addrmodepc:$addr)]>; 2241 2242def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2243 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 2244} 2245} // isNotDuplicable = 1 2246 2247 2248// LEApcrel - Load a pc-relative address into a register without offending the 2249// assembler. 2250let hasSideEffects = 0, isReMaterializable = 1 in 2251// The 'adr' mnemonic encodes differently if the label is before or after 2252// the instruction. The {24-21} opcode bits are set by the fixup, as we don't 2253// know until then which form of the instruction will be used. 2254def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), 2255 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>, 2256 Sched<[WriteALU, ReadALU]> { 2257 bits<4> Rd; 2258 bits<14> label; 2259 let Inst{27-25} = 0b001; 2260 let Inst{24} = 0; 2261 let Inst{23-22} = label{13-12}; 2262 let Inst{21} = 0; 2263 let Inst{20} = 0; 2264 let Inst{19-16} = 0b1111; 2265 let Inst{15-12} = Rd; 2266 let Inst{11-0} = label{11-0}; 2267} 2268 2269let hasSideEffects = 1 in { 2270def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 2271 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2272 2273def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd), 2274 (ins i32imm:$label, pred:$p), 2275 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2276} 2277 2278//===----------------------------------------------------------------------===// 2279// Control Flow Instructions. 2280// 2281 2282let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 2283 // ARMV4T and above 2284 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2285 "bx", "\tlr", [(ARMretflag)]>, 2286 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2287 let Inst{27-0} = 0b0001001011111111111100011110; 2288 } 2289 2290 // ARMV4 only 2291 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2292 "mov", "\tpc, lr", [(ARMretflag)]>, 2293 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> { 2294 let Inst{27-0} = 0b0001101000001111000000001110; 2295 } 2296 2297 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets 2298 // the user-space one). 2299 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p), 2300 4, IIC_Br, 2301 [(ARMintretflag imm:$offset)]>; 2302} 2303 2304// Indirect branches 2305let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 2306 // ARMV4T and above 2307 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst", 2308 [(brind GPR:$dst)]>, 2309 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2310 bits<4> dst; 2311 let Inst{31-4} = 0b1110000100101111111111110001; 2312 let Inst{3-0} = dst; 2313 } 2314 2315 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, 2316 "bx", "\t$dst", [/* pattern left blank */]>, 2317 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2318 bits<4> dst; 2319 let Inst{27-4} = 0b000100101111111111110001; 2320 let Inst{3-0} = dst; 2321 } 2322} 2323 2324// SP is marked as a use to prevent stack-pointer assignments that appear 2325// immediately before calls from potentially appearing dead. 2326let isCall = 1, 2327 // FIXME: Do we really need a non-predicated version? If so, it should 2328 // at least be a pseudo instruction expanding to the predicated version 2329 // at MC lowering time. 2330 Defs = [LR], Uses = [SP] in { 2331 def BL : ABXI<0b1011, (outs), (ins arm_bl_target:$func), 2332 IIC_Br, "bl\t$func", 2333 [(ARMcall tglobaladdr:$func)]>, 2334 Requires<[IsARM]>, Sched<[WriteBrL]> { 2335 let Inst{31-28} = 0b1110; 2336 bits<24> func; 2337 let Inst{23-0} = func; 2338 let DecoderMethod = "DecodeBranchImmInstruction"; 2339 } 2340 2341 def BL_pred : ABI<0b1011, (outs), (ins arm_bl_target:$func), 2342 IIC_Br, "bl", "\t$func", 2343 [(ARMcall_pred tglobaladdr:$func)]>, 2344 Requires<[IsARM]>, Sched<[WriteBrL]> { 2345 bits<24> func; 2346 let Inst{23-0} = func; 2347 let DecoderMethod = "DecodeBranchImmInstruction"; 2348 } 2349 2350 // ARMv5T and above 2351 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm, 2352 IIC_Br, "blx\t$func", 2353 [(ARMcall GPR:$func)]>, 2354 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2355 bits<4> func; 2356 let Inst{31-4} = 0b1110000100101111111111110011; 2357 let Inst{3-0} = func; 2358 } 2359 2360 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm, 2361 IIC_Br, "blx", "\t$func", 2362 [(ARMcall_pred GPR:$func)]>, 2363 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2364 bits<4> func; 2365 let Inst{27-4} = 0b000100101111111111110011; 2366 let Inst{3-0} = func; 2367 } 2368 2369 // ARMv4T 2370 // Note: Restrict $func to the tGPR regclass to prevent it being in LR. 2371 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2372 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2373 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>; 2374 2375 // ARMv4 2376 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2377 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2378 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 2379 2380 // mov lr, pc; b if callee is marked noreturn to avoid confusing the 2381 // return stack predictor. 2382 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins arm_bl_target:$func), 2383 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>, 2384 Requires<[IsARM]>, Sched<[WriteBr]>; 2385} 2386 2387let isBranch = 1, isTerminator = 1 in { 2388 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 2389 // a two-value operand where a dag node expects two operands. :( 2390 def Bcc : ABI<0b1010, (outs), (ins arm_br_target:$target), 2391 IIC_Br, "b", "\t$target", 2392 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>, 2393 Sched<[WriteBr]> { 2394 bits<24> target; 2395 let Inst{23-0} = target; 2396 let DecoderMethod = "DecodeBranchImmInstruction"; 2397 } 2398 2399 let isBarrier = 1 in { 2400 // B is "predicable" since it's just a Bcc with an 'always' condition. 2401 let isPredicable = 1 in 2402 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly 2403 // should be sufficient. 2404 // FIXME: Is B really a Barrier? That doesn't seem right. 2405 def B : ARMPseudoExpand<(outs), (ins arm_br_target:$target), 4, IIC_Br, 2406 [(br bb:$target)], (Bcc arm_br_target:$target, 2407 (ops 14, zero_reg))>, 2408 Sched<[WriteBr]>; 2409 2410 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in { 2411 def BR_JTr : ARMPseudoInst<(outs), 2412 (ins GPR:$target, i32imm:$jt), 2413 0, IIC_Br, 2414 [(ARMbrjt GPR:$target, tjumptable:$jt)]>, 2415 Sched<[WriteBr]>; 2416 def BR_JTm_i12 : ARMPseudoInst<(outs), 2417 (ins addrmode_imm12:$target, i32imm:$jt), 2418 0, IIC_Br, 2419 [(ARMbrjt (i32 (load addrmode_imm12:$target)), 2420 tjumptable:$jt)]>, Sched<[WriteBrTbl]>; 2421 def BR_JTm_rs : ARMPseudoInst<(outs), 2422 (ins ldst_so_reg:$target, i32imm:$jt), 2423 0, IIC_Br, 2424 [(ARMbrjt (i32 (load ldst_so_reg:$target)), 2425 tjumptable:$jt)]>, Sched<[WriteBrTbl]>; 2426 def BR_JTadd : ARMPseudoInst<(outs), 2427 (ins GPR:$target, GPR:$idx, i32imm:$jt), 2428 0, IIC_Br, 2429 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>, 2430 Sched<[WriteBrTbl]>; 2431 } // isNotDuplicable = 1, isIndirectBranch = 1 2432 } // isBarrier = 1 2433 2434} 2435 2436// BLX (immediate) 2437def BLXi : AXI<(outs), (ins arm_blx_target:$target), BrMiscFrm, NoItinerary, 2438 "blx\t$target", []>, 2439 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2440 let Inst{31-25} = 0b1111101; 2441 bits<25> target; 2442 let Inst{23-0} = target{24-1}; 2443 let Inst{24} = target{0}; 2444 let isCall = 1; 2445} 2446 2447// Branch and Exchange Jazelle 2448def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", 2449 [/* pattern left blank */]>, Sched<[WriteBr]> { 2450 bits<4> func; 2451 let Inst{23-20} = 0b0010; 2452 let Inst{19-8} = 0xfff; 2453 let Inst{7-4} = 0b0010; 2454 let Inst{3-0} = func; 2455 let isBranch = 1; 2456} 2457 2458// Tail calls. 2459 2460let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { 2461 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>, 2462 Sched<[WriteBr]>; 2463 2464 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>, 2465 Sched<[WriteBr]>; 2466 2467 def TAILJMPd : ARMPseudoExpand<(outs), (ins arm_br_target:$dst), 2468 4, IIC_Br, [], 2469 (Bcc arm_br_target:$dst, (ops 14, zero_reg))>, 2470 Requires<[IsARM]>, Sched<[WriteBr]>; 2471 2472 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst), 2473 4, IIC_Br, [], 2474 (BX GPR:$dst)>, Sched<[WriteBr]>, 2475 Requires<[IsARM, HasV4T]>; 2476} 2477 2478// Secure Monitor Call is a system instruction. 2479def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", 2480 []>, Requires<[IsARM, HasTrustZone]> { 2481 bits<4> opt; 2482 let Inst{23-4} = 0b01100000000000000111; 2483 let Inst{3-0} = opt; 2484} 2485def : MnemonicAlias<"smi", "smc">; 2486 2487// Supervisor Call (Software Interrupt) 2488let isCall = 1, Uses = [SP] in { 2489def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>, 2490 Sched<[WriteBr]> { 2491 bits<24> svc; 2492 let Inst{23-0} = svc; 2493} 2494} 2495 2496// Store Return State 2497class SRSI<bit wb, string asm> 2498 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm, 2499 NoItinerary, asm, "", []> { 2500 bits<5> mode; 2501 let Inst{31-28} = 0b1111; 2502 let Inst{27-25} = 0b100; 2503 let Inst{22} = 1; 2504 let Inst{21} = wb; 2505 let Inst{20} = 0; 2506 let Inst{19-16} = 0b1101; // SP 2507 let Inst{15-5} = 0b00000101000; 2508 let Inst{4-0} = mode; 2509} 2510 2511def SRSDA : SRSI<0, "srsda\tsp, $mode"> { 2512 let Inst{24-23} = 0; 2513} 2514def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> { 2515 let Inst{24-23} = 0; 2516} 2517def SRSDB : SRSI<0, "srsdb\tsp, $mode"> { 2518 let Inst{24-23} = 0b10; 2519} 2520def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> { 2521 let Inst{24-23} = 0b10; 2522} 2523def SRSIA : SRSI<0, "srsia\tsp, $mode"> { 2524 let Inst{24-23} = 0b01; 2525} 2526def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> { 2527 let Inst{24-23} = 0b01; 2528} 2529def SRSIB : SRSI<0, "srsib\tsp, $mode"> { 2530 let Inst{24-23} = 0b11; 2531} 2532def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> { 2533 let Inst{24-23} = 0b11; 2534} 2535 2536def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>; 2537def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>; 2538 2539def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>; 2540def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>; 2541 2542def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>; 2543def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>; 2544 2545def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>; 2546def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>; 2547 2548// Return From Exception 2549class RFEI<bit wb, string asm> 2550 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm, 2551 NoItinerary, asm, "", []> { 2552 bits<4> Rn; 2553 let Inst{31-28} = 0b1111; 2554 let Inst{27-25} = 0b100; 2555 let Inst{22} = 0; 2556 let Inst{21} = wb; 2557 let Inst{20} = 1; 2558 let Inst{19-16} = Rn; 2559 let Inst{15-0} = 0xa00; 2560} 2561 2562def RFEDA : RFEI<0, "rfeda\t$Rn"> { 2563 let Inst{24-23} = 0; 2564} 2565def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> { 2566 let Inst{24-23} = 0; 2567} 2568def RFEDB : RFEI<0, "rfedb\t$Rn"> { 2569 let Inst{24-23} = 0b10; 2570} 2571def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> { 2572 let Inst{24-23} = 0b10; 2573} 2574def RFEIA : RFEI<0, "rfeia\t$Rn"> { 2575 let Inst{24-23} = 0b01; 2576} 2577def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> { 2578 let Inst{24-23} = 0b01; 2579} 2580def RFEIB : RFEI<0, "rfeib\t$Rn"> { 2581 let Inst{24-23} = 0b11; 2582} 2583def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> { 2584 let Inst{24-23} = 0b11; 2585} 2586 2587// Hypervisor Call is a system instruction 2588let isCall = 1 in { 2589def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary, 2590 "hvc", "\t$imm", []>, 2591 Requires<[IsARM, HasVirtualization]> { 2592 bits<16> imm; 2593 2594 // Even though HVC isn't predicable, it's encoding includes a condition field. 2595 // The instruction is undefined if the condition field is 0xf otherwise it is 2596 // unpredictable if it isn't condition AL (0xe). 2597 let Inst{31-28} = 0b1110; 2598 let Unpredictable{31-28} = 0b1111; 2599 let Inst{27-24} = 0b0001; 2600 let Inst{23-20} = 0b0100; 2601 let Inst{19-8} = imm{15-4}; 2602 let Inst{7-4} = 0b0111; 2603 let Inst{3-0} = imm{3-0}; 2604} 2605} 2606 2607// Return from exception in Hypervisor mode. 2608let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in 2609def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>, 2610 Requires<[IsARM, HasVirtualization]> { 2611 let Inst{23-0} = 0b011000000000000001101110; 2612} 2613 2614//===----------------------------------------------------------------------===// 2615// Load / Store Instructions. 2616// 2617 2618// Load 2619 2620 2621defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si, load>; 2622defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si, 2623 zextloadi8>; 2624defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si, store>; 2625defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si, 2626 truncstorei8>; 2627 2628// Special LDR for loads from non-pc-relative constpools. 2629let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0, 2630 isReMaterializable = 1, isCodeGenOnly = 1 in 2631def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 2632 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", 2633 []> { 2634 bits<4> Rt; 2635 bits<17> addr; 2636 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2637 let Inst{19-16} = 0b1111; 2638 let Inst{15-12} = Rt; 2639 let Inst{11-0} = addr{11-0}; // imm12 2640} 2641 2642// Loads with zero extension 2643def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2644 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr", 2645 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>; 2646 2647// Loads with sign extension 2648def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2649 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr", 2650 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>; 2651 2652def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2653 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr", 2654 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>; 2655 2656let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in { 2657 // Load doubleword 2658 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr), 2659 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>, 2660 Requires<[IsARM, HasV5TE]>; 2661} 2662 2663def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2664 NoItinerary, "lda", "\t$Rt, $addr", []>; 2665def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2666 NoItinerary, "ldab", "\t$Rt, $addr", []>; 2667def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2668 NoItinerary, "ldah", "\t$Rt, $addr", []>; 2669 2670// Indexed loads 2671multiclass AI2_ldridx<bit isByte, string opc, 2672 InstrItinClass iii, InstrItinClass iir> { 2673 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2674 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii, 2675 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2676 bits<17> addr; 2677 let Inst{25} = 0; 2678 let Inst{23} = addr{12}; 2679 let Inst{19-16} = addr{16-13}; 2680 let Inst{11-0} = addr{11-0}; 2681 let DecoderMethod = "DecodeLDRPreImm"; 2682 } 2683 2684 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2685 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir, 2686 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2687 bits<17> addr; 2688 let Inst{25} = 1; 2689 let Inst{23} = addr{12}; 2690 let Inst{19-16} = addr{16-13}; 2691 let Inst{11-0} = addr{11-0}; 2692 let Inst{4} = 0; 2693 let DecoderMethod = "DecodeLDRPreReg"; 2694 } 2695 2696 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2697 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2698 IndexModePost, LdFrm, iir, 2699 opc, "\t$Rt, $addr, $offset", 2700 "$addr.base = $Rn_wb", []> { 2701 // {12} isAdd 2702 // {11-0} imm12/Rm 2703 bits<14> offset; 2704 bits<4> addr; 2705 let Inst{25} = 1; 2706 let Inst{23} = offset{12}; 2707 let Inst{19-16} = addr; 2708 let Inst{11-0} = offset{11-0}; 2709 let Inst{4} = 0; 2710 2711 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2712 } 2713 2714 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2715 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2716 IndexModePost, LdFrm, iii, 2717 opc, "\t$Rt, $addr, $offset", 2718 "$addr.base = $Rn_wb", []> { 2719 // {12} isAdd 2720 // {11-0} imm12/Rm 2721 bits<14> offset; 2722 bits<4> addr; 2723 let Inst{25} = 0; 2724 let Inst{23} = offset{12}; 2725 let Inst{19-16} = addr; 2726 let Inst{11-0} = offset{11-0}; 2727 2728 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2729 } 2730 2731} 2732 2733let mayLoad = 1, hasSideEffects = 0 in { 2734// FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or 2735// IIC_iLoad_siu depending on whether it the offset register is shifted. 2736defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>; 2737defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>; 2738} 2739 2740multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> { 2741 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2742 (ins addrmode3_pre:$addr), IndexModePre, 2743 LdMiscFrm, itin, 2744 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2745 bits<14> addr; 2746 let Inst{23} = addr{8}; // U bit 2747 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2748 let Inst{19-16} = addr{12-9}; // Rn 2749 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2750 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2751 let DecoderMethod = "DecodeAddrMode3Instruction"; 2752 } 2753 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2754 (ins addr_offset_none:$addr, am3offset:$offset), 2755 IndexModePost, LdMiscFrm, itin, 2756 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2757 []> { 2758 bits<10> offset; 2759 bits<4> addr; 2760 let Inst{23} = offset{8}; // U bit 2761 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2762 let Inst{19-16} = addr; 2763 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2764 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2765 let DecoderMethod = "DecodeAddrMode3Instruction"; 2766 } 2767} 2768 2769let mayLoad = 1, hasSideEffects = 0 in { 2770defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>; 2771defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>; 2772defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>; 2773let hasExtraDefRegAllocReq = 1 in { 2774def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2775 (ins addrmode3_pre:$addr), IndexModePre, 2776 LdMiscFrm, IIC_iLoad_d_ru, 2777 "ldrd", "\t$Rt, $Rt2, $addr!", 2778 "$addr.base = $Rn_wb", []> { 2779 bits<14> addr; 2780 let Inst{23} = addr{8}; // U bit 2781 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2782 let Inst{19-16} = addr{12-9}; // Rn 2783 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2784 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2785 let DecoderMethod = "DecodeAddrMode3Instruction"; 2786} 2787def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2788 (ins addr_offset_none:$addr, am3offset:$offset), 2789 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru, 2790 "ldrd", "\t$Rt, $Rt2, $addr, $offset", 2791 "$addr.base = $Rn_wb", []> { 2792 bits<10> offset; 2793 bits<4> addr; 2794 let Inst{23} = offset{8}; // U bit 2795 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2796 let Inst{19-16} = addr; 2797 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2798 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2799 let DecoderMethod = "DecodeAddrMode3Instruction"; 2800} 2801} // hasExtraDefRegAllocReq = 1 2802} // mayLoad = 1, hasSideEffects = 0 2803 2804// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT. 2805let mayLoad = 1, hasSideEffects = 0 in { 2806def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2807 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2808 IndexModePost, LdFrm, IIC_iLoad_ru, 2809 "ldrt", "\t$Rt, $addr, $offset", 2810 "$addr.base = $Rn_wb", []> { 2811 // {12} isAdd 2812 // {11-0} imm12/Rm 2813 bits<14> offset; 2814 bits<4> addr; 2815 let Inst{25} = 1; 2816 let Inst{23} = offset{12}; 2817 let Inst{21} = 1; // overwrite 2818 let Inst{19-16} = addr; 2819 let Inst{11-5} = offset{11-5}; 2820 let Inst{4} = 0; 2821 let Inst{3-0} = offset{3-0}; 2822 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2823} 2824 2825def LDRT_POST_IMM 2826 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2827 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2828 IndexModePost, LdFrm, IIC_iLoad_ru, 2829 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2830 // {12} isAdd 2831 // {11-0} imm12/Rm 2832 bits<14> offset; 2833 bits<4> addr; 2834 let Inst{25} = 0; 2835 let Inst{23} = offset{12}; 2836 let Inst{21} = 1; // overwrite 2837 let Inst{19-16} = addr; 2838 let Inst{11-0} = offset{11-0}; 2839 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2840} 2841 2842def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2843 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2844 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2845 "ldrbt", "\t$Rt, $addr, $offset", 2846 "$addr.base = $Rn_wb", []> { 2847 // {12} isAdd 2848 // {11-0} imm12/Rm 2849 bits<14> offset; 2850 bits<4> addr; 2851 let Inst{25} = 1; 2852 let Inst{23} = offset{12}; 2853 let Inst{21} = 1; // overwrite 2854 let Inst{19-16} = addr; 2855 let Inst{11-5} = offset{11-5}; 2856 let Inst{4} = 0; 2857 let Inst{3-0} = offset{3-0}; 2858 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2859} 2860 2861def LDRBT_POST_IMM 2862 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2863 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2864 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2865 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2866 // {12} isAdd 2867 // {11-0} imm12/Rm 2868 bits<14> offset; 2869 bits<4> addr; 2870 let Inst{25} = 0; 2871 let Inst{23} = offset{12}; 2872 let Inst{21} = 1; // overwrite 2873 let Inst{19-16} = addr; 2874 let Inst{11-0} = offset{11-0}; 2875 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2876} 2877 2878multiclass AI3ldrT<bits<4> op, string opc> { 2879 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb), 2880 (ins addr_offset_none:$addr, postidx_imm8:$offset), 2881 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2882 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 2883 bits<9> offset; 2884 let Inst{23} = offset{8}; 2885 let Inst{22} = 1; 2886 let Inst{11-8} = offset{7-4}; 2887 let Inst{3-0} = offset{3-0}; 2888 } 2889 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb), 2890 (ins addr_offset_none:$addr, postidx_reg:$Rm), 2891 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2892 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 2893 bits<5> Rm; 2894 let Inst{23} = Rm{4}; 2895 let Inst{22} = 0; 2896 let Inst{11-8} = 0; 2897 let Unpredictable{11-8} = 0b1111; 2898 let Inst{3-0} = Rm{3-0}; 2899 let DecoderMethod = "DecodeLDR"; 2900 } 2901} 2902 2903defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">; 2904defm LDRHT : AI3ldrT<0b1011, "ldrht">; 2905defm LDRSHT : AI3ldrT<0b1111, "ldrsht">; 2906} 2907 2908def LDRT_POST 2909 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2910 (outs GPR:$Rt)>; 2911 2912def LDRBT_POST 2913 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2914 (outs GPR:$Rt)>; 2915 2916// Pseudo instruction ldr Rt, =immediate 2917def LDRConstPool 2918 : ARMAsmPseudo<"ldr${q} $Rt, $immediate", 2919 (ins const_pool_asm_imm:$immediate, pred:$q), 2920 (outs GPR:$Rt)>; 2921 2922// Store 2923 2924// Stores with truncate 2925def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, 2926 IIC_iStore_bh_r, "strh", "\t$Rt, $addr", 2927 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>; 2928 2929// Store doubleword 2930let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 2931 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr), 2932 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>, 2933 Requires<[IsARM, HasV5TE]> { 2934 let Inst{21} = 0; 2935 } 2936} 2937 2938// Indexed stores 2939multiclass AI2_stridx<bit isByte, string opc, 2940 InstrItinClass iii, InstrItinClass iir> { 2941 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2942 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre, 2943 StFrm, iii, 2944 opc, "\t$Rt, $addr!", 2945 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2946 bits<17> addr; 2947 let Inst{25} = 0; 2948 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2949 let Inst{19-16} = addr{16-13}; // Rn 2950 let Inst{11-0} = addr{11-0}; // imm12 2951 let DecoderMethod = "DecodeSTRPreImm"; 2952 } 2953 2954 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2955 (ins GPR:$Rt, ldst_so_reg:$addr), 2956 IndexModePre, StFrm, iir, 2957 opc, "\t$Rt, $addr!", 2958 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2959 bits<17> addr; 2960 let Inst{25} = 1; 2961 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2962 let Inst{19-16} = addr{16-13}; // Rn 2963 let Inst{11-0} = addr{11-0}; 2964 let Inst{4} = 0; // Inst{4} = 0 2965 let DecoderMethod = "DecodeSTRPreReg"; 2966 } 2967 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2968 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2969 IndexModePost, StFrm, iir, 2970 opc, "\t$Rt, $addr, $offset", 2971 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2972 // {12} isAdd 2973 // {11-0} imm12/Rm 2974 bits<14> offset; 2975 bits<4> addr; 2976 let Inst{25} = 1; 2977 let Inst{23} = offset{12}; 2978 let Inst{19-16} = addr; 2979 let Inst{11-0} = offset{11-0}; 2980 let Inst{4} = 0; 2981 2982 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2983 } 2984 2985 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2986 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2987 IndexModePost, StFrm, iii, 2988 opc, "\t$Rt, $addr, $offset", 2989 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2990 // {12} isAdd 2991 // {11-0} imm12/Rm 2992 bits<14> offset; 2993 bits<4> addr; 2994 let Inst{25} = 0; 2995 let Inst{23} = offset{12}; 2996 let Inst{19-16} = addr; 2997 let Inst{11-0} = offset{11-0}; 2998 2999 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3000 } 3001} 3002 3003let mayStore = 1, hasSideEffects = 0 in { 3004// FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or 3005// IIC_iStore_siu depending on whether it the offset register is shifted. 3006defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>; 3007defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>; 3008} 3009 3010def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 3011 am2offset_reg:$offset), 3012 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr, 3013 am2offset_reg:$offset)>; 3014def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 3015 am2offset_imm:$offset), 3016 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr, 3017 am2offset_imm:$offset)>; 3018def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 3019 am2offset_reg:$offset), 3020 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr, 3021 am2offset_reg:$offset)>; 3022def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 3023 am2offset_imm:$offset), 3024 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr, 3025 am2offset_imm:$offset)>; 3026 3027// Pseudo-instructions for pattern matching the pre-indexed stores. We can't 3028// put the patterns on the instruction definitions directly as ISel wants 3029// the address base and offset to be separate operands, not a single 3030// complex operand like we represent the instructions themselves. The 3031// pseudos map between the two. 3032let usesCustomInserter = 1, 3033 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 3034def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3035 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 3036 4, IIC_iStore_ru, 3037 [(set GPR:$Rn_wb, 3038 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 3039def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3040 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 3041 4, IIC_iStore_ru, 3042 [(set GPR:$Rn_wb, 3043 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 3044def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3045 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 3046 4, IIC_iStore_ru, 3047 [(set GPR:$Rn_wb, 3048 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 3049def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3050 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 3051 4, IIC_iStore_ru, 3052 [(set GPR:$Rn_wb, 3053 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 3054def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3055 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p), 3056 4, IIC_iStore_ru, 3057 [(set GPR:$Rn_wb, 3058 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>; 3059} 3060 3061 3062 3063def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb), 3064 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre, 3065 StMiscFrm, IIC_iStore_bh_ru, 3066 "strh", "\t$Rt, $addr!", 3067 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3068 bits<14> addr; 3069 let Inst{23} = addr{8}; // U bit 3070 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 3071 let Inst{19-16} = addr{12-9}; // Rn 3072 let Inst{11-8} = addr{7-4}; // imm7_4/zero 3073 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 3074 let DecoderMethod = "DecodeAddrMode3Instruction"; 3075} 3076 3077def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb), 3078 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset), 3079 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, 3080 "strh", "\t$Rt, $addr, $offset", 3081 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", 3082 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt, 3083 addr_offset_none:$addr, 3084 am3offset:$offset))]> { 3085 bits<10> offset; 3086 bits<4> addr; 3087 let Inst{23} = offset{8}; // U bit 3088 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 3089 let Inst{19-16} = addr; 3090 let Inst{11-8} = offset{7-4}; // imm7_4/zero 3091 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 3092 let DecoderMethod = "DecodeAddrMode3Instruction"; 3093} 3094 3095let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 3096def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb), 3097 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr), 3098 IndexModePre, StMiscFrm, IIC_iStore_d_ru, 3099 "strd", "\t$Rt, $Rt2, $addr!", 3100 "$addr.base = $Rn_wb", []> { 3101 bits<14> addr; 3102 let Inst{23} = addr{8}; // U bit 3103 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 3104 let Inst{19-16} = addr{12-9}; // Rn 3105 let Inst{11-8} = addr{7-4}; // imm7_4/zero 3106 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 3107 let DecoderMethod = "DecodeAddrMode3Instruction"; 3108} 3109 3110def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb), 3111 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr, 3112 am3offset:$offset), 3113 IndexModePost, StMiscFrm, IIC_iStore_d_ru, 3114 "strd", "\t$Rt, $Rt2, $addr, $offset", 3115 "$addr.base = $Rn_wb", []> { 3116 bits<10> offset; 3117 bits<4> addr; 3118 let Inst{23} = offset{8}; // U bit 3119 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 3120 let Inst{19-16} = addr; 3121 let Inst{11-8} = offset{7-4}; // imm7_4/zero 3122 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 3123 let DecoderMethod = "DecodeAddrMode3Instruction"; 3124} 3125} // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 3126 3127// STRT, STRBT, and STRHT 3128 3129def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3130 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3131 IndexModePost, StFrm, IIC_iStore_bh_ru, 3132 "strbt", "\t$Rt, $addr, $offset", 3133 "$addr.base = $Rn_wb", []> { 3134 // {12} isAdd 3135 // {11-0} imm12/Rm 3136 bits<14> offset; 3137 bits<4> addr; 3138 let Inst{25} = 1; 3139 let Inst{23} = offset{12}; 3140 let Inst{21} = 1; // overwrite 3141 let Inst{19-16} = addr; 3142 let Inst{11-5} = offset{11-5}; 3143 let Inst{4} = 0; 3144 let Inst{3-0} = offset{3-0}; 3145 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3146} 3147 3148def STRBT_POST_IMM 3149 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3150 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3151 IndexModePost, StFrm, IIC_iStore_bh_ru, 3152 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3153 // {12} isAdd 3154 // {11-0} imm12/Rm 3155 bits<14> offset; 3156 bits<4> addr; 3157 let Inst{25} = 0; 3158 let Inst{23} = offset{12}; 3159 let Inst{21} = 1; // overwrite 3160 let Inst{19-16} = addr; 3161 let Inst{11-0} = offset{11-0}; 3162 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3163} 3164 3165def STRBT_POST 3166 : ARMAsmPseudo<"strbt${q} $Rt, $addr", 3167 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3168 3169let mayStore = 1, hasSideEffects = 0 in { 3170def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3171 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3172 IndexModePost, StFrm, IIC_iStore_ru, 3173 "strt", "\t$Rt, $addr, $offset", 3174 "$addr.base = $Rn_wb", []> { 3175 // {12} isAdd 3176 // {11-0} imm12/Rm 3177 bits<14> offset; 3178 bits<4> addr; 3179 let Inst{25} = 1; 3180 let Inst{23} = offset{12}; 3181 let Inst{21} = 1; // overwrite 3182 let Inst{19-16} = addr; 3183 let Inst{11-5} = offset{11-5}; 3184 let Inst{4} = 0; 3185 let Inst{3-0} = offset{3-0}; 3186 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3187} 3188 3189def STRT_POST_IMM 3190 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3191 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3192 IndexModePost, StFrm, IIC_iStore_ru, 3193 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3194 // {12} isAdd 3195 // {11-0} imm12/Rm 3196 bits<14> offset; 3197 bits<4> addr; 3198 let Inst{25} = 0; 3199 let Inst{23} = offset{12}; 3200 let Inst{21} = 1; // overwrite 3201 let Inst{19-16} = addr; 3202 let Inst{11-0} = offset{11-0}; 3203 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3204} 3205} 3206 3207def STRT_POST 3208 : ARMAsmPseudo<"strt${q} $Rt, $addr", 3209 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3210 3211multiclass AI3strT<bits<4> op, string opc> { 3212 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3213 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset), 3214 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3215 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 3216 bits<9> offset; 3217 let Inst{23} = offset{8}; 3218 let Inst{22} = 1; 3219 let Inst{11-8} = offset{7-4}; 3220 let Inst{3-0} = offset{3-0}; 3221 } 3222 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3223 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm), 3224 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3225 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 3226 bits<5> Rm; 3227 let Inst{23} = Rm{4}; 3228 let Inst{22} = 0; 3229 let Inst{11-8} = 0; 3230 let Inst{3-0} = Rm{3-0}; 3231 } 3232} 3233 3234 3235defm STRHT : AI3strT<0b1011, "strht">; 3236 3237def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3238 NoItinerary, "stl", "\t$Rt, $addr", []>; 3239def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3240 NoItinerary, "stlb", "\t$Rt, $addr", []>; 3241def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3242 NoItinerary, "stlh", "\t$Rt, $addr", []>; 3243 3244//===----------------------------------------------------------------------===// 3245// Load / store multiple Instructions. 3246// 3247 3248multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f, 3249 InstrItinClass itin, InstrItinClass itin_upd> { 3250 // IA is the default, so no need for an explicit suffix on the 3251 // mnemonic here. Without it is the canonical spelling. 3252 def IA : 3253 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3254 IndexModeNone, f, itin, 3255 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> { 3256 let Inst{24-23} = 0b01; // Increment After 3257 let Inst{22} = P_bit; 3258 let Inst{21} = 0; // No writeback 3259 let Inst{20} = L_bit; 3260 } 3261 def IA_UPD : 3262 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3263 IndexModeUpd, f, itin_upd, 3264 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3265 let Inst{24-23} = 0b01; // Increment After 3266 let Inst{22} = P_bit; 3267 let Inst{21} = 1; // Writeback 3268 let Inst{20} = L_bit; 3269 3270 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3271 } 3272 def DA : 3273 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3274 IndexModeNone, f, itin, 3275 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> { 3276 let Inst{24-23} = 0b00; // Decrement After 3277 let Inst{22} = P_bit; 3278 let Inst{21} = 0; // No writeback 3279 let Inst{20} = L_bit; 3280 } 3281 def DA_UPD : 3282 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3283 IndexModeUpd, f, itin_upd, 3284 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3285 let Inst{24-23} = 0b00; // Decrement After 3286 let Inst{22} = P_bit; 3287 let Inst{21} = 1; // Writeback 3288 let Inst{20} = L_bit; 3289 3290 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3291 } 3292 def DB : 3293 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3294 IndexModeNone, f, itin, 3295 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> { 3296 let Inst{24-23} = 0b10; // Decrement Before 3297 let Inst{22} = P_bit; 3298 let Inst{21} = 0; // No writeback 3299 let Inst{20} = L_bit; 3300 } 3301 def DB_UPD : 3302 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3303 IndexModeUpd, f, itin_upd, 3304 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3305 let Inst{24-23} = 0b10; // Decrement Before 3306 let Inst{22} = P_bit; 3307 let Inst{21} = 1; // Writeback 3308 let Inst{20} = L_bit; 3309 3310 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3311 } 3312 def IB : 3313 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3314 IndexModeNone, f, itin, 3315 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> { 3316 let Inst{24-23} = 0b11; // Increment Before 3317 let Inst{22} = P_bit; 3318 let Inst{21} = 0; // No writeback 3319 let Inst{20} = L_bit; 3320 } 3321 def IB_UPD : 3322 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3323 IndexModeUpd, f, itin_upd, 3324 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3325 let Inst{24-23} = 0b11; // Increment Before 3326 let Inst{22} = P_bit; 3327 let Inst{21} = 1; // Writeback 3328 let Inst{20} = L_bit; 3329 3330 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3331 } 3332} 3333 3334let hasSideEffects = 0 in { 3335 3336let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in 3337defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m, 3338 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">; 3339 3340let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3341defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m, 3342 IIC_iStore_mu>, 3343 ComplexDeprecationPredicate<"ARMStore">; 3344 3345} // hasSideEffects 3346 3347// FIXME: remove when we have a way to marking a MI with these properties. 3348// FIXME: Should pc be an implicit operand like PICADD, etc? 3349let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 3350 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 3351def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 3352 reglist:$regs, variable_ops), 3353 4, IIC_iLoad_mBr, [], 3354 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 3355 RegConstraint<"$Rn = $wb">; 3356 3357let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 3358defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m, 3359 IIC_iLoad_mu>; 3360 3361let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3362defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m, 3363 IIC_iStore_mu>; 3364 3365 3366 3367//===----------------------------------------------------------------------===// 3368// Move Instructions. 3369// 3370 3371let hasSideEffects = 0, isMoveReg = 1 in 3372def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr, 3373 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3374 bits<4> Rd; 3375 bits<4> Rm; 3376 3377 let Inst{19-16} = 0b0000; 3378 let Inst{11-4} = 0b00000000; 3379 let Inst{25} = 0; 3380 let Inst{3-0} = Rm; 3381 let Inst{15-12} = Rd; 3382} 3383 3384// A version for the smaller set of tail call registers. 3385let hasSideEffects = 0 in 3386def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, 3387 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3388 bits<4> Rd; 3389 bits<4> Rm; 3390 3391 let Inst{11-4} = 0b00000000; 3392 let Inst{25} = 0; 3393 let Inst{3-0} = Rm; 3394 let Inst{15-12} = Rd; 3395} 3396 3397def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src), 3398 DPSoRegRegFrm, IIC_iMOVsr, 3399 "mov", "\t$Rd, $src", 3400 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP, 3401 Sched<[WriteALU]> { 3402 bits<4> Rd; 3403 bits<12> src; 3404 let Inst{15-12} = Rd; 3405 let Inst{19-16} = 0b0000; 3406 let Inst{11-8} = src{11-8}; 3407 let Inst{7} = 0; 3408 let Inst{6-5} = src{6-5}; 3409 let Inst{4} = 1; 3410 let Inst{3-0} = src{3-0}; 3411 let Inst{25} = 0; 3412} 3413 3414def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src), 3415 DPSoRegImmFrm, IIC_iMOVsr, 3416 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>, 3417 UnaryDP, Sched<[WriteALU]> { 3418 bits<4> Rd; 3419 bits<12> src; 3420 let Inst{15-12} = Rd; 3421 let Inst{19-16} = 0b0000; 3422 let Inst{11-5} = src{11-5}; 3423 let Inst{4} = 0; 3424 let Inst{3-0} = src{3-0}; 3425 let Inst{25} = 0; 3426} 3427 3428let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3429def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi, 3430 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP, 3431 Sched<[WriteALU]> { 3432 bits<4> Rd; 3433 bits<12> imm; 3434 let Inst{25} = 1; 3435 let Inst{15-12} = Rd; 3436 let Inst{19-16} = 0b0000; 3437 let Inst{11-0} = imm; 3438} 3439 3440let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3441def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm), 3442 DPFrm, IIC_iMOVi, 3443 "movw", "\t$Rd, $imm", 3444 [(set GPR:$Rd, imm0_65535:$imm)]>, 3445 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> { 3446 bits<4> Rd; 3447 bits<16> imm; 3448 let Inst{15-12} = Rd; 3449 let Inst{11-0} = imm{11-0}; 3450 let Inst{19-16} = imm{15-12}; 3451 let Inst{20} = 0; 3452 let Inst{25} = 1; 3453 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3454} 3455 3456def : InstAlias<"mov${p} $Rd, $imm", 3457 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p), 0>, 3458 Requires<[IsARM, HasV6T2]>; 3459 3460def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3461 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3462 Sched<[WriteALU]>; 3463 3464let Constraints = "$src = $Rd" in { 3465def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd), 3466 (ins GPR:$src, imm0_65535_expr:$imm), 3467 DPFrm, IIC_iMOVi, 3468 "movt", "\t$Rd, $imm", 3469 [(set GPRnopc:$Rd, 3470 (or (and GPR:$src, 0xffff), 3471 lo16AllZero:$imm))]>, UnaryDP, 3472 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> { 3473 bits<4> Rd; 3474 bits<16> imm; 3475 let Inst{15-12} = Rd; 3476 let Inst{11-0} = imm{11-0}; 3477 let Inst{19-16} = imm{15-12}; 3478 let Inst{20} = 0; 3479 let Inst{25} = 1; 3480 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3481} 3482 3483def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3484 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3485 Sched<[WriteALU]>; 3486 3487} // Constraints 3488 3489def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>, 3490 Requires<[IsARM, HasV6T2]>; 3491 3492let Uses = [CPSR] in 3493def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, 3494 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP, 3495 Requires<[IsARM]>, Sched<[WriteALU]>; 3496 3497// These aren't really mov instructions, but we have to define them this way 3498// due to flag operands. 3499 3500let Defs = [CPSR] in { 3501def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3502 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP, 3503 Sched<[WriteALU]>, Requires<[IsARM]>; 3504def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3505 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP, 3506 Sched<[WriteALU]>, Requires<[IsARM]>; 3507} 3508 3509//===----------------------------------------------------------------------===// 3510// Extend Instructions. 3511// 3512 3513// Sign extenders 3514 3515def SXTB : AI_ext_rrot<0b01101010, 3516 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 3517def SXTH : AI_ext_rrot<0b01101011, 3518 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 3519 3520def SXTAB : AI_exta_rrot<0b01101010, 3521 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 3522def SXTAH : AI_exta_rrot<0b01101011, 3523 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 3524 3525def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8)), 3526 (SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3527def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot), 3528 i16)), 3529 (SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3530 3531def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; 3532def : ARMV6Pat<(int_arm_sxtb16 GPR:$Src), 3533 (SXTB16 GPR:$Src, 0)>; 3534def : ARMV6Pat<(int_arm_sxtb16 (rotr GPR:$Src, rot_imm:$rot)), 3535 (SXTB16 GPR:$Src, rot_imm:$rot)>; 3536 3537def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; 3538def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, GPR:$RHS), 3539 (SXTAB16 GPR:$LHS, GPR:$RHS, 0)>; 3540def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)), 3541 (SXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>; 3542 3543// Zero extenders 3544 3545let AddedComplexity = 16 in { 3546def UXTB : AI_ext_rrot<0b01101110, 3547 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 3548def UXTH : AI_ext_rrot<0b01101111, 3549 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 3550def UXTB16 : AI_ext_rrot<0b01101100, 3551 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 3552 3553// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 3554// The transformation should probably be done as a combiner action 3555// instead so we can include a check for masking back in the upper 3556// eight bits of the source into the lower eight bits of the result. 3557//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 3558// (UXTB16r_rot GPR:$Src, 3)>; 3559def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 3560 (UXTB16 GPR:$Src, 1)>; 3561def : ARMV6Pat<(int_arm_uxtb16 GPR:$Src), 3562 (UXTB16 GPR:$Src, 0)>; 3563def : ARMV6Pat<(int_arm_uxtb16 (rotr GPR:$Src, rot_imm:$rot)), 3564 (UXTB16 GPR:$Src, rot_imm:$rot)>; 3565 3566def UXTAB : AI_exta_rrot<0b01101110, "uxtab", 3567 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 3568def UXTAH : AI_exta_rrot<0b01101111, "uxtah", 3569 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 3570 3571def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 0xFF)), 3572 (UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3573def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 0xFFFF)), 3574 (UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3575} 3576 3577// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 3578def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; 3579def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, GPR:$RHS), 3580 (UXTAB16 GPR:$LHS, GPR:$RHS, 0)>; 3581def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)), 3582 (UXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>; 3583 3584 3585def SBFX : I<(outs GPRnopc:$Rd), 3586 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3587 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3588 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3589 Requires<[IsARM, HasV6T2]> { 3590 bits<4> Rd; 3591 bits<4> Rn; 3592 bits<5> lsb; 3593 bits<5> width; 3594 let Inst{27-21} = 0b0111101; 3595 let Inst{6-4} = 0b101; 3596 let Inst{20-16} = width; 3597 let Inst{15-12} = Rd; 3598 let Inst{11-7} = lsb; 3599 let Inst{3-0} = Rn; 3600} 3601 3602def UBFX : I<(outs GPRnopc:$Rd), 3603 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3604 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3605 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3606 Requires<[IsARM, HasV6T2]> { 3607 bits<4> Rd; 3608 bits<4> Rn; 3609 bits<5> lsb; 3610 bits<5> width; 3611 let Inst{27-21} = 0b0111111; 3612 let Inst{6-4} = 0b101; 3613 let Inst{20-16} = width; 3614 let Inst{15-12} = Rd; 3615 let Inst{11-7} = lsb; 3616 let Inst{3-0} = Rn; 3617} 3618 3619//===----------------------------------------------------------------------===// 3620// Arithmetic Instructions. 3621// 3622 3623let isAdd = 1 in 3624defm ADD : AsI1_bin_irs<0b0100, "add", 3625 IIC_iALUi, IIC_iALUr, IIC_iALUsr, add, 1>; 3626defm SUB : AsI1_bin_irs<0b0010, "sub", 3627 IIC_iALUi, IIC_iALUr, IIC_iALUsr, sub>; 3628 3629// ADD and SUB with 's' bit set. 3630// 3631// Currently, ADDS/SUBS are pseudo opcodes that exist only in the 3632// selection DAG. They are "lowered" to real ADD/SUB opcodes by 3633// AdjustInstrPostInstrSelection where we determine whether or not to 3634// set the "s" bit based on CPSR liveness. 3635// 3636// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen 3637// support for an optional CPSR definition that corresponds to the DAG 3638// node's second value. We can then eliminate the implicit def of CPSR. 3639let isAdd = 1 in 3640defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMaddc, 1>; 3641defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>; 3642 3643def : ARMPat<(ARMsubs GPR:$Rn, mod_imm:$imm), (SUBSri $Rn, mod_imm:$imm)>; 3644def : ARMPat<(ARMsubs GPR:$Rn, GPR:$Rm), (SUBSrr $Rn, $Rm)>; 3645def : ARMPat<(ARMsubs GPR:$Rn, so_reg_imm:$shift), 3646 (SUBSrsi $Rn, so_reg_imm:$shift)>; 3647def : ARMPat<(ARMsubs GPR:$Rn, so_reg_reg:$shift), 3648 (SUBSrsr $Rn, so_reg_reg:$shift)>; 3649 3650 3651let isAdd = 1 in 3652defm ADC : AI1_adde_sube_irs<0b0101, "adc", ARMadde, 1>; 3653defm SBC : AI1_adde_sube_irs<0b0110, "sbc", ARMsube>; 3654 3655defm RSB : AsI1_rbin_irs<0b0011, "rsb", 3656 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3657 sub>; 3658 3659// FIXME: Eliminate them if we can write def : Pat patterns which defines 3660// CPSR and the implicit def of CPSR is not needed. 3661defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>; 3662 3663defm RSC : AI1_rsc_irs<0b0111, "rsc", ARMsube>; 3664 3665// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 3666// The assume-no-carry-in form uses the negation of the input since add/sub 3667// assume opposite meanings of the carry flag (i.e., carry == !borrow). 3668// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 3669// details. 3670def : ARMPat<(add GPR:$src, mod_imm_neg:$imm), 3671 (SUBri GPR:$src, mod_imm_neg:$imm)>; 3672def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm), 3673 (SUBSri GPR:$src, mod_imm_neg:$imm)>; 3674 3675def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm), 3676 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3677 Requires<[IsARM, HasV6T2]>; 3678def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm), 3679 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3680 Requires<[IsARM, HasV6T2]>; 3681 3682// The with-carry-in form matches bitwise not instead of the negation. 3683// Effectively, the inverse interpretation of the carry flag already accounts 3684// for part of the negation. 3685def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR), 3686 (SBCri GPR:$src, mod_imm_not:$imm)>; 3687def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR), 3688 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>, 3689 Requires<[IsARM, HasV6T2]>; 3690 3691// Note: These are implemented in C++ code, because they have to generate 3692// ADD/SUBrs instructions, which use a complex pattern that a xform function 3693// cannot produce. 3694// (mul X, 2^n+1) -> (add (X << n), X) 3695// (mul X, 2^n-1) -> (rsb X, (X << n)) 3696 3697// ARM Arithmetic Instruction 3698// GPR:$dst = GPR:$a op GPR:$b 3699class AAI<bits<8> op27_20, bits<8> op11_4, string opc, 3700 list<dag> pattern = [], 3701 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm), 3702 string asm = "\t$Rd, $Rn, $Rm"> 3703 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>, 3704 Sched<[WriteALU, ReadALU, ReadALU]> { 3705 bits<4> Rn; 3706 bits<4> Rd; 3707 bits<4> Rm; 3708 let Inst{27-20} = op27_20; 3709 let Inst{11-4} = op11_4; 3710 let Inst{19-16} = Rn; 3711 let Inst{15-12} = Rd; 3712 let Inst{3-0} = Rm; 3713 3714 let Unpredictable{11-8} = 0b1111; 3715} 3716 3717// Wrappers around the AAI class 3718class AAIRevOpr<bits<8> op27_20, bits<8> op11_4, string opc, 3719 list<dag> pattern = []> 3720 : AAI<op27_20, op11_4, opc, 3721 pattern, 3722 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3723 "\t$Rd, $Rm, $Rn">; 3724 3725class AAIIntrinsic<bits<8> op27_20, bits<8> op11_4, string opc, 3726 Intrinsic intrinsic> 3727 : AAI<op27_20, op11_4, opc, 3728 [(set GPRnopc:$Rd, (intrinsic GPRnopc:$Rn, GPRnopc:$Rm))]>; 3729 3730// Saturating add/subtract 3731let hasSideEffects = 1 in { 3732def QADD8 : AAIIntrinsic<0b01100010, 0b11111001, "qadd8", int_arm_qadd8>; 3733def QADD16 : AAIIntrinsic<0b01100010, 0b11110001, "qadd16", int_arm_qadd16>; 3734def QSUB16 : AAIIntrinsic<0b01100010, 0b11110111, "qsub16", int_arm_qsub16>; 3735def QSUB8 : AAIIntrinsic<0b01100010, 0b11111111, "qsub8", int_arm_qsub8>; 3736 3737def QDADD : AAIRevOpr<0b00010100, 0b00000101, "qdadd", 3738 [(set GPRnopc:$Rd, (int_arm_qadd (int_arm_qadd GPRnopc:$Rm, 3739 GPRnopc:$Rm), 3740 GPRnopc:$Rn))]>; 3741def QDSUB : AAIRevOpr<0b00010110, 0b00000101, "qdsub", 3742 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, 3743 (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>; 3744def QSUB : AAIRevOpr<0b00010010, 0b00000101, "qsub", 3745 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))]>; 3746let DecoderMethod = "DecodeQADDInstruction" in 3747 def QADD : AAIRevOpr<0b00010000, 0b00000101, "qadd", 3748 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))]>; 3749} 3750 3751def UQADD16 : AAIIntrinsic<0b01100110, 0b11110001, "uqadd16", int_arm_uqadd16>; 3752def UQADD8 : AAIIntrinsic<0b01100110, 0b11111001, "uqadd8", int_arm_uqadd8>; 3753def UQSUB16 : AAIIntrinsic<0b01100110, 0b11110111, "uqsub16", int_arm_uqsub16>; 3754def UQSUB8 : AAIIntrinsic<0b01100110, 0b11111111, "uqsub8", int_arm_uqsub8>; 3755def QASX : AAIIntrinsic<0b01100010, 0b11110011, "qasx", int_arm_qasx>; 3756def QSAX : AAIIntrinsic<0b01100010, 0b11110101, "qsax", int_arm_qsax>; 3757def UQASX : AAIIntrinsic<0b01100110, 0b11110011, "uqasx", int_arm_uqasx>; 3758def UQSAX : AAIIntrinsic<0b01100110, 0b11110101, "uqsax", int_arm_uqsax>; 3759 3760// Signed/Unsigned add/subtract 3761 3762def SASX : AAIIntrinsic<0b01100001, 0b11110011, "sasx", int_arm_sasx>; 3763def SADD16 : AAIIntrinsic<0b01100001, 0b11110001, "sadd16", int_arm_sadd16>; 3764def SADD8 : AAIIntrinsic<0b01100001, 0b11111001, "sadd8", int_arm_sadd8>; 3765def SSAX : AAIIntrinsic<0b01100001, 0b11110101, "ssax", int_arm_ssax>; 3766def SSUB16 : AAIIntrinsic<0b01100001, 0b11110111, "ssub16", int_arm_ssub16>; 3767def SSUB8 : AAIIntrinsic<0b01100001, 0b11111111, "ssub8", int_arm_ssub8>; 3768def UASX : AAIIntrinsic<0b01100101, 0b11110011, "uasx", int_arm_uasx>; 3769def UADD16 : AAIIntrinsic<0b01100101, 0b11110001, "uadd16", int_arm_uadd16>; 3770def UADD8 : AAIIntrinsic<0b01100101, 0b11111001, "uadd8", int_arm_uadd8>; 3771def USAX : AAIIntrinsic<0b01100101, 0b11110101, "usax", int_arm_usax>; 3772def USUB16 : AAIIntrinsic<0b01100101, 0b11110111, "usub16", int_arm_usub16>; 3773def USUB8 : AAIIntrinsic<0b01100101, 0b11111111, "usub8", int_arm_usub8>; 3774 3775// Signed/Unsigned halving add/subtract 3776 3777def SHASX : AAIIntrinsic<0b01100011, 0b11110011, "shasx", int_arm_shasx>; 3778def SHADD16 : AAIIntrinsic<0b01100011, 0b11110001, "shadd16", int_arm_shadd16>; 3779def SHADD8 : AAIIntrinsic<0b01100011, 0b11111001, "shadd8", int_arm_shadd8>; 3780def SHSAX : AAIIntrinsic<0b01100011, 0b11110101, "shsax", int_arm_shsax>; 3781def SHSUB16 : AAIIntrinsic<0b01100011, 0b11110111, "shsub16", int_arm_shsub16>; 3782def SHSUB8 : AAIIntrinsic<0b01100011, 0b11111111, "shsub8", int_arm_shsub8>; 3783def UHASX : AAIIntrinsic<0b01100111, 0b11110011, "uhasx", int_arm_uhasx>; 3784def UHADD16 : AAIIntrinsic<0b01100111, 0b11110001, "uhadd16", int_arm_uhadd16>; 3785def UHADD8 : AAIIntrinsic<0b01100111, 0b11111001, "uhadd8", int_arm_uhadd8>; 3786def UHSAX : AAIIntrinsic<0b01100111, 0b11110101, "uhsax", int_arm_uhsax>; 3787def UHSUB16 : AAIIntrinsic<0b01100111, 0b11110111, "uhsub16", int_arm_uhsub16>; 3788def UHSUB8 : AAIIntrinsic<0b01100111, 0b11111111, "uhsub8", int_arm_uhsub8>; 3789 3790// Unsigned Sum of Absolute Differences [and Accumulate]. 3791 3792def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3793 MulFrm /* for convenience */, NoItinerary, "usad8", 3794 "\t$Rd, $Rn, $Rm", 3795 [(set GPR:$Rd, (int_arm_usad8 GPR:$Rn, GPR:$Rm))]>, 3796 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> { 3797 bits<4> Rd; 3798 bits<4> Rn; 3799 bits<4> Rm; 3800 let Inst{27-20} = 0b01111000; 3801 let Inst{15-12} = 0b1111; 3802 let Inst{7-4} = 0b0001; 3803 let Inst{19-16} = Rd; 3804 let Inst{11-8} = Rm; 3805 let Inst{3-0} = Rn; 3806} 3807def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3808 MulFrm /* for convenience */, NoItinerary, "usada8", 3809 "\t$Rd, $Rn, $Rm, $Ra", 3810 [(set GPR:$Rd, (int_arm_usada8 GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 3811 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{ 3812 bits<4> Rd; 3813 bits<4> Rn; 3814 bits<4> Rm; 3815 bits<4> Ra; 3816 let Inst{27-20} = 0b01111000; 3817 let Inst{7-4} = 0b0001; 3818 let Inst{19-16} = Rd; 3819 let Inst{15-12} = Ra; 3820 let Inst{11-8} = Rm; 3821 let Inst{3-0} = Rn; 3822} 3823 3824// Signed/Unsigned saturate 3825def SSAT : AI<(outs GPRnopc:$Rd), 3826 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3827 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>, 3828 Requires<[IsARM,HasV6]>{ 3829 bits<4> Rd; 3830 bits<5> sat_imm; 3831 bits<4> Rn; 3832 bits<8> sh; 3833 let Inst{27-21} = 0b0110101; 3834 let Inst{5-4} = 0b01; 3835 let Inst{20-16} = sat_imm; 3836 let Inst{15-12} = Rd; 3837 let Inst{11-7} = sh{4-0}; 3838 let Inst{6} = sh{5}; 3839 let Inst{3-0} = Rn; 3840} 3841 3842def SSAT16 : AI<(outs GPRnopc:$Rd), 3843 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm, 3844 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []>, 3845 Requires<[IsARM,HasV6]>{ 3846 bits<4> Rd; 3847 bits<4> sat_imm; 3848 bits<4> Rn; 3849 let Inst{27-20} = 0b01101010; 3850 let Inst{11-4} = 0b11110011; 3851 let Inst{15-12} = Rd; 3852 let Inst{19-16} = sat_imm; 3853 let Inst{3-0} = Rn; 3854} 3855 3856def USAT : AI<(outs GPRnopc:$Rd), 3857 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3858 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>, 3859 Requires<[IsARM,HasV6]> { 3860 bits<4> Rd; 3861 bits<5> sat_imm; 3862 bits<4> Rn; 3863 bits<8> sh; 3864 let Inst{27-21} = 0b0110111; 3865 let Inst{5-4} = 0b01; 3866 let Inst{15-12} = Rd; 3867 let Inst{11-7} = sh{4-0}; 3868 let Inst{6} = sh{5}; 3869 let Inst{20-16} = sat_imm; 3870 let Inst{3-0} = Rn; 3871} 3872 3873def USAT16 : AI<(outs GPRnopc:$Rd), 3874 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm, 3875 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []>, 3876 Requires<[IsARM,HasV6]>{ 3877 bits<4> Rd; 3878 bits<4> sat_imm; 3879 bits<4> Rn; 3880 let Inst{27-20} = 0b01101110; 3881 let Inst{11-4} = 0b11110011; 3882 let Inst{15-12} = Rd; 3883 let Inst{19-16} = sat_imm; 3884 let Inst{3-0} = Rn; 3885} 3886 3887def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos), 3888 (SSAT imm1_32:$pos, GPRnopc:$a, 0)>; 3889def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos), 3890 (USAT imm0_31:$pos, GPRnopc:$a, 0)>; 3891def : ARMPat<(ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm), 3892 (SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 3893def : ARMPat<(ARMusatnoshift GPRnopc:$Rn, imm0_31:$imm), 3894 (USAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 3895def : ARMV6Pat<(int_arm_ssat16 GPRnopc:$a, imm1_16:$pos), 3896 (SSAT16 imm1_16:$pos, GPRnopc:$a)>; 3897def : ARMV6Pat<(int_arm_usat16 GPRnopc:$a, imm0_15:$pos), 3898 (USAT16 imm0_15:$pos, GPRnopc:$a)>; 3899 3900//===----------------------------------------------------------------------===// 3901// Bitwise Instructions. 3902// 3903 3904defm AND : AsI1_bin_irs<0b0000, "and", 3905 IIC_iBITi, IIC_iBITr, IIC_iBITsr, and, 1>; 3906defm ORR : AsI1_bin_irs<0b1100, "orr", 3907 IIC_iBITi, IIC_iBITr, IIC_iBITsr, or, 1>; 3908defm EOR : AsI1_bin_irs<0b0001, "eor", 3909 IIC_iBITi, IIC_iBITr, IIC_iBITsr, xor, 1>; 3910defm BIC : AsI1_bin_irs<0b1110, "bic", 3911 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3912 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 3913 3914// FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just 3915// like in the actual instruction encoding. The complexity of mapping the mask 3916// to the lsb/msb pair should be handled by ISel, not encapsulated in the 3917// instruction description. 3918def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), 3919 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3920 "bfc", "\t$Rd, $imm", "$src = $Rd", 3921 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>, 3922 Requires<[IsARM, HasV6T2]> { 3923 bits<4> Rd; 3924 bits<10> imm; 3925 let Inst{27-21} = 0b0111110; 3926 let Inst{6-0} = 0b0011111; 3927 let Inst{15-12} = Rd; 3928 let Inst{11-7} = imm{4-0}; // lsb 3929 let Inst{20-16} = imm{9-5}; // msb 3930} 3931 3932// A8.6.18 BFI - Bitfield insert (Encoding A1) 3933def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm), 3934 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3935 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd", 3936 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn, 3937 bf_inv_mask_imm:$imm))]>, 3938 Requires<[IsARM, HasV6T2]> { 3939 bits<4> Rd; 3940 bits<4> Rn; 3941 bits<10> imm; 3942 let Inst{27-21} = 0b0111110; 3943 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 3944 let Inst{15-12} = Rd; 3945 let Inst{11-7} = imm{4-0}; // lsb 3946 let Inst{20-16} = imm{9-5}; // width 3947 let Inst{3-0} = Rn; 3948} 3949 3950def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr, 3951 "mvn", "\t$Rd, $Rm", 3952 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> { 3953 bits<4> Rd; 3954 bits<4> Rm; 3955 let Inst{25} = 0; 3956 let Inst{19-16} = 0b0000; 3957 let Inst{11-4} = 0b00000000; 3958 let Inst{15-12} = Rd; 3959 let Inst{3-0} = Rm; 3960 3961 let Unpredictable{19-16} = 0b1111; 3962} 3963def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift), 3964 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3965 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP, 3966 Sched<[WriteALU]> { 3967 bits<4> Rd; 3968 bits<12> shift; 3969 let Inst{25} = 0; 3970 let Inst{19-16} = 0b0000; 3971 let Inst{15-12} = Rd; 3972 let Inst{11-5} = shift{11-5}; 3973 let Inst{4} = 0; 3974 let Inst{3-0} = shift{3-0}; 3975 3976 let Unpredictable{19-16} = 0b1111; 3977} 3978def MVNsr : AsI1<0b1111, (outs GPRnopc:$Rd), (ins so_reg_reg:$shift), 3979 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3980 [(set GPRnopc:$Rd, (not so_reg_reg:$shift))]>, UnaryDP, 3981 Sched<[WriteALU]> { 3982 bits<4> Rd; 3983 bits<12> shift; 3984 let Inst{25} = 0; 3985 let Inst{19-16} = 0b0000; 3986 let Inst{15-12} = Rd; 3987 let Inst{11-8} = shift{11-8}; 3988 let Inst{7} = 0; 3989 let Inst{6-5} = shift{6-5}; 3990 let Inst{4} = 1; 3991 let Inst{3-0} = shift{3-0}; 3992 3993 let Unpredictable{19-16} = 0b1111; 3994} 3995let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3996def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, 3997 IIC_iMVNi, "mvn", "\t$Rd, $imm", 3998 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> { 3999 bits<4> Rd; 4000 bits<12> imm; 4001 let Inst{25} = 1; 4002 let Inst{19-16} = 0b0000; 4003 let Inst{15-12} = Rd; 4004 let Inst{11-0} = imm; 4005} 4006 4007let AddedComplexity = 1 in 4008def : ARMPat<(and GPR:$src, mod_imm_not:$imm), 4009 (BICri GPR:$src, mod_imm_not:$imm)>; 4010 4011//===----------------------------------------------------------------------===// 4012// Multiply Instructions. 4013// 4014class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4015 string opc, string asm, list<dag> pattern> 4016 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4017 bits<4> Rd; 4018 bits<4> Rm; 4019 bits<4> Rn; 4020 let Inst{19-16} = Rd; 4021 let Inst{11-8} = Rm; 4022 let Inst{3-0} = Rn; 4023} 4024class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4025 string opc, string asm, list<dag> pattern> 4026 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4027 bits<4> RdLo; 4028 bits<4> RdHi; 4029 bits<4> Rm; 4030 bits<4> Rn; 4031 let Inst{19-16} = RdHi; 4032 let Inst{15-12} = RdLo; 4033 let Inst{11-8} = Rm; 4034 let Inst{3-0} = Rn; 4035} 4036class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4037 string opc, string asm, list<dag> pattern> 4038 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4039 bits<4> RdLo; 4040 bits<4> RdHi; 4041 bits<4> Rm; 4042 bits<4> Rn; 4043 let Inst{19-16} = RdHi; 4044 let Inst{15-12} = RdLo; 4045 let Inst{11-8} = Rm; 4046 let Inst{3-0} = Rn; 4047} 4048 4049// FIXME: The v5 pseudos are only necessary for the additional Constraint 4050// property. Remove them when it's possible to add those properties 4051// on an individual MachineInstr, not just an instruction description. 4052let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in { 4053def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), 4054 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4055 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", 4056 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>, 4057 Requires<[IsARM, HasV6]>, 4058 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4059 let Inst{15-12} = 0b0000; 4060 let Unpredictable{15-12} = 0b1111; 4061} 4062 4063let Constraints = "@earlyclobber $Rd" in 4064def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, 4065 pred:$p, cc_out:$s), 4066 4, IIC_iMUL32, 4067 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))], 4068 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 4069 Requires<[IsARM, NoV6, UseMulOps]>, 4070 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4071} 4072 4073def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd), 4074 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra), 4075 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra", 4076 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>, 4077 Requires<[IsARM, HasV6, UseMulOps]>, 4078 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 4079 bits<4> Ra; 4080 let Inst{15-12} = Ra; 4081} 4082 4083let Constraints = "@earlyclobber $Rd" in 4084def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd), 4085 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 4086 pred:$p, cc_out:$s), 4, IIC_iMAC32, 4087 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))], 4088 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>, 4089 Requires<[IsARM, NoV6]>, 4090 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4091 4092def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4093 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra", 4094 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>, 4095 Requires<[IsARM, HasV6T2, UseMulOps]>, 4096 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 4097 bits<4> Rd; 4098 bits<4> Rm; 4099 bits<4> Rn; 4100 bits<4> Ra; 4101 let Inst{19-16} = Rd; 4102 let Inst{15-12} = Ra; 4103 let Inst{11-8} = Rm; 4104 let Inst{3-0} = Rn; 4105} 4106 4107// Extra precision multiplies with low / high results 4108let hasSideEffects = 0 in { 4109let isCommutable = 1 in { 4110def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi), 4111 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 4112 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", 4113 [(set GPR:$RdLo, GPR:$RdHi, 4114 (smullohi GPR:$Rn, GPR:$Rm))]>, 4115 Requires<[IsARM, HasV6]>, 4116 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4117 4118def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), 4119 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 4120 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", 4121 [(set GPR:$RdLo, GPR:$RdHi, 4122 (umullohi GPR:$Rn, GPR:$Rm))]>, 4123 Requires<[IsARM, HasV6]>, 4124 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL]>; 4125 4126let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { 4127def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4128 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 4129 4, IIC_iMUL64, 4130 [(set GPR:$RdLo, GPR:$RdHi, 4131 (smullohi GPR:$Rn, GPR:$Rm))], 4132 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 4133 Requires<[IsARM, NoV6]>, 4134 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4135 4136def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4137 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 4138 4, IIC_iMUL64, 4139 [(set GPR:$RdLo, GPR:$RdHi, 4140 (umullohi GPR:$Rn, GPR:$Rm))], 4141 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 4142 Requires<[IsARM, NoV6]>, 4143 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4144} 4145} 4146 4147// Multiply + accumulate 4148def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi), 4149 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4150 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4151 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4152 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4153def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi), 4154 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4155 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4156 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4157 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4158 4159def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi), 4160 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4161 IIC_iMAC64, 4162 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4163 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4164 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> { 4165 bits<4> RdLo; 4166 bits<4> RdHi; 4167 bits<4> Rm; 4168 bits<4> Rn; 4169 let Inst{19-16} = RdHi; 4170 let Inst{15-12} = RdLo; 4171 let Inst{11-8} = Rm; 4172 let Inst{3-0} = Rn; 4173} 4174 4175let Constraints = 4176 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in { 4177def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4178 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4179 4, IIC_iMAC64, [], 4180 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4181 pred:$p, cc_out:$s)>, 4182 Requires<[IsARM, NoV6]>, 4183 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4184def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4185 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4186 4, IIC_iMAC64, [], 4187 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4188 pred:$p, cc_out:$s)>, 4189 Requires<[IsARM, NoV6]>, 4190 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4191} 4192 4193} // hasSideEffects 4194 4195// Most significant word multiply 4196def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4197 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm", 4198 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>, 4199 Requires<[IsARM, HasV6]>, 4200 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4201 let Inst{15-12} = 0b1111; 4202} 4203 4204def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4205 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", 4206 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, (i32 0)))]>, 4207 Requires<[IsARM, HasV6]>, 4208 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4209 let Inst{15-12} = 0b1111; 4210} 4211 4212def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd), 4213 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4214 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra", 4215 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, 4216 Requires<[IsARM, HasV6, UseMulOps]>, 4217 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4218 4219def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd), 4220 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4221 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", 4222 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 4223 Requires<[IsARM, HasV6]>, 4224 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4225 4226def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd), 4227 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4228 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>, 4229 Requires<[IsARM, HasV6, UseMulOps]>, 4230 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4231 4232def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd), 4233 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4234 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", 4235 [(set GPR:$Rd, (ARMsmmlsr GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 4236 Requires<[IsARM, HasV6]>, 4237 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4238 4239multiclass AI_smul<string opc> { 4240 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4241 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 4242 [(set GPR:$Rd, (bb_mul GPR:$Rn, GPR:$Rm))]>, 4243 Requires<[IsARM, HasV5TE]>, 4244 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4245 4246 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4247 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 4248 [(set GPR:$Rd, (bt_mul GPR:$Rn, GPR:$Rm))]>, 4249 Requires<[IsARM, HasV5TE]>, 4250 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4251 4252 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4253 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 4254 [(set GPR:$Rd, (tb_mul GPR:$Rn, GPR:$Rm))]>, 4255 Requires<[IsARM, HasV5TE]>, 4256 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4257 4258 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4259 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 4260 [(set GPR:$Rd, (tt_mul GPR:$Rn, GPR:$Rm))]>, 4261 Requires<[IsARM, HasV5TE]>, 4262 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4263 4264 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4265 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 4266 [(set GPR:$Rd, (ARMsmulwb GPR:$Rn, GPR:$Rm))]>, 4267 Requires<[IsARM, HasV5TE]>, 4268 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4269 4270 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4271 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 4272 [(set GPR:$Rd, (ARMsmulwt GPR:$Rn, GPR:$Rm))]>, 4273 Requires<[IsARM, HasV5TE]>, 4274 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4275} 4276 4277 4278multiclass AI_smla<string opc> { 4279 let DecoderMethod = "DecodeSMLAInstruction" in { 4280 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd), 4281 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4282 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 4283 [(set GPRnopc:$Rd, (add GPR:$Ra, 4284 (bb_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4285 Requires<[IsARM, HasV5TE, UseMulOps]>, 4286 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4287 4288 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd), 4289 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4290 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 4291 [(set GPRnopc:$Rd, (add GPR:$Ra, 4292 (bt_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4293 Requires<[IsARM, HasV5TE, UseMulOps]>, 4294 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4295 4296 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd), 4297 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4298 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 4299 [(set GPRnopc:$Rd, (add GPR:$Ra, 4300 (tb_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4301 Requires<[IsARM, HasV5TE, UseMulOps]>, 4302 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4303 4304 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd), 4305 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4306 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 4307 [(set GPRnopc:$Rd, (add GPR:$Ra, 4308 (tt_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4309 Requires<[IsARM, HasV5TE, UseMulOps]>, 4310 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4311 4312 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd), 4313 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4314 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 4315 [(set GPRnopc:$Rd, 4316 (add GPR:$Ra, (ARMsmulwb GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4317 Requires<[IsARM, HasV5TE, UseMulOps]>, 4318 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4319 4320 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd), 4321 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4322 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 4323 [(set GPRnopc:$Rd, 4324 (add GPR:$Ra, (ARMsmulwt GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4325 Requires<[IsARM, HasV5TE, UseMulOps]>, 4326 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4327 } 4328} 4329 4330defm SMUL : AI_smul<"smul">; 4331defm SMLA : AI_smla<"smla">; 4332 4333// Halfword multiply accumulate long: SMLAL<x><y>. 4334class SMLAL<bits<2> opc1, string asm> 4335 : AMulxyI64<0b0001010, opc1, 4336 (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4337 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4338 IIC_iMAC64, asm, "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4339 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4340 Requires<[IsARM, HasV5TE]>, 4341 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4342 4343def SMLALBB : SMLAL<0b00, "smlalbb">; 4344def SMLALBT : SMLAL<0b10, "smlalbt">; 4345def SMLALTB : SMLAL<0b01, "smlaltb">; 4346def SMLALTT : SMLAL<0b11, "smlaltt">; 4347 4348def : ARMV5TEPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4349 (SMLALBB $Rn, $Rm, $RLo, $RHi)>; 4350def : ARMV5TEPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4351 (SMLALBT $Rn, $Rm, $RLo, $RHi)>; 4352def : ARMV5TEPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4353 (SMLALTB $Rn, $Rm, $RLo, $RHi)>; 4354def : ARMV5TEPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4355 (SMLALTT $Rn, $Rm, $RLo, $RHi)>; 4356 4357// Helper class for AI_smld. 4358class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops, 4359 InstrItinClass itin, string opc, string asm> 4360 : AI<oops, iops, MulFrm, itin, opc, asm, []>, 4361 Requires<[IsARM, HasV6]> { 4362 bits<4> Rn; 4363 bits<4> Rm; 4364 let Inst{27-23} = 0b01110; 4365 let Inst{22} = long; 4366 let Inst{21-20} = 0b00; 4367 let Inst{11-8} = Rm; 4368 let Inst{7} = 0; 4369 let Inst{6} = sub; 4370 let Inst{5} = swap; 4371 let Inst{4} = 1; 4372 let Inst{3-0} = Rn; 4373} 4374class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops, 4375 InstrItinClass itin, string opc, string asm> 4376 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4377 bits<4> Rd; 4378 let Inst{15-12} = 0b1111; 4379 let Inst{19-16} = Rd; 4380} 4381class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops, 4382 InstrItinClass itin, string opc, string asm> 4383 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4384 bits<4> Ra; 4385 bits<4> Rd; 4386 let Inst{19-16} = Rd; 4387 let Inst{15-12} = Ra; 4388} 4389class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops, 4390 InstrItinClass itin, string opc, string asm> 4391 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4392 bits<4> RdLo; 4393 bits<4> RdHi; 4394 let Inst{19-16} = RdHi; 4395 let Inst{15-12} = RdLo; 4396} 4397 4398multiclass AI_smld<bit sub, string opc> { 4399 4400 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd), 4401 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4402 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">, 4403 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4404 4405 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd), 4406 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4407 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">, 4408 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4409 4410 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4411 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4412 NoItinerary, 4413 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">, 4414 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4415 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4416 4417 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4418 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4419 NoItinerary, 4420 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">, 4421 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4422 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4423} 4424 4425defm SMLA : AI_smld<0, "smla">; 4426defm SMLS : AI_smld<1, "smls">; 4427 4428def : ARMV6Pat<(int_arm_smlad GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4429 (SMLAD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4430def : ARMV6Pat<(int_arm_smladx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4431 (SMLADX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4432def : ARMV6Pat<(int_arm_smlsd GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4433 (SMLSD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4434def : ARMV6Pat<(int_arm_smlsdx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4435 (SMLSDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4436def : ARMV6Pat<(ARMSmlald GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4437 (SMLALD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4438def : ARMV6Pat<(ARMSmlaldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4439 (SMLALDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4440def : ARMV6Pat<(ARMSmlsld GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4441 (SMLSLD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4442def : ARMV6Pat<(ARMSmlsldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4443 (SMLSLDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4444 4445multiclass AI_sdml<bit sub, string opc> { 4446 4447 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), 4448 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">, 4449 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4450 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm), 4451 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">, 4452 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4453} 4454 4455defm SMUA : AI_sdml<0, "smua">; 4456defm SMUS : AI_sdml<1, "smus">; 4457 4458def : ARMV6Pat<(int_arm_smuad GPRnopc:$Rn, GPRnopc:$Rm), 4459 (SMUAD GPRnopc:$Rn, GPRnopc:$Rm)>; 4460def : ARMV6Pat<(int_arm_smuadx GPRnopc:$Rn, GPRnopc:$Rm), 4461 (SMUADX GPRnopc:$Rn, GPRnopc:$Rm)>; 4462def : ARMV6Pat<(int_arm_smusd GPRnopc:$Rn, GPRnopc:$Rm), 4463 (SMUSD GPRnopc:$Rn, GPRnopc:$Rm)>; 4464def : ARMV6Pat<(int_arm_smusdx GPRnopc:$Rn, GPRnopc:$Rm), 4465 (SMUSDX GPRnopc:$Rn, GPRnopc:$Rm)>; 4466 4467//===----------------------------------------------------------------------===// 4468// Division Instructions (ARMv7-A with virtualization extension) 4469// 4470def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4471 "sdiv", "\t$Rd, $Rn, $Rm", 4472 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>, 4473 Requires<[IsARM, HasDivideInARM]>, 4474 Sched<[WriteDIV]>; 4475 4476def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4477 "udiv", "\t$Rd, $Rn, $Rm", 4478 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>, 4479 Requires<[IsARM, HasDivideInARM]>, 4480 Sched<[WriteDIV]>; 4481 4482//===----------------------------------------------------------------------===// 4483// Misc. Arithmetic Instructions. 4484// 4485 4486def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm), 4487 IIC_iUNAr, "clz", "\t$Rd, $Rm", 4488 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>, 4489 Sched<[WriteALU]>; 4490 4491def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4492 IIC_iUNAr, "rbit", "\t$Rd, $Rm", 4493 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>, 4494 Requires<[IsARM, HasV6T2]>, 4495 Sched<[WriteALU]>; 4496 4497def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4498 IIC_iUNAr, "rev", "\t$Rd, $Rm", 4499 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>, 4500 Sched<[WriteALU]>; 4501 4502let AddedComplexity = 5 in 4503def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4504 IIC_iUNAr, "rev16", "\t$Rd, $Rm", 4505 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>, 4506 Requires<[IsARM, HasV6]>, 4507 Sched<[WriteALU]>; 4508 4509def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)), 4510 (REV16 (LDRH addrmode3:$addr))>; 4511def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr), 4512 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>; 4513 4514let AddedComplexity = 5 in 4515def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4516 IIC_iUNAr, "revsh", "\t$Rd, $Rm", 4517 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>, 4518 Requires<[IsARM, HasV6]>, 4519 Sched<[WriteALU]>; 4520 4521def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)), 4522 (and (srl GPR:$Rm, (i32 8)), 0xFF)), 4523 (REVSH GPR:$Rm)>; 4524 4525def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd), 4526 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh), 4527 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 4528 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF), 4529 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh), 4530 0xFFFF0000)))]>, 4531 Requires<[IsARM, HasV6]>, 4532 Sched<[WriteALUsi, ReadALU]>; 4533 4534// Alternate cases for PKHBT where identities eliminate some nodes. 4535def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)), 4536 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>; 4537def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)), 4538 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>; 4539 4540// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 4541// will match the pattern below. 4542def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd), 4543 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh), 4544 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 4545 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000), 4546 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh), 4547 0xFFFF)))]>, 4548 Requires<[IsARM, HasV6]>, 4549 Sched<[WriteALUsi, ReadALU]>; 4550 4551// Alternate cases for PKHTB where identities eliminate some nodes. Note that 4552// a shift amount of 0 is *not legal* here, it is PKHBT instead. 4553// We also can not replace a srl (17..31) by an arithmetic shift we would use in 4554// pkhtb src1, src2, asr (17..31). 4555def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4556 (srl GPRnopc:$src2, imm16:$sh)), 4557 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>; 4558def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4559 (sra GPRnopc:$src2, imm16_31:$sh)), 4560 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>; 4561def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4562 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)), 4563 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>; 4564 4565//===----------------------------------------------------------------------===// 4566// CRC Instructions 4567// 4568// Polynomials: 4569// + CRC32{B,H,W} 0x04C11DB7 4570// + CRC32C{B,H,W} 0x1EDC6F41 4571// 4572 4573class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin> 4574 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary, 4575 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm", 4576 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>, 4577 Requires<[IsARM, HasV8, HasCRC]> { 4578 bits<4> Rd; 4579 bits<4> Rn; 4580 bits<4> Rm; 4581 4582 let Inst{31-28} = 0b1110; 4583 let Inst{27-23} = 0b00010; 4584 let Inst{22-21} = sz; 4585 let Inst{20} = 0; 4586 let Inst{19-16} = Rn; 4587 let Inst{15-12} = Rd; 4588 let Inst{11-10} = 0b00; 4589 let Inst{9} = C; 4590 let Inst{8} = 0; 4591 let Inst{7-4} = 0b0100; 4592 let Inst{3-0} = Rm; 4593 4594 let Unpredictable{11-8} = 0b1101; 4595} 4596 4597def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>; 4598def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>; 4599def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>; 4600def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>; 4601def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>; 4602def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>; 4603 4604//===----------------------------------------------------------------------===// 4605// ARMv8.1a Privilege Access Never extension 4606// 4607// SETPAN #imm1 4608 4609def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan", 4610 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> { 4611 bits<1> imm; 4612 4613 let Inst{31-28} = 0b1111; 4614 let Inst{27-20} = 0b00010001; 4615 let Inst{19-16} = 0b0000; 4616 let Inst{15-10} = 0b000000; 4617 let Inst{9} = imm; 4618 let Inst{8} = 0b0; 4619 let Inst{7-4} = 0b0000; 4620 let Inst{3-0} = 0b0000; 4621 4622 let Unpredictable{19-16} = 0b1111; 4623 let Unpredictable{15-10} = 0b111111; 4624 let Unpredictable{8} = 0b1; 4625 let Unpredictable{3-0} = 0b1111; 4626} 4627 4628//===----------------------------------------------------------------------===// 4629// Comparison Instructions... 4630// 4631 4632defm CMP : AI1_cmp_irs<0b1010, "cmp", 4633 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, ARMcmp>; 4634 4635// ARMcmpZ can re-use the above instruction definitions. 4636def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm), 4637 (CMPri GPR:$src, mod_imm:$imm)>; 4638def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs), 4639 (CMPrr GPR:$src, GPR:$rhs)>; 4640def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs), 4641 (CMPrsi GPR:$src, so_reg_imm:$rhs)>; 4642def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs), 4643 (CMPrsr GPR:$src, so_reg_reg:$rhs)>; 4644 4645// CMN register-integer 4646let isCompare = 1, Defs = [CPSR] in { 4647def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi, 4648 "cmn", "\t$Rn, $imm", 4649 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>, 4650 Sched<[WriteCMP, ReadALU]> { 4651 bits<4> Rn; 4652 bits<12> imm; 4653 let Inst{25} = 1; 4654 let Inst{20} = 1; 4655 let Inst{19-16} = Rn; 4656 let Inst{15-12} = 0b0000; 4657 let Inst{11-0} = imm; 4658 4659 let Unpredictable{15-12} = 0b1111; 4660} 4661 4662// CMN register-register/shift 4663def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr, 4664 "cmn", "\t$Rn, $Rm", 4665 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4666 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> { 4667 bits<4> Rn; 4668 bits<4> Rm; 4669 let isCommutable = 1; 4670 let Inst{25} = 0; 4671 let Inst{20} = 1; 4672 let Inst{19-16} = Rn; 4673 let Inst{15-12} = 0b0000; 4674 let Inst{11-4} = 0b00000000; 4675 let Inst{3-0} = Rm; 4676 4677 let Unpredictable{15-12} = 0b1111; 4678} 4679 4680def CMNzrsi : AI1<0b1011, (outs), 4681 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr, 4682 "cmn", "\t$Rn, $shift", 4683 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4684 GPR:$Rn, so_reg_imm:$shift)]>, 4685 Sched<[WriteCMPsi, ReadALU]> { 4686 bits<4> Rn; 4687 bits<12> shift; 4688 let Inst{25} = 0; 4689 let Inst{20} = 1; 4690 let Inst{19-16} = Rn; 4691 let Inst{15-12} = 0b0000; 4692 let Inst{11-5} = shift{11-5}; 4693 let Inst{4} = 0; 4694 let Inst{3-0} = shift{3-0}; 4695 4696 let Unpredictable{15-12} = 0b1111; 4697} 4698 4699def CMNzrsr : AI1<0b1011, (outs), 4700 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr, 4701 "cmn", "\t$Rn, $shift", 4702 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4703 GPRnopc:$Rn, so_reg_reg:$shift)]>, 4704 Sched<[WriteCMPsr, ReadALU]> { 4705 bits<4> Rn; 4706 bits<12> shift; 4707 let Inst{25} = 0; 4708 let Inst{20} = 1; 4709 let Inst{19-16} = Rn; 4710 let Inst{15-12} = 0b0000; 4711 let Inst{11-8} = shift{11-8}; 4712 let Inst{7} = 0; 4713 let Inst{6-5} = shift{6-5}; 4714 let Inst{4} = 1; 4715 let Inst{3-0} = shift{3-0}; 4716 4717 let Unpredictable{15-12} = 0b1111; 4718} 4719 4720} 4721 4722def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm), 4723 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4724 4725def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm), 4726 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4727 4728// Note that TST/TEQ don't set all the same flags that CMP does! 4729defm TST : AI1_cmp_irs<0b1000, "tst", 4730 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4731 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1, 4732 "DecodeTSTInstruction">; 4733defm TEQ : AI1_cmp_irs<0b1001, "teq", 4734 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4735 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>; 4736 4737// Pseudo i64 compares for some floating point compares. 4738let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, 4739 Defs = [CPSR] in { 4740def BCCi64 : PseudoInst<(outs), 4741 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst), 4742 IIC_Br, 4743 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>, 4744 Sched<[WriteBr]>; 4745 4746def BCCZi64 : PseudoInst<(outs), 4747 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, 4748 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>, 4749 Sched<[WriteBr]>; 4750} // usesCustomInserter 4751 4752 4753// Conditional moves 4754let hasSideEffects = 0 in { 4755 4756let isCommutable = 1, isSelect = 1 in 4757def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), 4758 (ins GPR:$false, GPR:$Rm, cmovpred:$p), 4759 4, IIC_iCMOVr, 4760 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, 4761 cmovpred:$p))]>, 4762 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4763 4764def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd), 4765 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p), 4766 4, IIC_iCMOVsr, 4767 [(set GPR:$Rd, 4768 (ARMcmov GPR:$false, so_reg_imm:$shift, 4769 cmovpred:$p))]>, 4770 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4771def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd), 4772 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p), 4773 4, IIC_iCMOVsr, 4774 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift, 4775 cmovpred:$p))]>, 4776 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4777 4778 4779let isMoveImm = 1 in 4780def MOVCCi16 4781 : ARMPseudoInst<(outs GPR:$Rd), 4782 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p), 4783 4, IIC_iMOVi, 4784 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm, 4785 cmovpred:$p))]>, 4786 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>, 4787 Sched<[WriteALU]>; 4788 4789let isMoveImm = 1 in 4790def MOVCCi : ARMPseudoInst<(outs GPR:$Rd), 4791 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 4792 4, IIC_iCMOVi, 4793 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm, 4794 cmovpred:$p))]>, 4795 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4796 4797// Two instruction predicate mov immediate. 4798let isMoveImm = 1 in 4799def MOVCCi32imm 4800 : ARMPseudoInst<(outs GPR:$Rd), 4801 (ins GPR:$false, i32imm:$src, cmovpred:$p), 4802 8, IIC_iCMOVix2, 4803 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src, 4804 cmovpred:$p))]>, 4805 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>; 4806 4807let isMoveImm = 1 in 4808def MVNCCi : ARMPseudoInst<(outs GPR:$Rd), 4809 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 4810 4, IIC_iCMOVi, 4811 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm, 4812 cmovpred:$p))]>, 4813 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4814 4815} // hasSideEffects 4816 4817 4818//===----------------------------------------------------------------------===// 4819// Atomic operations intrinsics 4820// 4821 4822def MemBarrierOptOperand : AsmOperandClass { 4823 let Name = "MemBarrierOpt"; 4824 let ParserMethod = "parseMemBarrierOptOperand"; 4825} 4826def memb_opt : Operand<i32> { 4827 let PrintMethod = "printMemBOption"; 4828 let ParserMatchClass = MemBarrierOptOperand; 4829 let DecoderMethod = "DecodeMemBarrierOption"; 4830} 4831 4832def InstSyncBarrierOptOperand : AsmOperandClass { 4833 let Name = "InstSyncBarrierOpt"; 4834 let ParserMethod = "parseInstSyncBarrierOptOperand"; 4835} 4836def instsyncb_opt : Operand<i32> { 4837 let PrintMethod = "printInstSyncBOption"; 4838 let ParserMatchClass = InstSyncBarrierOptOperand; 4839 let DecoderMethod = "DecodeInstSyncBarrierOption"; 4840} 4841 4842def TraceSyncBarrierOptOperand : AsmOperandClass { 4843 let Name = "TraceSyncBarrierOpt"; 4844 let ParserMethod = "parseTraceSyncBarrierOptOperand"; 4845} 4846def tsb_opt : Operand<i32> { 4847 let PrintMethod = "printTraceSyncBOption"; 4848 let ParserMatchClass = TraceSyncBarrierOptOperand; 4849} 4850 4851// Memory barriers protect the atomic sequences 4852let hasSideEffects = 1 in { 4853def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4854 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>, 4855 Requires<[IsARM, HasDB]> { 4856 bits<4> opt; 4857 let Inst{31-4} = 0xf57ff05; 4858 let Inst{3-0} = opt; 4859} 4860 4861def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4862 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>, 4863 Requires<[IsARM, HasDB]> { 4864 bits<4> opt; 4865 let Inst{31-4} = 0xf57ff04; 4866 let Inst{3-0} = opt; 4867} 4868 4869// ISB has only full system option 4870def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary, 4871 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>, 4872 Requires<[IsARM, HasDB]> { 4873 bits<4> opt; 4874 let Inst{31-4} = 0xf57ff06; 4875 let Inst{3-0} = opt; 4876} 4877 4878let hasNoSchedulingInfo = 1 in 4879def TSB : AInoP<(outs), (ins tsb_opt:$opt), MiscFrm, NoItinerary, 4880 "tsb", "\t$opt", []>, Requires<[IsARM, HasV8_4a]> { 4881 let Inst{31-0} = 0xe320f012; 4882} 4883 4884} 4885 4886// Armv8.5-A speculation barrier 4887def SB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "sb", "", []>, 4888 Requires<[IsARM, HasSB]>, Sched<[]> { 4889 let Inst{31-0} = 0xf57ff070; 4890 let Unpredictable = 0x000fff0f; 4891 let hasSideEffects = 1; 4892} 4893 4894let usesCustomInserter = 1, Defs = [CPSR] in { 4895 4896// Pseudo instruction that combines movs + predicated rsbmi 4897// to implement integer ABS 4898 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>; 4899} 4900 4901let usesCustomInserter = 1, Defs = [CPSR] in { 4902 def COPY_STRUCT_BYVAL_I32 : PseudoInst< 4903 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment), 4904 NoItinerary, 4905 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>; 4906} 4907 4908let hasPostISelHook = 1, Constraints = "$newdst = $dst, $newsrc = $src" in { 4909 // %newsrc, %newdst = MEMCPY %dst, %src, N, ...N scratch regs... 4910 // Copies N registers worth of memory from address %src to address %dst 4911 // and returns the incremented addresses. N scratch register will 4912 // be attached for the copy to use. 4913 def MEMCPY : PseudoInst< 4914 (outs GPR:$newdst, GPR:$newsrc), 4915 (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops), 4916 NoItinerary, 4917 [(set GPR:$newdst, GPR:$newsrc, 4918 (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>; 4919} 4920 4921def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4922 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4923}]>; 4924 4925def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4926 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4927}]>; 4928 4929def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4930 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4931}]>; 4932 4933def strex_1 : PatFrag<(ops node:$val, node:$ptr), 4934 (int_arm_strex node:$val, node:$ptr), [{ 4935 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4936}]>; 4937 4938def strex_2 : PatFrag<(ops node:$val, node:$ptr), 4939 (int_arm_strex node:$val, node:$ptr), [{ 4940 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4941}]>; 4942 4943def strex_4 : PatFrag<(ops node:$val, node:$ptr), 4944 (int_arm_strex node:$val, node:$ptr), [{ 4945 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4946}]>; 4947 4948def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4949 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4950}]>; 4951 4952def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4953 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4954}]>; 4955 4956def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4957 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4958}]>; 4959 4960def stlex_1 : PatFrag<(ops node:$val, node:$ptr), 4961 (int_arm_stlex node:$val, node:$ptr), [{ 4962 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4963}]>; 4964 4965def stlex_2 : PatFrag<(ops node:$val, node:$ptr), 4966 (int_arm_stlex node:$val, node:$ptr), [{ 4967 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4968}]>; 4969 4970def stlex_4 : PatFrag<(ops node:$val, node:$ptr), 4971 (int_arm_stlex node:$val, node:$ptr), [{ 4972 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4973}]>; 4974 4975let mayLoad = 1 in { 4976def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4977 NoItinerary, "ldrexb", "\t$Rt, $addr", 4978 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>; 4979def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4980 NoItinerary, "ldrexh", "\t$Rt, $addr", 4981 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>; 4982def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4983 NoItinerary, "ldrex", "\t$Rt, $addr", 4984 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>; 4985let hasExtraDefRegAllocReq = 1 in 4986def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 4987 NoItinerary, "ldrexd", "\t$Rt, $addr", []> { 4988 let DecoderMethod = "DecodeDoubleRegLoad"; 4989} 4990 4991def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4992 NoItinerary, "ldaexb", "\t$Rt, $addr", 4993 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>; 4994def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4995 NoItinerary, "ldaexh", "\t$Rt, $addr", 4996 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>; 4997def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4998 NoItinerary, "ldaex", "\t$Rt, $addr", 4999 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>; 5000let hasExtraDefRegAllocReq = 1 in 5001def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 5002 NoItinerary, "ldaexd", "\t$Rt, $addr", []> { 5003 let DecoderMethod = "DecodeDoubleRegLoad"; 5004} 5005} 5006 5007let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 5008def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5009 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", 5010 [(set GPR:$Rd, (strex_1 GPR:$Rt, 5011 addr_offset_none:$addr))]>; 5012def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5013 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", 5014 [(set GPR:$Rd, (strex_2 GPR:$Rt, 5015 addr_offset_none:$addr))]>; 5016def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5017 NoItinerary, "strex", "\t$Rd, $Rt, $addr", 5018 [(set GPR:$Rd, (strex_4 GPR:$Rt, 5019 addr_offset_none:$addr))]>; 5020let hasExtraSrcRegAllocReq = 1 in 5021def STREXD : AIstrex<0b01, (outs GPR:$Rd), 5022 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 5023 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> { 5024 let DecoderMethod = "DecodeDoubleRegStore"; 5025} 5026def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5027 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr", 5028 [(set GPR:$Rd, 5029 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>; 5030def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5031 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr", 5032 [(set GPR:$Rd, 5033 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>; 5034def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5035 NoItinerary, "stlex", "\t$Rd, $Rt, $addr", 5036 [(set GPR:$Rd, 5037 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>; 5038let hasExtraSrcRegAllocReq = 1 in 5039def STLEXD : AIstlex<0b01, (outs GPR:$Rd), 5040 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 5041 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> { 5042 let DecoderMethod = "DecodeDoubleRegStore"; 5043} 5044} 5045 5046def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", 5047 [(int_arm_clrex)]>, 5048 Requires<[IsARM, HasV6K]> { 5049 let Inst{31-0} = 0b11110101011111111111000000011111; 5050} 5051 5052def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 5053 (STREXB GPR:$Rt, addr_offset_none:$addr)>; 5054def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 5055 (STREXH GPR:$Rt, addr_offset_none:$addr)>; 5056 5057def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 5058 (STLEXB GPR:$Rt, addr_offset_none:$addr)>; 5059def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 5060 (STLEXH GPR:$Rt, addr_offset_none:$addr)>; 5061 5062class acquiring_load<PatFrag base> 5063 : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 5064 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 5065 return isAcquireOrStronger(Ordering); 5066}]>; 5067 5068def atomic_load_acquire_8 : acquiring_load<atomic_load_8>; 5069def atomic_load_acquire_16 : acquiring_load<atomic_load_16>; 5070def atomic_load_acquire_32 : acquiring_load<atomic_load_32>; 5071 5072class releasing_store<PatFrag base> 5073 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 5074 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 5075 return isReleaseOrStronger(Ordering); 5076}]>; 5077 5078def atomic_store_release_8 : releasing_store<atomic_store_8>; 5079def atomic_store_release_16 : releasing_store<atomic_store_16>; 5080def atomic_store_release_32 : releasing_store<atomic_store_32>; 5081 5082let AddedComplexity = 8 in { 5083 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>; 5084 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>; 5085 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>; 5086 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>; 5087 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>; 5088 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>; 5089} 5090 5091// SWP/SWPB are deprecated in V6/V7 and optional in v7VE. 5092// FIXME Use InstAlias to generate LDREX/STREX pairs instead. 5093let mayLoad = 1, mayStore = 1 in { 5094def SWP : AIswp<0, (outs GPRnopc:$Rt), 5095 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>, 5096 Requires<[IsARM,PreV8]>; 5097def SWPB: AIswp<1, (outs GPRnopc:$Rt), 5098 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>, 5099 Requires<[IsARM,PreV8]>; 5100} 5101 5102//===----------------------------------------------------------------------===// 5103// Coprocessor Instructions. 5104// 5105 5106def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5107 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5108 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5109 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 5110 imm:$CRm, imm:$opc2)]>, 5111 Requires<[IsARM,PreV8]> { 5112 bits<4> opc1; 5113 bits<4> CRn; 5114 bits<4> CRd; 5115 bits<4> cop; 5116 bits<3> opc2; 5117 bits<4> CRm; 5118 5119 let Inst{3-0} = CRm; 5120 let Inst{4} = 0; 5121 let Inst{7-5} = opc2; 5122 let Inst{11-8} = cop; 5123 let Inst{15-12} = CRd; 5124 let Inst{19-16} = CRn; 5125 let Inst{23-20} = opc1; 5126 5127 let DecoderNamespace = "CoProc"; 5128} 5129 5130def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5131 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5132 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5133 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 5134 imm:$CRm, imm:$opc2)]>, 5135 Requires<[IsARM,PreV8]> { 5136 let Inst{31-28} = 0b1111; 5137 bits<4> opc1; 5138 bits<4> CRn; 5139 bits<4> CRd; 5140 bits<4> cop; 5141 bits<3> opc2; 5142 bits<4> CRm; 5143 5144 let Inst{3-0} = CRm; 5145 let Inst{4} = 0; 5146 let Inst{7-5} = opc2; 5147 let Inst{11-8} = cop; 5148 let Inst{15-12} = CRd; 5149 let Inst{19-16} = CRn; 5150 let Inst{23-20} = opc1; 5151 5152 let DecoderNamespace = "CoProc"; 5153} 5154 5155class ACI<dag oops, dag iops, string opc, string asm, 5156 list<dag> pattern, IndexMode im = IndexModeNone> 5157 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 5158 opc, asm, "", pattern> { 5159 let Inst{27-25} = 0b110; 5160} 5161class ACInoP<dag oops, dag iops, string opc, string asm, 5162 list<dag> pattern, IndexMode im = IndexModeNone> 5163 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 5164 opc, asm, "", pattern> { 5165 let Inst{31-28} = 0b1111; 5166 let Inst{27-25} = 0b110; 5167} 5168 5169let DecoderNamespace = "CoProc" in { 5170multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> { 5171 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 5172 asm, "\t$cop, $CRd, $addr", pattern> { 5173 bits<13> addr; 5174 bits<4> cop; 5175 bits<4> CRd; 5176 let Inst{24} = 1; // P = 1 5177 let Inst{23} = addr{8}; 5178 let Inst{22} = Dbit; 5179 let Inst{21} = 0; // W = 0 5180 let Inst{20} = load; 5181 let Inst{19-16} = addr{12-9}; 5182 let Inst{15-12} = CRd; 5183 let Inst{11-8} = cop; 5184 let Inst{7-0} = addr{7-0}; 5185 let DecoderMethod = "DecodeCopMemInstruction"; 5186 } 5187 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 5188 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { 5189 bits<13> addr; 5190 bits<4> cop; 5191 bits<4> CRd; 5192 let Inst{24} = 1; // P = 1 5193 let Inst{23} = addr{8}; 5194 let Inst{22} = Dbit; 5195 let Inst{21} = 1; // W = 1 5196 let Inst{20} = load; 5197 let Inst{19-16} = addr{12-9}; 5198 let Inst{15-12} = CRd; 5199 let Inst{11-8} = cop; 5200 let Inst{7-0} = addr{7-0}; 5201 let DecoderMethod = "DecodeCopMemInstruction"; 5202 } 5203 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5204 postidx_imm8s4:$offset), 5205 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { 5206 bits<9> offset; 5207 bits<4> addr; 5208 bits<4> cop; 5209 bits<4> CRd; 5210 let Inst{24} = 0; // P = 0 5211 let Inst{23} = offset{8}; 5212 let Inst{22} = Dbit; 5213 let Inst{21} = 1; // W = 1 5214 let Inst{20} = load; 5215 let Inst{19-16} = addr; 5216 let Inst{15-12} = CRd; 5217 let Inst{11-8} = cop; 5218 let Inst{7-0} = offset{7-0}; 5219 let DecoderMethod = "DecodeCopMemInstruction"; 5220 } 5221 def _OPTION : ACI<(outs), 5222 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5223 coproc_option_imm:$option), 5224 asm, "\t$cop, $CRd, $addr, $option", []> { 5225 bits<8> option; 5226 bits<4> addr; 5227 bits<4> cop; 5228 bits<4> CRd; 5229 let Inst{24} = 0; // P = 0 5230 let Inst{23} = 1; // U = 1 5231 let Inst{22} = Dbit; 5232 let Inst{21} = 0; // W = 0 5233 let Inst{20} = load; 5234 let Inst{19-16} = addr; 5235 let Inst{15-12} = CRd; 5236 let Inst{11-8} = cop; 5237 let Inst{7-0} = option; 5238 let DecoderMethod = "DecodeCopMemInstruction"; 5239 } 5240} 5241multiclass LdSt2Cop<bit load, bit Dbit, string asm, list<dag> pattern> { 5242 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 5243 asm, "\t$cop, $CRd, $addr", pattern> { 5244 bits<13> addr; 5245 bits<4> cop; 5246 bits<4> CRd; 5247 let Inst{24} = 1; // P = 1 5248 let Inst{23} = addr{8}; 5249 let Inst{22} = Dbit; 5250 let Inst{21} = 0; // W = 0 5251 let Inst{20} = load; 5252 let Inst{19-16} = addr{12-9}; 5253 let Inst{15-12} = CRd; 5254 let Inst{11-8} = cop; 5255 let Inst{7-0} = addr{7-0}; 5256 let DecoderMethod = "DecodeCopMemInstruction"; 5257 } 5258 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 5259 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { 5260 bits<13> addr; 5261 bits<4> cop; 5262 bits<4> CRd; 5263 let Inst{24} = 1; // P = 1 5264 let Inst{23} = addr{8}; 5265 let Inst{22} = Dbit; 5266 let Inst{21} = 1; // W = 1 5267 let Inst{20} = load; 5268 let Inst{19-16} = addr{12-9}; 5269 let Inst{15-12} = CRd; 5270 let Inst{11-8} = cop; 5271 let Inst{7-0} = addr{7-0}; 5272 let DecoderMethod = "DecodeCopMemInstruction"; 5273 } 5274 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5275 postidx_imm8s4:$offset), 5276 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { 5277 bits<9> offset; 5278 bits<4> addr; 5279 bits<4> cop; 5280 bits<4> CRd; 5281 let Inst{24} = 0; // P = 0 5282 let Inst{23} = offset{8}; 5283 let Inst{22} = Dbit; 5284 let Inst{21} = 1; // W = 1 5285 let Inst{20} = load; 5286 let Inst{19-16} = addr; 5287 let Inst{15-12} = CRd; 5288 let Inst{11-8} = cop; 5289 let Inst{7-0} = offset{7-0}; 5290 let DecoderMethod = "DecodeCopMemInstruction"; 5291 } 5292 def _OPTION : ACInoP<(outs), 5293 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5294 coproc_option_imm:$option), 5295 asm, "\t$cop, $CRd, $addr, $option", []> { 5296 bits<8> option; 5297 bits<4> addr; 5298 bits<4> cop; 5299 bits<4> CRd; 5300 let Inst{24} = 0; // P = 0 5301 let Inst{23} = 1; // U = 1 5302 let Inst{22} = Dbit; 5303 let Inst{21} = 0; // W = 0 5304 let Inst{20} = load; 5305 let Inst{19-16} = addr; 5306 let Inst{15-12} = CRd; 5307 let Inst{11-8} = cop; 5308 let Inst{7-0} = option; 5309 let DecoderMethod = "DecodeCopMemInstruction"; 5310 } 5311} 5312 5313defm LDC : LdStCop <1, 0, "ldc", [(int_arm_ldc imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5314defm LDCL : LdStCop <1, 1, "ldcl", [(int_arm_ldcl imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5315defm LDC2 : LdSt2Cop<1, 0, "ldc2", [(int_arm_ldc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5316defm LDC2L : LdSt2Cop<1, 1, "ldc2l", [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5317 5318defm STC : LdStCop <0, 0, "stc", [(int_arm_stc imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5319defm STCL : LdStCop <0, 1, "stcl", [(int_arm_stcl imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5320defm STC2 : LdSt2Cop<0, 0, "stc2", [(int_arm_stc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5321defm STC2L : LdSt2Cop<0, 1, "stc2l", [(int_arm_stc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5322 5323} // DecoderNamespace = "CoProc" 5324 5325//===----------------------------------------------------------------------===// 5326// Move between coprocessor and ARM core register. 5327// 5328 5329class MovRCopro<string opc, bit direction, dag oops, dag iops, 5330 list<dag> pattern> 5331 : ABI<0b1110, oops, iops, NoItinerary, opc, 5332 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> { 5333 let Inst{20} = direction; 5334 let Inst{4} = 1; 5335 5336 bits<4> Rt; 5337 bits<4> cop; 5338 bits<3> opc1; 5339 bits<3> opc2; 5340 bits<4> CRm; 5341 bits<4> CRn; 5342 5343 let Inst{15-12} = Rt; 5344 let Inst{11-8} = cop; 5345 let Inst{23-21} = opc1; 5346 let Inst{7-5} = opc2; 5347 let Inst{3-0} = CRm; 5348 let Inst{19-16} = CRn; 5349 5350 let DecoderNamespace = "CoProc"; 5351} 5352 5353def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */, 5354 (outs), 5355 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5356 c_imm:$CRm, imm0_7:$opc2), 5357 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 5358 imm:$CRm, imm:$opc2)]>, 5359 ComplexDeprecationPredicate<"MCR">; 5360def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 5361 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5362 c_imm:$CRm, 0, pred:$p)>; 5363def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, 5364 (outs GPRwithAPSR:$Rt), 5365 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5366 imm0_7:$opc2), []>; 5367def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", 5368 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5369 c_imm:$CRm, 0, pred:$p)>; 5370 5371def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 5372 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 5373 5374class MovRCopro2<string opc, bit direction, dag oops, dag iops, 5375 list<dag> pattern> 5376 : ABXI<0b1110, oops, iops, NoItinerary, 5377 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> { 5378 let Inst{31-24} = 0b11111110; 5379 let Inst{20} = direction; 5380 let Inst{4} = 1; 5381 5382 bits<4> Rt; 5383 bits<4> cop; 5384 bits<3> opc1; 5385 bits<3> opc2; 5386 bits<4> CRm; 5387 bits<4> CRn; 5388 5389 let Inst{15-12} = Rt; 5390 let Inst{11-8} = cop; 5391 let Inst{23-21} = opc1; 5392 let Inst{7-5} = opc2; 5393 let Inst{3-0} = CRm; 5394 let Inst{19-16} = CRn; 5395 5396 let DecoderNamespace = "CoProc"; 5397} 5398 5399def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */, 5400 (outs), 5401 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5402 c_imm:$CRm, imm0_7:$opc2), 5403 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 5404 imm:$CRm, imm:$opc2)]>, 5405 Requires<[IsARM,PreV8]>; 5406def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm", 5407 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5408 c_imm:$CRm, 0)>; 5409def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, 5410 (outs GPRwithAPSR:$Rt), 5411 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5412 imm0_7:$opc2), []>, 5413 Requires<[IsARM,PreV8]>; 5414def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm", 5415 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5416 c_imm:$CRm, 0)>; 5417 5418def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, 5419 imm:$CRm, imm:$opc2), 5420 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 5421 5422class MovRRCopro<string opc, bit direction, dag oops, dag iops, list<dag> 5423 pattern = []> 5424 : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", 5425 pattern> { 5426 5427 let Inst{23-21} = 0b010; 5428 let Inst{20} = direction; 5429 5430 bits<4> Rt; 5431 bits<4> Rt2; 5432 bits<4> cop; 5433 bits<4> opc1; 5434 bits<4> CRm; 5435 5436 let Inst{15-12} = Rt; 5437 let Inst{19-16} = Rt2; 5438 let Inst{11-8} = cop; 5439 let Inst{7-4} = opc1; 5440 let Inst{3-0} = CRm; 5441} 5442 5443def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */, 5444 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5445 GPRnopc:$Rt2, c_imm:$CRm), 5446 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt, 5447 GPRnopc:$Rt2, imm:$CRm)]>; 5448def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */, 5449 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5450 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5451 5452class MovRRCopro2<string opc, bit direction, dag oops, dag iops, 5453 list<dag> pattern = []> 5454 : ABXI<0b1100, oops, iops, NoItinerary, 5455 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>, 5456 Requires<[IsARM,PreV8]> { 5457 let Inst{31-28} = 0b1111; 5458 let Inst{23-21} = 0b010; 5459 let Inst{20} = direction; 5460 5461 bits<4> Rt; 5462 bits<4> Rt2; 5463 bits<4> cop; 5464 bits<4> opc1; 5465 bits<4> CRm; 5466 5467 let Inst{15-12} = Rt; 5468 let Inst{19-16} = Rt2; 5469 let Inst{11-8} = cop; 5470 let Inst{7-4} = opc1; 5471 let Inst{3-0} = CRm; 5472 5473 let DecoderMethod = "DecoderForMRRC2AndMCRR2"; 5474} 5475 5476def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */, 5477 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5478 GPRnopc:$Rt2, c_imm:$CRm), 5479 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt, 5480 GPRnopc:$Rt2, imm:$CRm)]>; 5481 5482def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */, 5483 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5484 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5485 5486//===----------------------------------------------------------------------===// 5487// Move between special register and ARM core register 5488// 5489 5490// Move to ARM core register from Special Register 5491def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5492 "mrs", "\t$Rd, apsr", []> { 5493 bits<4> Rd; 5494 let Inst{23-16} = 0b00001111; 5495 let Unpredictable{19-17} = 0b111; 5496 5497 let Inst{15-12} = Rd; 5498 5499 let Inst{11-0} = 0b000000000000; 5500 let Unpredictable{11-0} = 0b110100001111; 5501} 5502 5503def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p), 0>, 5504 Requires<[IsARM]>; 5505 5506// The MRSsys instruction is the MRS instruction from the ARM ARM, 5507// section B9.3.9, with the R bit set to 1. 5508def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5509 "mrs", "\t$Rd, spsr", []> { 5510 bits<4> Rd; 5511 let Inst{23-16} = 0b01001111; 5512 let Unpredictable{19-16} = 0b1111; 5513 5514 let Inst{15-12} = Rd; 5515 5516 let Inst{11-0} = 0b000000000000; 5517 let Unpredictable{11-0} = 0b110100001111; 5518} 5519 5520// However, the MRS (banked register) system instruction (ARMv7VE) *does* have a 5521// separate encoding (distinguished by bit 5. 5522def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked), 5523 NoItinerary, "mrs", "\t$Rd, $banked", []>, 5524 Requires<[IsARM, HasVirtualization]> { 5525 bits<6> banked; 5526 bits<4> Rd; 5527 5528 let Inst{23} = 0; 5529 let Inst{22} = banked{5}; // R bit 5530 let Inst{21-20} = 0b00; 5531 let Inst{19-16} = banked{3-0}; 5532 let Inst{15-12} = Rd; 5533 let Inst{11-9} = 0b001; 5534 let Inst{8} = banked{4}; 5535 let Inst{7-0} = 0b00000000; 5536} 5537 5538// Move from ARM core register to Special Register 5539// 5540// No need to have both system and application versions of MSR (immediate) or 5541// MSR (register), the encodings are the same and the assembly parser has no way 5542// to distinguish between them. The mask operand contains the special register 5543// (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be 5544// accessed in the special register. 5545let Defs = [CPSR] in 5546def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, 5547 "msr", "\t$mask, $Rn", []> { 5548 bits<5> mask; 5549 bits<4> Rn; 5550 5551 let Inst{23} = 0; 5552 let Inst{22} = mask{4}; // R bit 5553 let Inst{21-20} = 0b10; 5554 let Inst{19-16} = mask{3-0}; 5555 let Inst{15-12} = 0b1111; 5556 let Inst{11-4} = 0b00000000; 5557 let Inst{3-0} = Rn; 5558} 5559 5560let Defs = [CPSR] in 5561def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary, 5562 "msr", "\t$mask, $imm", []> { 5563 bits<5> mask; 5564 bits<12> imm; 5565 5566 let Inst{23} = 0; 5567 let Inst{22} = mask{4}; // R bit 5568 let Inst{21-20} = 0b10; 5569 let Inst{19-16} = mask{3-0}; 5570 let Inst{15-12} = 0b1111; 5571 let Inst{11-0} = imm; 5572} 5573 5574// However, the MSR (banked register) system instruction (ARMv7VE) *does* have a 5575// separate encoding (distinguished by bit 5. 5576def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn), 5577 NoItinerary, "msr", "\t$banked, $Rn", []>, 5578 Requires<[IsARM, HasVirtualization]> { 5579 bits<6> banked; 5580 bits<4> Rn; 5581 5582 let Inst{23} = 0; 5583 let Inst{22} = banked{5}; // R bit 5584 let Inst{21-20} = 0b10; 5585 let Inst{19-16} = banked{3-0}; 5586 let Inst{15-12} = 0b1111; 5587 let Inst{11-9} = 0b001; 5588 let Inst{8} = banked{4}; 5589 let Inst{7-4} = 0b0000; 5590 let Inst{3-0} = Rn; 5591} 5592 5593// Dynamic stack allocation yields a _chkstk for Windows targets. These calls 5594// are needed to probe the stack when allocating more than 5595// 4k bytes in one go. Touching the stack at 4K increments is necessary to 5596// ensure that the guard pages used by the OS virtual memory manager are 5597// allocated in correct sequence. 5598// The main point of having separate instruction are extra unmodelled effects 5599// (compared to ordinary calls) like stack pointer change. 5600 5601def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone, 5602 [SDNPHasChain, SDNPSideEffect]>; 5603let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in 5604 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>; 5605 5606def win__dbzchk : SDNode<"ARMISD::WIN__DBZCHK", SDT_WIN__DBZCHK, 5607 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 5608let usesCustomInserter = 1, Defs = [CPSR] in 5609 def WIN__DBZCHK : PseudoInst<(outs), (ins tGPR:$divisor), NoItinerary, 5610 [(win__dbzchk tGPR:$divisor)]>; 5611 5612//===----------------------------------------------------------------------===// 5613// TLS Instructions 5614// 5615 5616// __aeabi_read_tp preserves the registers r1-r3. 5617// This is a pseudo inst so that we can get the encoding right, 5618// complete with fixup for the aeabi_read_tp function. 5619// TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern 5620// is defined in "ARMInstrThumb.td". 5621let isCall = 1, 5622 Defs = [R0, R12, LR, CPSR], Uses = [SP] in { 5623 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br, 5624 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>, 5625 Requires<[IsARM, IsReadTPSoft]>; 5626} 5627 5628// Reading thread pointer from coprocessor register 5629def : ARMPat<(ARMthread_pointer), (MRC 15, 0, 13, 0, 3)>, 5630 Requires<[IsARM, IsReadTPHard]>; 5631 5632//===----------------------------------------------------------------------===// 5633// SJLJ Exception handling intrinsics 5634// eh_sjlj_setjmp() is an instruction sequence to store the return 5635// address and save #0 in R0 for the non-longjmp case. 5636// Since by its nature we may be coming from some other function to get 5637// here, and we're using the stack frame for the containing function to 5638// save/restore registers, we can't keep anything live in regs across 5639// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 5640// when we get here from a longjmp(). We force everything out of registers 5641// except for our own input by listing the relevant registers in Defs. By 5642// doing so, we also cause the prologue/epilogue code to actively preserve 5643// all of the callee-saved resgisters, which is exactly what we want. 5644// A constant value is passed in $val, and we use the location as a scratch. 5645// 5646// These are pseudo-instructions and are lowered to individual MC-insts, so 5647// no encoding information is necessary. 5648let Defs = 5649 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 5650 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ], 5651 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5652 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5653 NoItinerary, 5654 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5655 Requires<[IsARM, HasVFP2]>; 5656} 5657 5658let Defs = 5659 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 5660 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5661 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5662 NoItinerary, 5663 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5664 Requires<[IsARM, NoVFP]>; 5665} 5666 5667// FIXME: Non-IOS version(s) 5668let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, 5669 Defs = [ R7, LR, SP ] in { 5670def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch), 5671 NoItinerary, 5672 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 5673 Requires<[IsARM]>; 5674} 5675 5676let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in 5677def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary, 5678 [(ARMeh_sjlj_setup_dispatch)]>; 5679 5680// eh.sjlj.dispatchsetup pseudo-instruction. 5681// This pseudo is used for both ARM and Thumb. Any differences are handled when 5682// the pseudo is expanded (which happens before any passes that need the 5683// instruction size). 5684let isBarrier = 1 in 5685def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>; 5686 5687 5688//===----------------------------------------------------------------------===// 5689// Non-Instruction Patterns 5690// 5691 5692// ARMv4 indirect branch using (MOVr PC, dst) 5693let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in 5694 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst), 5695 4, IIC_Br, [(brind GPR:$dst)], 5696 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5697 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5698 5699let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in 5700 def TAILJMPr4 : ARMPseudoExpand<(outs), (ins GPR:$dst), 5701 4, IIC_Br, [], 5702 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5703 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5704 5705// Large immediate handling. 5706 5707// 32-bit immediate using two piece mod_imms or movw + movt. 5708// This is a single pseudo instruction, the benefit is that it can be remat'd 5709// as a single unit instead of having to handle reg inputs. 5710// FIXME: Remove this when we can do generalized remat. 5711let isReMaterializable = 1, isMoveImm = 1 in 5712def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 5713 [(set GPR:$dst, (arm_i32imm:$src))]>, 5714 Requires<[IsARM]>; 5715 5716def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i, 5717 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>, 5718 Requires<[IsARM, DontUseMovt]>; 5719 5720// Pseudo instruction that combines movw + movt + add pc (if PIC). 5721// It also makes it possible to rematerialize the instructions. 5722// FIXME: Remove this when we can do generalized remat and when machine licm 5723// can properly the instructions. 5724let isReMaterializable = 1 in { 5725def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5726 IIC_iMOVix2addpc, 5727 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 5728 Requires<[IsARM, UseMovtInPic]>; 5729 5730def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5731 IIC_iLoadiALU, 5732 [(set GPR:$dst, 5733 (ARMWrapperPIC tglobaladdr:$addr))]>, 5734 Requires<[IsARM, DontUseMovtInPic]>; 5735 5736let AddedComplexity = 10 in 5737def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5738 NoItinerary, 5739 [(set GPR:$dst, 5740 (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5741 Requires<[IsARM, DontUseMovtInPic]>; 5742 5743let AddedComplexity = 10 in 5744def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5745 IIC_iMOVix2ld, 5746 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5747 Requires<[IsARM, UseMovtInPic]>; 5748} // isReMaterializable 5749 5750// The many different faces of TLS access. 5751def : ARMPat<(ARMWrapper tglobaltlsaddr :$dst), 5752 (MOVi32imm tglobaltlsaddr :$dst)>, 5753 Requires<[IsARM, UseMovt]>; 5754 5755def : Pat<(ARMWrapper tglobaltlsaddr:$src), 5756 (LDRLIT_ga_abs tglobaltlsaddr:$src)>, 5757 Requires<[IsARM, DontUseMovt]>; 5758 5759def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5760 (MOV_ga_pcrel tglobaltlsaddr:$addr)>, Requires<[IsARM, UseMovtInPic]>; 5761 5762def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5763 (LDRLIT_ga_pcrel tglobaltlsaddr:$addr)>, 5764 Requires<[IsARM, DontUseMovtInPic]>; 5765let AddedComplexity = 10 in 5766def : Pat<(load (ARMWrapperPIC tglobaltlsaddr:$addr)), 5767 (MOV_ga_pcrel_ldr tglobaltlsaddr:$addr)>, 5768 Requires<[IsARM, UseMovtInPic]>; 5769 5770 5771// ConstantPool, GlobalAddress, and JumpTable 5772def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 5773def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>, 5774 Requires<[IsARM, UseMovt]>; 5775def : ARMPat<(ARMWrapper texternalsym :$dst), (MOVi32imm texternalsym :$dst)>, 5776 Requires<[IsARM, UseMovt]>; 5777def : ARMPat<(ARMWrapperJT tjumptable:$dst), 5778 (LEApcrelJT tjumptable:$dst)>; 5779 5780// TODO: add,sub,and, 3-instr forms? 5781 5782// Tail calls. These patterns also apply to Thumb mode. 5783def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>; 5784def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>; 5785def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>; 5786 5787// Direct calls 5788def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; 5789def : ARMPat<(ARMcall_nolink texternalsym:$func), 5790 (BMOVPCB_CALL texternalsym:$func)>; 5791 5792// zextload i1 -> zextload i8 5793def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5794def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5795 5796// extload -> zextload 5797def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5798def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5799def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5800def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5801 5802def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 5803 5804def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; 5805def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; 5806 5807// smul* and smla* 5808def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 5809 (SMULBB GPR:$a, GPR:$b)>; 5810def : ARMV5TEPat<(mul sext_16_node:$a, (sext_bottom_16 GPR:$b)), 5811 (SMULBB GPR:$a, GPR:$b)>; 5812def : ARMV5TEPat<(mul sext_16_node:$a, (sext_top_16 GPR:$b)), 5813 (SMULBT GPR:$a, GPR:$b)>; 5814def : ARMV5TEPat<(mul (sext_top_16 GPR:$a), sext_16_node:$b), 5815 (SMULTB GPR:$a, GPR:$b)>; 5816def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, sext_16_node:$b)), 5817 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5818def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, (sext_bottom_16 GPR:$b))), 5819 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5820def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, (sext_top_16 GPR:$b))), 5821 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5822def : ARMV5MOPat<(add GPR:$acc, (mul (sext_top_16 GPR:$a), sext_16_node:$b)), 5823 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5824 5825def : ARMV5TEPat<(int_arm_smulbb GPR:$a, GPR:$b), 5826 (SMULBB GPR:$a, GPR:$b)>; 5827def : ARMV5TEPat<(int_arm_smulbt GPR:$a, GPR:$b), 5828 (SMULBT GPR:$a, GPR:$b)>; 5829def : ARMV5TEPat<(int_arm_smultb GPR:$a, GPR:$b), 5830 (SMULTB GPR:$a, GPR:$b)>; 5831def : ARMV5TEPat<(int_arm_smultt GPR:$a, GPR:$b), 5832 (SMULTT GPR:$a, GPR:$b)>; 5833def : ARMV5TEPat<(int_arm_smulwb GPR:$a, GPR:$b), 5834 (SMULWB GPR:$a, GPR:$b)>; 5835def : ARMV5TEPat<(int_arm_smulwt GPR:$a, GPR:$b), 5836 (SMULWT GPR:$a, GPR:$b)>; 5837 5838def : ARMV5TEPat<(int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc), 5839 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5840def : ARMV5TEPat<(int_arm_smlabt GPR:$a, GPR:$b, GPR:$acc), 5841 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5842def : ARMV5TEPat<(int_arm_smlatb GPR:$a, GPR:$b, GPR:$acc), 5843 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5844def : ARMV5TEPat<(int_arm_smlatt GPR:$a, GPR:$b, GPR:$acc), 5845 (SMLATT GPR:$a, GPR:$b, GPR:$acc)>; 5846def : ARMV5TEPat<(int_arm_smlawb GPR:$a, GPR:$b, GPR:$acc), 5847 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 5848def : ARMV5TEPat<(int_arm_smlawt GPR:$a, GPR:$b, GPR:$acc), 5849 (SMLAWT GPR:$a, GPR:$b, GPR:$acc)>; 5850 5851// Pre-v7 uses MCR for synchronization barriers. 5852def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>, 5853 Requires<[IsARM, HasV6]>; 5854 5855// SXT/UXT with no rotate 5856let AddedComplexity = 16 in { 5857def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>; 5858def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>; 5859def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>; 5860def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)), 5861 (UXTAB GPR:$Rn, GPR:$Rm, 0)>; 5862def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)), 5863 (UXTAH GPR:$Rn, GPR:$Rm, 0)>; 5864} 5865 5866def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>; 5867def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; 5868 5869def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)), 5870 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>; 5871def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)), 5872 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>; 5873 5874// Atomic load/store patterns 5875def : ARMPat<(atomic_load_8 ldst_so_reg:$src), 5876 (LDRBrs ldst_so_reg:$src)>; 5877def : ARMPat<(atomic_load_8 addrmode_imm12:$src), 5878 (LDRBi12 addrmode_imm12:$src)>; 5879def : ARMPat<(atomic_load_16 addrmode3:$src), 5880 (LDRH addrmode3:$src)>; 5881def : ARMPat<(atomic_load_32 ldst_so_reg:$src), 5882 (LDRrs ldst_so_reg:$src)>; 5883def : ARMPat<(atomic_load_32 addrmode_imm12:$src), 5884 (LDRi12 addrmode_imm12:$src)>; 5885def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val), 5886 (STRBrs GPR:$val, ldst_so_reg:$ptr)>; 5887def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val), 5888 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>; 5889def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val), 5890 (STRH GPR:$val, addrmode3:$ptr)>; 5891def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val), 5892 (STRrs GPR:$val, ldst_so_reg:$ptr)>; 5893def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val), 5894 (STRi12 GPR:$val, addrmode_imm12:$ptr)>; 5895 5896 5897//===----------------------------------------------------------------------===// 5898// Thumb Support 5899// 5900 5901include "ARMInstrThumb.td" 5902 5903//===----------------------------------------------------------------------===// 5904// Thumb2 Support 5905// 5906 5907include "ARMInstrThumb2.td" 5908 5909//===----------------------------------------------------------------------===// 5910// Floating Point Support 5911// 5912 5913include "ARMInstrVFP.td" 5914 5915//===----------------------------------------------------------------------===// 5916// Advanced SIMD (NEON) Support 5917// 5918 5919include "ARMInstrNEON.td" 5920 5921//===----------------------------------------------------------------------===// 5922// Assembler aliases 5923// 5924 5925// Memory barriers 5926def : InstAlias<"dmb", (DMB 0xf), 0>, Requires<[IsARM, HasDB]>; 5927def : InstAlias<"dsb", (DSB 0xf), 0>, Requires<[IsARM, HasDB]>; 5928def : InstAlias<"ssbb", (DSB 0x0), 1>, Requires<[IsARM, HasDB]>; 5929def : InstAlias<"pssbb", (DSB 0x4), 1>, Requires<[IsARM, HasDB]>; 5930def : InstAlias<"isb", (ISB 0xf), 0>, Requires<[IsARM, HasDB]>; 5931// Armv8-R 'Data Full Barrier' 5932def : InstAlias<"dfb", (DSB 0xc), 1>, Requires<[IsARM, HasDFB]>; 5933 5934// System instructions 5935def : MnemonicAlias<"swi", "svc">; 5936 5937// Load / Store Multiple 5938def : MnemonicAlias<"ldmfd", "ldm">; 5939def : MnemonicAlias<"ldmia", "ldm">; 5940def : MnemonicAlias<"ldmea", "ldmdb">; 5941def : MnemonicAlias<"stmfd", "stmdb">; 5942def : MnemonicAlias<"stmia", "stm">; 5943def : MnemonicAlias<"stmea", "stm">; 5944 5945// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the 5946// input operands swapped when the shift amount is zero (i.e., unspecified). 5947def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 5948 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p), 0>, 5949 Requires<[IsARM, HasV6]>; 5950def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 5951 (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p), 0>, 5952 Requires<[IsARM, HasV6]>; 5953 5954// PUSH/POP aliases for STM/LDM 5955def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>; 5956def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>; 5957 5958// SSAT/USAT optional shift operand. 5959def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 5960 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5961def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn", 5962 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5963 5964 5965// Extend instruction optional rotate operand. 5966def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm", 5967 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5968def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm", 5969 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5970def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 5971 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5972def : ARMInstAlias<"sxtb${p} $Rd, $Rm", 5973 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5974def : ARMInstAlias<"sxtb16${p} $Rd, $Rm", 5975 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5976def : ARMInstAlias<"sxth${p} $Rd, $Rm", 5977 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5978 5979def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm", 5980 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5981def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm", 5982 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5983def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 5984 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5985def : ARMInstAlias<"uxtb${p} $Rd, $Rm", 5986 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5987def : ARMInstAlias<"uxtb16${p} $Rd, $Rm", 5988 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5989def : ARMInstAlias<"uxth${p} $Rd, $Rm", 5990 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5991 5992 5993// RFE aliases 5994def : MnemonicAlias<"rfefa", "rfeda">; 5995def : MnemonicAlias<"rfeea", "rfedb">; 5996def : MnemonicAlias<"rfefd", "rfeia">; 5997def : MnemonicAlias<"rfeed", "rfeib">; 5998def : MnemonicAlias<"rfe", "rfeia">; 5999 6000// SRS aliases 6001def : MnemonicAlias<"srsfa", "srsib">; 6002def : MnemonicAlias<"srsea", "srsia">; 6003def : MnemonicAlias<"srsfd", "srsdb">; 6004def : MnemonicAlias<"srsed", "srsda">; 6005def : MnemonicAlias<"srs", "srsia">; 6006 6007// QSAX == QSUBADDX 6008def : MnemonicAlias<"qsubaddx", "qsax">; 6009// SASX == SADDSUBX 6010def : MnemonicAlias<"saddsubx", "sasx">; 6011// SHASX == SHADDSUBX 6012def : MnemonicAlias<"shaddsubx", "shasx">; 6013// SHSAX == SHSUBADDX 6014def : MnemonicAlias<"shsubaddx", "shsax">; 6015// SSAX == SSUBADDX 6016def : MnemonicAlias<"ssubaddx", "ssax">; 6017// UASX == UADDSUBX 6018def : MnemonicAlias<"uaddsubx", "uasx">; 6019// UHASX == UHADDSUBX 6020def : MnemonicAlias<"uhaddsubx", "uhasx">; 6021// UHSAX == UHSUBADDX 6022def : MnemonicAlias<"uhsubaddx", "uhsax">; 6023// UQASX == UQADDSUBX 6024def : MnemonicAlias<"uqaddsubx", "uqasx">; 6025// UQSAX == UQSUBADDX 6026def : MnemonicAlias<"uqsubaddx", "uqsax">; 6027// USAX == USUBADDX 6028def : MnemonicAlias<"usubaddx", "usax">; 6029 6030// "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like 6031// for isel. 6032def : ARMInstSubst<"mov${s}${p} $Rd, $imm", 6033 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6034def : ARMInstSubst<"mvn${s}${p} $Rd, $imm", 6035 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6036// Same for AND <--> BIC 6037def : ARMInstSubst<"bic${s}${p} $Rd, $Rn, $imm", 6038 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 6039 pred:$p, cc_out:$s)>; 6040def : ARMInstSubst<"bic${s}${p} $Rdn, $imm", 6041 (ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 6042 pred:$p, cc_out:$s)>; 6043def : ARMInstSubst<"and${s}${p} $Rd, $Rn, $imm", 6044 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 6045 pred:$p, cc_out:$s)>; 6046def : ARMInstSubst<"and${s}${p} $Rdn, $imm", 6047 (BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 6048 pred:$p, cc_out:$s)>; 6049 6050// Likewise, "add Rd, mod_imm_neg" -> sub 6051def : ARMInstSubst<"add${s}${p} $Rd, $Rn, $imm", 6052 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6053def : ARMInstSubst<"add${s}${p} $Rd, $imm", 6054 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6055// Likewise, "sub Rd, mod_imm_neg" -> add 6056def : ARMInstSubst<"sub${s}${p} $Rd, $Rn, $imm", 6057 (ADDri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6058def : ARMInstSubst<"sub${s}${p} $Rd, $imm", 6059 (ADDri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6060 6061 6062def : ARMInstSubst<"adc${s}${p} $Rd, $Rn, $imm", 6063 (SBCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6064def : ARMInstSubst<"adc${s}${p} $Rdn, $imm", 6065 (SBCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6066def : ARMInstSubst<"sbc${s}${p} $Rd, $Rn, $imm", 6067 (ADCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6068def : ARMInstSubst<"sbc${s}${p} $Rdn, $imm", 6069 (ADCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6070 6071// Same for CMP <--> CMN via mod_imm_neg 6072def : ARMInstSubst<"cmp${p} $Rd, $imm", 6073 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 6074def : ARMInstSubst<"cmn${p} $Rd, $imm", 6075 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 6076 6077// The shifter forms of the MOV instruction are aliased to the ASR, LSL, 6078// LSR, ROR, and RRX instructions. 6079// FIXME: We need C++ parser hooks to map the alias to the MOV 6080// encoding. It seems we should be able to do that sort of thing 6081// in tblgen, but it could get ugly. 6082let TwoOperandAliasConstraint = "$Rm = $Rd" in { 6083def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm", 6084 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 6085 cc_out:$s)>; 6086def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm", 6087 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 6088 cc_out:$s)>; 6089def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm", 6090 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 6091 cc_out:$s)>; 6092def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm", 6093 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 6094 cc_out:$s)>; 6095} 6096def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm", 6097 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>; 6098let TwoOperandAliasConstraint = "$Rn = $Rd" in { 6099def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm", 6100 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6101 cc_out:$s)>; 6102def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm", 6103 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6104 cc_out:$s)>; 6105def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm", 6106 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6107 cc_out:$s)>; 6108def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm", 6109 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6110 cc_out:$s)>; 6111} 6112 6113// "neg" is and alias for "rsb rd, rn, #0" 6114def : ARMInstAlias<"neg${s}${p} $Rd, $Rm", 6115 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>; 6116 6117// Pre-v6, 'mov r0, r0' was used as a NOP encoding. 6118def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>, 6119 Requires<[IsARM, NoV6]>; 6120 6121// MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but 6122// the instruction definitions need difference constraints pre-v6. 6123// Use these aliases for the assembly parsing on pre-v6. 6124def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm", 6125 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s), 0>, 6126 Requires<[IsARM, NoV6]>; 6127def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra", 6128 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 6129 pred:$p, cc_out:$s), 0>, 6130 Requires<[IsARM, NoV6]>; 6131def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6132 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6133 Requires<[IsARM, NoV6]>; 6134def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6135 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6136 Requires<[IsARM, NoV6]>; 6137def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6138 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6139 Requires<[IsARM, NoV6]>; 6140def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6141 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6142 Requires<[IsARM, NoV6]>; 6143 6144// 'it' blocks in ARM mode just validate the predicates. The IT itself 6145// is discarded. 6146def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>, 6147 ComplexDeprecationPredicate<"IT">; 6148 6149let mayLoad = 1, mayStore =1, hasSideEffects = 1 in 6150def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn), 6151 NoItinerary, 6152 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>; 6153 6154//===---------------------------------- 6155// Atomic cmpxchg for -O0 6156//===---------------------------------- 6157 6158// The fast register allocator used during -O0 inserts spills to cover any VRegs 6159// live across basic block boundaries. When this happens between an LDXR and an 6160// STXR it can clear the exclusive monitor, causing all cmpxchg attempts to 6161// fail. 6162 6163// Unfortunately, this means we have to have an alternative (expanded 6164// post-regalloc) path for -O0 compilations. Fortunately this path can be 6165// significantly more naive than the standard expansion: we conservatively 6166// assume seq_cst, strong cmpxchg and omit clrex on failure. 6167 6168let Constraints = "@earlyclobber $Rd,@earlyclobber $temp", 6169 mayLoad = 1, mayStore = 1 in { 6170def CMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6171 (ins GPR:$addr, GPR:$desired, GPR:$new), 6172 NoItinerary, []>, Sched<[]>; 6173 6174def CMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6175 (ins GPR:$addr, GPR:$desired, GPR:$new), 6176 NoItinerary, []>, Sched<[]>; 6177 6178def CMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6179 (ins GPR:$addr, GPR:$desired, GPR:$new), 6180 NoItinerary, []>, Sched<[]>; 6181 6182def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$temp), 6183 (ins GPR:$addr, GPRPair:$desired, GPRPair:$new), 6184 NoItinerary, []>, Sched<[]>; 6185} 6186 6187def CompilerBarrier : PseudoInst<(outs), (ins i32imm:$ordering), NoItinerary, 6188 [(atomic_fence imm:$ordering, 0)]> { 6189 let hasSideEffects = 1; 6190 let Size = 0; 6191 let AsmString = "@ COMPILER BARRIER"; 6192} 6193