1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// ARM specific DAG Nodes. 16// 17 18// Type profiles. 19def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 20 SDTCisVT<1, i32> ]>; 21def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 22def SDT_ARMStructByVal : SDTypeProfile<0, 4, 23 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 24 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 25 26def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 27 28def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 29 30def SDT_ARMCMov : SDTypeProfile<1, 3, 31 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 32 SDTCisVT<3, i32>]>; 33 34def SDT_ARMBrcond : SDTypeProfile<0, 2, 35 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 36 37def SDT_ARMBrJT : SDTypeProfile<0, 2, 38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 39 40def SDT_ARMBr2JT : SDTypeProfile<0, 3, 41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 42 SDTCisVT<2, i32>]>; 43 44def SDT_ARMBCC_i64 : SDTypeProfile<0, 6, 45 [SDTCisVT<0, i32>, 46 SDTCisVT<1, i32>, SDTCisVT<2, i32>, 47 SDTCisVT<3, i32>, SDTCisVT<4, i32>, 48 SDTCisVT<5, OtherVT>]>; 49 50def SDT_ARMAnd : SDTypeProfile<1, 2, 51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 52 SDTCisVT<2, i32>]>; 53 54def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 55def SDT_ARMFCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, 56 SDTCisVT<2, i32>]>; 57 58def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 59 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 60 61def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 62def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, 63 SDTCisInt<2>]>; 64def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 65def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>; 66 67def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 68 69def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, 70 SDTCisInt<1>]>; 71 72def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 73 74def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 75 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 76 77def SDT_WIN__DBZCHK : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 78 79def SDT_ARMMEMCPY : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 80 SDTCisVT<2, i32>, SDTCisVT<3, i32>, 81 SDTCisVT<4, i32>]>; 82 83def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 84 [SDTCisSameAs<0, 2>, 85 SDTCisSameAs<0, 3>, 86 SDTCisInt<0>, SDTCisVT<1, i32>]>; 87 88// SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR 89def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 90 [SDTCisSameAs<0, 2>, 91 SDTCisSameAs<0, 3>, 92 SDTCisInt<0>, 93 SDTCisVT<1, i32>, 94 SDTCisVT<4, i32>]>; 95 96def SDT_LongMac : SDTypeProfile<2, 4, [SDTCisVT<0, i32>, 97 SDTCisSameAs<0, 1>, 98 SDTCisSameAs<0, 2>, 99 SDTCisSameAs<0, 3>, 100 SDTCisSameAs<0, 4>, 101 SDTCisSameAs<0, 5>]>; 102 103def ARMSmlald : SDNode<"ARMISD::SMLALD", SDT_LongMac>; 104def ARMSmlaldx : SDNode<"ARMISD::SMLALDX", SDT_LongMac>; 105def ARMSmlsld : SDNode<"ARMISD::SMLSLD", SDT_LongMac>; 106def ARMSmlsldx : SDNode<"ARMISD::SMLSLDX", SDT_LongMac>; 107 108def SDT_MulHSR : SDTypeProfile<1, 3, [SDTCisVT<0,i32>, 109 SDTCisSameAs<0, 1>, 110 SDTCisSameAs<0, 2>, 111 SDTCisSameAs<0, 3>]>; 112 113def ARMsmmlar : SDNode<"ARMISD::SMMLAR", SDT_MulHSR>; 114def ARMsmmlsr : SDNode<"ARMISD::SMMLSR", SDT_MulHSR>; 115 116// Node definitions. 117def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 118def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>; 119def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>; 120 121def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 122 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 123def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 124 [SDNPHasChain, SDNPSideEffect, 125 SDNPOptInGlue, SDNPOutGlue]>; 126def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" , 127 SDT_ARMStructByVal, 128 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 129 SDNPMayStore, SDNPMayLoad]>; 130 131def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 132 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 133 SDNPVariadic]>; 134def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 135 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 136 SDNPVariadic]>; 137def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 139 SDNPVariadic]>; 140 141def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, 142 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 143def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall, 144 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 145def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 146 [SDNPInGlue]>; 147def ARMsubs : SDNode<"ARMISD::SUBS", SDTIntBinOp, [SDNPOutGlue]>; 148 149def ARMssatnoshift : SDNode<"ARMISD::SSAT", SDTIntSatNoShOp, []>; 150 151def ARMusatnoshift : SDNode<"ARMISD::USAT", SDTIntSatNoShOp, []>; 152 153def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 154 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 155 156def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 157 [SDNPHasChain]>; 158def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, 159 [SDNPHasChain]>; 160 161def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64, 162 [SDNPHasChain]>; 163 164def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 165 [SDNPOutGlue]>; 166 167def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp, 168 [SDNPOutGlue]>; 169 170def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, 171 [SDNPOutGlue, SDNPCommutative]>; 172 173def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 174 175def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 176def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 177def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>; 178 179def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags, 180 [SDNPCommutative]>; 181def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>; 182def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>; 183def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>; 184 185def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 186def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", 187 SDT_ARMEH_SJLJ_Setjmp, 188 [SDNPHasChain, SDNPSideEffect]>; 189def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP", 190 SDT_ARMEH_SJLJ_Longjmp, 191 [SDNPHasChain, SDNPSideEffect]>; 192def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH", 193 SDT_ARMEH_SJLJ_SetupDispatch, 194 [SDNPHasChain, SDNPSideEffect]>; 195 196def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER, 197 [SDNPHasChain, SDNPSideEffect]>; 198def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH, 199 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 200 201def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET, 202 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 203 204def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; 205 206def ARMmemcopy : SDNode<"ARMISD::MEMCPY", SDT_ARMMEMCPY, 207 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 208 SDNPMayStore, SDNPMayLoad]>; 209 210def ARMsmulwb : SDNode<"ARMISD::SMULWB", SDTIntBinOp, []>; 211def ARMsmulwt : SDNode<"ARMISD::SMULWT", SDTIntBinOp, []>; 212def ARMsmlalbb : SDNode<"ARMISD::SMLALBB", SDT_LongMac, []>; 213def ARMsmlalbt : SDNode<"ARMISD::SMLALBT", SDT_LongMac, []>; 214def ARMsmlaltb : SDNode<"ARMISD::SMLALTB", SDT_LongMac, []>; 215def ARMsmlaltt : SDNode<"ARMISD::SMLALTT", SDT_LongMac, []>; 216 217//===----------------------------------------------------------------------===// 218// ARM Instruction Predicate Definitions. 219// 220def HasV4T : Predicate<"Subtarget->hasV4TOps()">, 221 AssemblerPredicate<"HasV4TOps", "armv4t">; 222def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; 223def HasV5T : Predicate<"Subtarget->hasV5TOps()">, 224 AssemblerPredicate<"HasV5TOps", "armv5t">; 225def NoV5T : Predicate<"!Subtarget->hasV5TOps()">; 226def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, 227 AssemblerPredicate<"HasV5TEOps", "armv5te">; 228def HasV6 : Predicate<"Subtarget->hasV6Ops()">, 229 AssemblerPredicate<"HasV6Ops", "armv6">; 230def NoV6 : Predicate<"!Subtarget->hasV6Ops()">; 231def HasV6M : Predicate<"Subtarget->hasV6MOps()">, 232 AssemblerPredicate<"HasV6MOps", 233 "armv6m or armv6t2">; 234def HasV8MBaseline : Predicate<"Subtarget->hasV8MBaselineOps()">, 235 AssemblerPredicate<"HasV8MBaselineOps", 236 "armv8m.base">; 237def HasV8MMainline : Predicate<"Subtarget->hasV8MMainlineOps()">, 238 AssemblerPredicate<"HasV8MMainlineOps", 239 "armv8m.main">; 240def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, 241 AssemblerPredicate<"HasV6T2Ops", "armv6t2">; 242def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; 243def HasV6K : Predicate<"Subtarget->hasV6KOps()">, 244 AssemblerPredicate<"HasV6KOps", "armv6k">; 245def NoV6K : Predicate<"!Subtarget->hasV6KOps()">; 246def HasV7 : Predicate<"Subtarget->hasV7Ops()">, 247 AssemblerPredicate<"HasV7Ops", "armv7">; 248def HasV8 : Predicate<"Subtarget->hasV8Ops()">, 249 AssemblerPredicate<"HasV8Ops", "armv8">; 250def PreV8 : Predicate<"!Subtarget->hasV8Ops()">, 251 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">; 252def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">, 253 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">; 254def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">, 255 AssemblerPredicate<"HasV8_2aOps", "armv8.2a">; 256def HasV8_3a : Predicate<"Subtarget->hasV8_3aOps()">, 257 AssemblerPredicate<"HasV8_3aOps", "armv8.3a">; 258def HasV8_4a : Predicate<"Subtarget->hasV8_4aOps()">, 259 AssemblerPredicate<"HasV8_4aOps", "armv8.4a">; 260def HasV8_5a : Predicate<"Subtarget->hasV8_5aOps()">, 261 AssemblerPredicate<"HasV8_5aOps", "armv8.5a">; 262def NoVFP : Predicate<"!Subtarget->hasVFP2()">; 263def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, 264 AssemblerPredicate<"FeatureVFP2", "VFP2">; 265def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, 266 AssemblerPredicate<"FeatureVFP3", "VFP3">; 267def HasVFP4 : Predicate<"Subtarget->hasVFP4()">, 268 AssemblerPredicate<"FeatureVFP4", "VFP4">; 269def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">, 270 AssemblerPredicate<"!FeatureVFPOnlySP", 271 "double precision VFP">; 272def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, 273 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">; 274def HasNEON : Predicate<"Subtarget->hasNEON()">, 275 AssemblerPredicate<"FeatureNEON", "NEON">; 276def HasSHA2 : Predicate<"Subtarget->hasSHA2()">, 277 AssemblerPredicate<"FeatureSHA2", "sha2">; 278def HasAES : Predicate<"Subtarget->hasAES()">, 279 AssemblerPredicate<"FeatureAES", "aes">; 280def HasCrypto : Predicate<"Subtarget->hasCrypto()">, 281 AssemblerPredicate<"FeatureCrypto", "crypto">; 282def HasDotProd : Predicate<"Subtarget->hasDotProd()">, 283 AssemblerPredicate<"FeatureDotProd", "dotprod">; 284def HasCRC : Predicate<"Subtarget->hasCRC()">, 285 AssemblerPredicate<"FeatureCRC", "crc">; 286def HasRAS : Predicate<"Subtarget->hasRAS()">, 287 AssemblerPredicate<"FeatureRAS", "ras">; 288def HasFP16 : Predicate<"Subtarget->hasFP16()">, 289 AssemblerPredicate<"FeatureFP16","half-float conversions">; 290def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">, 291 AssemblerPredicate<"FeatureFullFP16","full half-float">; 292def HasFP16FML : Predicate<"Subtarget->hasFP16FML()">, 293 AssemblerPredicate<"FeatureFP16FML","full half-float fml">; 294def HasDivideInThumb : Predicate<"Subtarget->hasDivideInThumbMode()">, 295 AssemblerPredicate<"FeatureHWDivThumb", "divide in THUMB">; 296def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">, 297 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">; 298def HasDSP : Predicate<"Subtarget->hasDSP()">, 299 AssemblerPredicate<"FeatureDSP", "dsp">; 300def HasDB : Predicate<"Subtarget->hasDataBarrier()">, 301 AssemblerPredicate<"FeatureDB", 302 "data-barriers">; 303def HasDFB : Predicate<"Subtarget->hasFullDataBarrier()">, 304 AssemblerPredicate<"FeatureDFB", 305 "full-data-barrier">; 306def HasV7Clrex : Predicate<"Subtarget->hasV7Clrex()">, 307 AssemblerPredicate<"FeatureV7Clrex", 308 "v7 clrex">; 309def HasAcquireRelease : Predicate<"Subtarget->hasAcquireRelease()">, 310 AssemblerPredicate<"FeatureAcquireRelease", 311 "acquire/release">; 312def HasMP : Predicate<"Subtarget->hasMPExtension()">, 313 AssemblerPredicate<"FeatureMP", 314 "mp-extensions">; 315def HasVirtualization: Predicate<"false">, 316 AssemblerPredicate<"FeatureVirtualization", 317 "virtualization-extensions">; 318def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">, 319 AssemblerPredicate<"FeatureTrustZone", 320 "TrustZone">; 321def Has8MSecExt : Predicate<"Subtarget->has8MSecExt()">, 322 AssemblerPredicate<"Feature8MSecExt", 323 "ARMv8-M Security Extensions">; 324def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">; 325def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; 326def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; 327def IsThumb : Predicate<"Subtarget->isThumb()">, 328 AssemblerPredicate<"ModeThumb", "thumb">; 329def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; 330def IsThumb2 : Predicate<"Subtarget->isThumb2()">, 331 AssemblerPredicate<"ModeThumb,FeatureThumb2", 332 "thumb2">; 333def IsMClass : Predicate<"Subtarget->isMClass()">, 334 AssemblerPredicate<"FeatureMClass", "armv*m">; 335def IsNotMClass : Predicate<"!Subtarget->isMClass()">, 336 AssemblerPredicate<"!FeatureMClass", 337 "!armv*m">; 338def IsARM : Predicate<"!Subtarget->isThumb()">, 339 AssemblerPredicate<"!ModeThumb", "arm-mode">; 340def IsMachO : Predicate<"Subtarget->isTargetMachO()">; 341def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">; 342def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 343def IsWindows : Predicate<"Subtarget->isTargetWindows()">; 344def IsNotWindows : Predicate<"!Subtarget->isTargetWindows()">; 345def IsReadTPHard : Predicate<"Subtarget->isReadTPHard()">; 346def IsReadTPSoft : Predicate<"!Subtarget->isReadTPHard()">; 347def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">, 348 AssemblerPredicate<"FeatureNaClTrap", "NaCl">; 349def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">; 350 351def UseNegativeImmediates : 352 Predicate<"false">, 353 AssemblerPredicate<"!FeatureNoNegativeImmediates", 354 "NegativeImmediates">; 355 356// FIXME: Eventually this will be just "hasV6T2Ops". 357let RecomputePerFunction = 1 in { 358 def UseMovt : Predicate<"Subtarget->useMovt(*MF)">; 359 def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">; 360 def UseMovtInPic : Predicate<"Subtarget->useMovt(*MF) && Subtarget->allowPositionIndependentMovt()">; 361 def DontUseMovtInPic : Predicate<"!Subtarget->useMovt(*MF) || !Subtarget->allowPositionIndependentMovt()">; 362 363 def UseFPVMLx: Predicate<"((Subtarget->useFPVMLx() &&" 364 " TM.Options.AllowFPOpFusion != FPOpFusion::Fast) ||" 365 "MF->getFunction().optForMinSize())">; 366} 367def UseMulOps : Predicate<"Subtarget->useMulOps()">; 368 369// Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available. 370// But only select them if more precision in FP computation is allowed, and when 371// they are not slower than a mul + add sequence. 372// Do not use them for Darwin platforms. 373def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion ==" 374 " FPOpFusion::Fast && " 375 " Subtarget->hasVFP4()) && " 376 "!Subtarget->isTargetDarwin() &&" 377 "Subtarget->useFPVMLx()">; 378 379def HasFastVGETLNi32 : Predicate<"!Subtarget->hasSlowVGETLNi32()">; 380def HasSlowVGETLNi32 : Predicate<"Subtarget->hasSlowVGETLNi32()">; 381 382def HasFastVDUP32 : Predicate<"!Subtarget->hasSlowVDUP32()">; 383def HasSlowVDUP32 : Predicate<"Subtarget->hasSlowVDUP32()">; 384 385def UseVMOVSR : Predicate<"Subtarget->preferVMOVSR() ||" 386 "!Subtarget->useNEONForSinglePrecisionFP()">; 387def DontUseVMOVSR : Predicate<"!Subtarget->preferVMOVSR() &&" 388 "Subtarget->useNEONForSinglePrecisionFP()">; 389 390let RecomputePerFunction = 1 in { 391 def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">; 392 def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">; 393} 394 395def GenExecuteOnly : Predicate<"Subtarget->genExecuteOnly()">; 396 397// Armv8.5-A extensions 398def HasSpecCtrl : Predicate<"Subtarget->hasSpecCtrl()">, 399 AssemblerPredicate<"FeatureSpecCtrl", "specctrl">; 400 401//===----------------------------------------------------------------------===// 402// ARM Flag Definitions. 403 404class RegConstraint<string C> { 405 string Constraints = C; 406} 407 408//===----------------------------------------------------------------------===// 409// ARM specific transformation functions and pattern fragments. 410// 411 412// imm_neg_XFORM - Return the negation of an i32 immediate value. 413def imm_neg_XFORM : SDNodeXForm<imm, [{ 414 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32); 415}]>; 416 417// imm_not_XFORM - Return the complement of a i32 immediate value. 418def imm_not_XFORM : SDNodeXForm<imm, [{ 419 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32); 420}]>; 421 422/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 423def imm16_31 : ImmLeaf<i32, [{ 424 return (int32_t)Imm >= 16 && (int32_t)Imm < 32; 425}]>; 426 427// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 428def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 429 if (CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17) 430 return true; 431 432 if (N->getOpcode() != ISD::SRA) 433 return false; 434 if (N->getOperand(0).getOpcode() != ISD::SHL) 435 return false; 436 437 auto *ShiftVal = dyn_cast<ConstantSDNode>(N->getOperand(1)); 438 if (!ShiftVal || ShiftVal->getZExtValue() != 16) 439 return false; 440 441 ShiftVal = dyn_cast<ConstantSDNode>(N->getOperand(0)->getOperand(1)); 442 if (!ShiftVal || ShiftVal->getZExtValue() != 16) 443 return false; 444 445 return true; 446}]>; 447 448/// Split a 32-bit immediate into two 16 bit parts. 449def hi16 : SDNodeXForm<imm, [{ 450 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N), 451 MVT::i32); 452}]>; 453 454def lo16AllZero : PatLeaf<(i32 imm), [{ 455 // Returns true if all low 16-bits are 0. 456 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 457}], hi16>; 458 459class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 460class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 461 462// An 'and' node with a single use. 463def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 464 return N->hasOneUse(); 465}]>; 466 467// An 'xor' node with a single use. 468def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{ 469 return N->hasOneUse(); 470}]>; 471 472// An 'fmul' node with a single use. 473def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{ 474 return N->hasOneUse(); 475}]>; 476 477// An 'fadd' node which checks for single non-hazardous use. 478def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{ 479 return hasNoVMLxHazardUse(N); 480}]>; 481 482// An 'fsub' node which checks for single non-hazardous use. 483def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{ 484 return hasNoVMLxHazardUse(N); 485}]>; 486 487//===----------------------------------------------------------------------===// 488// Operand Definitions. 489// 490 491// Immediate operands with a shared generic asm render method. 492class ImmAsmOperand<int Low, int High> : AsmOperandClass { 493 let RenderMethod = "addImmOperands"; 494 let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; 495 let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]"; 496} 497 498class ImmAsmOperandMinusOne<int Low, int High> : AsmOperandClass { 499 let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; 500 let DiagnosticType = "ImmRange" # Low # "_" # High; 501 let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]"; 502} 503 504// Operands that are part of a memory addressing mode. 505class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; } 506 507// Branch target. 508// FIXME: rename brtarget to t2_brtarget 509def brtarget : Operand<OtherVT> { 510 let EncoderMethod = "getBranchTargetOpValue"; 511 let OperandType = "OPERAND_PCREL"; 512 let DecoderMethod = "DecodeT2BROperand"; 513} 514 515// Branches targeting ARM-mode must be divisible by 4 if they're a raw 516// immediate. 517def ARMBranchTarget : AsmOperandClass { 518 let Name = "ARMBranchTarget"; 519} 520 521// Branches targeting Thumb-mode must be divisible by 2 if they're a raw 522// immediate. 523def ThumbBranchTarget : AsmOperandClass { 524 let Name = "ThumbBranchTarget"; 525} 526 527def arm_br_target : Operand<OtherVT> { 528 let ParserMatchClass = ARMBranchTarget; 529 let EncoderMethod = "getARMBranchTargetOpValue"; 530 let OperandType = "OPERAND_PCREL"; 531} 532 533// Call target for ARM. Handles conditional/unconditional 534// FIXME: rename bl_target to t2_bltarget? 535def arm_bl_target : Operand<i32> { 536 let ParserMatchClass = ARMBranchTarget; 537 let EncoderMethod = "getARMBLTargetOpValue"; 538 let OperandType = "OPERAND_PCREL"; 539} 540 541// Target for BLX *from* ARM mode. 542def arm_blx_target : Operand<i32> { 543 let ParserMatchClass = ThumbBranchTarget; 544 let EncoderMethod = "getARMBLXTargetOpValue"; 545 let OperandType = "OPERAND_PCREL"; 546} 547 548// A list of registers separated by comma. Used by load/store multiple. 549def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; } 550def reglist : Operand<i32> { 551 let EncoderMethod = "getRegisterListOpValue"; 552 let ParserMatchClass = RegListAsmOperand; 553 let PrintMethod = "printRegisterList"; 554 let DecoderMethod = "DecodeRegListOperand"; 555} 556 557def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">; 558 559def DPRRegListAsmOperand : AsmOperandClass { 560 let Name = "DPRRegList"; 561 let DiagnosticType = "DPR_RegList"; 562} 563def dpr_reglist : Operand<i32> { 564 let EncoderMethod = "getRegisterListOpValue"; 565 let ParserMatchClass = DPRRegListAsmOperand; 566 let PrintMethod = "printRegisterList"; 567 let DecoderMethod = "DecodeDPRRegListOperand"; 568} 569 570def SPRRegListAsmOperand : AsmOperandClass { 571 let Name = "SPRRegList"; 572 let DiagnosticString = "operand must be a list of registers in range [s0, s31]"; 573} 574def spr_reglist : Operand<i32> { 575 let EncoderMethod = "getRegisterListOpValue"; 576 let ParserMatchClass = SPRRegListAsmOperand; 577 let PrintMethod = "printRegisterList"; 578 let DecoderMethod = "DecodeSPRRegListOperand"; 579} 580 581// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 582def cpinst_operand : Operand<i32> { 583 let PrintMethod = "printCPInstOperand"; 584} 585 586// Local PC labels. 587def pclabel : Operand<i32> { 588 let PrintMethod = "printPCLabel"; 589} 590 591// ADR instruction labels. 592def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; } 593def adrlabel : Operand<i32> { 594 let EncoderMethod = "getAdrLabelOpValue"; 595 let ParserMatchClass = AdrLabelAsmOperand; 596 let PrintMethod = "printAdrLabelOperand<0>"; 597} 598 599def neon_vcvt_imm32 : Operand<i32> { 600 let EncoderMethod = "getNEONVcvtImm32OpValue"; 601 let DecoderMethod = "DecodeVCVTImmOperand"; 602} 603 604// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. 605def rot_imm_XFORM: SDNodeXForm<imm, [{ 606 switch (N->getZExtValue()){ 607 default: llvm_unreachable(nullptr); 608 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); 609 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32); 610 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32); 611 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32); 612 } 613}]>; 614def RotImmAsmOperand : AsmOperandClass { 615 let Name = "RotImm"; 616 let ParserMethod = "parseRotImm"; 617} 618def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{ 619 int32_t v = N->getZExtValue(); 620 return v == 8 || v == 16 || v == 24; }], 621 rot_imm_XFORM> { 622 let PrintMethod = "printRotImmOperand"; 623 let ParserMatchClass = RotImmAsmOperand; 624} 625 626// shift_imm: An integer that encodes a shift amount and the type of shift 627// (asr or lsl). The 6-bit immediate encodes as: 628// {5} 0 ==> lsl 629// 1 asr 630// {4-0} imm5 shift amount. 631// asr #32 encoded as imm5 == 0. 632def ShifterImmAsmOperand : AsmOperandClass { 633 let Name = "ShifterImm"; 634 let ParserMethod = "parseShifterImm"; 635} 636def shift_imm : Operand<i32> { 637 let PrintMethod = "printShiftImmOperand"; 638 let ParserMatchClass = ShifterImmAsmOperand; 639} 640 641// shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm. 642def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; } 643def so_reg_reg : Operand<i32>, // reg reg imm 644 ComplexPattern<i32, 3, "SelectRegShifterOperand", 645 [shl, srl, sra, rotr]> { 646 let EncoderMethod = "getSORegRegOpValue"; 647 let PrintMethod = "printSORegRegOperand"; 648 let DecoderMethod = "DecodeSORegRegOperand"; 649 let ParserMatchClass = ShiftedRegAsmOperand; 650 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm); 651} 652 653def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; } 654def so_reg_imm : Operand<i32>, // reg imm 655 ComplexPattern<i32, 2, "SelectImmShifterOperand", 656 [shl, srl, sra, rotr]> { 657 let EncoderMethod = "getSORegImmOpValue"; 658 let PrintMethod = "printSORegImmOperand"; 659 let DecoderMethod = "DecodeSORegImmOperand"; 660 let ParserMatchClass = ShiftedImmAsmOperand; 661 let MIOperandInfo = (ops GPR, i32imm); 662} 663 664// FIXME: Does this need to be distinct from so_reg? 665def shift_so_reg_reg : Operand<i32>, // reg reg imm 666 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand", 667 [shl,srl,sra,rotr]> { 668 let EncoderMethod = "getSORegRegOpValue"; 669 let PrintMethod = "printSORegRegOperand"; 670 let DecoderMethod = "DecodeSORegRegOperand"; 671 let ParserMatchClass = ShiftedRegAsmOperand; 672 let MIOperandInfo = (ops GPR, GPR, i32imm); 673} 674 675// FIXME: Does this need to be distinct from so_reg? 676def shift_so_reg_imm : Operand<i32>, // reg reg imm 677 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand", 678 [shl,srl,sra,rotr]> { 679 let EncoderMethod = "getSORegImmOpValue"; 680 let PrintMethod = "printSORegImmOperand"; 681 let DecoderMethod = "DecodeSORegImmOperand"; 682 let ParserMatchClass = ShiftedImmAsmOperand; 683 let MIOperandInfo = (ops GPR, i32imm); 684} 685 686// mod_imm: match a 32-bit immediate operand, which can be encoded into 687// a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM 688// - "Modified Immediate Constants"). Within the MC layer we keep this 689// immediate in its encoded form. 690def ModImmAsmOperand: AsmOperandClass { 691 let Name = "ModImm"; 692 let ParserMethod = "parseModImm"; 693} 694def mod_imm : Operand<i32>, ImmLeaf<i32, [{ 695 return ARM_AM::getSOImmVal(Imm) != -1; 696 }]> { 697 let EncoderMethod = "getModImmOpValue"; 698 let PrintMethod = "printModImmOperand"; 699 let ParserMatchClass = ModImmAsmOperand; 700} 701 702// Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder 703// method and such, as they are only used on aliases (Pat<> and InstAlias<>). 704// The actual parsing, encoding, decoding are handled by the destination 705// instructions, which use mod_imm. 706 707def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; } 708def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{ 709 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1; 710 }], imm_not_XFORM> { 711 let ParserMatchClass = ModImmNotAsmOperand; 712} 713 714def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; } 715def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{ 716 unsigned Value = -(unsigned)N->getZExtValue(); 717 return Value && ARM_AM::getSOImmVal(Value) != -1; 718 }], imm_neg_XFORM> { 719 let ParserMatchClass = ModImmNegAsmOperand; 720} 721 722/// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal() 723def arm_i32imm : PatLeaf<(imm), [{ 724 if (Subtarget->useMovt(*MF)) 725 return true; 726 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 727}]>; 728 729/// imm0_1 predicate - Immediate in the range [0,1]. 730def Imm0_1AsmOperand: ImmAsmOperand<0,1> { let Name = "Imm0_1"; } 731def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; } 732 733/// imm0_3 predicate - Immediate in the range [0,3]. 734def Imm0_3AsmOperand: ImmAsmOperand<0,3> { let Name = "Imm0_3"; } 735def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; } 736 737/// imm0_7 predicate - Immediate in the range [0,7]. 738def Imm0_7AsmOperand: ImmAsmOperand<0,7> { 739 let Name = "Imm0_7"; 740} 741def imm0_7 : Operand<i32>, ImmLeaf<i32, [{ 742 return Imm >= 0 && Imm < 8; 743}]> { 744 let ParserMatchClass = Imm0_7AsmOperand; 745} 746 747/// imm8_255 predicate - Immediate in the range [8,255]. 748def Imm8_255AsmOperand: ImmAsmOperand<8,255> { let Name = "Imm8_255"; } 749def imm8_255 : Operand<i32>, ImmLeaf<i32, [{ 750 return Imm >= 8 && Imm < 256; 751}]> { 752 let ParserMatchClass = Imm8_255AsmOperand; 753} 754 755/// imm8 predicate - Immediate is exactly 8. 756def Imm8AsmOperand: ImmAsmOperand<8,8> { let Name = "Imm8"; } 757def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> { 758 let ParserMatchClass = Imm8AsmOperand; 759} 760 761/// imm16 predicate - Immediate is exactly 16. 762def Imm16AsmOperand: ImmAsmOperand<16,16> { let Name = "Imm16"; } 763def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> { 764 let ParserMatchClass = Imm16AsmOperand; 765} 766 767/// imm32 predicate - Immediate is exactly 32. 768def Imm32AsmOperand: ImmAsmOperand<32,32> { let Name = "Imm32"; } 769def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> { 770 let ParserMatchClass = Imm32AsmOperand; 771} 772 773def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>; 774 775/// imm1_7 predicate - Immediate in the range [1,7]. 776def Imm1_7AsmOperand: ImmAsmOperand<1,7> { let Name = "Imm1_7"; } 777def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> { 778 let ParserMatchClass = Imm1_7AsmOperand; 779} 780 781/// imm1_15 predicate - Immediate in the range [1,15]. 782def Imm1_15AsmOperand: ImmAsmOperand<1,15> { let Name = "Imm1_15"; } 783def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> { 784 let ParserMatchClass = Imm1_15AsmOperand; 785} 786 787/// imm1_31 predicate - Immediate in the range [1,31]. 788def Imm1_31AsmOperand: ImmAsmOperand<1,31> { let Name = "Imm1_31"; } 789def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> { 790 let ParserMatchClass = Imm1_31AsmOperand; 791} 792 793/// imm0_15 predicate - Immediate in the range [0,15]. 794def Imm0_15AsmOperand: ImmAsmOperand<0,15> { 795 let Name = "Imm0_15"; 796} 797def imm0_15 : Operand<i32>, ImmLeaf<i32, [{ 798 return Imm >= 0 && Imm < 16; 799}]> { 800 let ParserMatchClass = Imm0_15AsmOperand; 801} 802 803/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31]. 804def Imm0_31AsmOperand: ImmAsmOperand<0,31> { let Name = "Imm0_31"; } 805def imm0_31 : Operand<i32>, ImmLeaf<i32, [{ 806 return Imm >= 0 && Imm < 32; 807}]> { 808 let ParserMatchClass = Imm0_31AsmOperand; 809} 810 811/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32]. 812def Imm0_32AsmOperand: ImmAsmOperand<0,32> { let Name = "Imm0_32"; } 813def imm0_32 : Operand<i32>, ImmLeaf<i32, [{ 814 return Imm >= 0 && Imm < 33; 815}]> { 816 let ParserMatchClass = Imm0_32AsmOperand; 817} 818 819/// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63]. 820def Imm0_63AsmOperand: ImmAsmOperand<0,63> { let Name = "Imm0_63"; } 821def imm0_63 : Operand<i32>, ImmLeaf<i32, [{ 822 return Imm >= 0 && Imm < 64; 823}]> { 824 let ParserMatchClass = Imm0_63AsmOperand; 825} 826 827/// imm0_239 predicate - Immediate in the range [0,239]. 828def Imm0_239AsmOperand : ImmAsmOperand<0,239> { 829 let Name = "Imm0_239"; 830} 831def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> { 832 let ParserMatchClass = Imm0_239AsmOperand; 833} 834 835/// imm0_255 predicate - Immediate in the range [0,255]. 836def Imm0_255AsmOperand : ImmAsmOperand<0,255> { let Name = "Imm0_255"; } 837def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> { 838 let ParserMatchClass = Imm0_255AsmOperand; 839} 840 841/// imm0_65535 - An immediate is in the range [0,65535]. 842def Imm0_65535AsmOperand: ImmAsmOperand<0,65535> { let Name = "Imm0_65535"; } 843def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{ 844 return Imm >= 0 && Imm < 65536; 845}]> { 846 let ParserMatchClass = Imm0_65535AsmOperand; 847} 848 849// imm0_65535_neg - An immediate whose negative value is in the range [0.65535]. 850def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{ 851 return -Imm >= 0 && -Imm < 65536; 852}]>; 853 854// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference 855// a relocatable expression. 856// 857// FIXME: This really needs a Thumb version separate from the ARM version. 858// While the range is the same, and can thus use the same match class, 859// the encoding is different so it should have a different encoder method. 860def Imm0_65535ExprAsmOperand: AsmOperandClass { 861 let Name = "Imm0_65535Expr"; 862 let RenderMethod = "addImmOperands"; 863 let DiagnosticString = "operand must be an immediate in the range [0,0xffff] or a relocatable expression"; 864} 865 866def imm0_65535_expr : Operand<i32> { 867 let EncoderMethod = "getHiLo16ImmOpValue"; 868 let ParserMatchClass = Imm0_65535ExprAsmOperand; 869} 870 871def Imm256_65535ExprAsmOperand: ImmAsmOperand<256,65535> { let Name = "Imm256_65535Expr"; } 872def imm256_65535_expr : Operand<i32> { 873 let ParserMatchClass = Imm256_65535ExprAsmOperand; 874} 875 876/// imm24b - True if the 32-bit immediate is encodable in 24 bits. 877def Imm24bitAsmOperand: ImmAsmOperand<0,0xffffff> { 878 let Name = "Imm24bit"; 879 let DiagnosticString = "operand must be an immediate in the range [0,0xffffff]"; 880} 881def imm24b : Operand<i32>, ImmLeaf<i32, [{ 882 return Imm >= 0 && Imm <= 0xffffff; 883}]> { 884 let ParserMatchClass = Imm24bitAsmOperand; 885} 886 887 888/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield 889/// e.g., 0xf000ffff 890def BitfieldAsmOperand : AsmOperandClass { 891 let Name = "Bitfield"; 892 let ParserMethod = "parseBitfield"; 893} 894 895def bf_inv_mask_imm : Operand<i32>, 896 PatLeaf<(imm), [{ 897 return ARM::isBitFieldInvertedMask(N->getZExtValue()); 898}] > { 899 let EncoderMethod = "getBitfieldInvertedMaskOpValue"; 900 let PrintMethod = "printBitfieldInvMaskImmOperand"; 901 let DecoderMethod = "DecodeBitfieldMaskOperand"; 902 let ParserMatchClass = BitfieldAsmOperand; 903 let GISelPredicateCode = [{ 904 // There's better methods of implementing this check. IntImmLeaf<> would be 905 // equivalent and have less boilerplate but we need a test for C++ 906 // predicates and this one causes new rules to be imported into GlobalISel 907 // without requiring additional features first. 908 const auto &MO = MI.getOperand(1); 909 if (!MO.isCImm()) 910 return false; 911 return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue()); 912 }]; 913} 914 915def imm1_32_XFORM: SDNodeXForm<imm, [{ 916 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 917 MVT::i32); 918}]>; 919def Imm1_32AsmOperand: ImmAsmOperandMinusOne<1,32> { 920 let Name = "Imm1_32"; 921} 922def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ 923 uint64_t Imm = N->getZExtValue(); 924 return Imm > 0 && Imm <= 32; 925 }], 926 imm1_32_XFORM> { 927 let PrintMethod = "printImmPlusOneOperand"; 928 let ParserMatchClass = Imm1_32AsmOperand; 929} 930 931def imm1_16_XFORM: SDNodeXForm<imm, [{ 932 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 933 MVT::i32); 934}]>; 935def Imm1_16AsmOperand: ImmAsmOperandMinusOne<1,16> { let Name = "Imm1_16"; } 936def imm1_16 : Operand<i32>, ImmLeaf<i32, [{ 937 return Imm > 0 && Imm <= 16; 938 }], 939 imm1_16_XFORM> { 940 let PrintMethod = "printImmPlusOneOperand"; 941 let ParserMatchClass = Imm1_16AsmOperand; 942} 943 944// Define ARM specific addressing modes. 945// addrmode_imm12 := reg +/- imm12 946// 947def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; } 948class AddrMode_Imm12 : MemOperand, 949 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> { 950 // 12-bit immediate operand. Note that instructions using this encode 951 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other 952 // immediate values are as normal. 953 954 let EncoderMethod = "getAddrModeImm12OpValue"; 955 let DecoderMethod = "DecodeAddrModeImm12Operand"; 956 let ParserMatchClass = MemImm12OffsetAsmOperand; 957 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 958} 959 960def addrmode_imm12 : AddrMode_Imm12 { 961 let PrintMethod = "printAddrModeImm12Operand<false>"; 962} 963 964def addrmode_imm12_pre : AddrMode_Imm12 { 965 let PrintMethod = "printAddrModeImm12Operand<true>"; 966} 967 968// ldst_so_reg := reg +/- reg shop imm 969// 970def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; } 971def ldst_so_reg : MemOperand, 972 ComplexPattern<i32, 3, "SelectLdStSOReg", []> { 973 let EncoderMethod = "getLdStSORegOpValue"; 974 // FIXME: Simplify the printer 975 let PrintMethod = "printAddrMode2Operand"; 976 let DecoderMethod = "DecodeSORegMemOperand"; 977 let ParserMatchClass = MemRegOffsetAsmOperand; 978 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift); 979} 980 981// postidx_imm8 := +/- [0,255] 982// 983// 9 bit value: 984// {8} 1 is imm8 is non-negative. 0 otherwise. 985// {7-0} [0,255] imm8 value. 986def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; } 987def postidx_imm8 : MemOperand { 988 let PrintMethod = "printPostIdxImm8Operand"; 989 let ParserMatchClass = PostIdxImm8AsmOperand; 990 let MIOperandInfo = (ops i32imm); 991} 992 993// postidx_imm8s4 := +/- [0,1020] 994// 995// 9 bit value: 996// {8} 1 is imm8 is non-negative. 0 otherwise. 997// {7-0} [0,255] imm8 value, scaled by 4. 998def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; } 999def postidx_imm8s4 : MemOperand { 1000 let PrintMethod = "printPostIdxImm8s4Operand"; 1001 let ParserMatchClass = PostIdxImm8s4AsmOperand; 1002 let MIOperandInfo = (ops i32imm); 1003} 1004 1005 1006// postidx_reg := +/- reg 1007// 1008def PostIdxRegAsmOperand : AsmOperandClass { 1009 let Name = "PostIdxReg"; 1010 let ParserMethod = "parsePostIdxReg"; 1011} 1012def postidx_reg : MemOperand { 1013 let EncoderMethod = "getPostIdxRegOpValue"; 1014 let DecoderMethod = "DecodePostIdxReg"; 1015 let PrintMethod = "printPostIdxRegOperand"; 1016 let ParserMatchClass = PostIdxRegAsmOperand; 1017 let MIOperandInfo = (ops GPRnopc, i32imm); 1018} 1019 1020def PostIdxRegShiftedAsmOperand : AsmOperandClass { 1021 let Name = "PostIdxRegShifted"; 1022 let ParserMethod = "parsePostIdxReg"; 1023} 1024def am2offset_reg : MemOperand, 1025 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg", 1026 [], [SDNPWantRoot]> { 1027 let EncoderMethod = "getAddrMode2OffsetOpValue"; 1028 let PrintMethod = "printAddrMode2OffsetOperand"; 1029 // When using this for assembly, it's always as a post-index offset. 1030 let ParserMatchClass = PostIdxRegShiftedAsmOperand; 1031 let MIOperandInfo = (ops GPRnopc, i32imm); 1032} 1033 1034// FIXME: am2offset_imm should only need the immediate, not the GPR. Having 1035// the GPR is purely vestigal at this point. 1036def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; } 1037def am2offset_imm : MemOperand, 1038 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm", 1039 [], [SDNPWantRoot]> { 1040 let EncoderMethod = "getAddrMode2OffsetOpValue"; 1041 let PrintMethod = "printAddrMode2OffsetOperand"; 1042 let ParserMatchClass = AM2OffsetImmAsmOperand; 1043 let MIOperandInfo = (ops GPRnopc, i32imm); 1044} 1045 1046 1047// addrmode3 := reg +/- reg 1048// addrmode3 := reg +/- imm8 1049// 1050// FIXME: split into imm vs. reg versions. 1051def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; } 1052class AddrMode3 : MemOperand, 1053 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 1054 let EncoderMethod = "getAddrMode3OpValue"; 1055 let ParserMatchClass = AddrMode3AsmOperand; 1056 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 1057} 1058 1059def addrmode3 : AddrMode3 1060{ 1061 let PrintMethod = "printAddrMode3Operand<false>"; 1062} 1063 1064def addrmode3_pre : AddrMode3 1065{ 1066 let PrintMethod = "printAddrMode3Operand<true>"; 1067} 1068 1069// FIXME: split into imm vs. reg versions. 1070// FIXME: parser method to handle +/- register. 1071def AM3OffsetAsmOperand : AsmOperandClass { 1072 let Name = "AM3Offset"; 1073 let ParserMethod = "parseAM3Offset"; 1074} 1075def am3offset : MemOperand, 1076 ComplexPattern<i32, 2, "SelectAddrMode3Offset", 1077 [], [SDNPWantRoot]> { 1078 let EncoderMethod = "getAddrMode3OffsetOpValue"; 1079 let PrintMethod = "printAddrMode3OffsetOperand"; 1080 let ParserMatchClass = AM3OffsetAsmOperand; 1081 let MIOperandInfo = (ops GPR, i32imm); 1082} 1083 1084// ldstm_mode := {ia, ib, da, db} 1085// 1086def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> { 1087 let EncoderMethod = "getLdStmModeOpValue"; 1088 let PrintMethod = "printLdStmModeOperand"; 1089} 1090 1091// addrmode5 := reg +/- imm8*4 1092// 1093def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; } 1094class AddrMode5 : MemOperand, 1095 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 1096 let EncoderMethod = "getAddrMode5OpValue"; 1097 let DecoderMethod = "DecodeAddrMode5Operand"; 1098 let ParserMatchClass = AddrMode5AsmOperand; 1099 let MIOperandInfo = (ops GPR:$base, i32imm); 1100} 1101 1102def addrmode5 : AddrMode5 { 1103 let PrintMethod = "printAddrMode5Operand<false>"; 1104} 1105 1106def addrmode5_pre : AddrMode5 { 1107 let PrintMethod = "printAddrMode5Operand<true>"; 1108} 1109 1110// addrmode5fp16 := reg +/- imm8*2 1111// 1112def AddrMode5FP16AsmOperand : AsmOperandClass { let Name = "AddrMode5FP16"; } 1113class AddrMode5FP16 : Operand<i32>, 1114 ComplexPattern<i32, 2, "SelectAddrMode5FP16", []> { 1115 let EncoderMethod = "getAddrMode5FP16OpValue"; 1116 let DecoderMethod = "DecodeAddrMode5FP16Operand"; 1117 let ParserMatchClass = AddrMode5FP16AsmOperand; 1118 let MIOperandInfo = (ops GPR:$base, i32imm); 1119} 1120 1121def addrmode5fp16 : AddrMode5FP16 { 1122 let PrintMethod = "printAddrMode5FP16Operand<false>"; 1123} 1124 1125// addrmode6 := reg with optional alignment 1126// 1127def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; } 1128def addrmode6 : MemOperand, 1129 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1130 let PrintMethod = "printAddrMode6Operand"; 1131 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1132 let EncoderMethod = "getAddrMode6AddressOpValue"; 1133 let DecoderMethod = "DecodeAddrMode6Operand"; 1134 let ParserMatchClass = AddrMode6AsmOperand; 1135} 1136 1137def am6offset : MemOperand, 1138 ComplexPattern<i32, 1, "SelectAddrMode6Offset", 1139 [], [SDNPWantRoot]> { 1140 let PrintMethod = "printAddrMode6OffsetOperand"; 1141 let MIOperandInfo = (ops GPR); 1142 let EncoderMethod = "getAddrMode6OffsetOpValue"; 1143 let DecoderMethod = "DecodeGPRRegisterClass"; 1144} 1145 1146// Special version of addrmode6 to handle alignment encoding for VST1/VLD1 1147// (single element from one lane) for size 32. 1148def addrmode6oneL32 : MemOperand, 1149 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1150 let PrintMethod = "printAddrMode6Operand"; 1151 let MIOperandInfo = (ops GPR:$addr, i32imm); 1152 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue"; 1153} 1154 1155// Base class for addrmode6 with specific alignment restrictions. 1156class AddrMode6Align : MemOperand, 1157 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1158 let PrintMethod = "printAddrMode6Operand"; 1159 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1160 let EncoderMethod = "getAddrMode6AddressOpValue"; 1161 let DecoderMethod = "DecodeAddrMode6Operand"; 1162} 1163 1164// Special version of addrmode6 to handle no allowed alignment encoding for 1165// VLD/VST instructions and checking the alignment is not specified. 1166def AddrMode6AlignNoneAsmOperand : AsmOperandClass { 1167 let Name = "AlignedMemoryNone"; 1168 let DiagnosticString = "alignment must be omitted"; 1169} 1170def addrmode6alignNone : AddrMode6Align { 1171 // The alignment specifier can only be omitted. 1172 let ParserMatchClass = AddrMode6AlignNoneAsmOperand; 1173} 1174 1175// Special version of addrmode6 to handle 16-bit alignment encoding for 1176// VLD/VST instructions and checking the alignment value. 1177def AddrMode6Align16AsmOperand : AsmOperandClass { 1178 let Name = "AlignedMemory16"; 1179 let DiagnosticString = "alignment must be 16 or omitted"; 1180} 1181def addrmode6align16 : AddrMode6Align { 1182 // The alignment specifier can only be 16 or omitted. 1183 let ParserMatchClass = AddrMode6Align16AsmOperand; 1184} 1185 1186// Special version of addrmode6 to handle 32-bit alignment encoding for 1187// VLD/VST instructions and checking the alignment value. 1188def AddrMode6Align32AsmOperand : AsmOperandClass { 1189 let Name = "AlignedMemory32"; 1190 let DiagnosticString = "alignment must be 32 or omitted"; 1191} 1192def addrmode6align32 : AddrMode6Align { 1193 // The alignment specifier can only be 32 or omitted. 1194 let ParserMatchClass = AddrMode6Align32AsmOperand; 1195} 1196 1197// Special version of addrmode6 to handle 64-bit alignment encoding for 1198// VLD/VST instructions and checking the alignment value. 1199def AddrMode6Align64AsmOperand : AsmOperandClass { 1200 let Name = "AlignedMemory64"; 1201 let DiagnosticString = "alignment must be 64 or omitted"; 1202} 1203def addrmode6align64 : AddrMode6Align { 1204 // The alignment specifier can only be 64 or omitted. 1205 let ParserMatchClass = AddrMode6Align64AsmOperand; 1206} 1207 1208// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1209// for VLD/VST instructions and checking the alignment value. 1210def AddrMode6Align64or128AsmOperand : AsmOperandClass { 1211 let Name = "AlignedMemory64or128"; 1212 let DiagnosticString = "alignment must be 64, 128 or omitted"; 1213} 1214def addrmode6align64or128 : AddrMode6Align { 1215 // The alignment specifier can only be 64, 128 or omitted. 1216 let ParserMatchClass = AddrMode6Align64or128AsmOperand; 1217} 1218 1219// Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment 1220// encoding for VLD/VST instructions and checking the alignment value. 1221def AddrMode6Align64or128or256AsmOperand : AsmOperandClass { 1222 let Name = "AlignedMemory64or128or256"; 1223 let DiagnosticString = "alignment must be 64, 128, 256 or omitted"; 1224} 1225def addrmode6align64or128or256 : AddrMode6Align { 1226 // The alignment specifier can only be 64, 128, 256 or omitted. 1227 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand; 1228} 1229 1230// Special version of addrmode6 to handle alignment encoding for VLD-dup 1231// instructions, specifically VLD4-dup. 1232def addrmode6dup : MemOperand, 1233 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1234 let PrintMethod = "printAddrMode6Operand"; 1235 let MIOperandInfo = (ops GPR:$addr, i32imm); 1236 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1237 // FIXME: This is close, but not quite right. The alignment specifier is 1238 // different. 1239 let ParserMatchClass = AddrMode6AsmOperand; 1240} 1241 1242// Base class for addrmode6dup with specific alignment restrictions. 1243class AddrMode6DupAlign : MemOperand, 1244 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1245 let PrintMethod = "printAddrMode6Operand"; 1246 let MIOperandInfo = (ops GPR:$addr, i32imm); 1247 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1248} 1249 1250// Special version of addrmode6 to handle no allowed alignment encoding for 1251// VLD-dup instruction and checking the alignment is not specified. 1252def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass { 1253 let Name = "DupAlignedMemoryNone"; 1254 let DiagnosticString = "alignment must be omitted"; 1255} 1256def addrmode6dupalignNone : AddrMode6DupAlign { 1257 // The alignment specifier can only be omitted. 1258 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand; 1259} 1260 1261// Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup 1262// instruction and checking the alignment value. 1263def AddrMode6dupAlign16AsmOperand : AsmOperandClass { 1264 let Name = "DupAlignedMemory16"; 1265 let DiagnosticString = "alignment must be 16 or omitted"; 1266} 1267def addrmode6dupalign16 : AddrMode6DupAlign { 1268 // The alignment specifier can only be 16 or omitted. 1269 let ParserMatchClass = AddrMode6dupAlign16AsmOperand; 1270} 1271 1272// Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup 1273// instruction and checking the alignment value. 1274def AddrMode6dupAlign32AsmOperand : AsmOperandClass { 1275 let Name = "DupAlignedMemory32"; 1276 let DiagnosticString = "alignment must be 32 or omitted"; 1277} 1278def addrmode6dupalign32 : AddrMode6DupAlign { 1279 // The alignment specifier can only be 32 or omitted. 1280 let ParserMatchClass = AddrMode6dupAlign32AsmOperand; 1281} 1282 1283// Special version of addrmode6 to handle 64-bit alignment encoding for VLD 1284// instructions and checking the alignment value. 1285def AddrMode6dupAlign64AsmOperand : AsmOperandClass { 1286 let Name = "DupAlignedMemory64"; 1287 let DiagnosticString = "alignment must be 64 or omitted"; 1288} 1289def addrmode6dupalign64 : AddrMode6DupAlign { 1290 // The alignment specifier can only be 64 or omitted. 1291 let ParserMatchClass = AddrMode6dupAlign64AsmOperand; 1292} 1293 1294// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1295// for VLD instructions and checking the alignment value. 1296def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass { 1297 let Name = "DupAlignedMemory64or128"; 1298 let DiagnosticString = "alignment must be 64, 128 or omitted"; 1299} 1300def addrmode6dupalign64or128 : AddrMode6DupAlign { 1301 // The alignment specifier can only be 64, 128 or omitted. 1302 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand; 1303} 1304 1305// addrmodepc := pc + reg 1306// 1307def addrmodepc : MemOperand, 1308 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 1309 let PrintMethod = "printAddrModePCOperand"; 1310 let MIOperandInfo = (ops GPR, i32imm); 1311} 1312 1313// addr_offset_none := reg 1314// 1315def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; } 1316def addr_offset_none : MemOperand, 1317 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> { 1318 let PrintMethod = "printAddrMode7Operand"; 1319 let DecoderMethod = "DecodeAddrMode7Operand"; 1320 let ParserMatchClass = MemNoOffsetAsmOperand; 1321 let MIOperandInfo = (ops GPR:$base); 1322} 1323 1324def nohash_imm : Operand<i32> { 1325 let PrintMethod = "printNoHashImmediate"; 1326} 1327 1328def CoprocNumAsmOperand : AsmOperandClass { 1329 let Name = "CoprocNum"; 1330 let ParserMethod = "parseCoprocNumOperand"; 1331} 1332def p_imm : Operand<i32> { 1333 let PrintMethod = "printPImmediate"; 1334 let ParserMatchClass = CoprocNumAsmOperand; 1335 let DecoderMethod = "DecodeCoprocessor"; 1336} 1337 1338def CoprocRegAsmOperand : AsmOperandClass { 1339 let Name = "CoprocReg"; 1340 let ParserMethod = "parseCoprocRegOperand"; 1341} 1342def c_imm : Operand<i32> { 1343 let PrintMethod = "printCImmediate"; 1344 let ParserMatchClass = CoprocRegAsmOperand; 1345} 1346def CoprocOptionAsmOperand : AsmOperandClass { 1347 let Name = "CoprocOption"; 1348 let ParserMethod = "parseCoprocOptionOperand"; 1349} 1350def coproc_option_imm : Operand<i32> { 1351 let PrintMethod = "printCoprocOptionImm"; 1352 let ParserMatchClass = CoprocOptionAsmOperand; 1353} 1354 1355//===----------------------------------------------------------------------===// 1356 1357include "ARMInstrFormats.td" 1358 1359//===----------------------------------------------------------------------===// 1360// Multiclass helpers... 1361// 1362 1363/// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a 1364/// binop that produces a value. 1365let TwoOperandAliasConstraint = "$Rn = $Rd" in 1366multiclass AsI1_bin_irs<bits<4> opcod, string opc, 1367 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1368 SDPatternOperator opnode, bit Commutable = 0> { 1369 // The register-immediate version is re-materializable. This is useful 1370 // in particular for taking the address of a local. 1371 let isReMaterializable = 1 in { 1372 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1373 iii, opc, "\t$Rd, $Rn, $imm", 1374 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>, 1375 Sched<[WriteALU, ReadALU]> { 1376 bits<4> Rd; 1377 bits<4> Rn; 1378 bits<12> imm; 1379 let Inst{25} = 1; 1380 let Inst{19-16} = Rn; 1381 let Inst{15-12} = Rd; 1382 let Inst{11-0} = imm; 1383 } 1384 } 1385 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1386 iir, opc, "\t$Rd, $Rn, $Rm", 1387 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, 1388 Sched<[WriteALU, ReadALU, ReadALU]> { 1389 bits<4> Rd; 1390 bits<4> Rn; 1391 bits<4> Rm; 1392 let Inst{25} = 0; 1393 let isCommutable = Commutable; 1394 let Inst{19-16} = Rn; 1395 let Inst{15-12} = Rd; 1396 let Inst{11-4} = 0b00000000; 1397 let Inst{3-0} = Rm; 1398 } 1399 1400 def rsi : AsI1<opcod, (outs GPR:$Rd), 1401 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1402 iis, opc, "\t$Rd, $Rn, $shift", 1403 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>, 1404 Sched<[WriteALUsi, ReadALU]> { 1405 bits<4> Rd; 1406 bits<4> Rn; 1407 bits<12> shift; 1408 let Inst{25} = 0; 1409 let Inst{19-16} = Rn; 1410 let Inst{15-12} = Rd; 1411 let Inst{11-5} = shift{11-5}; 1412 let Inst{4} = 0; 1413 let Inst{3-0} = shift{3-0}; 1414 } 1415 1416 def rsr : AsI1<opcod, (outs GPR:$Rd), 1417 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1418 iis, opc, "\t$Rd, $Rn, $shift", 1419 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>, 1420 Sched<[WriteALUsr, ReadALUsr]> { 1421 bits<4> Rd; 1422 bits<4> Rn; 1423 bits<12> shift; 1424 let Inst{25} = 0; 1425 let Inst{19-16} = Rn; 1426 let Inst{15-12} = Rd; 1427 let Inst{11-8} = shift{11-8}; 1428 let Inst{7} = 0; 1429 let Inst{6-5} = shift{6-5}; 1430 let Inst{4} = 1; 1431 let Inst{3-0} = shift{3-0}; 1432 } 1433} 1434 1435/// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are 1436/// reversed. The 'rr' form is only defined for the disassembler; for codegen 1437/// it is equivalent to the AsI1_bin_irs counterpart. 1438let TwoOperandAliasConstraint = "$Rn = $Rd" in 1439multiclass AsI1_rbin_irs<bits<4> opcod, string opc, 1440 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1441 SDNode opnode, bit Commutable = 0> { 1442 // The register-immediate version is re-materializable. This is useful 1443 // in particular for taking the address of a local. 1444 let isReMaterializable = 1 in { 1445 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1446 iii, opc, "\t$Rd, $Rn, $imm", 1447 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>, 1448 Sched<[WriteALU, ReadALU]> { 1449 bits<4> Rd; 1450 bits<4> Rn; 1451 bits<12> imm; 1452 let Inst{25} = 1; 1453 let Inst{19-16} = Rn; 1454 let Inst{15-12} = Rd; 1455 let Inst{11-0} = imm; 1456 } 1457 } 1458 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1459 iir, opc, "\t$Rd, $Rn, $Rm", 1460 [/* pattern left blank */]>, 1461 Sched<[WriteALU, ReadALU, ReadALU]> { 1462 bits<4> Rd; 1463 bits<4> Rn; 1464 bits<4> Rm; 1465 let Inst{11-4} = 0b00000000; 1466 let Inst{25} = 0; 1467 let Inst{3-0} = Rm; 1468 let Inst{15-12} = Rd; 1469 let Inst{19-16} = Rn; 1470 } 1471 1472 def rsi : AsI1<opcod, (outs GPR:$Rd), 1473 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1474 iis, opc, "\t$Rd, $Rn, $shift", 1475 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>, 1476 Sched<[WriteALUsi, ReadALU]> { 1477 bits<4> Rd; 1478 bits<4> Rn; 1479 bits<12> shift; 1480 let Inst{25} = 0; 1481 let Inst{19-16} = Rn; 1482 let Inst{15-12} = Rd; 1483 let Inst{11-5} = shift{11-5}; 1484 let Inst{4} = 0; 1485 let Inst{3-0} = shift{3-0}; 1486 } 1487 1488 def rsr : AsI1<opcod, (outs GPR:$Rd), 1489 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1490 iis, opc, "\t$Rd, $Rn, $shift", 1491 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>, 1492 Sched<[WriteALUsr, ReadALUsr]> { 1493 bits<4> Rd; 1494 bits<4> Rn; 1495 bits<12> shift; 1496 let Inst{25} = 0; 1497 let Inst{19-16} = Rn; 1498 let Inst{15-12} = Rd; 1499 let Inst{11-8} = shift{11-8}; 1500 let Inst{7} = 0; 1501 let Inst{6-5} = shift{6-5}; 1502 let Inst{4} = 1; 1503 let Inst{3-0} = shift{3-0}; 1504 } 1505} 1506 1507/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default. 1508/// 1509/// These opcodes will be converted to the real non-S opcodes by 1510/// AdjustInstrPostInstrSelection after giving them an optional CPSR operand. 1511let hasPostISelHook = 1, Defs = [CPSR] in { 1512multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir, 1513 InstrItinClass iis, SDNode opnode, 1514 bit Commutable = 0> { 1515 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1516 4, iii, 1517 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>, 1518 Sched<[WriteALU, ReadALU]>; 1519 1520 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p), 1521 4, iir, 1522 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>, 1523 Sched<[WriteALU, ReadALU, ReadALU]> { 1524 let isCommutable = Commutable; 1525 } 1526 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1527 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1528 4, iis, 1529 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1530 so_reg_imm:$shift))]>, 1531 Sched<[WriteALUsi, ReadALU]>; 1532 1533 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1534 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1535 4, iis, 1536 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1537 so_reg_reg:$shift))]>, 1538 Sched<[WriteALUSsr, ReadALUsr]>; 1539} 1540} 1541 1542/// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG 1543/// operands are reversed. 1544let hasPostISelHook = 1, Defs = [CPSR] in { 1545multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir, 1546 InstrItinClass iis, SDNode opnode, 1547 bit Commutable = 0> { 1548 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1549 4, iii, 1550 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>, 1551 Sched<[WriteALU, ReadALU]>; 1552 1553 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1554 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1555 4, iis, 1556 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, 1557 GPR:$Rn))]>, 1558 Sched<[WriteALUsi, ReadALU]>; 1559 1560 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1561 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1562 4, iis, 1563 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, 1564 GPR:$Rn))]>, 1565 Sched<[WriteALUSsr, ReadALUsr]>; 1566} 1567} 1568 1569/// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test 1570/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 1571/// a explicit result, only implicitly set CPSR. 1572let isCompare = 1, Defs = [CPSR] in { 1573multiclass AI1_cmp_irs<bits<4> opcod, string opc, 1574 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1575 SDPatternOperator opnode, bit Commutable = 0, 1576 string rrDecoderMethod = ""> { 1577 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii, 1578 opc, "\t$Rn, $imm", 1579 [(opnode GPR:$Rn, mod_imm:$imm)]>, 1580 Sched<[WriteCMP, ReadALU]> { 1581 bits<4> Rn; 1582 bits<12> imm; 1583 let Inst{25} = 1; 1584 let Inst{20} = 1; 1585 let Inst{19-16} = Rn; 1586 let Inst{15-12} = 0b0000; 1587 let Inst{11-0} = imm; 1588 1589 let Unpredictable{15-12} = 0b1111; 1590 } 1591 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir, 1592 opc, "\t$Rn, $Rm", 1593 [(opnode GPR:$Rn, GPR:$Rm)]>, 1594 Sched<[WriteCMP, ReadALU, ReadALU]> { 1595 bits<4> Rn; 1596 bits<4> Rm; 1597 let isCommutable = Commutable; 1598 let Inst{25} = 0; 1599 let Inst{20} = 1; 1600 let Inst{19-16} = Rn; 1601 let Inst{15-12} = 0b0000; 1602 let Inst{11-4} = 0b00000000; 1603 let Inst{3-0} = Rm; 1604 let DecoderMethod = rrDecoderMethod; 1605 1606 let Unpredictable{15-12} = 0b1111; 1607 } 1608 def rsi : AI1<opcod, (outs), 1609 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis, 1610 opc, "\t$Rn, $shift", 1611 [(opnode GPR:$Rn, so_reg_imm:$shift)]>, 1612 Sched<[WriteCMPsi, ReadALU]> { 1613 bits<4> Rn; 1614 bits<12> shift; 1615 let Inst{25} = 0; 1616 let Inst{20} = 1; 1617 let Inst{19-16} = Rn; 1618 let Inst{15-12} = 0b0000; 1619 let Inst{11-5} = shift{11-5}; 1620 let Inst{4} = 0; 1621 let Inst{3-0} = shift{3-0}; 1622 1623 let Unpredictable{15-12} = 0b1111; 1624 } 1625 def rsr : AI1<opcod, (outs), 1626 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis, 1627 opc, "\t$Rn, $shift", 1628 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>, 1629 Sched<[WriteCMPsr, ReadALU]> { 1630 bits<4> Rn; 1631 bits<12> shift; 1632 let Inst{25} = 0; 1633 let Inst{20} = 1; 1634 let Inst{19-16} = Rn; 1635 let Inst{15-12} = 0b0000; 1636 let Inst{11-8} = shift{11-8}; 1637 let Inst{7} = 0; 1638 let Inst{6-5} = shift{6-5}; 1639 let Inst{4} = 1; 1640 let Inst{3-0} = shift{3-0}; 1641 1642 let Unpredictable{15-12} = 0b1111; 1643 } 1644 1645} 1646} 1647 1648/// AI_ext_rrot - A unary operation with two forms: one whose operand is a 1649/// register and one whose operand is a register rotated by 8/16/24. 1650/// FIXME: Remove the 'r' variant. Its rot_imm is zero. 1651class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> 1652 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1653 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", 1654 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1655 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1656 bits<4> Rd; 1657 bits<4> Rm; 1658 bits<2> rot; 1659 let Inst{19-16} = 0b1111; 1660 let Inst{15-12} = Rd; 1661 let Inst{11-10} = rot; 1662 let Inst{3-0} = Rm; 1663} 1664 1665class AI_ext_rrot_np<bits<8> opcod, string opc> 1666 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1667 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>, 1668 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1669 bits<2> rot; 1670 let Inst{19-16} = 0b1111; 1671 let Inst{11-10} = rot; 1672 } 1673 1674/// AI_exta_rrot - A binary operation with two forms: one whose operand is a 1675/// register and one whose operand is a register rotated by 8/16/24. 1676class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> 1677 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1678 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", 1679 [(set GPRnopc:$Rd, (opnode GPR:$Rn, 1680 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1681 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1682 bits<4> Rd; 1683 bits<4> Rm; 1684 bits<4> Rn; 1685 bits<2> rot; 1686 let Inst{19-16} = Rn; 1687 let Inst{15-12} = Rd; 1688 let Inst{11-10} = rot; 1689 let Inst{9-4} = 0b000111; 1690 let Inst{3-0} = Rm; 1691} 1692 1693class AI_exta_rrot_np<bits<8> opcod, string opc> 1694 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1695 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>, 1696 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1697 bits<4> Rn; 1698 bits<2> rot; 1699 let Inst{19-16} = Rn; 1700 let Inst{11-10} = rot; 1701} 1702 1703/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. 1704let TwoOperandAliasConstraint = "$Rn = $Rd" in 1705multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode, 1706 bit Commutable = 0> { 1707 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1708 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1709 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1710 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>, 1711 Requires<[IsARM]>, 1712 Sched<[WriteALU, ReadALU]> { 1713 bits<4> Rd; 1714 bits<4> Rn; 1715 bits<12> imm; 1716 let Inst{25} = 1; 1717 let Inst{15-12} = Rd; 1718 let Inst{19-16} = Rn; 1719 let Inst{11-0} = imm; 1720 } 1721 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1722 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1723 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>, 1724 Requires<[IsARM]>, 1725 Sched<[WriteALU, ReadALU, ReadALU]> { 1726 bits<4> Rd; 1727 bits<4> Rn; 1728 bits<4> Rm; 1729 let Inst{11-4} = 0b00000000; 1730 let Inst{25} = 0; 1731 let isCommutable = Commutable; 1732 let Inst{3-0} = Rm; 1733 let Inst{15-12} = Rd; 1734 let Inst{19-16} = Rn; 1735 } 1736 def rsi : AsI1<opcod, (outs GPR:$Rd), 1737 (ins GPR:$Rn, so_reg_imm:$shift), 1738 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1739 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>, 1740 Requires<[IsARM]>, 1741 Sched<[WriteALUsi, ReadALU]> { 1742 bits<4> Rd; 1743 bits<4> Rn; 1744 bits<12> shift; 1745 let Inst{25} = 0; 1746 let Inst{19-16} = Rn; 1747 let Inst{15-12} = Rd; 1748 let Inst{11-5} = shift{11-5}; 1749 let Inst{4} = 0; 1750 let Inst{3-0} = shift{3-0}; 1751 } 1752 def rsr : AsI1<opcod, (outs GPRnopc:$Rd), 1753 (ins GPRnopc:$Rn, so_reg_reg:$shift), 1754 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1755 [(set GPRnopc:$Rd, CPSR, 1756 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>, 1757 Requires<[IsARM]>, 1758 Sched<[WriteALUsr, ReadALUsr]> { 1759 bits<4> Rd; 1760 bits<4> Rn; 1761 bits<12> shift; 1762 let Inst{25} = 0; 1763 let Inst{19-16} = Rn; 1764 let Inst{15-12} = Rd; 1765 let Inst{11-8} = shift{11-8}; 1766 let Inst{7} = 0; 1767 let Inst{6-5} = shift{6-5}; 1768 let Inst{4} = 1; 1769 let Inst{3-0} = shift{3-0}; 1770 } 1771 } 1772} 1773 1774/// AI1_rsc_irs - Define instructions and patterns for rsc 1775let TwoOperandAliasConstraint = "$Rn = $Rd" in 1776multiclass AI1_rsc_irs<bits<4> opcod, string opc, SDNode opnode> { 1777 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1778 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1779 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1780 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>, 1781 Requires<[IsARM]>, 1782 Sched<[WriteALU, ReadALU]> { 1783 bits<4> Rd; 1784 bits<4> Rn; 1785 bits<12> imm; 1786 let Inst{25} = 1; 1787 let Inst{15-12} = Rd; 1788 let Inst{19-16} = Rn; 1789 let Inst{11-0} = imm; 1790 } 1791 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1792 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1793 [/* pattern left blank */]>, 1794 Sched<[WriteALU, ReadALU, ReadALU]> { 1795 bits<4> Rd; 1796 bits<4> Rn; 1797 bits<4> Rm; 1798 let Inst{11-4} = 0b00000000; 1799 let Inst{25} = 0; 1800 let Inst{3-0} = Rm; 1801 let Inst{15-12} = Rd; 1802 let Inst{19-16} = Rn; 1803 } 1804 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), 1805 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1806 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>, 1807 Requires<[IsARM]>, 1808 Sched<[WriteALUsi, ReadALU]> { 1809 bits<4> Rd; 1810 bits<4> Rn; 1811 bits<12> shift; 1812 let Inst{25} = 0; 1813 let Inst{19-16} = Rn; 1814 let Inst{15-12} = Rd; 1815 let Inst{11-5} = shift{11-5}; 1816 let Inst{4} = 0; 1817 let Inst{3-0} = shift{3-0}; 1818 } 1819 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), 1820 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1821 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>, 1822 Requires<[IsARM]>, 1823 Sched<[WriteALUsr, ReadALUsr]> { 1824 bits<4> Rd; 1825 bits<4> Rn; 1826 bits<12> shift; 1827 let Inst{25} = 0; 1828 let Inst{19-16} = Rn; 1829 let Inst{15-12} = Rd; 1830 let Inst{11-8} = shift{11-8}; 1831 let Inst{7} = 0; 1832 let Inst{6-5} = shift{6-5}; 1833 let Inst{4} = 1; 1834 let Inst{3-0} = shift{3-0}; 1835 } 1836 } 1837} 1838 1839let canFoldAsLoad = 1, isReMaterializable = 1 in { 1840multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii, 1841 InstrItinClass iir, PatFrag opnode> { 1842 // Note: We use the complex addrmode_imm12 rather than just an input 1843 // GPR and a constrained immediate so that we can use this to match 1844 // frame index references and avoid matching constant pool references. 1845 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 1846 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1847 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { 1848 bits<4> Rt; 1849 bits<17> addr; 1850 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1851 let Inst{19-16} = addr{16-13}; // Rn 1852 let Inst{15-12} = Rt; 1853 let Inst{11-0} = addr{11-0}; // imm12 1854 } 1855 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift), 1856 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1857 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { 1858 bits<4> Rt; 1859 bits<17> shift; 1860 let shift{4} = 0; // Inst{4} = 0 1861 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1862 let Inst{19-16} = shift{16-13}; // Rn 1863 let Inst{15-12} = Rt; 1864 let Inst{11-0} = shift{11-0}; 1865 } 1866} 1867} 1868 1869let canFoldAsLoad = 1, isReMaterializable = 1 in { 1870multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii, 1871 InstrItinClass iir, PatFrag opnode> { 1872 // Note: We use the complex addrmode_imm12 rather than just an input 1873 // GPR and a constrained immediate so that we can use this to match 1874 // frame index references and avoid matching constant pool references. 1875 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), 1876 (ins addrmode_imm12:$addr), 1877 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1878 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> { 1879 bits<4> Rt; 1880 bits<17> addr; 1881 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1882 let Inst{19-16} = addr{16-13}; // Rn 1883 let Inst{15-12} = Rt; 1884 let Inst{11-0} = addr{11-0}; // imm12 1885 } 1886 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), 1887 (ins ldst_so_reg:$shift), 1888 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1889 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> { 1890 bits<4> Rt; 1891 bits<17> shift; 1892 let shift{4} = 0; // Inst{4} = 0 1893 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1894 let Inst{19-16} = shift{16-13}; // Rn 1895 let Inst{15-12} = Rt; 1896 let Inst{11-0} = shift{11-0}; 1897 } 1898} 1899} 1900 1901 1902multiclass AI_str1<bit isByte, string opc, InstrItinClass iii, 1903 InstrItinClass iir, PatFrag opnode> { 1904 // Note: We use the complex addrmode_imm12 rather than just an input 1905 // GPR and a constrained immediate so that we can use this to match 1906 // frame index references and avoid matching constant pool references. 1907 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1908 (ins GPR:$Rt, addrmode_imm12:$addr), 1909 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1910 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> { 1911 bits<4> Rt; 1912 bits<17> addr; 1913 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1914 let Inst{19-16} = addr{16-13}; // Rn 1915 let Inst{15-12} = Rt; 1916 let Inst{11-0} = addr{11-0}; // imm12 1917 } 1918 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift), 1919 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1920 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> { 1921 bits<4> Rt; 1922 bits<17> shift; 1923 let shift{4} = 0; // Inst{4} = 0 1924 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1925 let Inst{19-16} = shift{16-13}; // Rn 1926 let Inst{15-12} = Rt; 1927 let Inst{11-0} = shift{11-0}; 1928 } 1929} 1930 1931multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii, 1932 InstrItinClass iir, PatFrag opnode> { 1933 // Note: We use the complex addrmode_imm12 rather than just an input 1934 // GPR and a constrained immediate so that we can use this to match 1935 // frame index references and avoid matching constant pool references. 1936 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1937 (ins GPRnopc:$Rt, addrmode_imm12:$addr), 1938 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1939 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> { 1940 bits<4> Rt; 1941 bits<17> addr; 1942 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1943 let Inst{19-16} = addr{16-13}; // Rn 1944 let Inst{15-12} = Rt; 1945 let Inst{11-0} = addr{11-0}; // imm12 1946 } 1947 def rs : AI2ldst<0b011, 0, isByte, (outs), 1948 (ins GPRnopc:$Rt, ldst_so_reg:$shift), 1949 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1950 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> { 1951 bits<4> Rt; 1952 bits<17> shift; 1953 let shift{4} = 0; // Inst{4} = 0 1954 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1955 let Inst{19-16} = shift{16-13}; // Rn 1956 let Inst{15-12} = Rt; 1957 let Inst{11-0} = shift{11-0}; 1958 } 1959} 1960 1961 1962//===----------------------------------------------------------------------===// 1963// Instructions 1964//===----------------------------------------------------------------------===// 1965 1966//===----------------------------------------------------------------------===// 1967// Miscellaneous Instructions. 1968// 1969 1970/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 1971/// the function. The first operand is the ID# for this instruction, the second 1972/// is the index into the MachineConstantPool that this is, the third is the 1973/// size in bytes of this constant pool entry. 1974let hasSideEffects = 0, isNotDuplicable = 1 in 1975def CONSTPOOL_ENTRY : 1976PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1977 i32imm:$size), NoItinerary, []>; 1978 1979/// A jumptable consisting of direct 32-bit addresses of the destination basic 1980/// blocks (either absolute, or relative to the start of the jump-table in PIC 1981/// mode). Used mostly in ARM and Thumb-1 modes. 1982def JUMPTABLE_ADDRS : 1983PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1984 i32imm:$size), NoItinerary, []>; 1985 1986/// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables 1987/// that cannot be optimised to use TBB or TBH. 1988def JUMPTABLE_INSTS : 1989PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1990 i32imm:$size), NoItinerary, []>; 1991 1992/// A jumptable consisting of 8-bit unsigned integers representing offsets from 1993/// a TBB instruction. 1994def JUMPTABLE_TBB : 1995PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1996 i32imm:$size), NoItinerary, []>; 1997 1998/// A jumptable consisting of 16-bit unsigned integers representing offsets from 1999/// a TBH instruction. 2000def JUMPTABLE_TBH : 2001PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2002 i32imm:$size), NoItinerary, []>; 2003 2004 2005// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 2006// from removing one half of the matched pairs. That breaks PEI, which assumes 2007// these will always be in pairs, and asserts if it finds otherwise. Better way? 2008let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 2009def ADJCALLSTACKUP : 2010PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, 2011 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; 2012 2013def ADJCALLSTACKDOWN : 2014PseudoInst<(outs), (ins i32imm:$amt, i32imm:$amt2, pred:$p), NoItinerary, 2015 [(ARMcallseq_start timm:$amt, timm:$amt2)]>; 2016} 2017 2018def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary, 2019 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>, 2020 Requires<[IsARM, HasV6]> { 2021 bits<8> imm; 2022 let Inst{27-8} = 0b00110010000011110000; 2023 let Inst{7-0} = imm; 2024 let DecoderMethod = "DecodeHINTInstruction"; 2025} 2026 2027def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>; 2028def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>; 2029def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>; 2030def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>; 2031def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>; 2032def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>; 2033def : InstAlias<"esb$p", (HINT 16, pred:$p)>, Requires<[IsARM, HasRAS]>; 2034def : InstAlias<"csdb$p", (HINT 20, pred:$p)>, Requires<[IsARM, HasV6K]>; 2035 2036def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel", 2037 "\t$Rd, $Rn, $Rm", 2038 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>, 2039 Requires<[IsARM, HasV6]> { 2040 bits<4> Rd; 2041 bits<4> Rn; 2042 bits<4> Rm; 2043 let Inst{3-0} = Rm; 2044 let Inst{15-12} = Rd; 2045 let Inst{19-16} = Rn; 2046 let Inst{27-20} = 0b01101000; 2047 let Inst{7-4} = 0b1011; 2048 let Inst{11-8} = 0b1111; 2049 let Unpredictable{11-8} = 0b1111; 2050} 2051 2052// The 16-bit operand $val can be used by a debugger to store more information 2053// about the breakpoint. 2054def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 2055 "bkpt", "\t$val", []>, Requires<[IsARM]> { 2056 bits<16> val; 2057 let Inst{3-0} = val{3-0}; 2058 let Inst{19-8} = val{15-4}; 2059 let Inst{27-20} = 0b00010010; 2060 let Inst{31-28} = 0xe; // AL 2061 let Inst{7-4} = 0b0111; 2062} 2063// default immediate for breakpoint mnemonic 2064def : InstAlias<"bkpt", (BKPT 0), 0>, Requires<[IsARM]>; 2065 2066def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 2067 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> { 2068 bits<16> val; 2069 let Inst{3-0} = val{3-0}; 2070 let Inst{19-8} = val{15-4}; 2071 let Inst{27-20} = 0b00010000; 2072 let Inst{31-28} = 0xe; // AL 2073 let Inst{7-4} = 0b0111; 2074} 2075 2076// Change Processor State 2077// FIXME: We should use InstAlias to handle the optional operands. 2078class CPS<dag iops, string asm_ops> 2079 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops), 2080 []>, Requires<[IsARM]> { 2081 bits<2> imod; 2082 bits<3> iflags; 2083 bits<5> mode; 2084 bit M; 2085 2086 let Inst{31-28} = 0b1111; 2087 let Inst{27-20} = 0b00010000; 2088 let Inst{19-18} = imod; 2089 let Inst{17} = M; // Enabled if mode is set; 2090 let Inst{16-9} = 0b00000000; 2091 let Inst{8-6} = iflags; 2092 let Inst{5} = 0; 2093 let Inst{4-0} = mode; 2094} 2095 2096let DecoderMethod = "DecodeCPSInstruction" in { 2097let M = 1 in 2098 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode), 2099 "$imod\t$iflags, $mode">; 2100let mode = 0, M = 0 in 2101 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">; 2102 2103let imod = 0, iflags = 0, M = 1 in 2104 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">; 2105} 2106 2107// Preload signals the memory system of possible future data/instruction access. 2108multiclass APreLoad<bits<1> read, bits<1> data, string opc> { 2109 2110 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm, 2111 IIC_Preload, !strconcat(opc, "\t$addr"), 2112 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>, 2113 Sched<[WritePreLd]> { 2114 bits<4> Rt; 2115 bits<17> addr; 2116 let Inst{31-26} = 0b111101; 2117 let Inst{25} = 0; // 0 for immediate form 2118 let Inst{24} = data; 2119 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2120 let Inst{22} = read; 2121 let Inst{21-20} = 0b01; 2122 let Inst{19-16} = addr{16-13}; // Rn 2123 let Inst{15-12} = 0b1111; 2124 let Inst{11-0} = addr{11-0}; // imm12 2125 } 2126 2127 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, 2128 !strconcat(opc, "\t$shift"), 2129 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>, 2130 Sched<[WritePreLd]> { 2131 bits<17> shift; 2132 let Inst{31-26} = 0b111101; 2133 let Inst{25} = 1; // 1 for register form 2134 let Inst{24} = data; 2135 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2136 let Inst{22} = read; 2137 let Inst{21-20} = 0b01; 2138 let Inst{19-16} = shift{16-13}; // Rn 2139 let Inst{15-12} = 0b1111; 2140 let Inst{11-0} = shift{11-0}; 2141 let Inst{4} = 0; 2142 } 2143} 2144 2145defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>; 2146defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>; 2147defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>; 2148 2149def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary, 2150 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> { 2151 bits<1> end; 2152 let Inst{31-10} = 0b1111000100000001000000; 2153 let Inst{9} = end; 2154 let Inst{8-0} = 0; 2155} 2156 2157def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", 2158 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> { 2159 bits<4> opt; 2160 let Inst{27-4} = 0b001100100000111100001111; 2161 let Inst{3-0} = opt; 2162} 2163 2164// A8.8.247 UDF - Undefined (Encoding A1) 2165def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary, 2166 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> { 2167 bits<16> imm16; 2168 let Inst{31-28} = 0b1110; // AL 2169 let Inst{27-25} = 0b011; 2170 let Inst{24-20} = 0b11111; 2171 let Inst{19-8} = imm16{15-4}; 2172 let Inst{7-4} = 0b1111; 2173 let Inst{3-0} = imm16{3-0}; 2174} 2175 2176/* 2177 * A5.4 Permanently UNDEFINED instructions. 2178 * 2179 * For most targets use UDF #65006, for which the OS will generate SIGTRAP. 2180 * Other UDF encodings generate SIGILL. 2181 * 2182 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb. 2183 * Encoding A1: 2184 * 1110 0111 1111 iiii iiii iiii 1111 iiii 2185 * Encoding T1: 2186 * 1101 1110 iiii iiii 2187 * It uses the following encoding: 2188 * 1110 0111 1111 1110 1101 1110 1111 0000 2189 * - In ARM: UDF #60896; 2190 * - In Thumb: UDF #254 followed by a branch-to-self. 2191 */ 2192let isBarrier = 1, isTerminator = 1 in 2193def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary, 2194 "trap", [(trap)]>, 2195 Requires<[IsARM,UseNaClTrap]> { 2196 let Inst = 0xe7fedef0; 2197} 2198let isBarrier = 1, isTerminator = 1 in 2199def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, 2200 "trap", [(trap)]>, 2201 Requires<[IsARM,DontUseNaClTrap]> { 2202 let Inst = 0xe7ffdefe; 2203} 2204 2205def : Pat<(debugtrap), (BKPT 0)>, Requires<[IsARM, HasV5T]>; 2206def : Pat<(debugtrap), (UDF 254)>, Requires<[IsARM, NoV5T]>; 2207 2208// Address computation and loads and stores in PIC mode. 2209let isNotDuplicable = 1 in { 2210def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 2211 4, IIC_iALUr, 2212 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>, 2213 Sched<[WriteALU, ReadALU]>; 2214 2215let AddedComplexity = 10 in { 2216def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 2217 4, IIC_iLoad_r, 2218 [(set GPR:$dst, (load addrmodepc:$addr))]>; 2219 2220def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2221 4, IIC_iLoad_bh_r, 2222 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>; 2223 2224def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2225 4, IIC_iLoad_bh_r, 2226 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>; 2227 2228def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2229 4, IIC_iLoad_bh_r, 2230 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>; 2231 2232def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2233 4, IIC_iLoad_bh_r, 2234 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>; 2235} 2236let AddedComplexity = 10 in { 2237def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2238 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>; 2239 2240def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2241 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, 2242 addrmodepc:$addr)]>; 2243 2244def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2245 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 2246} 2247} // isNotDuplicable = 1 2248 2249 2250// LEApcrel - Load a pc-relative address into a register without offending the 2251// assembler. 2252let hasSideEffects = 0, isReMaterializable = 1 in 2253// The 'adr' mnemonic encodes differently if the label is before or after 2254// the instruction. The {24-21} opcode bits are set by the fixup, as we don't 2255// know until then which form of the instruction will be used. 2256def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), 2257 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>, 2258 Sched<[WriteALU, ReadALU]> { 2259 bits<4> Rd; 2260 bits<14> label; 2261 let Inst{27-25} = 0b001; 2262 let Inst{24} = 0; 2263 let Inst{23-22} = label{13-12}; 2264 let Inst{21} = 0; 2265 let Inst{20} = 0; 2266 let Inst{19-16} = 0b1111; 2267 let Inst{15-12} = Rd; 2268 let Inst{11-0} = label{11-0}; 2269} 2270 2271let hasSideEffects = 1 in { 2272def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 2273 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2274 2275def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd), 2276 (ins i32imm:$label, pred:$p), 2277 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2278} 2279 2280//===----------------------------------------------------------------------===// 2281// Control Flow Instructions. 2282// 2283 2284let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 2285 // ARMV4T and above 2286 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2287 "bx", "\tlr", [(ARMretflag)]>, 2288 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2289 let Inst{27-0} = 0b0001001011111111111100011110; 2290 } 2291 2292 // ARMV4 only 2293 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2294 "mov", "\tpc, lr", [(ARMretflag)]>, 2295 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> { 2296 let Inst{27-0} = 0b0001101000001111000000001110; 2297 } 2298 2299 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets 2300 // the user-space one). 2301 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p), 2302 4, IIC_Br, 2303 [(ARMintretflag imm:$offset)]>; 2304} 2305 2306// Indirect branches 2307let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 2308 // ARMV4T and above 2309 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst", 2310 [(brind GPR:$dst)]>, 2311 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2312 bits<4> dst; 2313 let Inst{31-4} = 0b1110000100101111111111110001; 2314 let Inst{3-0} = dst; 2315 } 2316 2317 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, 2318 "bx", "\t$dst", [/* pattern left blank */]>, 2319 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2320 bits<4> dst; 2321 let Inst{27-4} = 0b000100101111111111110001; 2322 let Inst{3-0} = dst; 2323 } 2324} 2325 2326// SP is marked as a use to prevent stack-pointer assignments that appear 2327// immediately before calls from potentially appearing dead. 2328let isCall = 1, 2329 // FIXME: Do we really need a non-predicated version? If so, it should 2330 // at least be a pseudo instruction expanding to the predicated version 2331 // at MC lowering time. 2332 Defs = [LR], Uses = [SP] in { 2333 def BL : ABXI<0b1011, (outs), (ins arm_bl_target:$func), 2334 IIC_Br, "bl\t$func", 2335 [(ARMcall tglobaladdr:$func)]>, 2336 Requires<[IsARM]>, Sched<[WriteBrL]> { 2337 let Inst{31-28} = 0b1110; 2338 bits<24> func; 2339 let Inst{23-0} = func; 2340 let DecoderMethod = "DecodeBranchImmInstruction"; 2341 } 2342 2343 def BL_pred : ABI<0b1011, (outs), (ins arm_bl_target:$func), 2344 IIC_Br, "bl", "\t$func", 2345 [(ARMcall_pred tglobaladdr:$func)]>, 2346 Requires<[IsARM]>, Sched<[WriteBrL]> { 2347 bits<24> func; 2348 let Inst{23-0} = func; 2349 let DecoderMethod = "DecodeBranchImmInstruction"; 2350 } 2351 2352 // ARMv5T and above 2353 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm, 2354 IIC_Br, "blx\t$func", 2355 [(ARMcall GPR:$func)]>, 2356 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2357 bits<4> func; 2358 let Inst{31-4} = 0b1110000100101111111111110011; 2359 let Inst{3-0} = func; 2360 } 2361 2362 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm, 2363 IIC_Br, "blx", "\t$func", 2364 [(ARMcall_pred GPR:$func)]>, 2365 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2366 bits<4> func; 2367 let Inst{27-4} = 0b000100101111111111110011; 2368 let Inst{3-0} = func; 2369 } 2370 2371 // ARMv4T 2372 // Note: Restrict $func to the tGPR regclass to prevent it being in LR. 2373 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2374 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2375 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>; 2376 2377 // ARMv4 2378 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2379 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2380 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 2381 2382 // mov lr, pc; b if callee is marked noreturn to avoid confusing the 2383 // return stack predictor. 2384 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins arm_bl_target:$func), 2385 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>, 2386 Requires<[IsARM]>, Sched<[WriteBr]>; 2387} 2388 2389let isBranch = 1, isTerminator = 1 in { 2390 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 2391 // a two-value operand where a dag node expects two operands. :( 2392 def Bcc : ABI<0b1010, (outs), (ins arm_br_target:$target), 2393 IIC_Br, "b", "\t$target", 2394 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>, 2395 Sched<[WriteBr]> { 2396 bits<24> target; 2397 let Inst{23-0} = target; 2398 let DecoderMethod = "DecodeBranchImmInstruction"; 2399 } 2400 2401 let isBarrier = 1 in { 2402 // B is "predicable" since it's just a Bcc with an 'always' condition. 2403 let isPredicable = 1 in 2404 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly 2405 // should be sufficient. 2406 // FIXME: Is B really a Barrier? That doesn't seem right. 2407 def B : ARMPseudoExpand<(outs), (ins arm_br_target:$target), 4, IIC_Br, 2408 [(br bb:$target)], (Bcc arm_br_target:$target, 2409 (ops 14, zero_reg))>, 2410 Sched<[WriteBr]>; 2411 2412 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in { 2413 def BR_JTr : ARMPseudoInst<(outs), 2414 (ins GPR:$target, i32imm:$jt), 2415 0, IIC_Br, 2416 [(ARMbrjt GPR:$target, tjumptable:$jt)]>, 2417 Sched<[WriteBr]>; 2418 def BR_JTm_i12 : ARMPseudoInst<(outs), 2419 (ins addrmode_imm12:$target, i32imm:$jt), 2420 0, IIC_Br, 2421 [(ARMbrjt (i32 (load addrmode_imm12:$target)), 2422 tjumptable:$jt)]>, Sched<[WriteBrTbl]>; 2423 def BR_JTm_rs : ARMPseudoInst<(outs), 2424 (ins ldst_so_reg:$target, i32imm:$jt), 2425 0, IIC_Br, 2426 [(ARMbrjt (i32 (load ldst_so_reg:$target)), 2427 tjumptable:$jt)]>, Sched<[WriteBrTbl]>; 2428 def BR_JTadd : ARMPseudoInst<(outs), 2429 (ins GPR:$target, GPR:$idx, i32imm:$jt), 2430 0, IIC_Br, 2431 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>, 2432 Sched<[WriteBrTbl]>; 2433 } // isNotDuplicable = 1, isIndirectBranch = 1 2434 } // isBarrier = 1 2435 2436} 2437 2438// BLX (immediate) 2439def BLXi : AXI<(outs), (ins arm_blx_target:$target), BrMiscFrm, NoItinerary, 2440 "blx\t$target", []>, 2441 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2442 let Inst{31-25} = 0b1111101; 2443 bits<25> target; 2444 let Inst{23-0} = target{24-1}; 2445 let Inst{24} = target{0}; 2446 let isCall = 1; 2447} 2448 2449// Branch and Exchange Jazelle 2450def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", 2451 [/* pattern left blank */]>, Sched<[WriteBr]> { 2452 bits<4> func; 2453 let Inst{23-20} = 0b0010; 2454 let Inst{19-8} = 0xfff; 2455 let Inst{7-4} = 0b0010; 2456 let Inst{3-0} = func; 2457 let isBranch = 1; 2458} 2459 2460// Tail calls. 2461 2462let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { 2463 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>, 2464 Sched<[WriteBr]>; 2465 2466 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>, 2467 Sched<[WriteBr]>; 2468 2469 def TAILJMPd : ARMPseudoExpand<(outs), (ins arm_br_target:$dst), 2470 4, IIC_Br, [], 2471 (Bcc arm_br_target:$dst, (ops 14, zero_reg))>, 2472 Requires<[IsARM]>, Sched<[WriteBr]>; 2473 2474 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst), 2475 4, IIC_Br, [], 2476 (BX GPR:$dst)>, Sched<[WriteBr]>, 2477 Requires<[IsARM, HasV4T]>; 2478} 2479 2480// Secure Monitor Call is a system instruction. 2481def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", 2482 []>, Requires<[IsARM, HasTrustZone]> { 2483 bits<4> opt; 2484 let Inst{23-4} = 0b01100000000000000111; 2485 let Inst{3-0} = opt; 2486} 2487def : MnemonicAlias<"smi", "smc">; 2488 2489// Supervisor Call (Software Interrupt) 2490let isCall = 1, Uses = [SP] in { 2491def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>, 2492 Sched<[WriteBr]> { 2493 bits<24> svc; 2494 let Inst{23-0} = svc; 2495} 2496} 2497 2498// Store Return State 2499class SRSI<bit wb, string asm> 2500 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm, 2501 NoItinerary, asm, "", []> { 2502 bits<5> mode; 2503 let Inst{31-28} = 0b1111; 2504 let Inst{27-25} = 0b100; 2505 let Inst{22} = 1; 2506 let Inst{21} = wb; 2507 let Inst{20} = 0; 2508 let Inst{19-16} = 0b1101; // SP 2509 let Inst{15-5} = 0b00000101000; 2510 let Inst{4-0} = mode; 2511} 2512 2513def SRSDA : SRSI<0, "srsda\tsp, $mode"> { 2514 let Inst{24-23} = 0; 2515} 2516def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> { 2517 let Inst{24-23} = 0; 2518} 2519def SRSDB : SRSI<0, "srsdb\tsp, $mode"> { 2520 let Inst{24-23} = 0b10; 2521} 2522def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> { 2523 let Inst{24-23} = 0b10; 2524} 2525def SRSIA : SRSI<0, "srsia\tsp, $mode"> { 2526 let Inst{24-23} = 0b01; 2527} 2528def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> { 2529 let Inst{24-23} = 0b01; 2530} 2531def SRSIB : SRSI<0, "srsib\tsp, $mode"> { 2532 let Inst{24-23} = 0b11; 2533} 2534def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> { 2535 let Inst{24-23} = 0b11; 2536} 2537 2538def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>; 2539def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>; 2540 2541def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>; 2542def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>; 2543 2544def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>; 2545def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>; 2546 2547def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>; 2548def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>; 2549 2550// Return From Exception 2551class RFEI<bit wb, string asm> 2552 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm, 2553 NoItinerary, asm, "", []> { 2554 bits<4> Rn; 2555 let Inst{31-28} = 0b1111; 2556 let Inst{27-25} = 0b100; 2557 let Inst{22} = 0; 2558 let Inst{21} = wb; 2559 let Inst{20} = 1; 2560 let Inst{19-16} = Rn; 2561 let Inst{15-0} = 0xa00; 2562} 2563 2564def RFEDA : RFEI<0, "rfeda\t$Rn"> { 2565 let Inst{24-23} = 0; 2566} 2567def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> { 2568 let Inst{24-23} = 0; 2569} 2570def RFEDB : RFEI<0, "rfedb\t$Rn"> { 2571 let Inst{24-23} = 0b10; 2572} 2573def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> { 2574 let Inst{24-23} = 0b10; 2575} 2576def RFEIA : RFEI<0, "rfeia\t$Rn"> { 2577 let Inst{24-23} = 0b01; 2578} 2579def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> { 2580 let Inst{24-23} = 0b01; 2581} 2582def RFEIB : RFEI<0, "rfeib\t$Rn"> { 2583 let Inst{24-23} = 0b11; 2584} 2585def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> { 2586 let Inst{24-23} = 0b11; 2587} 2588 2589// Hypervisor Call is a system instruction 2590let isCall = 1 in { 2591def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary, 2592 "hvc", "\t$imm", []>, 2593 Requires<[IsARM, HasVirtualization]> { 2594 bits<16> imm; 2595 2596 // Even though HVC isn't predicable, it's encoding includes a condition field. 2597 // The instruction is undefined if the condition field is 0xf otherwise it is 2598 // unpredictable if it isn't condition AL (0xe). 2599 let Inst{31-28} = 0b1110; 2600 let Unpredictable{31-28} = 0b1111; 2601 let Inst{27-24} = 0b0001; 2602 let Inst{23-20} = 0b0100; 2603 let Inst{19-8} = imm{15-4}; 2604 let Inst{7-4} = 0b0111; 2605 let Inst{3-0} = imm{3-0}; 2606} 2607} 2608 2609// Return from exception in Hypervisor mode. 2610let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in 2611def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>, 2612 Requires<[IsARM, HasVirtualization]> { 2613 let Inst{23-0} = 0b011000000000000001101110; 2614} 2615 2616//===----------------------------------------------------------------------===// 2617// Load / Store Instructions. 2618// 2619 2620// Load 2621 2622 2623defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si, load>; 2624defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si, 2625 zextloadi8>; 2626defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si, store>; 2627defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si, 2628 truncstorei8>; 2629 2630// Special LDR for loads from non-pc-relative constpools. 2631let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0, 2632 isReMaterializable = 1, isCodeGenOnly = 1 in 2633def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 2634 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", 2635 []> { 2636 bits<4> Rt; 2637 bits<17> addr; 2638 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2639 let Inst{19-16} = 0b1111; 2640 let Inst{15-12} = Rt; 2641 let Inst{11-0} = addr{11-0}; // imm12 2642} 2643 2644// Loads with zero extension 2645def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2646 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr", 2647 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>; 2648 2649// Loads with sign extension 2650def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2651 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr", 2652 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>; 2653 2654def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2655 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr", 2656 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>; 2657 2658let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in { 2659 // Load doubleword 2660 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr), 2661 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>, 2662 Requires<[IsARM, HasV5TE]>; 2663} 2664 2665def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2666 NoItinerary, "lda", "\t$Rt, $addr", []>; 2667def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2668 NoItinerary, "ldab", "\t$Rt, $addr", []>; 2669def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2670 NoItinerary, "ldah", "\t$Rt, $addr", []>; 2671 2672// Indexed loads 2673multiclass AI2_ldridx<bit isByte, string opc, 2674 InstrItinClass iii, InstrItinClass iir> { 2675 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2676 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii, 2677 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2678 bits<17> addr; 2679 let Inst{25} = 0; 2680 let Inst{23} = addr{12}; 2681 let Inst{19-16} = addr{16-13}; 2682 let Inst{11-0} = addr{11-0}; 2683 let DecoderMethod = "DecodeLDRPreImm"; 2684 } 2685 2686 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2687 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir, 2688 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2689 bits<17> addr; 2690 let Inst{25} = 1; 2691 let Inst{23} = addr{12}; 2692 let Inst{19-16} = addr{16-13}; 2693 let Inst{11-0} = addr{11-0}; 2694 let Inst{4} = 0; 2695 let DecoderMethod = "DecodeLDRPreReg"; 2696 } 2697 2698 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2699 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2700 IndexModePost, LdFrm, iir, 2701 opc, "\t$Rt, $addr, $offset", 2702 "$addr.base = $Rn_wb", []> { 2703 // {12} isAdd 2704 // {11-0} imm12/Rm 2705 bits<14> offset; 2706 bits<4> addr; 2707 let Inst{25} = 1; 2708 let Inst{23} = offset{12}; 2709 let Inst{19-16} = addr; 2710 let Inst{11-0} = offset{11-0}; 2711 let Inst{4} = 0; 2712 2713 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2714 } 2715 2716 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2717 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2718 IndexModePost, LdFrm, iii, 2719 opc, "\t$Rt, $addr, $offset", 2720 "$addr.base = $Rn_wb", []> { 2721 // {12} isAdd 2722 // {11-0} imm12/Rm 2723 bits<14> offset; 2724 bits<4> addr; 2725 let Inst{25} = 0; 2726 let Inst{23} = offset{12}; 2727 let Inst{19-16} = addr; 2728 let Inst{11-0} = offset{11-0}; 2729 2730 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2731 } 2732 2733} 2734 2735let mayLoad = 1, hasSideEffects = 0 in { 2736// FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or 2737// IIC_iLoad_siu depending on whether it the offset register is shifted. 2738defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>; 2739defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>; 2740} 2741 2742multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> { 2743 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2744 (ins addrmode3_pre:$addr), IndexModePre, 2745 LdMiscFrm, itin, 2746 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2747 bits<14> addr; 2748 let Inst{23} = addr{8}; // U bit 2749 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2750 let Inst{19-16} = addr{12-9}; // Rn 2751 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2752 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2753 let DecoderMethod = "DecodeAddrMode3Instruction"; 2754 } 2755 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2756 (ins addr_offset_none:$addr, am3offset:$offset), 2757 IndexModePost, LdMiscFrm, itin, 2758 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2759 []> { 2760 bits<10> offset; 2761 bits<4> addr; 2762 let Inst{23} = offset{8}; // U bit 2763 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2764 let Inst{19-16} = addr; 2765 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2766 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2767 let DecoderMethod = "DecodeAddrMode3Instruction"; 2768 } 2769} 2770 2771let mayLoad = 1, hasSideEffects = 0 in { 2772defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>; 2773defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>; 2774defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>; 2775let hasExtraDefRegAllocReq = 1 in { 2776def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2777 (ins addrmode3_pre:$addr), IndexModePre, 2778 LdMiscFrm, IIC_iLoad_d_ru, 2779 "ldrd", "\t$Rt, $Rt2, $addr!", 2780 "$addr.base = $Rn_wb", []> { 2781 bits<14> addr; 2782 let Inst{23} = addr{8}; // U bit 2783 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2784 let Inst{19-16} = addr{12-9}; // Rn 2785 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2786 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2787 let DecoderMethod = "DecodeAddrMode3Instruction"; 2788} 2789def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2790 (ins addr_offset_none:$addr, am3offset:$offset), 2791 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru, 2792 "ldrd", "\t$Rt, $Rt2, $addr, $offset", 2793 "$addr.base = $Rn_wb", []> { 2794 bits<10> offset; 2795 bits<4> addr; 2796 let Inst{23} = offset{8}; // U bit 2797 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2798 let Inst{19-16} = addr; 2799 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2800 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2801 let DecoderMethod = "DecodeAddrMode3Instruction"; 2802} 2803} // hasExtraDefRegAllocReq = 1 2804} // mayLoad = 1, hasSideEffects = 0 2805 2806// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT. 2807let mayLoad = 1, hasSideEffects = 0 in { 2808def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2809 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2810 IndexModePost, LdFrm, IIC_iLoad_ru, 2811 "ldrt", "\t$Rt, $addr, $offset", 2812 "$addr.base = $Rn_wb", []> { 2813 // {12} isAdd 2814 // {11-0} imm12/Rm 2815 bits<14> offset; 2816 bits<4> addr; 2817 let Inst{25} = 1; 2818 let Inst{23} = offset{12}; 2819 let Inst{21} = 1; // overwrite 2820 let Inst{19-16} = addr; 2821 let Inst{11-5} = offset{11-5}; 2822 let Inst{4} = 0; 2823 let Inst{3-0} = offset{3-0}; 2824 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2825} 2826 2827def LDRT_POST_IMM 2828 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2829 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2830 IndexModePost, LdFrm, IIC_iLoad_ru, 2831 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2832 // {12} isAdd 2833 // {11-0} imm12/Rm 2834 bits<14> offset; 2835 bits<4> addr; 2836 let Inst{25} = 0; 2837 let Inst{23} = offset{12}; 2838 let Inst{21} = 1; // overwrite 2839 let Inst{19-16} = addr; 2840 let Inst{11-0} = offset{11-0}; 2841 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2842} 2843 2844def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2845 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2846 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2847 "ldrbt", "\t$Rt, $addr, $offset", 2848 "$addr.base = $Rn_wb", []> { 2849 // {12} isAdd 2850 // {11-0} imm12/Rm 2851 bits<14> offset; 2852 bits<4> addr; 2853 let Inst{25} = 1; 2854 let Inst{23} = offset{12}; 2855 let Inst{21} = 1; // overwrite 2856 let Inst{19-16} = addr; 2857 let Inst{11-5} = offset{11-5}; 2858 let Inst{4} = 0; 2859 let Inst{3-0} = offset{3-0}; 2860 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2861} 2862 2863def LDRBT_POST_IMM 2864 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2865 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2866 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2867 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2868 // {12} isAdd 2869 // {11-0} imm12/Rm 2870 bits<14> offset; 2871 bits<4> addr; 2872 let Inst{25} = 0; 2873 let Inst{23} = offset{12}; 2874 let Inst{21} = 1; // overwrite 2875 let Inst{19-16} = addr; 2876 let Inst{11-0} = offset{11-0}; 2877 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2878} 2879 2880multiclass AI3ldrT<bits<4> op, string opc> { 2881 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb), 2882 (ins addr_offset_none:$addr, postidx_imm8:$offset), 2883 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2884 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 2885 bits<9> offset; 2886 let Inst{23} = offset{8}; 2887 let Inst{22} = 1; 2888 let Inst{11-8} = offset{7-4}; 2889 let Inst{3-0} = offset{3-0}; 2890 } 2891 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb), 2892 (ins addr_offset_none:$addr, postidx_reg:$Rm), 2893 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2894 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 2895 bits<5> Rm; 2896 let Inst{23} = Rm{4}; 2897 let Inst{22} = 0; 2898 let Inst{11-8} = 0; 2899 let Unpredictable{11-8} = 0b1111; 2900 let Inst{3-0} = Rm{3-0}; 2901 let DecoderMethod = "DecodeLDR"; 2902 } 2903} 2904 2905defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">; 2906defm LDRHT : AI3ldrT<0b1011, "ldrht">; 2907defm LDRSHT : AI3ldrT<0b1111, "ldrsht">; 2908} 2909 2910def LDRT_POST 2911 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2912 (outs GPR:$Rt)>; 2913 2914def LDRBT_POST 2915 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2916 (outs GPR:$Rt)>; 2917 2918// Pseudo instruction ldr Rt, =immediate 2919def LDRConstPool 2920 : ARMAsmPseudo<"ldr${q} $Rt, $immediate", 2921 (ins const_pool_asm_imm:$immediate, pred:$q), 2922 (outs GPR:$Rt)>; 2923 2924// Store 2925 2926// Stores with truncate 2927def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, 2928 IIC_iStore_bh_r, "strh", "\t$Rt, $addr", 2929 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>; 2930 2931// Store doubleword 2932let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 2933 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr), 2934 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>, 2935 Requires<[IsARM, HasV5TE]> { 2936 let Inst{21} = 0; 2937 } 2938} 2939 2940// Indexed stores 2941multiclass AI2_stridx<bit isByte, string opc, 2942 InstrItinClass iii, InstrItinClass iir> { 2943 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2944 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre, 2945 StFrm, iii, 2946 opc, "\t$Rt, $addr!", 2947 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2948 bits<17> addr; 2949 let Inst{25} = 0; 2950 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2951 let Inst{19-16} = addr{16-13}; // Rn 2952 let Inst{11-0} = addr{11-0}; // imm12 2953 let DecoderMethod = "DecodeSTRPreImm"; 2954 } 2955 2956 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2957 (ins GPR:$Rt, ldst_so_reg:$addr), 2958 IndexModePre, StFrm, iir, 2959 opc, "\t$Rt, $addr!", 2960 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2961 bits<17> addr; 2962 let Inst{25} = 1; 2963 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2964 let Inst{19-16} = addr{16-13}; // Rn 2965 let Inst{11-0} = addr{11-0}; 2966 let Inst{4} = 0; // Inst{4} = 0 2967 let DecoderMethod = "DecodeSTRPreReg"; 2968 } 2969 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2970 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2971 IndexModePost, StFrm, iir, 2972 opc, "\t$Rt, $addr, $offset", 2973 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2974 // {12} isAdd 2975 // {11-0} imm12/Rm 2976 bits<14> offset; 2977 bits<4> addr; 2978 let Inst{25} = 1; 2979 let Inst{23} = offset{12}; 2980 let Inst{19-16} = addr; 2981 let Inst{11-0} = offset{11-0}; 2982 let Inst{4} = 0; 2983 2984 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2985 } 2986 2987 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2988 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2989 IndexModePost, StFrm, iii, 2990 opc, "\t$Rt, $addr, $offset", 2991 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2992 // {12} isAdd 2993 // {11-0} imm12/Rm 2994 bits<14> offset; 2995 bits<4> addr; 2996 let Inst{25} = 0; 2997 let Inst{23} = offset{12}; 2998 let Inst{19-16} = addr; 2999 let Inst{11-0} = offset{11-0}; 3000 3001 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3002 } 3003} 3004 3005let mayStore = 1, hasSideEffects = 0 in { 3006// FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or 3007// IIC_iStore_siu depending on whether it the offset register is shifted. 3008defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>; 3009defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>; 3010} 3011 3012def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 3013 am2offset_reg:$offset), 3014 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr, 3015 am2offset_reg:$offset)>; 3016def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 3017 am2offset_imm:$offset), 3018 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr, 3019 am2offset_imm:$offset)>; 3020def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 3021 am2offset_reg:$offset), 3022 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr, 3023 am2offset_reg:$offset)>; 3024def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 3025 am2offset_imm:$offset), 3026 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr, 3027 am2offset_imm:$offset)>; 3028 3029// Pseudo-instructions for pattern matching the pre-indexed stores. We can't 3030// put the patterns on the instruction definitions directly as ISel wants 3031// the address base and offset to be separate operands, not a single 3032// complex operand like we represent the instructions themselves. The 3033// pseudos map between the two. 3034let usesCustomInserter = 1, 3035 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 3036def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3037 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 3038 4, IIC_iStore_ru, 3039 [(set GPR:$Rn_wb, 3040 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 3041def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3042 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 3043 4, IIC_iStore_ru, 3044 [(set GPR:$Rn_wb, 3045 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 3046def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3047 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 3048 4, IIC_iStore_ru, 3049 [(set GPR:$Rn_wb, 3050 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 3051def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3052 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 3053 4, IIC_iStore_ru, 3054 [(set GPR:$Rn_wb, 3055 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 3056def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3057 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p), 3058 4, IIC_iStore_ru, 3059 [(set GPR:$Rn_wb, 3060 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>; 3061} 3062 3063 3064 3065def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb), 3066 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre, 3067 StMiscFrm, IIC_iStore_bh_ru, 3068 "strh", "\t$Rt, $addr!", 3069 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3070 bits<14> addr; 3071 let Inst{23} = addr{8}; // U bit 3072 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 3073 let Inst{19-16} = addr{12-9}; // Rn 3074 let Inst{11-8} = addr{7-4}; // imm7_4/zero 3075 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 3076 let DecoderMethod = "DecodeAddrMode3Instruction"; 3077} 3078 3079def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb), 3080 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset), 3081 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, 3082 "strh", "\t$Rt, $addr, $offset", 3083 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", 3084 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt, 3085 addr_offset_none:$addr, 3086 am3offset:$offset))]> { 3087 bits<10> offset; 3088 bits<4> addr; 3089 let Inst{23} = offset{8}; // U bit 3090 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 3091 let Inst{19-16} = addr; 3092 let Inst{11-8} = offset{7-4}; // imm7_4/zero 3093 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 3094 let DecoderMethod = "DecodeAddrMode3Instruction"; 3095} 3096 3097let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 3098def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb), 3099 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr), 3100 IndexModePre, StMiscFrm, IIC_iStore_d_ru, 3101 "strd", "\t$Rt, $Rt2, $addr!", 3102 "$addr.base = $Rn_wb", []> { 3103 bits<14> addr; 3104 let Inst{23} = addr{8}; // U bit 3105 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 3106 let Inst{19-16} = addr{12-9}; // Rn 3107 let Inst{11-8} = addr{7-4}; // imm7_4/zero 3108 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 3109 let DecoderMethod = "DecodeAddrMode3Instruction"; 3110} 3111 3112def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb), 3113 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr, 3114 am3offset:$offset), 3115 IndexModePost, StMiscFrm, IIC_iStore_d_ru, 3116 "strd", "\t$Rt, $Rt2, $addr, $offset", 3117 "$addr.base = $Rn_wb", []> { 3118 bits<10> offset; 3119 bits<4> addr; 3120 let Inst{23} = offset{8}; // U bit 3121 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 3122 let Inst{19-16} = addr; 3123 let Inst{11-8} = offset{7-4}; // imm7_4/zero 3124 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 3125 let DecoderMethod = "DecodeAddrMode3Instruction"; 3126} 3127} // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 3128 3129// STRT, STRBT, and STRHT 3130 3131def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3132 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3133 IndexModePost, StFrm, IIC_iStore_bh_ru, 3134 "strbt", "\t$Rt, $addr, $offset", 3135 "$addr.base = $Rn_wb", []> { 3136 // {12} isAdd 3137 // {11-0} imm12/Rm 3138 bits<14> offset; 3139 bits<4> addr; 3140 let Inst{25} = 1; 3141 let Inst{23} = offset{12}; 3142 let Inst{21} = 1; // overwrite 3143 let Inst{19-16} = addr; 3144 let Inst{11-5} = offset{11-5}; 3145 let Inst{4} = 0; 3146 let Inst{3-0} = offset{3-0}; 3147 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3148} 3149 3150def STRBT_POST_IMM 3151 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3152 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3153 IndexModePost, StFrm, IIC_iStore_bh_ru, 3154 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3155 // {12} isAdd 3156 // {11-0} imm12/Rm 3157 bits<14> offset; 3158 bits<4> addr; 3159 let Inst{25} = 0; 3160 let Inst{23} = offset{12}; 3161 let Inst{21} = 1; // overwrite 3162 let Inst{19-16} = addr; 3163 let Inst{11-0} = offset{11-0}; 3164 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3165} 3166 3167def STRBT_POST 3168 : ARMAsmPseudo<"strbt${q} $Rt, $addr", 3169 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3170 3171let mayStore = 1, hasSideEffects = 0 in { 3172def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3173 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3174 IndexModePost, StFrm, IIC_iStore_ru, 3175 "strt", "\t$Rt, $addr, $offset", 3176 "$addr.base = $Rn_wb", []> { 3177 // {12} isAdd 3178 // {11-0} imm12/Rm 3179 bits<14> offset; 3180 bits<4> addr; 3181 let Inst{25} = 1; 3182 let Inst{23} = offset{12}; 3183 let Inst{21} = 1; // overwrite 3184 let Inst{19-16} = addr; 3185 let Inst{11-5} = offset{11-5}; 3186 let Inst{4} = 0; 3187 let Inst{3-0} = offset{3-0}; 3188 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3189} 3190 3191def STRT_POST_IMM 3192 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3193 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3194 IndexModePost, StFrm, IIC_iStore_ru, 3195 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3196 // {12} isAdd 3197 // {11-0} imm12/Rm 3198 bits<14> offset; 3199 bits<4> addr; 3200 let Inst{25} = 0; 3201 let Inst{23} = offset{12}; 3202 let Inst{21} = 1; // overwrite 3203 let Inst{19-16} = addr; 3204 let Inst{11-0} = offset{11-0}; 3205 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3206} 3207} 3208 3209def STRT_POST 3210 : ARMAsmPseudo<"strt${q} $Rt, $addr", 3211 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3212 3213multiclass AI3strT<bits<4> op, string opc> { 3214 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3215 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset), 3216 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3217 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 3218 bits<9> offset; 3219 let Inst{23} = offset{8}; 3220 let Inst{22} = 1; 3221 let Inst{11-8} = offset{7-4}; 3222 let Inst{3-0} = offset{3-0}; 3223 } 3224 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3225 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm), 3226 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3227 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 3228 bits<5> Rm; 3229 let Inst{23} = Rm{4}; 3230 let Inst{22} = 0; 3231 let Inst{11-8} = 0; 3232 let Inst{3-0} = Rm{3-0}; 3233 } 3234} 3235 3236 3237defm STRHT : AI3strT<0b1011, "strht">; 3238 3239def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3240 NoItinerary, "stl", "\t$Rt, $addr", []>; 3241def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3242 NoItinerary, "stlb", "\t$Rt, $addr", []>; 3243def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3244 NoItinerary, "stlh", "\t$Rt, $addr", []>; 3245 3246//===----------------------------------------------------------------------===// 3247// Load / store multiple Instructions. 3248// 3249 3250multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f, 3251 InstrItinClass itin, InstrItinClass itin_upd> { 3252 // IA is the default, so no need for an explicit suffix on the 3253 // mnemonic here. Without it is the canonical spelling. 3254 def IA : 3255 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3256 IndexModeNone, f, itin, 3257 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> { 3258 let Inst{24-23} = 0b01; // Increment After 3259 let Inst{22} = P_bit; 3260 let Inst{21} = 0; // No writeback 3261 let Inst{20} = L_bit; 3262 } 3263 def IA_UPD : 3264 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3265 IndexModeUpd, f, itin_upd, 3266 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3267 let Inst{24-23} = 0b01; // Increment After 3268 let Inst{22} = P_bit; 3269 let Inst{21} = 1; // Writeback 3270 let Inst{20} = L_bit; 3271 3272 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3273 } 3274 def DA : 3275 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3276 IndexModeNone, f, itin, 3277 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> { 3278 let Inst{24-23} = 0b00; // Decrement After 3279 let Inst{22} = P_bit; 3280 let Inst{21} = 0; // No writeback 3281 let Inst{20} = L_bit; 3282 } 3283 def DA_UPD : 3284 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3285 IndexModeUpd, f, itin_upd, 3286 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3287 let Inst{24-23} = 0b00; // Decrement After 3288 let Inst{22} = P_bit; 3289 let Inst{21} = 1; // Writeback 3290 let Inst{20} = L_bit; 3291 3292 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3293 } 3294 def DB : 3295 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3296 IndexModeNone, f, itin, 3297 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> { 3298 let Inst{24-23} = 0b10; // Decrement Before 3299 let Inst{22} = P_bit; 3300 let Inst{21} = 0; // No writeback 3301 let Inst{20} = L_bit; 3302 } 3303 def DB_UPD : 3304 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3305 IndexModeUpd, f, itin_upd, 3306 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3307 let Inst{24-23} = 0b10; // Decrement Before 3308 let Inst{22} = P_bit; 3309 let Inst{21} = 1; // Writeback 3310 let Inst{20} = L_bit; 3311 3312 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3313 } 3314 def IB : 3315 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3316 IndexModeNone, f, itin, 3317 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> { 3318 let Inst{24-23} = 0b11; // Increment Before 3319 let Inst{22} = P_bit; 3320 let Inst{21} = 0; // No writeback 3321 let Inst{20} = L_bit; 3322 } 3323 def IB_UPD : 3324 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3325 IndexModeUpd, f, itin_upd, 3326 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3327 let Inst{24-23} = 0b11; // Increment Before 3328 let Inst{22} = P_bit; 3329 let Inst{21} = 1; // Writeback 3330 let Inst{20} = L_bit; 3331 3332 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3333 } 3334} 3335 3336let hasSideEffects = 0 in { 3337 3338let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in 3339defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m, 3340 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">; 3341 3342let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3343defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m, 3344 IIC_iStore_mu>, 3345 ComplexDeprecationPredicate<"ARMStore">; 3346 3347} // hasSideEffects 3348 3349// FIXME: remove when we have a way to marking a MI with these properties. 3350// FIXME: Should pc be an implicit operand like PICADD, etc? 3351let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 3352 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 3353def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 3354 reglist:$regs, variable_ops), 3355 4, IIC_iLoad_mBr, [], 3356 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 3357 RegConstraint<"$Rn = $wb">; 3358 3359let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 3360defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m, 3361 IIC_iLoad_mu>; 3362 3363let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3364defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m, 3365 IIC_iStore_mu>; 3366 3367 3368 3369//===----------------------------------------------------------------------===// 3370// Move Instructions. 3371// 3372 3373let hasSideEffects = 0, isMoveReg = 1 in 3374def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr, 3375 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3376 bits<4> Rd; 3377 bits<4> Rm; 3378 3379 let Inst{19-16} = 0b0000; 3380 let Inst{11-4} = 0b00000000; 3381 let Inst{25} = 0; 3382 let Inst{3-0} = Rm; 3383 let Inst{15-12} = Rd; 3384} 3385 3386// A version for the smaller set of tail call registers. 3387let hasSideEffects = 0 in 3388def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, 3389 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3390 bits<4> Rd; 3391 bits<4> Rm; 3392 3393 let Inst{11-4} = 0b00000000; 3394 let Inst{25} = 0; 3395 let Inst{3-0} = Rm; 3396 let Inst{15-12} = Rd; 3397} 3398 3399def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src), 3400 DPSoRegRegFrm, IIC_iMOVsr, 3401 "mov", "\t$Rd, $src", 3402 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP, 3403 Sched<[WriteALU]> { 3404 bits<4> Rd; 3405 bits<12> src; 3406 let Inst{15-12} = Rd; 3407 let Inst{19-16} = 0b0000; 3408 let Inst{11-8} = src{11-8}; 3409 let Inst{7} = 0; 3410 let Inst{6-5} = src{6-5}; 3411 let Inst{4} = 1; 3412 let Inst{3-0} = src{3-0}; 3413 let Inst{25} = 0; 3414} 3415 3416def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src), 3417 DPSoRegImmFrm, IIC_iMOVsr, 3418 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>, 3419 UnaryDP, Sched<[WriteALU]> { 3420 bits<4> Rd; 3421 bits<12> src; 3422 let Inst{15-12} = Rd; 3423 let Inst{19-16} = 0b0000; 3424 let Inst{11-5} = src{11-5}; 3425 let Inst{4} = 0; 3426 let Inst{3-0} = src{3-0}; 3427 let Inst{25} = 0; 3428} 3429 3430let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3431def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi, 3432 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP, 3433 Sched<[WriteALU]> { 3434 bits<4> Rd; 3435 bits<12> imm; 3436 let Inst{25} = 1; 3437 let Inst{15-12} = Rd; 3438 let Inst{19-16} = 0b0000; 3439 let Inst{11-0} = imm; 3440} 3441 3442let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3443def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm), 3444 DPFrm, IIC_iMOVi, 3445 "movw", "\t$Rd, $imm", 3446 [(set GPR:$Rd, imm0_65535:$imm)]>, 3447 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> { 3448 bits<4> Rd; 3449 bits<16> imm; 3450 let Inst{15-12} = Rd; 3451 let Inst{11-0} = imm{11-0}; 3452 let Inst{19-16} = imm{15-12}; 3453 let Inst{20} = 0; 3454 let Inst{25} = 1; 3455 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3456} 3457 3458def : InstAlias<"mov${p} $Rd, $imm", 3459 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p), 0>, 3460 Requires<[IsARM, HasV6T2]>; 3461 3462def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3463 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3464 Sched<[WriteALU]>; 3465 3466let Constraints = "$src = $Rd" in { 3467def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd), 3468 (ins GPR:$src, imm0_65535_expr:$imm), 3469 DPFrm, IIC_iMOVi, 3470 "movt", "\t$Rd, $imm", 3471 [(set GPRnopc:$Rd, 3472 (or (and GPR:$src, 0xffff), 3473 lo16AllZero:$imm))]>, UnaryDP, 3474 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> { 3475 bits<4> Rd; 3476 bits<16> imm; 3477 let Inst{15-12} = Rd; 3478 let Inst{11-0} = imm{11-0}; 3479 let Inst{19-16} = imm{15-12}; 3480 let Inst{20} = 0; 3481 let Inst{25} = 1; 3482 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3483} 3484 3485def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3486 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3487 Sched<[WriteALU]>; 3488 3489} // Constraints 3490 3491def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>, 3492 Requires<[IsARM, HasV6T2]>; 3493 3494let Uses = [CPSR] in 3495def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, 3496 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP, 3497 Requires<[IsARM]>, Sched<[WriteALU]>; 3498 3499// These aren't really mov instructions, but we have to define them this way 3500// due to flag operands. 3501 3502let Defs = [CPSR] in { 3503def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3504 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP, 3505 Sched<[WriteALU]>, Requires<[IsARM]>; 3506def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3507 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP, 3508 Sched<[WriteALU]>, Requires<[IsARM]>; 3509} 3510 3511//===----------------------------------------------------------------------===// 3512// Extend Instructions. 3513// 3514 3515// Sign extenders 3516 3517def SXTB : AI_ext_rrot<0b01101010, 3518 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 3519def SXTH : AI_ext_rrot<0b01101011, 3520 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 3521 3522def SXTAB : AI_exta_rrot<0b01101010, 3523 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 3524def SXTAH : AI_exta_rrot<0b01101011, 3525 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 3526 3527def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8)), 3528 (SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3529def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot), 3530 i16)), 3531 (SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3532 3533def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; 3534def : ARMV6Pat<(int_arm_sxtb16 GPR:$Src), 3535 (SXTB16 GPR:$Src, 0)>; 3536def : ARMV6Pat<(int_arm_sxtb16 (rotr GPR:$Src, rot_imm:$rot)), 3537 (SXTB16 GPR:$Src, rot_imm:$rot)>; 3538 3539def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; 3540def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, GPR:$RHS), 3541 (SXTAB16 GPR:$LHS, GPR:$RHS, 0)>; 3542def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)), 3543 (SXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>; 3544 3545// Zero extenders 3546 3547let AddedComplexity = 16 in { 3548def UXTB : AI_ext_rrot<0b01101110, 3549 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 3550def UXTH : AI_ext_rrot<0b01101111, 3551 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 3552def UXTB16 : AI_ext_rrot<0b01101100, 3553 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 3554 3555// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 3556// The transformation should probably be done as a combiner action 3557// instead so we can include a check for masking back in the upper 3558// eight bits of the source into the lower eight bits of the result. 3559//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 3560// (UXTB16r_rot GPR:$Src, 3)>; 3561def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 3562 (UXTB16 GPR:$Src, 1)>; 3563def : ARMV6Pat<(int_arm_uxtb16 GPR:$Src), 3564 (UXTB16 GPR:$Src, 0)>; 3565def : ARMV6Pat<(int_arm_uxtb16 (rotr GPR:$Src, rot_imm:$rot)), 3566 (UXTB16 GPR:$Src, rot_imm:$rot)>; 3567 3568def UXTAB : AI_exta_rrot<0b01101110, "uxtab", 3569 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 3570def UXTAH : AI_exta_rrot<0b01101111, "uxtah", 3571 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 3572 3573def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 0xFF)), 3574 (UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3575def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 0xFFFF)), 3576 (UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3577} 3578 3579// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 3580def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; 3581def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, GPR:$RHS), 3582 (UXTAB16 GPR:$LHS, GPR:$RHS, 0)>; 3583def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)), 3584 (UXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>; 3585 3586 3587def SBFX : I<(outs GPRnopc:$Rd), 3588 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3589 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3590 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3591 Requires<[IsARM, HasV6T2]> { 3592 bits<4> Rd; 3593 bits<4> Rn; 3594 bits<5> lsb; 3595 bits<5> width; 3596 let Inst{27-21} = 0b0111101; 3597 let Inst{6-4} = 0b101; 3598 let Inst{20-16} = width; 3599 let Inst{15-12} = Rd; 3600 let Inst{11-7} = lsb; 3601 let Inst{3-0} = Rn; 3602} 3603 3604def UBFX : I<(outs GPRnopc:$Rd), 3605 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3606 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3607 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3608 Requires<[IsARM, HasV6T2]> { 3609 bits<4> Rd; 3610 bits<4> Rn; 3611 bits<5> lsb; 3612 bits<5> width; 3613 let Inst{27-21} = 0b0111111; 3614 let Inst{6-4} = 0b101; 3615 let Inst{20-16} = width; 3616 let Inst{15-12} = Rd; 3617 let Inst{11-7} = lsb; 3618 let Inst{3-0} = Rn; 3619} 3620 3621//===----------------------------------------------------------------------===// 3622// Arithmetic Instructions. 3623// 3624 3625let isAdd = 1 in 3626defm ADD : AsI1_bin_irs<0b0100, "add", 3627 IIC_iALUi, IIC_iALUr, IIC_iALUsr, add, 1>; 3628defm SUB : AsI1_bin_irs<0b0010, "sub", 3629 IIC_iALUi, IIC_iALUr, IIC_iALUsr, sub>; 3630 3631// ADD and SUB with 's' bit set. 3632// 3633// Currently, ADDS/SUBS are pseudo opcodes that exist only in the 3634// selection DAG. They are "lowered" to real ADD/SUB opcodes by 3635// AdjustInstrPostInstrSelection where we determine whether or not to 3636// set the "s" bit based on CPSR liveness. 3637// 3638// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen 3639// support for an optional CPSR definition that corresponds to the DAG 3640// node's second value. We can then eliminate the implicit def of CPSR. 3641let isAdd = 1 in 3642defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMaddc, 1>; 3643defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>; 3644 3645def : ARMPat<(ARMsubs GPR:$Rn, mod_imm:$imm), (SUBSri $Rn, mod_imm:$imm)>; 3646def : ARMPat<(ARMsubs GPR:$Rn, GPR:$Rm), (SUBSrr $Rn, $Rm)>; 3647def : ARMPat<(ARMsubs GPR:$Rn, so_reg_imm:$shift), 3648 (SUBSrsi $Rn, so_reg_imm:$shift)>; 3649def : ARMPat<(ARMsubs GPR:$Rn, so_reg_reg:$shift), 3650 (SUBSrsr $Rn, so_reg_reg:$shift)>; 3651 3652 3653let isAdd = 1 in 3654defm ADC : AI1_adde_sube_irs<0b0101, "adc", ARMadde, 1>; 3655defm SBC : AI1_adde_sube_irs<0b0110, "sbc", ARMsube>; 3656 3657defm RSB : AsI1_rbin_irs<0b0011, "rsb", 3658 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3659 sub>; 3660 3661// FIXME: Eliminate them if we can write def : Pat patterns which defines 3662// CPSR and the implicit def of CPSR is not needed. 3663defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>; 3664 3665defm RSC : AI1_rsc_irs<0b0111, "rsc", ARMsube>; 3666 3667// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 3668// The assume-no-carry-in form uses the negation of the input since add/sub 3669// assume opposite meanings of the carry flag (i.e., carry == !borrow). 3670// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 3671// details. 3672def : ARMPat<(add GPR:$src, mod_imm_neg:$imm), 3673 (SUBri GPR:$src, mod_imm_neg:$imm)>; 3674def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm), 3675 (SUBSri GPR:$src, mod_imm_neg:$imm)>; 3676 3677def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm), 3678 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3679 Requires<[IsARM, HasV6T2]>; 3680def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm), 3681 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3682 Requires<[IsARM, HasV6T2]>; 3683 3684// The with-carry-in form matches bitwise not instead of the negation. 3685// Effectively, the inverse interpretation of the carry flag already accounts 3686// for part of the negation. 3687def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR), 3688 (SBCri GPR:$src, mod_imm_not:$imm)>; 3689def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR), 3690 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>, 3691 Requires<[IsARM, HasV6T2]>; 3692 3693// Note: These are implemented in C++ code, because they have to generate 3694// ADD/SUBrs instructions, which use a complex pattern that a xform function 3695// cannot produce. 3696// (mul X, 2^n+1) -> (add (X << n), X) 3697// (mul X, 2^n-1) -> (rsb X, (X << n)) 3698 3699// ARM Arithmetic Instruction 3700// GPR:$dst = GPR:$a op GPR:$b 3701class AAI<bits<8> op27_20, bits<8> op11_4, string opc, 3702 list<dag> pattern = [], 3703 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm), 3704 string asm = "\t$Rd, $Rn, $Rm"> 3705 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>, 3706 Sched<[WriteALU, ReadALU, ReadALU]> { 3707 bits<4> Rn; 3708 bits<4> Rd; 3709 bits<4> Rm; 3710 let Inst{27-20} = op27_20; 3711 let Inst{11-4} = op11_4; 3712 let Inst{19-16} = Rn; 3713 let Inst{15-12} = Rd; 3714 let Inst{3-0} = Rm; 3715 3716 let Unpredictable{11-8} = 0b1111; 3717} 3718 3719// Wrappers around the AAI class 3720class AAIRevOpr<bits<8> op27_20, bits<8> op11_4, string opc, 3721 list<dag> pattern = []> 3722 : AAI<op27_20, op11_4, opc, 3723 pattern, 3724 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3725 "\t$Rd, $Rm, $Rn">; 3726 3727class AAIIntrinsic<bits<8> op27_20, bits<8> op11_4, string opc, 3728 Intrinsic intrinsic> 3729 : AAI<op27_20, op11_4, opc, 3730 [(set GPRnopc:$Rd, (intrinsic GPRnopc:$Rn, GPRnopc:$Rm))]>; 3731 3732// Saturating add/subtract 3733let hasSideEffects = 1 in { 3734def QADD8 : AAIIntrinsic<0b01100010, 0b11111001, "qadd8", int_arm_qadd8>; 3735def QADD16 : AAIIntrinsic<0b01100010, 0b11110001, "qadd16", int_arm_qadd16>; 3736def QSUB16 : AAIIntrinsic<0b01100010, 0b11110111, "qsub16", int_arm_qsub16>; 3737def QSUB8 : AAIIntrinsic<0b01100010, 0b11111111, "qsub8", int_arm_qsub8>; 3738 3739def QDADD : AAIRevOpr<0b00010100, 0b00000101, "qdadd", 3740 [(set GPRnopc:$Rd, (int_arm_qadd (int_arm_qadd GPRnopc:$Rm, 3741 GPRnopc:$Rm), 3742 GPRnopc:$Rn))]>; 3743def QDSUB : AAIRevOpr<0b00010110, 0b00000101, "qdsub", 3744 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, 3745 (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>; 3746def QSUB : AAIRevOpr<0b00010010, 0b00000101, "qsub", 3747 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))]>; 3748let DecoderMethod = "DecodeQADDInstruction" in 3749 def QADD : AAIRevOpr<0b00010000, 0b00000101, "qadd", 3750 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))]>; 3751} 3752 3753def UQADD16 : AAIIntrinsic<0b01100110, 0b11110001, "uqadd16", int_arm_uqadd16>; 3754def UQADD8 : AAIIntrinsic<0b01100110, 0b11111001, "uqadd8", int_arm_uqadd8>; 3755def UQSUB16 : AAIIntrinsic<0b01100110, 0b11110111, "uqsub16", int_arm_uqsub16>; 3756def UQSUB8 : AAIIntrinsic<0b01100110, 0b11111111, "uqsub8", int_arm_uqsub8>; 3757def QASX : AAIIntrinsic<0b01100010, 0b11110011, "qasx", int_arm_qasx>; 3758def QSAX : AAIIntrinsic<0b01100010, 0b11110101, "qsax", int_arm_qsax>; 3759def UQASX : AAIIntrinsic<0b01100110, 0b11110011, "uqasx", int_arm_uqasx>; 3760def UQSAX : AAIIntrinsic<0b01100110, 0b11110101, "uqsax", int_arm_uqsax>; 3761 3762// Signed/Unsigned add/subtract 3763 3764def SASX : AAIIntrinsic<0b01100001, 0b11110011, "sasx", int_arm_sasx>; 3765def SADD16 : AAIIntrinsic<0b01100001, 0b11110001, "sadd16", int_arm_sadd16>; 3766def SADD8 : AAIIntrinsic<0b01100001, 0b11111001, "sadd8", int_arm_sadd8>; 3767def SSAX : AAIIntrinsic<0b01100001, 0b11110101, "ssax", int_arm_ssax>; 3768def SSUB16 : AAIIntrinsic<0b01100001, 0b11110111, "ssub16", int_arm_ssub16>; 3769def SSUB8 : AAIIntrinsic<0b01100001, 0b11111111, "ssub8", int_arm_ssub8>; 3770def UASX : AAIIntrinsic<0b01100101, 0b11110011, "uasx", int_arm_uasx>; 3771def UADD16 : AAIIntrinsic<0b01100101, 0b11110001, "uadd16", int_arm_uadd16>; 3772def UADD8 : AAIIntrinsic<0b01100101, 0b11111001, "uadd8", int_arm_uadd8>; 3773def USAX : AAIIntrinsic<0b01100101, 0b11110101, "usax", int_arm_usax>; 3774def USUB16 : AAIIntrinsic<0b01100101, 0b11110111, "usub16", int_arm_usub16>; 3775def USUB8 : AAIIntrinsic<0b01100101, 0b11111111, "usub8", int_arm_usub8>; 3776 3777// Signed/Unsigned halving add/subtract 3778 3779def SHASX : AAIIntrinsic<0b01100011, 0b11110011, "shasx", int_arm_shasx>; 3780def SHADD16 : AAIIntrinsic<0b01100011, 0b11110001, "shadd16", int_arm_shadd16>; 3781def SHADD8 : AAIIntrinsic<0b01100011, 0b11111001, "shadd8", int_arm_shadd8>; 3782def SHSAX : AAIIntrinsic<0b01100011, 0b11110101, "shsax", int_arm_shsax>; 3783def SHSUB16 : AAIIntrinsic<0b01100011, 0b11110111, "shsub16", int_arm_shsub16>; 3784def SHSUB8 : AAIIntrinsic<0b01100011, 0b11111111, "shsub8", int_arm_shsub8>; 3785def UHASX : AAIIntrinsic<0b01100111, 0b11110011, "uhasx", int_arm_uhasx>; 3786def UHADD16 : AAIIntrinsic<0b01100111, 0b11110001, "uhadd16", int_arm_uhadd16>; 3787def UHADD8 : AAIIntrinsic<0b01100111, 0b11111001, "uhadd8", int_arm_uhadd8>; 3788def UHSAX : AAIIntrinsic<0b01100111, 0b11110101, "uhsax", int_arm_uhsax>; 3789def UHSUB16 : AAIIntrinsic<0b01100111, 0b11110111, "uhsub16", int_arm_uhsub16>; 3790def UHSUB8 : AAIIntrinsic<0b01100111, 0b11111111, "uhsub8", int_arm_uhsub8>; 3791 3792// Unsigned Sum of Absolute Differences [and Accumulate]. 3793 3794def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3795 MulFrm /* for convenience */, NoItinerary, "usad8", 3796 "\t$Rd, $Rn, $Rm", 3797 [(set GPR:$Rd, (int_arm_usad8 GPR:$Rn, GPR:$Rm))]>, 3798 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> { 3799 bits<4> Rd; 3800 bits<4> Rn; 3801 bits<4> Rm; 3802 let Inst{27-20} = 0b01111000; 3803 let Inst{15-12} = 0b1111; 3804 let Inst{7-4} = 0b0001; 3805 let Inst{19-16} = Rd; 3806 let Inst{11-8} = Rm; 3807 let Inst{3-0} = Rn; 3808} 3809def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3810 MulFrm /* for convenience */, NoItinerary, "usada8", 3811 "\t$Rd, $Rn, $Rm, $Ra", 3812 [(set GPR:$Rd, (int_arm_usada8 GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 3813 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{ 3814 bits<4> Rd; 3815 bits<4> Rn; 3816 bits<4> Rm; 3817 bits<4> Ra; 3818 let Inst{27-20} = 0b01111000; 3819 let Inst{7-4} = 0b0001; 3820 let Inst{19-16} = Rd; 3821 let Inst{15-12} = Ra; 3822 let Inst{11-8} = Rm; 3823 let Inst{3-0} = Rn; 3824} 3825 3826// Signed/Unsigned saturate 3827def SSAT : AI<(outs GPRnopc:$Rd), 3828 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3829 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>, 3830 Requires<[IsARM,HasV6]>{ 3831 bits<4> Rd; 3832 bits<5> sat_imm; 3833 bits<4> Rn; 3834 bits<8> sh; 3835 let Inst{27-21} = 0b0110101; 3836 let Inst{5-4} = 0b01; 3837 let Inst{20-16} = sat_imm; 3838 let Inst{15-12} = Rd; 3839 let Inst{11-7} = sh{4-0}; 3840 let Inst{6} = sh{5}; 3841 let Inst{3-0} = Rn; 3842} 3843 3844def SSAT16 : AI<(outs GPRnopc:$Rd), 3845 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm, 3846 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []>, 3847 Requires<[IsARM,HasV6]>{ 3848 bits<4> Rd; 3849 bits<4> sat_imm; 3850 bits<4> Rn; 3851 let Inst{27-20} = 0b01101010; 3852 let Inst{11-4} = 0b11110011; 3853 let Inst{15-12} = Rd; 3854 let Inst{19-16} = sat_imm; 3855 let Inst{3-0} = Rn; 3856} 3857 3858def USAT : AI<(outs GPRnopc:$Rd), 3859 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3860 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>, 3861 Requires<[IsARM,HasV6]> { 3862 bits<4> Rd; 3863 bits<5> sat_imm; 3864 bits<4> Rn; 3865 bits<8> sh; 3866 let Inst{27-21} = 0b0110111; 3867 let Inst{5-4} = 0b01; 3868 let Inst{15-12} = Rd; 3869 let Inst{11-7} = sh{4-0}; 3870 let Inst{6} = sh{5}; 3871 let Inst{20-16} = sat_imm; 3872 let Inst{3-0} = Rn; 3873} 3874 3875def USAT16 : AI<(outs GPRnopc:$Rd), 3876 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm, 3877 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []>, 3878 Requires<[IsARM,HasV6]>{ 3879 bits<4> Rd; 3880 bits<4> sat_imm; 3881 bits<4> Rn; 3882 let Inst{27-20} = 0b01101110; 3883 let Inst{11-4} = 0b11110011; 3884 let Inst{15-12} = Rd; 3885 let Inst{19-16} = sat_imm; 3886 let Inst{3-0} = Rn; 3887} 3888 3889def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos), 3890 (SSAT imm1_32:$pos, GPRnopc:$a, 0)>; 3891def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos), 3892 (USAT imm0_31:$pos, GPRnopc:$a, 0)>; 3893def : ARMPat<(ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm), 3894 (SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 3895def : ARMPat<(ARMusatnoshift GPRnopc:$Rn, imm0_31:$imm), 3896 (USAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 3897def : ARMV6Pat<(int_arm_ssat16 GPRnopc:$a, imm1_16:$pos), 3898 (SSAT16 imm1_16:$pos, GPRnopc:$a)>; 3899def : ARMV6Pat<(int_arm_usat16 GPRnopc:$a, imm0_15:$pos), 3900 (USAT16 imm0_15:$pos, GPRnopc:$a)>; 3901 3902//===----------------------------------------------------------------------===// 3903// Bitwise Instructions. 3904// 3905 3906defm AND : AsI1_bin_irs<0b0000, "and", 3907 IIC_iBITi, IIC_iBITr, IIC_iBITsr, and, 1>; 3908defm ORR : AsI1_bin_irs<0b1100, "orr", 3909 IIC_iBITi, IIC_iBITr, IIC_iBITsr, or, 1>; 3910defm EOR : AsI1_bin_irs<0b0001, "eor", 3911 IIC_iBITi, IIC_iBITr, IIC_iBITsr, xor, 1>; 3912defm BIC : AsI1_bin_irs<0b1110, "bic", 3913 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3914 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 3915 3916// FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just 3917// like in the actual instruction encoding. The complexity of mapping the mask 3918// to the lsb/msb pair should be handled by ISel, not encapsulated in the 3919// instruction description. 3920def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), 3921 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3922 "bfc", "\t$Rd, $imm", "$src = $Rd", 3923 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>, 3924 Requires<[IsARM, HasV6T2]> { 3925 bits<4> Rd; 3926 bits<10> imm; 3927 let Inst{27-21} = 0b0111110; 3928 let Inst{6-0} = 0b0011111; 3929 let Inst{15-12} = Rd; 3930 let Inst{11-7} = imm{4-0}; // lsb 3931 let Inst{20-16} = imm{9-5}; // msb 3932} 3933 3934// A8.6.18 BFI - Bitfield insert (Encoding A1) 3935def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm), 3936 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3937 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd", 3938 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn, 3939 bf_inv_mask_imm:$imm))]>, 3940 Requires<[IsARM, HasV6T2]> { 3941 bits<4> Rd; 3942 bits<4> Rn; 3943 bits<10> imm; 3944 let Inst{27-21} = 0b0111110; 3945 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 3946 let Inst{15-12} = Rd; 3947 let Inst{11-7} = imm{4-0}; // lsb 3948 let Inst{20-16} = imm{9-5}; // width 3949 let Inst{3-0} = Rn; 3950} 3951 3952def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr, 3953 "mvn", "\t$Rd, $Rm", 3954 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> { 3955 bits<4> Rd; 3956 bits<4> Rm; 3957 let Inst{25} = 0; 3958 let Inst{19-16} = 0b0000; 3959 let Inst{11-4} = 0b00000000; 3960 let Inst{15-12} = Rd; 3961 let Inst{3-0} = Rm; 3962 3963 let Unpredictable{19-16} = 0b1111; 3964} 3965def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift), 3966 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3967 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP, 3968 Sched<[WriteALU]> { 3969 bits<4> Rd; 3970 bits<12> shift; 3971 let Inst{25} = 0; 3972 let Inst{19-16} = 0b0000; 3973 let Inst{15-12} = Rd; 3974 let Inst{11-5} = shift{11-5}; 3975 let Inst{4} = 0; 3976 let Inst{3-0} = shift{3-0}; 3977 3978 let Unpredictable{19-16} = 0b1111; 3979} 3980def MVNsr : AsI1<0b1111, (outs GPRnopc:$Rd), (ins so_reg_reg:$shift), 3981 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3982 [(set GPRnopc:$Rd, (not so_reg_reg:$shift))]>, UnaryDP, 3983 Sched<[WriteALU]> { 3984 bits<4> Rd; 3985 bits<12> shift; 3986 let Inst{25} = 0; 3987 let Inst{19-16} = 0b0000; 3988 let Inst{15-12} = Rd; 3989 let Inst{11-8} = shift{11-8}; 3990 let Inst{7} = 0; 3991 let Inst{6-5} = shift{6-5}; 3992 let Inst{4} = 1; 3993 let Inst{3-0} = shift{3-0}; 3994 3995 let Unpredictable{19-16} = 0b1111; 3996} 3997let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3998def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, 3999 IIC_iMVNi, "mvn", "\t$Rd, $imm", 4000 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> { 4001 bits<4> Rd; 4002 bits<12> imm; 4003 let Inst{25} = 1; 4004 let Inst{19-16} = 0b0000; 4005 let Inst{15-12} = Rd; 4006 let Inst{11-0} = imm; 4007} 4008 4009let AddedComplexity = 1 in 4010def : ARMPat<(and GPR:$src, mod_imm_not:$imm), 4011 (BICri GPR:$src, mod_imm_not:$imm)>; 4012 4013//===----------------------------------------------------------------------===// 4014// Multiply Instructions. 4015// 4016class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4017 string opc, string asm, list<dag> pattern> 4018 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4019 bits<4> Rd; 4020 bits<4> Rm; 4021 bits<4> Rn; 4022 let Inst{19-16} = Rd; 4023 let Inst{11-8} = Rm; 4024 let Inst{3-0} = Rn; 4025} 4026class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4027 string opc, string asm, list<dag> pattern> 4028 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4029 bits<4> RdLo; 4030 bits<4> RdHi; 4031 bits<4> Rm; 4032 bits<4> Rn; 4033 let Inst{19-16} = RdHi; 4034 let Inst{15-12} = RdLo; 4035 let Inst{11-8} = Rm; 4036 let Inst{3-0} = Rn; 4037} 4038class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4039 string opc, string asm, list<dag> pattern> 4040 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4041 bits<4> RdLo; 4042 bits<4> RdHi; 4043 bits<4> Rm; 4044 bits<4> Rn; 4045 let Inst{19-16} = RdHi; 4046 let Inst{15-12} = RdLo; 4047 let Inst{11-8} = Rm; 4048 let Inst{3-0} = Rn; 4049} 4050 4051// FIXME: The v5 pseudos are only necessary for the additional Constraint 4052// property. Remove them when it's possible to add those properties 4053// on an individual MachineInstr, not just an instruction description. 4054let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in { 4055def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), 4056 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4057 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", 4058 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>, 4059 Requires<[IsARM, HasV6]>, 4060 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4061 let Inst{15-12} = 0b0000; 4062 let Unpredictable{15-12} = 0b1111; 4063} 4064 4065let Constraints = "@earlyclobber $Rd" in 4066def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, 4067 pred:$p, cc_out:$s), 4068 4, IIC_iMUL32, 4069 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))], 4070 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 4071 Requires<[IsARM, NoV6, UseMulOps]>, 4072 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4073} 4074 4075def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd), 4076 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra), 4077 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra", 4078 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>, 4079 Requires<[IsARM, HasV6, UseMulOps]>, 4080 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 4081 bits<4> Ra; 4082 let Inst{15-12} = Ra; 4083} 4084 4085let Constraints = "@earlyclobber $Rd" in 4086def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd), 4087 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 4088 pred:$p, cc_out:$s), 4, IIC_iMAC32, 4089 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))], 4090 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>, 4091 Requires<[IsARM, NoV6]>, 4092 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4093 4094def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4095 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra", 4096 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>, 4097 Requires<[IsARM, HasV6T2, UseMulOps]>, 4098 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 4099 bits<4> Rd; 4100 bits<4> Rm; 4101 bits<4> Rn; 4102 bits<4> Ra; 4103 let Inst{19-16} = Rd; 4104 let Inst{15-12} = Ra; 4105 let Inst{11-8} = Rm; 4106 let Inst{3-0} = Rn; 4107} 4108 4109// Extra precision multiplies with low / high results 4110let hasSideEffects = 0 in { 4111let isCommutable = 1 in { 4112def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi), 4113 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 4114 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", 4115 [(set GPR:$RdLo, GPR:$RdHi, 4116 (smullohi GPR:$Rn, GPR:$Rm))]>, 4117 Requires<[IsARM, HasV6]>, 4118 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4119 4120def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), 4121 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 4122 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", 4123 [(set GPR:$RdLo, GPR:$RdHi, 4124 (umullohi GPR:$Rn, GPR:$Rm))]>, 4125 Requires<[IsARM, HasV6]>, 4126 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL]>; 4127 4128let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { 4129def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4130 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 4131 4, IIC_iMUL64, 4132 [(set GPR:$RdLo, GPR:$RdHi, 4133 (smullohi GPR:$Rn, GPR:$Rm))], 4134 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 4135 Requires<[IsARM, NoV6]>, 4136 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4137 4138def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4139 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 4140 4, IIC_iMUL64, 4141 [(set GPR:$RdLo, GPR:$RdHi, 4142 (umullohi GPR:$Rn, GPR:$Rm))], 4143 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 4144 Requires<[IsARM, NoV6]>, 4145 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4146} 4147} 4148 4149// Multiply + accumulate 4150def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi), 4151 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4152 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4153 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4154 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4155def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi), 4156 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4157 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4158 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4159 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4160 4161def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi), 4162 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4163 IIC_iMAC64, 4164 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4165 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4166 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> { 4167 bits<4> RdLo; 4168 bits<4> RdHi; 4169 bits<4> Rm; 4170 bits<4> Rn; 4171 let Inst{19-16} = RdHi; 4172 let Inst{15-12} = RdLo; 4173 let Inst{11-8} = Rm; 4174 let Inst{3-0} = Rn; 4175} 4176 4177let Constraints = 4178 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in { 4179def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4180 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4181 4, IIC_iMAC64, [], 4182 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4183 pred:$p, cc_out:$s)>, 4184 Requires<[IsARM, NoV6]>, 4185 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4186def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4187 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4188 4, IIC_iMAC64, [], 4189 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4190 pred:$p, cc_out:$s)>, 4191 Requires<[IsARM, NoV6]>, 4192 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4193} 4194 4195} // hasSideEffects 4196 4197// Most significant word multiply 4198def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4199 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm", 4200 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>, 4201 Requires<[IsARM, HasV6]>, 4202 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4203 let Inst{15-12} = 0b1111; 4204} 4205 4206def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4207 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", 4208 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, (i32 0)))]>, 4209 Requires<[IsARM, HasV6]>, 4210 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4211 let Inst{15-12} = 0b1111; 4212} 4213 4214def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd), 4215 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4216 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra", 4217 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, 4218 Requires<[IsARM, HasV6, UseMulOps]>, 4219 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4220 4221def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd), 4222 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4223 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", 4224 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 4225 Requires<[IsARM, HasV6]>, 4226 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4227 4228def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd), 4229 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4230 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>, 4231 Requires<[IsARM, HasV6, UseMulOps]>, 4232 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4233 4234def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd), 4235 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4236 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", 4237 [(set GPR:$Rd, (ARMsmmlsr GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 4238 Requires<[IsARM, HasV6]>, 4239 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4240 4241multiclass AI_smul<string opc> { 4242 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4243 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 4244 [(set GPR:$Rd, (mul (sext_inreg GPR:$Rn, i16), 4245 (sext_inreg GPR:$Rm, i16)))]>, 4246 Requires<[IsARM, HasV5TE]>, 4247 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4248 4249 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4250 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 4251 [(set GPR:$Rd, (mul (sext_inreg GPR:$Rn, i16), 4252 (sra GPR:$Rm, (i32 16))))]>, 4253 Requires<[IsARM, HasV5TE]>, 4254 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4255 4256 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4257 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 4258 [(set GPR:$Rd, (mul (sra GPR:$Rn, (i32 16)), 4259 (sext_inreg GPR:$Rm, i16)))]>, 4260 Requires<[IsARM, HasV5TE]>, 4261 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4262 4263 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4264 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 4265 [(set GPR:$Rd, (mul (sra GPR:$Rn, (i32 16)), 4266 (sra GPR:$Rm, (i32 16))))]>, 4267 Requires<[IsARM, HasV5TE]>, 4268 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4269 4270 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4271 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 4272 [(set GPR:$Rd, (ARMsmulwb GPR:$Rn, GPR:$Rm))]>, 4273 Requires<[IsARM, HasV5TE]>, 4274 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4275 4276 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4277 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 4278 [(set GPR:$Rd, (ARMsmulwt GPR:$Rn, GPR:$Rm))]>, 4279 Requires<[IsARM, HasV5TE]>, 4280 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4281} 4282 4283 4284multiclass AI_smla<string opc> { 4285 let DecoderMethod = "DecodeSMLAInstruction" in { 4286 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd), 4287 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4288 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 4289 [(set GPRnopc:$Rd, (add GPR:$Ra, 4290 (mul (sext_inreg GPRnopc:$Rn, i16), 4291 (sext_inreg GPRnopc:$Rm, i16))))]>, 4292 Requires<[IsARM, HasV5TE, UseMulOps]>, 4293 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4294 4295 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd), 4296 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4297 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 4298 [(set GPRnopc:$Rd, 4299 (add GPR:$Ra, (mul (sext_inreg GPRnopc:$Rn, i16), 4300 (sra GPRnopc:$Rm, (i32 16)))))]>, 4301 Requires<[IsARM, HasV5TE, UseMulOps]>, 4302 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4303 4304 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd), 4305 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4306 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 4307 [(set GPRnopc:$Rd, 4308 (add GPR:$Ra, (mul (sra GPRnopc:$Rn, (i32 16)), 4309 (sext_inreg GPRnopc:$Rm, i16))))]>, 4310 Requires<[IsARM, HasV5TE, UseMulOps]>, 4311 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4312 4313 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd), 4314 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4315 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 4316 [(set GPRnopc:$Rd, 4317 (add GPR:$Ra, (mul (sra GPRnopc:$Rn, (i32 16)), 4318 (sra GPRnopc:$Rm, (i32 16)))))]>, 4319 Requires<[IsARM, HasV5TE, UseMulOps]>, 4320 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4321 4322 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd), 4323 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4324 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 4325 [(set GPRnopc:$Rd, 4326 (add GPR:$Ra, (ARMsmulwb GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4327 Requires<[IsARM, HasV5TE, UseMulOps]>, 4328 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4329 4330 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd), 4331 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4332 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 4333 [(set GPRnopc:$Rd, 4334 (add GPR:$Ra, (ARMsmulwt GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4335 Requires<[IsARM, HasV5TE, UseMulOps]>, 4336 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4337 } 4338} 4339 4340defm SMUL : AI_smul<"smul">; 4341defm SMLA : AI_smla<"smla">; 4342 4343// Halfword multiply accumulate long: SMLAL<x><y>. 4344class SMLAL<bits<2> opc1, string asm> 4345 : AMulxyI64<0b0001010, opc1, 4346 (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4347 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4348 IIC_iMAC64, asm, "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4349 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4350 Requires<[IsARM, HasV5TE]>, 4351 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4352 4353def SMLALBB : SMLAL<0b00, "smlalbb">; 4354def SMLALBT : SMLAL<0b10, "smlalbt">; 4355def SMLALTB : SMLAL<0b01, "smlaltb">; 4356def SMLALTT : SMLAL<0b11, "smlaltt">; 4357 4358def : ARMV5TEPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4359 (SMLALBB $Rn, $Rm, $RLo, $RHi)>; 4360def : ARMV5TEPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4361 (SMLALBT $Rn, $Rm, $RLo, $RHi)>; 4362def : ARMV5TEPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4363 (SMLALTB $Rn, $Rm, $RLo, $RHi)>; 4364def : ARMV5TEPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4365 (SMLALTT $Rn, $Rm, $RLo, $RHi)>; 4366 4367// Helper class for AI_smld. 4368class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops, 4369 InstrItinClass itin, string opc, string asm> 4370 : AI<oops, iops, MulFrm, itin, opc, asm, []>, 4371 Requires<[IsARM, HasV6]> { 4372 bits<4> Rn; 4373 bits<4> Rm; 4374 let Inst{27-23} = 0b01110; 4375 let Inst{22} = long; 4376 let Inst{21-20} = 0b00; 4377 let Inst{11-8} = Rm; 4378 let Inst{7} = 0; 4379 let Inst{6} = sub; 4380 let Inst{5} = swap; 4381 let Inst{4} = 1; 4382 let Inst{3-0} = Rn; 4383} 4384class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops, 4385 InstrItinClass itin, string opc, string asm> 4386 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4387 bits<4> Rd; 4388 let Inst{15-12} = 0b1111; 4389 let Inst{19-16} = Rd; 4390} 4391class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops, 4392 InstrItinClass itin, string opc, string asm> 4393 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4394 bits<4> Ra; 4395 bits<4> Rd; 4396 let Inst{19-16} = Rd; 4397 let Inst{15-12} = Ra; 4398} 4399class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops, 4400 InstrItinClass itin, string opc, string asm> 4401 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4402 bits<4> RdLo; 4403 bits<4> RdHi; 4404 let Inst{19-16} = RdHi; 4405 let Inst{15-12} = RdLo; 4406} 4407 4408multiclass AI_smld<bit sub, string opc> { 4409 4410 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd), 4411 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4412 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">, 4413 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4414 4415 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd), 4416 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4417 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">, 4418 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4419 4420 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4421 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4422 NoItinerary, 4423 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">, 4424 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4425 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4426 4427 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4428 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4429 NoItinerary, 4430 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">, 4431 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4432 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4433} 4434 4435defm SMLA : AI_smld<0, "smla">; 4436defm SMLS : AI_smld<1, "smls">; 4437 4438def : ARMV6Pat<(int_arm_smlad GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4439 (SMLAD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4440def : ARMV6Pat<(int_arm_smladx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4441 (SMLADX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4442def : ARMV6Pat<(int_arm_smlsd GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4443 (SMLSD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4444def : ARMV6Pat<(int_arm_smlsdx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4445 (SMLSDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4446def : ARMV6Pat<(ARMSmlald GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4447 (SMLALD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4448def : ARMV6Pat<(ARMSmlaldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4449 (SMLALDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4450def : ARMV6Pat<(ARMSmlsld GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4451 (SMLSLD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4452def : ARMV6Pat<(ARMSmlsldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4453 (SMLSLDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4454 4455multiclass AI_sdml<bit sub, string opc> { 4456 4457 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), 4458 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">, 4459 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4460 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm), 4461 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">, 4462 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4463} 4464 4465defm SMUA : AI_sdml<0, "smua">; 4466defm SMUS : AI_sdml<1, "smus">; 4467 4468def : ARMV6Pat<(int_arm_smuad GPRnopc:$Rn, GPRnopc:$Rm), 4469 (SMUAD GPRnopc:$Rn, GPRnopc:$Rm)>; 4470def : ARMV6Pat<(int_arm_smuadx GPRnopc:$Rn, GPRnopc:$Rm), 4471 (SMUADX GPRnopc:$Rn, GPRnopc:$Rm)>; 4472def : ARMV6Pat<(int_arm_smusd GPRnopc:$Rn, GPRnopc:$Rm), 4473 (SMUSD GPRnopc:$Rn, GPRnopc:$Rm)>; 4474def : ARMV6Pat<(int_arm_smusdx GPRnopc:$Rn, GPRnopc:$Rm), 4475 (SMUSDX GPRnopc:$Rn, GPRnopc:$Rm)>; 4476 4477//===----------------------------------------------------------------------===// 4478// Division Instructions (ARMv7-A with virtualization extension) 4479// 4480def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4481 "sdiv", "\t$Rd, $Rn, $Rm", 4482 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>, 4483 Requires<[IsARM, HasDivideInARM]>, 4484 Sched<[WriteDIV]>; 4485 4486def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4487 "udiv", "\t$Rd, $Rn, $Rm", 4488 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>, 4489 Requires<[IsARM, HasDivideInARM]>, 4490 Sched<[WriteDIV]>; 4491 4492//===----------------------------------------------------------------------===// 4493// Misc. Arithmetic Instructions. 4494// 4495 4496def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm), 4497 IIC_iUNAr, "clz", "\t$Rd, $Rm", 4498 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>, 4499 Sched<[WriteALU]>; 4500 4501def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4502 IIC_iUNAr, "rbit", "\t$Rd, $Rm", 4503 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>, 4504 Requires<[IsARM, HasV6T2]>, 4505 Sched<[WriteALU]>; 4506 4507def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4508 IIC_iUNAr, "rev", "\t$Rd, $Rm", 4509 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>, 4510 Sched<[WriteALU]>; 4511 4512let AddedComplexity = 5 in 4513def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4514 IIC_iUNAr, "rev16", "\t$Rd, $Rm", 4515 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>, 4516 Requires<[IsARM, HasV6]>, 4517 Sched<[WriteALU]>; 4518 4519def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)), 4520 (REV16 (LDRH addrmode3:$addr))>; 4521def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr), 4522 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>; 4523 4524let AddedComplexity = 5 in 4525def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4526 IIC_iUNAr, "revsh", "\t$Rd, $Rm", 4527 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>, 4528 Requires<[IsARM, HasV6]>, 4529 Sched<[WriteALU]>; 4530 4531def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)), 4532 (and (srl GPR:$Rm, (i32 8)), 0xFF)), 4533 (REVSH GPR:$Rm)>; 4534 4535def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd), 4536 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh), 4537 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 4538 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF), 4539 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh), 4540 0xFFFF0000)))]>, 4541 Requires<[IsARM, HasV6]>, 4542 Sched<[WriteALUsi, ReadALU]>; 4543 4544// Alternate cases for PKHBT where identities eliminate some nodes. 4545def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)), 4546 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>; 4547def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)), 4548 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>; 4549 4550// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 4551// will match the pattern below. 4552def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd), 4553 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh), 4554 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 4555 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000), 4556 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh), 4557 0xFFFF)))]>, 4558 Requires<[IsARM, HasV6]>, 4559 Sched<[WriteALUsi, ReadALU]>; 4560 4561// Alternate cases for PKHTB where identities eliminate some nodes. Note that 4562// a shift amount of 0 is *not legal* here, it is PKHBT instead. 4563// We also can not replace a srl (17..31) by an arithmetic shift we would use in 4564// pkhtb src1, src2, asr (17..31). 4565def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4566 (srl GPRnopc:$src2, imm16:$sh)), 4567 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>; 4568def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4569 (sra GPRnopc:$src2, imm16_31:$sh)), 4570 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>; 4571def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4572 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)), 4573 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>; 4574 4575//===----------------------------------------------------------------------===// 4576// CRC Instructions 4577// 4578// Polynomials: 4579// + CRC32{B,H,W} 0x04C11DB7 4580// + CRC32C{B,H,W} 0x1EDC6F41 4581// 4582 4583class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin> 4584 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary, 4585 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm", 4586 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>, 4587 Requires<[IsARM, HasV8, HasCRC]> { 4588 bits<4> Rd; 4589 bits<4> Rn; 4590 bits<4> Rm; 4591 4592 let Inst{31-28} = 0b1110; 4593 let Inst{27-23} = 0b00010; 4594 let Inst{22-21} = sz; 4595 let Inst{20} = 0; 4596 let Inst{19-16} = Rn; 4597 let Inst{15-12} = Rd; 4598 let Inst{11-10} = 0b00; 4599 let Inst{9} = C; 4600 let Inst{8} = 0; 4601 let Inst{7-4} = 0b0100; 4602 let Inst{3-0} = Rm; 4603 4604 let Unpredictable{11-8} = 0b1101; 4605} 4606 4607def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>; 4608def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>; 4609def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>; 4610def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>; 4611def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>; 4612def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>; 4613 4614//===----------------------------------------------------------------------===// 4615// ARMv8.1a Privilege Access Never extension 4616// 4617// SETPAN #imm1 4618 4619def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan", 4620 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> { 4621 bits<1> imm; 4622 4623 let Inst{31-28} = 0b1111; 4624 let Inst{27-20} = 0b00010001; 4625 let Inst{19-16} = 0b0000; 4626 let Inst{15-10} = 0b000000; 4627 let Inst{9} = imm; 4628 let Inst{8} = 0b0; 4629 let Inst{7-4} = 0b0000; 4630 let Inst{3-0} = 0b0000; 4631 4632 let Unpredictable{19-16} = 0b1111; 4633 let Unpredictable{15-10} = 0b111111; 4634 let Unpredictable{8} = 0b1; 4635 let Unpredictable{3-0} = 0b1111; 4636} 4637 4638//===----------------------------------------------------------------------===// 4639// Comparison Instructions... 4640// 4641 4642defm CMP : AI1_cmp_irs<0b1010, "cmp", 4643 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, ARMcmp>; 4644 4645// ARMcmpZ can re-use the above instruction definitions. 4646def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm), 4647 (CMPri GPR:$src, mod_imm:$imm)>; 4648def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs), 4649 (CMPrr GPR:$src, GPR:$rhs)>; 4650def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs), 4651 (CMPrsi GPR:$src, so_reg_imm:$rhs)>; 4652def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs), 4653 (CMPrsr GPR:$src, so_reg_reg:$rhs)>; 4654 4655// CMN register-integer 4656let isCompare = 1, Defs = [CPSR] in { 4657def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi, 4658 "cmn", "\t$Rn, $imm", 4659 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>, 4660 Sched<[WriteCMP, ReadALU]> { 4661 bits<4> Rn; 4662 bits<12> imm; 4663 let Inst{25} = 1; 4664 let Inst{20} = 1; 4665 let Inst{19-16} = Rn; 4666 let Inst{15-12} = 0b0000; 4667 let Inst{11-0} = imm; 4668 4669 let Unpredictable{15-12} = 0b1111; 4670} 4671 4672// CMN register-register/shift 4673def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr, 4674 "cmn", "\t$Rn, $Rm", 4675 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4676 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> { 4677 bits<4> Rn; 4678 bits<4> Rm; 4679 let isCommutable = 1; 4680 let Inst{25} = 0; 4681 let Inst{20} = 1; 4682 let Inst{19-16} = Rn; 4683 let Inst{15-12} = 0b0000; 4684 let Inst{11-4} = 0b00000000; 4685 let Inst{3-0} = Rm; 4686 4687 let Unpredictable{15-12} = 0b1111; 4688} 4689 4690def CMNzrsi : AI1<0b1011, (outs), 4691 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr, 4692 "cmn", "\t$Rn, $shift", 4693 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4694 GPR:$Rn, so_reg_imm:$shift)]>, 4695 Sched<[WriteCMPsi, ReadALU]> { 4696 bits<4> Rn; 4697 bits<12> shift; 4698 let Inst{25} = 0; 4699 let Inst{20} = 1; 4700 let Inst{19-16} = Rn; 4701 let Inst{15-12} = 0b0000; 4702 let Inst{11-5} = shift{11-5}; 4703 let Inst{4} = 0; 4704 let Inst{3-0} = shift{3-0}; 4705 4706 let Unpredictable{15-12} = 0b1111; 4707} 4708 4709def CMNzrsr : AI1<0b1011, (outs), 4710 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr, 4711 "cmn", "\t$Rn, $shift", 4712 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4713 GPRnopc:$Rn, so_reg_reg:$shift)]>, 4714 Sched<[WriteCMPsr, ReadALU]> { 4715 bits<4> Rn; 4716 bits<12> shift; 4717 let Inst{25} = 0; 4718 let Inst{20} = 1; 4719 let Inst{19-16} = Rn; 4720 let Inst{15-12} = 0b0000; 4721 let Inst{11-8} = shift{11-8}; 4722 let Inst{7} = 0; 4723 let Inst{6-5} = shift{6-5}; 4724 let Inst{4} = 1; 4725 let Inst{3-0} = shift{3-0}; 4726 4727 let Unpredictable{15-12} = 0b1111; 4728} 4729 4730} 4731 4732def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm), 4733 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4734 4735def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm), 4736 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4737 4738// Note that TST/TEQ don't set all the same flags that CMP does! 4739defm TST : AI1_cmp_irs<0b1000, "tst", 4740 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4741 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1, 4742 "DecodeTSTInstruction">; 4743defm TEQ : AI1_cmp_irs<0b1001, "teq", 4744 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4745 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>; 4746 4747// Pseudo i64 compares for some floating point compares. 4748let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, 4749 Defs = [CPSR] in { 4750def BCCi64 : PseudoInst<(outs), 4751 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst), 4752 IIC_Br, 4753 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>, 4754 Sched<[WriteBr]>; 4755 4756def BCCZi64 : PseudoInst<(outs), 4757 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, 4758 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>, 4759 Sched<[WriteBr]>; 4760} // usesCustomInserter 4761 4762 4763// Conditional moves 4764let hasSideEffects = 0 in { 4765 4766let isCommutable = 1, isSelect = 1 in 4767def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), 4768 (ins GPR:$false, GPR:$Rm, cmovpred:$p), 4769 4, IIC_iCMOVr, 4770 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, 4771 cmovpred:$p))]>, 4772 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4773 4774def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd), 4775 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p), 4776 4, IIC_iCMOVsr, 4777 [(set GPR:$Rd, 4778 (ARMcmov GPR:$false, so_reg_imm:$shift, 4779 cmovpred:$p))]>, 4780 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4781def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd), 4782 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p), 4783 4, IIC_iCMOVsr, 4784 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift, 4785 cmovpred:$p))]>, 4786 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4787 4788 4789let isMoveImm = 1 in 4790def MOVCCi16 4791 : ARMPseudoInst<(outs GPR:$Rd), 4792 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p), 4793 4, IIC_iMOVi, 4794 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm, 4795 cmovpred:$p))]>, 4796 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>, 4797 Sched<[WriteALU]>; 4798 4799let isMoveImm = 1 in 4800def MOVCCi : ARMPseudoInst<(outs GPR:$Rd), 4801 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 4802 4, IIC_iCMOVi, 4803 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm, 4804 cmovpred:$p))]>, 4805 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4806 4807// Two instruction predicate mov immediate. 4808let isMoveImm = 1 in 4809def MOVCCi32imm 4810 : ARMPseudoInst<(outs GPR:$Rd), 4811 (ins GPR:$false, i32imm:$src, cmovpred:$p), 4812 8, IIC_iCMOVix2, 4813 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src, 4814 cmovpred:$p))]>, 4815 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>; 4816 4817let isMoveImm = 1 in 4818def MVNCCi : ARMPseudoInst<(outs GPR:$Rd), 4819 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 4820 4, IIC_iCMOVi, 4821 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm, 4822 cmovpred:$p))]>, 4823 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4824 4825} // hasSideEffects 4826 4827 4828//===----------------------------------------------------------------------===// 4829// Atomic operations intrinsics 4830// 4831 4832def MemBarrierOptOperand : AsmOperandClass { 4833 let Name = "MemBarrierOpt"; 4834 let ParserMethod = "parseMemBarrierOptOperand"; 4835} 4836def memb_opt : Operand<i32> { 4837 let PrintMethod = "printMemBOption"; 4838 let ParserMatchClass = MemBarrierOptOperand; 4839 let DecoderMethod = "DecodeMemBarrierOption"; 4840} 4841 4842def InstSyncBarrierOptOperand : AsmOperandClass { 4843 let Name = "InstSyncBarrierOpt"; 4844 let ParserMethod = "parseInstSyncBarrierOptOperand"; 4845} 4846def instsyncb_opt : Operand<i32> { 4847 let PrintMethod = "printInstSyncBOption"; 4848 let ParserMatchClass = InstSyncBarrierOptOperand; 4849 let DecoderMethod = "DecodeInstSyncBarrierOption"; 4850} 4851 4852def TraceSyncBarrierOptOperand : AsmOperandClass { 4853 let Name = "TraceSyncBarrierOpt"; 4854 let ParserMethod = "parseTraceSyncBarrierOptOperand"; 4855} 4856def tsb_opt : Operand<i32> { 4857 let PrintMethod = "printTraceSyncBOption"; 4858 let ParserMatchClass = TraceSyncBarrierOptOperand; 4859} 4860 4861// Memory barriers protect the atomic sequences 4862let hasSideEffects = 1 in { 4863def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4864 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>, 4865 Requires<[IsARM, HasDB]> { 4866 bits<4> opt; 4867 let Inst{31-4} = 0xf57ff05; 4868 let Inst{3-0} = opt; 4869} 4870 4871def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4872 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>, 4873 Requires<[IsARM, HasDB]> { 4874 bits<4> opt; 4875 let Inst{31-4} = 0xf57ff04; 4876 let Inst{3-0} = opt; 4877} 4878 4879// ISB has only full system option 4880def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary, 4881 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>, 4882 Requires<[IsARM, HasDB]> { 4883 bits<4> opt; 4884 let Inst{31-4} = 0xf57ff06; 4885 let Inst{3-0} = opt; 4886} 4887 4888let hasNoSchedulingInfo = 1 in 4889def TSB : AInoP<(outs), (ins tsb_opt:$opt), MiscFrm, NoItinerary, 4890 "tsb", "\t$opt", []>, Requires<[IsARM, HasV8_4a]> { 4891 let Inst{31-0} = 0xe320f012; 4892} 4893 4894} 4895 4896// Armv8.5-A speculation barrier 4897def SB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "sb", "", []>, 4898 Requires<[IsARM, HasSpecCtrl]>, Sched<[]> { 4899 let Inst{31-0} = 0xf57ff070; 4900 let Unpredictable = 0x000fff0f; 4901 let hasSideEffects = 1; 4902} 4903 4904let usesCustomInserter = 1, Defs = [CPSR] in { 4905 4906// Pseudo instruction that combines movs + predicated rsbmi 4907// to implement integer ABS 4908 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>; 4909} 4910 4911let usesCustomInserter = 1 in { 4912 def COPY_STRUCT_BYVAL_I32 : PseudoInst< 4913 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment), 4914 NoItinerary, 4915 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>; 4916} 4917 4918let hasPostISelHook = 1, Constraints = "$newdst = $dst, $newsrc = $src" in { 4919 // %newsrc, %newdst = MEMCPY %dst, %src, N, ...N scratch regs... 4920 // Copies N registers worth of memory from address %src to address %dst 4921 // and returns the incremented addresses. N scratch register will 4922 // be attached for the copy to use. 4923 def MEMCPY : PseudoInst< 4924 (outs GPR:$newdst, GPR:$newsrc), 4925 (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops), 4926 NoItinerary, 4927 [(set GPR:$newdst, GPR:$newsrc, 4928 (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>; 4929} 4930 4931def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4932 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4933}]>; 4934 4935def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4936 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4937}]>; 4938 4939def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4940 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4941}]>; 4942 4943def strex_1 : PatFrag<(ops node:$val, node:$ptr), 4944 (int_arm_strex node:$val, node:$ptr), [{ 4945 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4946}]>; 4947 4948def strex_2 : PatFrag<(ops node:$val, node:$ptr), 4949 (int_arm_strex node:$val, node:$ptr), [{ 4950 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4951}]>; 4952 4953def strex_4 : PatFrag<(ops node:$val, node:$ptr), 4954 (int_arm_strex node:$val, node:$ptr), [{ 4955 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4956}]>; 4957 4958def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4959 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4960}]>; 4961 4962def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4963 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4964}]>; 4965 4966def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4967 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4968}]>; 4969 4970def stlex_1 : PatFrag<(ops node:$val, node:$ptr), 4971 (int_arm_stlex node:$val, node:$ptr), [{ 4972 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4973}]>; 4974 4975def stlex_2 : PatFrag<(ops node:$val, node:$ptr), 4976 (int_arm_stlex node:$val, node:$ptr), [{ 4977 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4978}]>; 4979 4980def stlex_4 : PatFrag<(ops node:$val, node:$ptr), 4981 (int_arm_stlex node:$val, node:$ptr), [{ 4982 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4983}]>; 4984 4985let mayLoad = 1 in { 4986def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4987 NoItinerary, "ldrexb", "\t$Rt, $addr", 4988 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>; 4989def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4990 NoItinerary, "ldrexh", "\t$Rt, $addr", 4991 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>; 4992def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4993 NoItinerary, "ldrex", "\t$Rt, $addr", 4994 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>; 4995let hasExtraDefRegAllocReq = 1 in 4996def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 4997 NoItinerary, "ldrexd", "\t$Rt, $addr", []> { 4998 let DecoderMethod = "DecodeDoubleRegLoad"; 4999} 5000 5001def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5002 NoItinerary, "ldaexb", "\t$Rt, $addr", 5003 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>; 5004def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5005 NoItinerary, "ldaexh", "\t$Rt, $addr", 5006 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>; 5007def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5008 NoItinerary, "ldaex", "\t$Rt, $addr", 5009 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>; 5010let hasExtraDefRegAllocReq = 1 in 5011def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 5012 NoItinerary, "ldaexd", "\t$Rt, $addr", []> { 5013 let DecoderMethod = "DecodeDoubleRegLoad"; 5014} 5015} 5016 5017let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 5018def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5019 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", 5020 [(set GPR:$Rd, (strex_1 GPR:$Rt, 5021 addr_offset_none:$addr))]>; 5022def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5023 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", 5024 [(set GPR:$Rd, (strex_2 GPR:$Rt, 5025 addr_offset_none:$addr))]>; 5026def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5027 NoItinerary, "strex", "\t$Rd, $Rt, $addr", 5028 [(set GPR:$Rd, (strex_4 GPR:$Rt, 5029 addr_offset_none:$addr))]>; 5030let hasExtraSrcRegAllocReq = 1 in 5031def STREXD : AIstrex<0b01, (outs GPR:$Rd), 5032 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 5033 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> { 5034 let DecoderMethod = "DecodeDoubleRegStore"; 5035} 5036def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5037 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr", 5038 [(set GPR:$Rd, 5039 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>; 5040def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5041 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr", 5042 [(set GPR:$Rd, 5043 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>; 5044def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5045 NoItinerary, "stlex", "\t$Rd, $Rt, $addr", 5046 [(set GPR:$Rd, 5047 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>; 5048let hasExtraSrcRegAllocReq = 1 in 5049def STLEXD : AIstlex<0b01, (outs GPR:$Rd), 5050 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 5051 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> { 5052 let DecoderMethod = "DecodeDoubleRegStore"; 5053} 5054} 5055 5056def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", 5057 [(int_arm_clrex)]>, 5058 Requires<[IsARM, HasV6K]> { 5059 let Inst{31-0} = 0b11110101011111111111000000011111; 5060} 5061 5062def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 5063 (STREXB GPR:$Rt, addr_offset_none:$addr)>; 5064def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 5065 (STREXH GPR:$Rt, addr_offset_none:$addr)>; 5066 5067def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 5068 (STLEXB GPR:$Rt, addr_offset_none:$addr)>; 5069def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 5070 (STLEXH GPR:$Rt, addr_offset_none:$addr)>; 5071 5072class acquiring_load<PatFrag base> 5073 : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 5074 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 5075 return isAcquireOrStronger(Ordering); 5076}]>; 5077 5078def atomic_load_acquire_8 : acquiring_load<atomic_load_8>; 5079def atomic_load_acquire_16 : acquiring_load<atomic_load_16>; 5080def atomic_load_acquire_32 : acquiring_load<atomic_load_32>; 5081 5082class releasing_store<PatFrag base> 5083 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 5084 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 5085 return isReleaseOrStronger(Ordering); 5086}]>; 5087 5088def atomic_store_release_8 : releasing_store<atomic_store_8>; 5089def atomic_store_release_16 : releasing_store<atomic_store_16>; 5090def atomic_store_release_32 : releasing_store<atomic_store_32>; 5091 5092let AddedComplexity = 8 in { 5093 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>; 5094 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>; 5095 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>; 5096 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>; 5097 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>; 5098 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>; 5099} 5100 5101// SWP/SWPB are deprecated in V6/V7 and optional in v7VE. 5102// FIXME Use InstAlias to generate LDREX/STREX pairs instead. 5103let mayLoad = 1, mayStore = 1 in { 5104def SWP : AIswp<0, (outs GPRnopc:$Rt), 5105 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>, 5106 Requires<[IsARM,PreV8]>; 5107def SWPB: AIswp<1, (outs GPRnopc:$Rt), 5108 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>, 5109 Requires<[IsARM,PreV8]>; 5110} 5111 5112//===----------------------------------------------------------------------===// 5113// Coprocessor Instructions. 5114// 5115 5116def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5117 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5118 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5119 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 5120 imm:$CRm, imm:$opc2)]>, 5121 Requires<[IsARM,PreV8]> { 5122 bits<4> opc1; 5123 bits<4> CRn; 5124 bits<4> CRd; 5125 bits<4> cop; 5126 bits<3> opc2; 5127 bits<4> CRm; 5128 5129 let Inst{3-0} = CRm; 5130 let Inst{4} = 0; 5131 let Inst{7-5} = opc2; 5132 let Inst{11-8} = cop; 5133 let Inst{15-12} = CRd; 5134 let Inst{19-16} = CRn; 5135 let Inst{23-20} = opc1; 5136 5137 let DecoderNamespace = "CoProc"; 5138} 5139 5140def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5141 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5142 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5143 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 5144 imm:$CRm, imm:$opc2)]>, 5145 Requires<[IsARM,PreV8]> { 5146 let Inst{31-28} = 0b1111; 5147 bits<4> opc1; 5148 bits<4> CRn; 5149 bits<4> CRd; 5150 bits<4> cop; 5151 bits<3> opc2; 5152 bits<4> CRm; 5153 5154 let Inst{3-0} = CRm; 5155 let Inst{4} = 0; 5156 let Inst{7-5} = opc2; 5157 let Inst{11-8} = cop; 5158 let Inst{15-12} = CRd; 5159 let Inst{19-16} = CRn; 5160 let Inst{23-20} = opc1; 5161 5162 let DecoderNamespace = "CoProc"; 5163} 5164 5165class ACI<dag oops, dag iops, string opc, string asm, 5166 list<dag> pattern, IndexMode im = IndexModeNone> 5167 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 5168 opc, asm, "", pattern> { 5169 let Inst{27-25} = 0b110; 5170} 5171class ACInoP<dag oops, dag iops, string opc, string asm, 5172 list<dag> pattern, IndexMode im = IndexModeNone> 5173 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 5174 opc, asm, "", pattern> { 5175 let Inst{31-28} = 0b1111; 5176 let Inst{27-25} = 0b110; 5177} 5178 5179let DecoderNamespace = "CoProc" in { 5180multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> { 5181 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 5182 asm, "\t$cop, $CRd, $addr", pattern> { 5183 bits<13> addr; 5184 bits<4> cop; 5185 bits<4> CRd; 5186 let Inst{24} = 1; // P = 1 5187 let Inst{23} = addr{8}; 5188 let Inst{22} = Dbit; 5189 let Inst{21} = 0; // W = 0 5190 let Inst{20} = load; 5191 let Inst{19-16} = addr{12-9}; 5192 let Inst{15-12} = CRd; 5193 let Inst{11-8} = cop; 5194 let Inst{7-0} = addr{7-0}; 5195 let DecoderMethod = "DecodeCopMemInstruction"; 5196 } 5197 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 5198 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { 5199 bits<13> addr; 5200 bits<4> cop; 5201 bits<4> CRd; 5202 let Inst{24} = 1; // P = 1 5203 let Inst{23} = addr{8}; 5204 let Inst{22} = Dbit; 5205 let Inst{21} = 1; // W = 1 5206 let Inst{20} = load; 5207 let Inst{19-16} = addr{12-9}; 5208 let Inst{15-12} = CRd; 5209 let Inst{11-8} = cop; 5210 let Inst{7-0} = addr{7-0}; 5211 let DecoderMethod = "DecodeCopMemInstruction"; 5212 } 5213 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5214 postidx_imm8s4:$offset), 5215 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { 5216 bits<9> offset; 5217 bits<4> addr; 5218 bits<4> cop; 5219 bits<4> CRd; 5220 let Inst{24} = 0; // P = 0 5221 let Inst{23} = offset{8}; 5222 let Inst{22} = Dbit; 5223 let Inst{21} = 1; // W = 1 5224 let Inst{20} = load; 5225 let Inst{19-16} = addr; 5226 let Inst{15-12} = CRd; 5227 let Inst{11-8} = cop; 5228 let Inst{7-0} = offset{7-0}; 5229 let DecoderMethod = "DecodeCopMemInstruction"; 5230 } 5231 def _OPTION : ACI<(outs), 5232 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5233 coproc_option_imm:$option), 5234 asm, "\t$cop, $CRd, $addr, $option", []> { 5235 bits<8> option; 5236 bits<4> addr; 5237 bits<4> cop; 5238 bits<4> CRd; 5239 let Inst{24} = 0; // P = 0 5240 let Inst{23} = 1; // U = 1 5241 let Inst{22} = Dbit; 5242 let Inst{21} = 0; // W = 0 5243 let Inst{20} = load; 5244 let Inst{19-16} = addr; 5245 let Inst{15-12} = CRd; 5246 let Inst{11-8} = cop; 5247 let Inst{7-0} = option; 5248 let DecoderMethod = "DecodeCopMemInstruction"; 5249 } 5250} 5251multiclass LdSt2Cop<bit load, bit Dbit, string asm, list<dag> pattern> { 5252 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 5253 asm, "\t$cop, $CRd, $addr", pattern> { 5254 bits<13> addr; 5255 bits<4> cop; 5256 bits<4> CRd; 5257 let Inst{24} = 1; // P = 1 5258 let Inst{23} = addr{8}; 5259 let Inst{22} = Dbit; 5260 let Inst{21} = 0; // W = 0 5261 let Inst{20} = load; 5262 let Inst{19-16} = addr{12-9}; 5263 let Inst{15-12} = CRd; 5264 let Inst{11-8} = cop; 5265 let Inst{7-0} = addr{7-0}; 5266 let DecoderMethod = "DecodeCopMemInstruction"; 5267 } 5268 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 5269 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { 5270 bits<13> addr; 5271 bits<4> cop; 5272 bits<4> CRd; 5273 let Inst{24} = 1; // P = 1 5274 let Inst{23} = addr{8}; 5275 let Inst{22} = Dbit; 5276 let Inst{21} = 1; // W = 1 5277 let Inst{20} = load; 5278 let Inst{19-16} = addr{12-9}; 5279 let Inst{15-12} = CRd; 5280 let Inst{11-8} = cop; 5281 let Inst{7-0} = addr{7-0}; 5282 let DecoderMethod = "DecodeCopMemInstruction"; 5283 } 5284 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5285 postidx_imm8s4:$offset), 5286 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { 5287 bits<9> offset; 5288 bits<4> addr; 5289 bits<4> cop; 5290 bits<4> CRd; 5291 let Inst{24} = 0; // P = 0 5292 let Inst{23} = offset{8}; 5293 let Inst{22} = Dbit; 5294 let Inst{21} = 1; // W = 1 5295 let Inst{20} = load; 5296 let Inst{19-16} = addr; 5297 let Inst{15-12} = CRd; 5298 let Inst{11-8} = cop; 5299 let Inst{7-0} = offset{7-0}; 5300 let DecoderMethod = "DecodeCopMemInstruction"; 5301 } 5302 def _OPTION : ACInoP<(outs), 5303 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5304 coproc_option_imm:$option), 5305 asm, "\t$cop, $CRd, $addr, $option", []> { 5306 bits<8> option; 5307 bits<4> addr; 5308 bits<4> cop; 5309 bits<4> CRd; 5310 let Inst{24} = 0; // P = 0 5311 let Inst{23} = 1; // U = 1 5312 let Inst{22} = Dbit; 5313 let Inst{21} = 0; // W = 0 5314 let Inst{20} = load; 5315 let Inst{19-16} = addr; 5316 let Inst{15-12} = CRd; 5317 let Inst{11-8} = cop; 5318 let Inst{7-0} = option; 5319 let DecoderMethod = "DecodeCopMemInstruction"; 5320 } 5321} 5322 5323defm LDC : LdStCop <1, 0, "ldc", [(int_arm_ldc imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5324defm LDCL : LdStCop <1, 1, "ldcl", [(int_arm_ldcl imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5325defm LDC2 : LdSt2Cop<1, 0, "ldc2", [(int_arm_ldc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5326defm LDC2L : LdSt2Cop<1, 1, "ldc2l", [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5327 5328defm STC : LdStCop <0, 0, "stc", [(int_arm_stc imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5329defm STCL : LdStCop <0, 1, "stcl", [(int_arm_stcl imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5330defm STC2 : LdSt2Cop<0, 0, "stc2", [(int_arm_stc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5331defm STC2L : LdSt2Cop<0, 1, "stc2l", [(int_arm_stc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5332 5333} // DecoderNamespace = "CoProc" 5334 5335//===----------------------------------------------------------------------===// 5336// Move between coprocessor and ARM core register. 5337// 5338 5339class MovRCopro<string opc, bit direction, dag oops, dag iops, 5340 list<dag> pattern> 5341 : ABI<0b1110, oops, iops, NoItinerary, opc, 5342 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> { 5343 let Inst{20} = direction; 5344 let Inst{4} = 1; 5345 5346 bits<4> Rt; 5347 bits<4> cop; 5348 bits<3> opc1; 5349 bits<3> opc2; 5350 bits<4> CRm; 5351 bits<4> CRn; 5352 5353 let Inst{15-12} = Rt; 5354 let Inst{11-8} = cop; 5355 let Inst{23-21} = opc1; 5356 let Inst{7-5} = opc2; 5357 let Inst{3-0} = CRm; 5358 let Inst{19-16} = CRn; 5359 5360 let DecoderNamespace = "CoProc"; 5361} 5362 5363def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */, 5364 (outs), 5365 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5366 c_imm:$CRm, imm0_7:$opc2), 5367 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 5368 imm:$CRm, imm:$opc2)]>, 5369 ComplexDeprecationPredicate<"MCR">; 5370def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 5371 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5372 c_imm:$CRm, 0, pred:$p)>; 5373def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, 5374 (outs GPRwithAPSR:$Rt), 5375 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5376 imm0_7:$opc2), []>; 5377def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", 5378 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5379 c_imm:$CRm, 0, pred:$p)>; 5380 5381def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 5382 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 5383 5384class MovRCopro2<string opc, bit direction, dag oops, dag iops, 5385 list<dag> pattern> 5386 : ABXI<0b1110, oops, iops, NoItinerary, 5387 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> { 5388 let Inst{31-24} = 0b11111110; 5389 let Inst{20} = direction; 5390 let Inst{4} = 1; 5391 5392 bits<4> Rt; 5393 bits<4> cop; 5394 bits<3> opc1; 5395 bits<3> opc2; 5396 bits<4> CRm; 5397 bits<4> CRn; 5398 5399 let Inst{15-12} = Rt; 5400 let Inst{11-8} = cop; 5401 let Inst{23-21} = opc1; 5402 let Inst{7-5} = opc2; 5403 let Inst{3-0} = CRm; 5404 let Inst{19-16} = CRn; 5405 5406 let DecoderNamespace = "CoProc"; 5407} 5408 5409def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */, 5410 (outs), 5411 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5412 c_imm:$CRm, imm0_7:$opc2), 5413 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 5414 imm:$CRm, imm:$opc2)]>, 5415 Requires<[IsARM,PreV8]>; 5416def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm", 5417 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5418 c_imm:$CRm, 0)>; 5419def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, 5420 (outs GPRwithAPSR:$Rt), 5421 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5422 imm0_7:$opc2), []>, 5423 Requires<[IsARM,PreV8]>; 5424def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm", 5425 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5426 c_imm:$CRm, 0)>; 5427 5428def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, 5429 imm:$CRm, imm:$opc2), 5430 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 5431 5432class MovRRCopro<string opc, bit direction, dag oops, dag iops, list<dag> 5433 pattern = []> 5434 : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", 5435 pattern> { 5436 5437 let Inst{23-21} = 0b010; 5438 let Inst{20} = direction; 5439 5440 bits<4> Rt; 5441 bits<4> Rt2; 5442 bits<4> cop; 5443 bits<4> opc1; 5444 bits<4> CRm; 5445 5446 let Inst{15-12} = Rt; 5447 let Inst{19-16} = Rt2; 5448 let Inst{11-8} = cop; 5449 let Inst{7-4} = opc1; 5450 let Inst{3-0} = CRm; 5451} 5452 5453def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */, 5454 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5455 GPRnopc:$Rt2, c_imm:$CRm), 5456 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt, 5457 GPRnopc:$Rt2, imm:$CRm)]>; 5458def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */, 5459 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5460 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5461 5462class MovRRCopro2<string opc, bit direction, dag oops, dag iops, 5463 list<dag> pattern = []> 5464 : ABXI<0b1100, oops, iops, NoItinerary, 5465 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>, 5466 Requires<[IsARM,PreV8]> { 5467 let Inst{31-28} = 0b1111; 5468 let Inst{23-21} = 0b010; 5469 let Inst{20} = direction; 5470 5471 bits<4> Rt; 5472 bits<4> Rt2; 5473 bits<4> cop; 5474 bits<4> opc1; 5475 bits<4> CRm; 5476 5477 let Inst{15-12} = Rt; 5478 let Inst{19-16} = Rt2; 5479 let Inst{11-8} = cop; 5480 let Inst{7-4} = opc1; 5481 let Inst{3-0} = CRm; 5482 5483 let DecoderMethod = "DecoderForMRRC2AndMCRR2"; 5484} 5485 5486def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */, 5487 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5488 GPRnopc:$Rt2, c_imm:$CRm), 5489 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt, 5490 GPRnopc:$Rt2, imm:$CRm)]>; 5491 5492def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */, 5493 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5494 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5495 5496//===----------------------------------------------------------------------===// 5497// Move between special register and ARM core register 5498// 5499 5500// Move to ARM core register from Special Register 5501def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5502 "mrs", "\t$Rd, apsr", []> { 5503 bits<4> Rd; 5504 let Inst{23-16} = 0b00001111; 5505 let Unpredictable{19-17} = 0b111; 5506 5507 let Inst{15-12} = Rd; 5508 5509 let Inst{11-0} = 0b000000000000; 5510 let Unpredictable{11-0} = 0b110100001111; 5511} 5512 5513def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p), 0>, 5514 Requires<[IsARM]>; 5515 5516// The MRSsys instruction is the MRS instruction from the ARM ARM, 5517// section B9.3.9, with the R bit set to 1. 5518def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5519 "mrs", "\t$Rd, spsr", []> { 5520 bits<4> Rd; 5521 let Inst{23-16} = 0b01001111; 5522 let Unpredictable{19-16} = 0b1111; 5523 5524 let Inst{15-12} = Rd; 5525 5526 let Inst{11-0} = 0b000000000000; 5527 let Unpredictable{11-0} = 0b110100001111; 5528} 5529 5530// However, the MRS (banked register) system instruction (ARMv7VE) *does* have a 5531// separate encoding (distinguished by bit 5. 5532def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked), 5533 NoItinerary, "mrs", "\t$Rd, $banked", []>, 5534 Requires<[IsARM, HasVirtualization]> { 5535 bits<6> banked; 5536 bits<4> Rd; 5537 5538 let Inst{23} = 0; 5539 let Inst{22} = banked{5}; // R bit 5540 let Inst{21-20} = 0b00; 5541 let Inst{19-16} = banked{3-0}; 5542 let Inst{15-12} = Rd; 5543 let Inst{11-9} = 0b001; 5544 let Inst{8} = banked{4}; 5545 let Inst{7-0} = 0b00000000; 5546} 5547 5548// Move from ARM core register to Special Register 5549// 5550// No need to have both system and application versions of MSR (immediate) or 5551// MSR (register), the encodings are the same and the assembly parser has no way 5552// to distinguish between them. The mask operand contains the special register 5553// (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be 5554// accessed in the special register. 5555let Defs = [CPSR] in 5556def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, 5557 "msr", "\t$mask, $Rn", []> { 5558 bits<5> mask; 5559 bits<4> Rn; 5560 5561 let Inst{23} = 0; 5562 let Inst{22} = mask{4}; // R bit 5563 let Inst{21-20} = 0b10; 5564 let Inst{19-16} = mask{3-0}; 5565 let Inst{15-12} = 0b1111; 5566 let Inst{11-4} = 0b00000000; 5567 let Inst{3-0} = Rn; 5568} 5569 5570let Defs = [CPSR] in 5571def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary, 5572 "msr", "\t$mask, $imm", []> { 5573 bits<5> mask; 5574 bits<12> imm; 5575 5576 let Inst{23} = 0; 5577 let Inst{22} = mask{4}; // R bit 5578 let Inst{21-20} = 0b10; 5579 let Inst{19-16} = mask{3-0}; 5580 let Inst{15-12} = 0b1111; 5581 let Inst{11-0} = imm; 5582} 5583 5584// However, the MSR (banked register) system instruction (ARMv7VE) *does* have a 5585// separate encoding (distinguished by bit 5. 5586def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn), 5587 NoItinerary, "msr", "\t$banked, $Rn", []>, 5588 Requires<[IsARM, HasVirtualization]> { 5589 bits<6> banked; 5590 bits<4> Rn; 5591 5592 let Inst{23} = 0; 5593 let Inst{22} = banked{5}; // R bit 5594 let Inst{21-20} = 0b10; 5595 let Inst{19-16} = banked{3-0}; 5596 let Inst{15-12} = 0b1111; 5597 let Inst{11-9} = 0b001; 5598 let Inst{8} = banked{4}; 5599 let Inst{7-4} = 0b0000; 5600 let Inst{3-0} = Rn; 5601} 5602 5603// Dynamic stack allocation yields a _chkstk for Windows targets. These calls 5604// are needed to probe the stack when allocating more than 5605// 4k bytes in one go. Touching the stack at 4K increments is necessary to 5606// ensure that the guard pages used by the OS virtual memory manager are 5607// allocated in correct sequence. 5608// The main point of having separate instruction are extra unmodelled effects 5609// (compared to ordinary calls) like stack pointer change. 5610 5611def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone, 5612 [SDNPHasChain, SDNPSideEffect]>; 5613let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in 5614 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>; 5615 5616def win__dbzchk : SDNode<"ARMISD::WIN__DBZCHK", SDT_WIN__DBZCHK, 5617 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 5618let usesCustomInserter = 1, Defs = [CPSR] in 5619 def WIN__DBZCHK : PseudoInst<(outs), (ins tGPR:$divisor), NoItinerary, 5620 [(win__dbzchk tGPR:$divisor)]>; 5621 5622//===----------------------------------------------------------------------===// 5623// TLS Instructions 5624// 5625 5626// __aeabi_read_tp preserves the registers r1-r3. 5627// This is a pseudo inst so that we can get the encoding right, 5628// complete with fixup for the aeabi_read_tp function. 5629// TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern 5630// is defined in "ARMInstrThumb.td". 5631let isCall = 1, 5632 Defs = [R0, R12, LR, CPSR], Uses = [SP] in { 5633 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br, 5634 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>, 5635 Requires<[IsARM, IsReadTPSoft]>; 5636} 5637 5638// Reading thread pointer from coprocessor register 5639def : ARMPat<(ARMthread_pointer), (MRC 15, 0, 13, 0, 3)>, 5640 Requires<[IsARM, IsReadTPHard]>; 5641 5642//===----------------------------------------------------------------------===// 5643// SJLJ Exception handling intrinsics 5644// eh_sjlj_setjmp() is an instruction sequence to store the return 5645// address and save #0 in R0 for the non-longjmp case. 5646// Since by its nature we may be coming from some other function to get 5647// here, and we're using the stack frame for the containing function to 5648// save/restore registers, we can't keep anything live in regs across 5649// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 5650// when we get here from a longjmp(). We force everything out of registers 5651// except for our own input by listing the relevant registers in Defs. By 5652// doing so, we also cause the prologue/epilogue code to actively preserve 5653// all of the callee-saved resgisters, which is exactly what we want. 5654// A constant value is passed in $val, and we use the location as a scratch. 5655// 5656// These are pseudo-instructions and are lowered to individual MC-insts, so 5657// no encoding information is necessary. 5658let Defs = 5659 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 5660 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ], 5661 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5662 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5663 NoItinerary, 5664 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5665 Requires<[IsARM, HasVFP2]>; 5666} 5667 5668let Defs = 5669 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 5670 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5671 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5672 NoItinerary, 5673 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5674 Requires<[IsARM, NoVFP]>; 5675} 5676 5677// FIXME: Non-IOS version(s) 5678let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, 5679 Defs = [ R7, LR, SP ] in { 5680def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch), 5681 NoItinerary, 5682 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 5683 Requires<[IsARM]>; 5684} 5685 5686let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in 5687def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary, 5688 [(ARMeh_sjlj_setup_dispatch)]>; 5689 5690// eh.sjlj.dispatchsetup pseudo-instruction. 5691// This pseudo is used for both ARM and Thumb. Any differences are handled when 5692// the pseudo is expanded (which happens before any passes that need the 5693// instruction size). 5694let isBarrier = 1 in 5695def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>; 5696 5697 5698//===----------------------------------------------------------------------===// 5699// Non-Instruction Patterns 5700// 5701 5702// ARMv4 indirect branch using (MOVr PC, dst) 5703let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in 5704 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst), 5705 4, IIC_Br, [(brind GPR:$dst)], 5706 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5707 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5708 5709let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in 5710 def TAILJMPr4 : ARMPseudoExpand<(outs), (ins GPR:$dst), 5711 4, IIC_Br, [], 5712 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5713 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5714 5715// Large immediate handling. 5716 5717// 32-bit immediate using two piece mod_imms or movw + movt. 5718// This is a single pseudo instruction, the benefit is that it can be remat'd 5719// as a single unit instead of having to handle reg inputs. 5720// FIXME: Remove this when we can do generalized remat. 5721let isReMaterializable = 1, isMoveImm = 1 in 5722def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 5723 [(set GPR:$dst, (arm_i32imm:$src))]>, 5724 Requires<[IsARM]>; 5725 5726def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i, 5727 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>, 5728 Requires<[IsARM, DontUseMovt]>; 5729 5730// Pseudo instruction that combines movw + movt + add pc (if PIC). 5731// It also makes it possible to rematerialize the instructions. 5732// FIXME: Remove this when we can do generalized remat and when machine licm 5733// can properly the instructions. 5734let isReMaterializable = 1 in { 5735def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5736 IIC_iMOVix2addpc, 5737 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 5738 Requires<[IsARM, UseMovtInPic]>; 5739 5740def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5741 IIC_iLoadiALU, 5742 [(set GPR:$dst, 5743 (ARMWrapperPIC tglobaladdr:$addr))]>, 5744 Requires<[IsARM, DontUseMovtInPic]>; 5745 5746let AddedComplexity = 10 in 5747def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5748 NoItinerary, 5749 [(set GPR:$dst, 5750 (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5751 Requires<[IsARM, DontUseMovtInPic]>; 5752 5753let AddedComplexity = 10 in 5754def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5755 IIC_iMOVix2ld, 5756 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5757 Requires<[IsARM, UseMovtInPic]>; 5758} // isReMaterializable 5759 5760// The many different faces of TLS access. 5761def : ARMPat<(ARMWrapper tglobaltlsaddr :$dst), 5762 (MOVi32imm tglobaltlsaddr :$dst)>, 5763 Requires<[IsARM, UseMovt]>; 5764 5765def : Pat<(ARMWrapper tglobaltlsaddr:$src), 5766 (LDRLIT_ga_abs tglobaltlsaddr:$src)>, 5767 Requires<[IsARM, DontUseMovt]>; 5768 5769def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5770 (MOV_ga_pcrel tglobaltlsaddr:$addr)>, Requires<[IsARM, UseMovtInPic]>; 5771 5772def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5773 (LDRLIT_ga_pcrel tglobaltlsaddr:$addr)>, 5774 Requires<[IsARM, DontUseMovtInPic]>; 5775let AddedComplexity = 10 in 5776def : Pat<(load (ARMWrapperPIC tglobaltlsaddr:$addr)), 5777 (MOV_ga_pcrel_ldr tglobaltlsaddr:$addr)>, 5778 Requires<[IsARM, UseMovtInPic]>; 5779 5780 5781// ConstantPool, GlobalAddress, and JumpTable 5782def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 5783def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>, 5784 Requires<[IsARM, UseMovt]>; 5785def : ARMPat<(ARMWrapper texternalsym :$dst), (MOVi32imm texternalsym :$dst)>, 5786 Requires<[IsARM, UseMovt]>; 5787def : ARMPat<(ARMWrapperJT tjumptable:$dst), 5788 (LEApcrelJT tjumptable:$dst)>; 5789 5790// TODO: add,sub,and, 3-instr forms? 5791 5792// Tail calls. These patterns also apply to Thumb mode. 5793def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>; 5794def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>; 5795def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>; 5796 5797// Direct calls 5798def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; 5799def : ARMPat<(ARMcall_nolink texternalsym:$func), 5800 (BMOVPCB_CALL texternalsym:$func)>; 5801 5802// zextload i1 -> zextload i8 5803def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5804def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5805 5806// extload -> zextload 5807def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5808def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5809def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5810def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5811 5812def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 5813 5814def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; 5815def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; 5816 5817// smul* and smla* 5818def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 5819 (SMULBB GPR:$a, GPR:$b)>, 5820 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 5821def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))), 5822 (SMULBT GPR:$a, GPR:$b)>, 5823 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 5824def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b), 5825 (SMULTB GPR:$a, GPR:$b)>, 5826 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 5827def : ARMV5MOPat<(add GPR:$acc, 5828 (mul sext_16_node:$a, sext_16_node:$b)), 5829 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>, 5830 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 5831def : ARMV5MOPat<(add GPR:$acc, 5832 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))), 5833 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>, 5834 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 5835def : ARMV5MOPat<(add GPR:$acc, 5836 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)), 5837 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>, 5838 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 5839 5840def : ARMV5TEPat<(int_arm_smulbb GPR:$a, GPR:$b), 5841 (SMULBB GPR:$a, GPR:$b)>; 5842def : ARMV5TEPat<(int_arm_smulbt GPR:$a, GPR:$b), 5843 (SMULBT GPR:$a, GPR:$b)>; 5844def : ARMV5TEPat<(int_arm_smultb GPR:$a, GPR:$b), 5845 (SMULTB GPR:$a, GPR:$b)>; 5846def : ARMV5TEPat<(int_arm_smultt GPR:$a, GPR:$b), 5847 (SMULTT GPR:$a, GPR:$b)>; 5848def : ARMV5TEPat<(int_arm_smulwb GPR:$a, GPR:$b), 5849 (SMULWB GPR:$a, GPR:$b)>; 5850def : ARMV5TEPat<(int_arm_smulwt GPR:$a, GPR:$b), 5851 (SMULWT GPR:$a, GPR:$b)>; 5852 5853def : ARMV5TEPat<(int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc), 5854 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5855def : ARMV5TEPat<(int_arm_smlabt GPR:$a, GPR:$b, GPR:$acc), 5856 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5857def : ARMV5TEPat<(int_arm_smlatb GPR:$a, GPR:$b, GPR:$acc), 5858 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5859def : ARMV5TEPat<(int_arm_smlatt GPR:$a, GPR:$b, GPR:$acc), 5860 (SMLATT GPR:$a, GPR:$b, GPR:$acc)>; 5861def : ARMV5TEPat<(int_arm_smlawb GPR:$a, GPR:$b, GPR:$acc), 5862 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 5863def : ARMV5TEPat<(int_arm_smlawt GPR:$a, GPR:$b, GPR:$acc), 5864 (SMLAWT GPR:$a, GPR:$b, GPR:$acc)>; 5865 5866// Pre-v7 uses MCR for synchronization barriers. 5867def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>, 5868 Requires<[IsARM, HasV6]>; 5869 5870// SXT/UXT with no rotate 5871let AddedComplexity = 16 in { 5872def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>; 5873def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>; 5874def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>; 5875def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)), 5876 (UXTAB GPR:$Rn, GPR:$Rm, 0)>; 5877def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)), 5878 (UXTAH GPR:$Rn, GPR:$Rm, 0)>; 5879} 5880 5881def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>; 5882def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; 5883 5884def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)), 5885 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>; 5886def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)), 5887 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>; 5888 5889// Atomic load/store patterns 5890def : ARMPat<(atomic_load_8 ldst_so_reg:$src), 5891 (LDRBrs ldst_so_reg:$src)>; 5892def : ARMPat<(atomic_load_8 addrmode_imm12:$src), 5893 (LDRBi12 addrmode_imm12:$src)>; 5894def : ARMPat<(atomic_load_16 addrmode3:$src), 5895 (LDRH addrmode3:$src)>; 5896def : ARMPat<(atomic_load_32 ldst_so_reg:$src), 5897 (LDRrs ldst_so_reg:$src)>; 5898def : ARMPat<(atomic_load_32 addrmode_imm12:$src), 5899 (LDRi12 addrmode_imm12:$src)>; 5900def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val), 5901 (STRBrs GPR:$val, ldst_so_reg:$ptr)>; 5902def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val), 5903 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>; 5904def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val), 5905 (STRH GPR:$val, addrmode3:$ptr)>; 5906def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val), 5907 (STRrs GPR:$val, ldst_so_reg:$ptr)>; 5908def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val), 5909 (STRi12 GPR:$val, addrmode_imm12:$ptr)>; 5910 5911 5912//===----------------------------------------------------------------------===// 5913// Thumb Support 5914// 5915 5916include "ARMInstrThumb.td" 5917 5918//===----------------------------------------------------------------------===// 5919// Thumb2 Support 5920// 5921 5922include "ARMInstrThumb2.td" 5923 5924//===----------------------------------------------------------------------===// 5925// Floating Point Support 5926// 5927 5928include "ARMInstrVFP.td" 5929 5930//===----------------------------------------------------------------------===// 5931// Advanced SIMD (NEON) Support 5932// 5933 5934include "ARMInstrNEON.td" 5935 5936//===----------------------------------------------------------------------===// 5937// Assembler aliases 5938// 5939 5940// Memory barriers 5941def : InstAlias<"dmb", (DMB 0xf), 0>, Requires<[IsARM, HasDB]>; 5942def : InstAlias<"dsb", (DSB 0xf), 0>, Requires<[IsARM, HasDB]>; 5943def : InstAlias<"ssbb", (DSB 0x0), 1>, Requires<[IsARM, HasDB]>; 5944def : InstAlias<"pssbb", (DSB 0x4), 1>, Requires<[IsARM, HasDB]>; 5945def : InstAlias<"isb", (ISB 0xf), 0>, Requires<[IsARM, HasDB]>; 5946// Armv8-R 'Data Full Barrier' 5947def : InstAlias<"dfb", (DSB 0xc), 1>, Requires<[IsARM, HasDFB]>; 5948 5949// System instructions 5950def : MnemonicAlias<"swi", "svc">; 5951 5952// Load / Store Multiple 5953def : MnemonicAlias<"ldmfd", "ldm">; 5954def : MnemonicAlias<"ldmia", "ldm">; 5955def : MnemonicAlias<"ldmea", "ldmdb">; 5956def : MnemonicAlias<"stmfd", "stmdb">; 5957def : MnemonicAlias<"stmia", "stm">; 5958def : MnemonicAlias<"stmea", "stm">; 5959 5960// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the 5961// input operands swapped when the shift amount is zero (i.e., unspecified). 5962def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 5963 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p), 0>, 5964 Requires<[IsARM, HasV6]>; 5965def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 5966 (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p), 0>, 5967 Requires<[IsARM, HasV6]>; 5968 5969// PUSH/POP aliases for STM/LDM 5970def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>; 5971def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>; 5972 5973// SSAT/USAT optional shift operand. 5974def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 5975 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5976def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn", 5977 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5978 5979 5980// Extend instruction optional rotate operand. 5981def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm", 5982 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5983def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm", 5984 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5985def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 5986 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5987def : ARMInstAlias<"sxtb${p} $Rd, $Rm", 5988 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5989def : ARMInstAlias<"sxtb16${p} $Rd, $Rm", 5990 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5991def : ARMInstAlias<"sxth${p} $Rd, $Rm", 5992 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5993 5994def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm", 5995 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5996def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm", 5997 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5998def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 5999 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6000def : ARMInstAlias<"uxtb${p} $Rd, $Rm", 6001 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6002def : ARMInstAlias<"uxtb16${p} $Rd, $Rm", 6003 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6004def : ARMInstAlias<"uxth${p} $Rd, $Rm", 6005 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6006 6007 6008// RFE aliases 6009def : MnemonicAlias<"rfefa", "rfeda">; 6010def : MnemonicAlias<"rfeea", "rfedb">; 6011def : MnemonicAlias<"rfefd", "rfeia">; 6012def : MnemonicAlias<"rfeed", "rfeib">; 6013def : MnemonicAlias<"rfe", "rfeia">; 6014 6015// SRS aliases 6016def : MnemonicAlias<"srsfa", "srsib">; 6017def : MnemonicAlias<"srsea", "srsia">; 6018def : MnemonicAlias<"srsfd", "srsdb">; 6019def : MnemonicAlias<"srsed", "srsda">; 6020def : MnemonicAlias<"srs", "srsia">; 6021 6022// QSAX == QSUBADDX 6023def : MnemonicAlias<"qsubaddx", "qsax">; 6024// SASX == SADDSUBX 6025def : MnemonicAlias<"saddsubx", "sasx">; 6026// SHASX == SHADDSUBX 6027def : MnemonicAlias<"shaddsubx", "shasx">; 6028// SHSAX == SHSUBADDX 6029def : MnemonicAlias<"shsubaddx", "shsax">; 6030// SSAX == SSUBADDX 6031def : MnemonicAlias<"ssubaddx", "ssax">; 6032// UASX == UADDSUBX 6033def : MnemonicAlias<"uaddsubx", "uasx">; 6034// UHASX == UHADDSUBX 6035def : MnemonicAlias<"uhaddsubx", "uhasx">; 6036// UHSAX == UHSUBADDX 6037def : MnemonicAlias<"uhsubaddx", "uhsax">; 6038// UQASX == UQADDSUBX 6039def : MnemonicAlias<"uqaddsubx", "uqasx">; 6040// UQSAX == UQSUBADDX 6041def : MnemonicAlias<"uqsubaddx", "uqsax">; 6042// USAX == USUBADDX 6043def : MnemonicAlias<"usubaddx", "usax">; 6044 6045// "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like 6046// for isel. 6047def : ARMInstSubst<"mov${s}${p} $Rd, $imm", 6048 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6049def : ARMInstSubst<"mvn${s}${p} $Rd, $imm", 6050 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6051// Same for AND <--> BIC 6052def : ARMInstSubst<"bic${s}${p} $Rd, $Rn, $imm", 6053 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 6054 pred:$p, cc_out:$s)>; 6055def : ARMInstSubst<"bic${s}${p} $Rdn, $imm", 6056 (ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 6057 pred:$p, cc_out:$s)>; 6058def : ARMInstSubst<"and${s}${p} $Rd, $Rn, $imm", 6059 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 6060 pred:$p, cc_out:$s)>; 6061def : ARMInstSubst<"and${s}${p} $Rdn, $imm", 6062 (BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 6063 pred:$p, cc_out:$s)>; 6064 6065// Likewise, "add Rd, mod_imm_neg" -> sub 6066def : ARMInstSubst<"add${s}${p} $Rd, $Rn, $imm", 6067 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6068def : ARMInstSubst<"add${s}${p} $Rd, $imm", 6069 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6070// Likewise, "sub Rd, mod_imm_neg" -> add 6071def : ARMInstSubst<"sub${s}${p} $Rd, $Rn, $imm", 6072 (ADDri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6073def : ARMInstSubst<"sub${s}${p} $Rd, $imm", 6074 (ADDri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6075 6076 6077def : ARMInstSubst<"adc${s}${p} $Rd, $Rn, $imm", 6078 (SBCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6079def : ARMInstSubst<"adc${s}${p} $Rdn, $imm", 6080 (SBCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6081def : ARMInstSubst<"sbc${s}${p} $Rd, $Rn, $imm", 6082 (ADCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6083def : ARMInstSubst<"sbc${s}${p} $Rdn, $imm", 6084 (ADCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6085 6086// Same for CMP <--> CMN via mod_imm_neg 6087def : ARMInstSubst<"cmp${p} $Rd, $imm", 6088 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 6089def : ARMInstSubst<"cmn${p} $Rd, $imm", 6090 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 6091 6092// The shifter forms of the MOV instruction are aliased to the ASR, LSL, 6093// LSR, ROR, and RRX instructions. 6094// FIXME: We need C++ parser hooks to map the alias to the MOV 6095// encoding. It seems we should be able to do that sort of thing 6096// in tblgen, but it could get ugly. 6097let TwoOperandAliasConstraint = "$Rm = $Rd" in { 6098def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm", 6099 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 6100 cc_out:$s)>; 6101def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm", 6102 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 6103 cc_out:$s)>; 6104def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm", 6105 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 6106 cc_out:$s)>; 6107def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm", 6108 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 6109 cc_out:$s)>; 6110} 6111def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm", 6112 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>; 6113let TwoOperandAliasConstraint = "$Rn = $Rd" in { 6114def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm", 6115 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6116 cc_out:$s)>; 6117def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm", 6118 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6119 cc_out:$s)>; 6120def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm", 6121 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6122 cc_out:$s)>; 6123def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm", 6124 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6125 cc_out:$s)>; 6126} 6127 6128// "neg" is and alias for "rsb rd, rn, #0" 6129def : ARMInstAlias<"neg${s}${p} $Rd, $Rm", 6130 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>; 6131 6132// Pre-v6, 'mov r0, r0' was used as a NOP encoding. 6133def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>, 6134 Requires<[IsARM, NoV6]>; 6135 6136// MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but 6137// the instruction definitions need difference constraints pre-v6. 6138// Use these aliases for the assembly parsing on pre-v6. 6139def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm", 6140 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s), 0>, 6141 Requires<[IsARM, NoV6]>; 6142def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra", 6143 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 6144 pred:$p, cc_out:$s), 0>, 6145 Requires<[IsARM, NoV6]>; 6146def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6147 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6148 Requires<[IsARM, NoV6]>; 6149def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6150 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6151 Requires<[IsARM, NoV6]>; 6152def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6153 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6154 Requires<[IsARM, NoV6]>; 6155def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6156 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6157 Requires<[IsARM, NoV6]>; 6158 6159// 'it' blocks in ARM mode just validate the predicates. The IT itself 6160// is discarded. 6161def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>, 6162 ComplexDeprecationPredicate<"IT">; 6163 6164let mayLoad = 1, mayStore =1, hasSideEffects = 1 in 6165def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn), 6166 NoItinerary, 6167 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>; 6168 6169//===---------------------------------- 6170// Atomic cmpxchg for -O0 6171//===---------------------------------- 6172 6173// The fast register allocator used during -O0 inserts spills to cover any VRegs 6174// live across basic block boundaries. When this happens between an LDXR and an 6175// STXR it can clear the exclusive monitor, causing all cmpxchg attempts to 6176// fail. 6177 6178// Unfortunately, this means we have to have an alternative (expanded 6179// post-regalloc) path for -O0 compilations. Fortunately this path can be 6180// significantly more naive than the standard expansion: we conservatively 6181// assume seq_cst, strong cmpxchg and omit clrex on failure. 6182 6183let Constraints = "@earlyclobber $Rd,@earlyclobber $temp", 6184 mayLoad = 1, mayStore = 1 in { 6185def CMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6186 (ins GPR:$addr, GPR:$desired, GPR:$new), 6187 NoItinerary, []>, Sched<[]>; 6188 6189def CMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6190 (ins GPR:$addr, GPR:$desired, GPR:$new), 6191 NoItinerary, []>, Sched<[]>; 6192 6193def CMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6194 (ins GPR:$addr, GPR:$desired, GPR:$new), 6195 NoItinerary, []>, Sched<[]>; 6196 6197def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$temp), 6198 (ins GPR:$addr, GPRPair:$desired, GPRPair:$new), 6199 NoItinerary, []>, Sched<[]>; 6200} 6201 6202def CompilerBarrier : PseudoInst<(outs), (ins i32imm:$ordering), NoItinerary, 6203 [(atomic_fence imm:$ordering, 0)]> { 6204 let hasSideEffects = 1; 6205 let Size = 0; 6206 let AsmString = "@ COMPILER BARRIER"; 6207} 6208