1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the ARM instructions in TableGen format. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// ARM specific DAG Nodes. 15// 16 17// Type profiles. 18def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 19 SDTCisVT<1, i32> ]>; 20def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 21def SDT_ARMStructByVal : SDTypeProfile<0, 4, 22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 24 25def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 26 27def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 28 29def SDT_ARMCMov : SDTypeProfile<1, 3, 30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 31 SDTCisVT<3, i32>]>; 32 33def SDT_ARMBrcond : SDTypeProfile<0, 2, 34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 35 36def SDT_ARMBrJT : SDTypeProfile<0, 2, 37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 38 39def SDT_ARMBr2JT : SDTypeProfile<0, 3, 40 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 41 SDTCisVT<2, i32>]>; 42 43def SDT_ARMBCC_i64 : SDTypeProfile<0, 6, 44 [SDTCisVT<0, i32>, 45 SDTCisVT<1, i32>, SDTCisVT<2, i32>, 46 SDTCisVT<3, i32>, SDTCisVT<4, i32>, 47 SDTCisVT<5, OtherVT>]>; 48 49def SDT_ARMAnd : SDTypeProfile<1, 2, 50 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 51 SDTCisVT<2, i32>]>; 52 53def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 54 55def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 56 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 57 58def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 59def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, 60 SDTCisInt<2>]>; 61def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 62def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>; 63 64def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 65 66def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, 67 SDTCisInt<1>]>; 68 69def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 70 71def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 73 74def SDT_WIN__DBZCHK : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 75 76def SDT_ARMMEMCPY : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 77 SDTCisVT<2, i32>, SDTCisVT<3, i32>, 78 SDTCisVT<4, i32>]>; 79 80def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 81 [SDTCisSameAs<0, 2>, 82 SDTCisSameAs<0, 3>, 83 SDTCisInt<0>, SDTCisVT<1, i32>]>; 84 85// SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR 86def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 87 [SDTCisSameAs<0, 2>, 88 SDTCisSameAs<0, 3>, 89 SDTCisInt<0>, 90 SDTCisVT<1, i32>, 91 SDTCisVT<4, i32>]>; 92 93def SDT_LongMac : SDTypeProfile<2, 4, [SDTCisVT<0, i32>, 94 SDTCisSameAs<0, 1>, 95 SDTCisSameAs<0, 2>, 96 SDTCisSameAs<0, 3>, 97 SDTCisSameAs<0, 4>, 98 SDTCisSameAs<0, 5>]>; 99 100// ARMlsll, ARMlsrl, ARMasrl 101def SDT_ARMIntShiftParts : SDTypeProfile<2, 3, [SDTCisSameAs<0, 1>, 102 SDTCisSameAs<0, 2>, 103 SDTCisSameAs<0, 3>, 104 SDTCisInt<0>, 105 SDTCisInt<4>]>; 106 107def ARMSmlald : SDNode<"ARMISD::SMLALD", SDT_LongMac>; 108def ARMSmlaldx : SDNode<"ARMISD::SMLALDX", SDT_LongMac>; 109def ARMSmlsld : SDNode<"ARMISD::SMLSLD", SDT_LongMac>; 110def ARMSmlsldx : SDNode<"ARMISD::SMLSLDX", SDT_LongMac>; 111 112def SDT_ARMCSel : SDTypeProfile<1, 3, 113 [SDTCisSameAs<0, 1>, 114 SDTCisSameAs<0, 2>, 115 SDTCisInt<3>, 116 SDTCisVT<3, i32>]>; 117 118def ARMcsinv : SDNode<"ARMISD::CSINV", SDT_ARMCSel, [SDNPOptInGlue]>; 119def ARMcsneg : SDNode<"ARMISD::CSNEG", SDT_ARMCSel, [SDNPOptInGlue]>; 120def ARMcsinc : SDNode<"ARMISD::CSINC", SDT_ARMCSel, [SDNPOptInGlue]>; 121 122def SDT_MulHSR : SDTypeProfile<1, 3, [SDTCisVT<0,i32>, 123 SDTCisSameAs<0, 1>, 124 SDTCisSameAs<0, 2>, 125 SDTCisSameAs<0, 3>]>; 126 127def ARMsmmlar : SDNode<"ARMISD::SMMLAR", SDT_MulHSR>; 128def ARMsmmlsr : SDNode<"ARMISD::SMMLSR", SDT_MulHSR>; 129 130// Node definitions. 131def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 132def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>; 133def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>; 134 135def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 136 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 137def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 138 [SDNPHasChain, SDNPSideEffect, 139 SDNPOptInGlue, SDNPOutGlue]>; 140def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" , 141 SDT_ARMStructByVal, 142 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 143 SDNPMayStore, SDNPMayLoad]>; 144 145def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 147 SDNPVariadic]>; 148def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 149 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 150 SDNPVariadic]>; 151def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 152 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 153 SDNPVariadic]>; 154 155def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, 156 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 157def ARMseretflag : SDNode<"ARMISD::SERET_FLAG", SDTNone, 158 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 159def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall, 160 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 161def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 162 [SDNPInGlue]>; 163def ARMsubs : SDNode<"ARMISD::SUBS", SDTIntBinOp, [SDNPOutGlue]>; 164 165def ARMssat : SDNode<"ARMISD::SSAT", SDTIntSatNoShOp, []>; 166 167def ARMusat : SDNode<"ARMISD::USAT", SDTIntSatNoShOp, []>; 168 169def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 170 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 171 172def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 173 [SDNPHasChain]>; 174def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, 175 [SDNPHasChain]>; 176 177def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64, 178 [SDNPHasChain]>; 179 180def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 181 [SDNPOutGlue]>; 182 183def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp, 184 [SDNPOutGlue]>; 185 186def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, 187 [SDNPOutGlue, SDNPCommutative]>; 188 189def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 190 191def ARMasrl : SDNode<"ARMISD::ASRL", SDT_ARMIntShiftParts, []>; 192def ARMlsrl : SDNode<"ARMISD::LSRL", SDT_ARMIntShiftParts, []>; 193def ARMlsll : SDNode<"ARMISD::LSLL", SDT_ARMIntShiftParts, []>; 194 195def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 196def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 197def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>; 198 199def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags, 200 [SDNPCommutative]>; 201def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>; 202def ARMlsls : SDNode<"ARMISD::LSLS", SDTBinaryArithWithFlags>; 203def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>; 204def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>; 205 206def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 207def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", 208 SDT_ARMEH_SJLJ_Setjmp, 209 [SDNPHasChain, SDNPSideEffect]>; 210def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP", 211 SDT_ARMEH_SJLJ_Longjmp, 212 [SDNPHasChain, SDNPSideEffect]>; 213def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH", 214 SDT_ARMEH_SJLJ_SetupDispatch, 215 [SDNPHasChain, SDNPSideEffect]>; 216 217def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER, 218 [SDNPHasChain, SDNPSideEffect]>; 219def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH, 220 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 221 222def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET, 223 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 224 225def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; 226 227def ARMmemcopy : SDNode<"ARMISD::MEMCPY", SDT_ARMMEMCPY, 228 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 229 SDNPMayStore, SDNPMayLoad]>; 230 231def ARMsmulwb : SDNode<"ARMISD::SMULWB", SDTIntBinOp, []>; 232def ARMsmulwt : SDNode<"ARMISD::SMULWT", SDTIntBinOp, []>; 233def ARMsmlalbb : SDNode<"ARMISD::SMLALBB", SDT_LongMac, []>; 234def ARMsmlalbt : SDNode<"ARMISD::SMLALBT", SDT_LongMac, []>; 235def ARMsmlaltb : SDNode<"ARMISD::SMLALTB", SDT_LongMac, []>; 236def ARMsmlaltt : SDNode<"ARMISD::SMLALTT", SDT_LongMac, []>; 237 238def ARMqadd8b : SDNode<"ARMISD::QADD8b", SDT_ARMAnd, []>; 239def ARMqsub8b : SDNode<"ARMISD::QSUB8b", SDT_ARMAnd, []>; 240def ARMqadd16b : SDNode<"ARMISD::QADD16b", SDT_ARMAnd, []>; 241def ARMqsub16b : SDNode<"ARMISD::QSUB16b", SDT_ARMAnd, []>; 242 243def SDT_ARMldrd : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>; 244def ARMldrd : SDNode<"ARMISD::LDRD", SDT_ARMldrd, [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 245 246def SDT_ARMstrd : SDTypeProfile<0, 3, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>; 247def ARMstrd : SDNode<"ARMISD::STRD", SDT_ARMstrd, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 248 249// Vector operations shared between NEON and MVE 250 251def ARMvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>; 252 253// VDUPLANE can produce a quad-register result from a double-register source, 254// so the result is not constrained to match the source. 255def ARMvduplane : SDNode<"ARMISD::VDUPLANE", 256 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 257 SDTCisVT<2, i32>]>>; 258 259def SDTARMVIDUP : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisVT<1, i32>, 260 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 261def ARMvidup : SDNode<"ARMISD::VIDUP", SDTARMVIDUP>; 262 263def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>; 264def ARMvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>; 265def ARMvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>; 266def ARMvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>; 267 268def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVec<1>, 269 SDTCisVT<2, i32>]>; 270def ARMvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>; 271def ARMvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>; 272 273def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>; 274def ARMvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>; 275def ARMvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>; 276def ARMvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>; 277 278def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, 279 SDTCisVT<2, i32>]>; 280def ARMvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>; 281def ARMvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>; 282 283def SDTARMVSHIMM : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 284 SDTCisVT<2, i32>]>; 285def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 286 SDTCisSameAs<0, 2>,]>; 287def ARMvshlImm : SDNode<"ARMISD::VSHLIMM", SDTARMVSHIMM>; 288def ARMvshrsImm : SDNode<"ARMISD::VSHRsIMM", SDTARMVSHIMM>; 289def ARMvshruImm : SDNode<"ARMISD::VSHRuIMM", SDTARMVSHIMM>; 290def ARMvshls : SDNode<"ARMISD::VSHLs", SDTARMVSH>; 291def ARMvshlu : SDNode<"ARMISD::VSHLu", SDTARMVSH>; 292 293def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, 294 SDTCisSameAs<1, 2>]>; 295def ARMvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>; 296def ARMvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>; 297 298def SDTARMVCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, 299 SDTCisInt<3>]>; 300def SDTARMVCMPZ : SDTypeProfile<1, 2, [SDTCisInt<2>]>; 301 302def ARMvcmp : SDNode<"ARMISD::VCMP", SDTARMVCMP>; 303def ARMvcmpz : SDNode<"ARMISD::VCMPZ", SDTARMVCMPZ>; 304 305// 'VECTOR_REG_CAST' is an operation that reinterprets the contents of a 306// vector register as a different vector type, without changing the contents of 307// the register. It differs from 'bitconvert' in that bitconvert reinterprets 308// the _memory_ storage format of the vector, whereas VECTOR_REG_CAST 309// reinterprets the _register_ format - and in big-endian, the memory and 310// register formats are different, so they are different operations. 311// 312// For example, 'VECTOR_REG_CAST' between v8i16 and v16i8 will map the LSB of 313// the zeroth i16 lane to the zeroth i8 lane, regardless of system endianness, 314// whereas 'bitconvert' will map it to the high byte in big-endian mode, 315// because that's what (MVE) VSTRH.16 followed by VLDRB.8 would do. So the 316// bitconvert would have to emit a VREV16.8 instruction, whereas the 317// VECTOR_REG_CAST emits no code at all if the vector is already in a register. 318def ARMVectorRegCastImpl : SDNode<"ARMISD::VECTOR_REG_CAST", SDTUnaryOp>; 319 320// In little-endian, VECTOR_REG_CAST is often turned into bitconvert during 321// lowering (because in that situation they're identical). So an isel pattern 322// that needs to match something that's _logically_ a VECTOR_REG_CAST must 323// _physically_ match a different node type depending on endianness. 324// 325// This 'PatFrags' instance is a centralized facility to make that easy. It 326// matches VECTOR_REG_CAST in either endianness, and also bitconvert in the 327// endianness where it's equivalent. 328def ARMVectorRegCast: PatFrags< 329 (ops node:$x), [(ARMVectorRegCastImpl node:$x), (bitconvert node:$x)], [{ 330 // Reject a match against bitconvert (aka ISD::BITCAST) if big-endian 331 return !(CurDAG->getDataLayout().isBigEndian() && 332 N->getOpcode() == ISD::BITCAST); 333 }]>; 334 335//===----------------------------------------------------------------------===// 336// ARM Flag Definitions. 337 338class RegConstraint<string C> { 339 string Constraints = C; 340} 341 342// ARMCC condition codes. See ARMCC::CondCodes 343def ARMCCeq : PatLeaf<(i32 0)>; 344def ARMCCne : PatLeaf<(i32 1)>; 345def ARMCChs : PatLeaf<(i32 2)>; 346def ARMCClo : PatLeaf<(i32 3)>; 347def ARMCCmi : PatLeaf<(i32 4)>; 348def ARMCCpl : PatLeaf<(i32 5)>; 349def ARMCCvs : PatLeaf<(i32 6)>; 350def ARMCCvc : PatLeaf<(i32 7)>; 351def ARMCChi : PatLeaf<(i32 8)>; 352def ARMCCls : PatLeaf<(i32 9)>; 353def ARMCCge : PatLeaf<(i32 10)>; 354def ARMCClt : PatLeaf<(i32 11)>; 355def ARMCCgt : PatLeaf<(i32 12)>; 356def ARMCCle : PatLeaf<(i32 13)>; 357def ARMCCal : PatLeaf<(i32 14)>; 358 359// VCC predicates. See ARMVCC::VPTCodes 360def ARMVCCNone : PatLeaf<(i32 0)>; 361def ARMVCCThen : PatLeaf<(i32 1)>; 362def ARMVCCElse : PatLeaf<(i32 2)>; 363 364//===----------------------------------------------------------------------===// 365// ARM specific transformation functions and pattern fragments. 366// 367 368// imm_neg_XFORM - Return the negation of an i32 immediate value. 369def imm_neg_XFORM : SDNodeXForm<imm, [{ 370 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32); 371}]>; 372 373// imm_not_XFORM - Return the complement of a i32 immediate value. 374def imm_not_XFORM : SDNodeXForm<imm, [{ 375 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32); 376}]>; 377 378// asr_imm_XFORM - Returns a shift immediate with bit {5} set to 1 379def asr_imm_XFORM : SDNodeXForm<imm, [{ 380 return CurDAG->getTargetConstant(0x20 | N->getZExtValue(), SDLoc(N), MVT:: i32); 381}]>; 382 383/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 384def imm16_31 : ImmLeaf<i32, [{ 385 return (int32_t)Imm >= 16 && (int32_t)Imm < 32; 386}]>; 387 388// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 389def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 390 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; 391}]>; 392 393def sext_bottom_16 : PatFrag<(ops node:$a), 394 (sext_inreg node:$a, i16)>; 395def sext_top_16 : PatFrag<(ops node:$a), 396 (i32 (sra node:$a, (i32 16)))>; 397 398def bb_mul : PatFrag<(ops node:$a, node:$b), 399 (mul (sext_bottom_16 node:$a), (sext_bottom_16 node:$b))>; 400def bt_mul : PatFrag<(ops node:$a, node:$b), 401 (mul (sext_bottom_16 node:$a), (sra node:$b, (i32 16)))>; 402def tb_mul : PatFrag<(ops node:$a, node:$b), 403 (mul (sra node:$a, (i32 16)), (sext_bottom_16 node:$b))>; 404def tt_mul : PatFrag<(ops node:$a, node:$b), 405 (mul (sra node:$a, (i32 16)), (sra node:$b, (i32 16)))>; 406 407/// Split a 32-bit immediate into two 16 bit parts. 408def hi16 : SDNodeXForm<imm, [{ 409 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N), 410 MVT::i32); 411}]>; 412 413def lo16AllZero : PatLeaf<(i32 imm), [{ 414 // Returns true if all low 16-bits are 0. 415 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 416}], hi16>; 417 418class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 419class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 420 421// An 'and' node with a single use. 422def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 423 return N->hasOneUse(); 424}]>; 425 426// An 'xor' node with a single use. 427def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{ 428 return N->hasOneUse(); 429}]>; 430 431// An 'fmul' node with a single use. 432def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{ 433 return N->hasOneUse(); 434}]>; 435 436// An 'fadd' node which checks for single non-hazardous use. 437def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{ 438 return hasNoVMLxHazardUse(N); 439}]>; 440 441// An 'fsub' node which checks for single non-hazardous use. 442def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{ 443 return hasNoVMLxHazardUse(N); 444}]>; 445 446def imm_even : ImmLeaf<i32, [{ return (Imm & 1) == 0; }]>; 447def imm_odd : ImmLeaf<i32, [{ return (Imm & 1) == 1; }]>; 448 449def asr_imm : ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }], asr_imm_XFORM>; 450 451//===----------------------------------------------------------------------===// 452// NEON/MVE pattern fragments 453// 454 455// Extract D sub-registers of Q registers. 456def DSubReg_i8_reg : SDNodeXForm<imm, [{ 457 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 458 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, SDLoc(N), 459 MVT::i32); 460}]>; 461def DSubReg_i16_reg : SDNodeXForm<imm, [{ 462 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 463 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, SDLoc(N), 464 MVT::i32); 465}]>; 466def DSubReg_i32_reg : SDNodeXForm<imm, [{ 467 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 468 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, SDLoc(N), 469 MVT::i32); 470}]>; 471def DSubReg_f64_reg : SDNodeXForm<imm, [{ 472 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 473 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), SDLoc(N), 474 MVT::i32); 475}]>; 476 477// Extract S sub-registers of Q/D registers. 478def SSubReg_f32_reg : SDNodeXForm<imm, [{ 479 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering"); 480 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), SDLoc(N), 481 MVT::i32); 482}]>; 483 484// Extract S sub-registers of Q/D registers containing a given f16/bf16 lane. 485def SSubReg_f16_reg : SDNodeXForm<imm, [{ 486 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering"); 487 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue()/2, SDLoc(N), 488 MVT::i32); 489}]>; 490 491// Translate lane numbers from Q registers to D subregs. 492def SubReg_i8_lane : SDNodeXForm<imm, [{ 493 return CurDAG->getTargetConstant(N->getZExtValue() & 7, SDLoc(N), MVT::i32); 494}]>; 495def SubReg_i16_lane : SDNodeXForm<imm, [{ 496 return CurDAG->getTargetConstant(N->getZExtValue() & 3, SDLoc(N), MVT::i32); 497}]>; 498def SubReg_i32_lane : SDNodeXForm<imm, [{ 499 return CurDAG->getTargetConstant(N->getZExtValue() & 1, SDLoc(N), MVT::i32); 500}]>; 501 502 503def ARMimmAllZerosV: PatLeaf<(bitconvert (v4i32 (ARMvmovImm (i32 0))))>; 504def ARMimmAllZerosD: PatLeaf<(bitconvert (v2i32 (ARMvmovImm (i32 0))))>; 505def ARMimmAllOnesV: PatLeaf<(bitconvert (v16i8 (ARMvmovImm (i32 0xEFF))))>; 506def ARMimmAllOnesD: PatLeaf<(bitconvert (v8i8 (ARMvmovImm (i32 0xEFF))))>; 507 508def ARMimmOneV: PatLeaf<(ARMvmovImm (i32 timm)), [{ 509 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0)); 510 unsigned EltBits = 0; 511 uint64_t EltVal = ARM_AM::decodeVMOVModImm(ConstVal->getZExtValue(), EltBits); 512 return (EltBits == N->getValueType(0).getScalarSizeInBits() && EltVal == 0x01); 513}]>; 514 515 516//===----------------------------------------------------------------------===// 517// Operand Definitions. 518// 519 520// Immediate operands with a shared generic asm render method. 521class ImmAsmOperand<int Low, int High> : AsmOperandClass { 522 let RenderMethod = "addImmOperands"; 523 let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; 524 let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]"; 525} 526 527class ImmAsmOperandMinusOne<int Low, int High> : AsmOperandClass { 528 let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; 529 let DiagnosticType = "ImmRange" # Low # "_" # High; 530 let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]"; 531} 532 533// Operands that are part of a memory addressing mode. 534class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; } 535 536// Branch target. 537// FIXME: rename brtarget to t2_brtarget 538def brtarget : Operand<OtherVT> { 539 let EncoderMethod = "getBranchTargetOpValue"; 540 let OperandType = "OPERAND_PCREL"; 541 let DecoderMethod = "DecodeT2BROperand"; 542} 543 544// Branches targeting ARM-mode must be divisible by 4 if they're a raw 545// immediate. 546def ARMBranchTarget : AsmOperandClass { 547 let Name = "ARMBranchTarget"; 548} 549 550// Branches targeting Thumb-mode must be divisible by 2 if they're a raw 551// immediate. 552def ThumbBranchTarget : AsmOperandClass { 553 let Name = "ThumbBranchTarget"; 554} 555 556def arm_br_target : Operand<OtherVT> { 557 let ParserMatchClass = ARMBranchTarget; 558 let EncoderMethod = "getARMBranchTargetOpValue"; 559 let OperandType = "OPERAND_PCREL"; 560} 561 562// Call target for ARM. Handles conditional/unconditional 563// FIXME: rename bl_target to t2_bltarget? 564def arm_bl_target : Operand<i32> { 565 let ParserMatchClass = ARMBranchTarget; 566 let EncoderMethod = "getARMBLTargetOpValue"; 567 let OperandType = "OPERAND_PCREL"; 568} 569 570// Target for BLX *from* ARM mode. 571def arm_blx_target : Operand<i32> { 572 let ParserMatchClass = ThumbBranchTarget; 573 let EncoderMethod = "getARMBLXTargetOpValue"; 574 let OperandType = "OPERAND_PCREL"; 575} 576 577// A list of registers separated by comma. Used by load/store multiple. 578def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; } 579def reglist : Operand<i32> { 580 let EncoderMethod = "getRegisterListOpValue"; 581 let ParserMatchClass = RegListAsmOperand; 582 let PrintMethod = "printRegisterList"; 583 let DecoderMethod = "DecodeRegListOperand"; 584} 585 586// A list of general purpose registers and APSR separated by comma. 587// Used by CLRM 588def RegListWithAPSRAsmOperand : AsmOperandClass { let Name = "RegListWithAPSR"; } 589def reglist_with_apsr : Operand<i32> { 590 let EncoderMethod = "getRegisterListOpValue"; 591 let ParserMatchClass = RegListWithAPSRAsmOperand; 592 let PrintMethod = "printRegisterList"; 593 let DecoderMethod = "DecodeRegListOperand"; 594} 595 596def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">; 597 598def DPRRegListAsmOperand : AsmOperandClass { 599 let Name = "DPRRegList"; 600 let DiagnosticType = "DPR_RegList"; 601} 602def dpr_reglist : Operand<i32> { 603 let EncoderMethod = "getRegisterListOpValue"; 604 let ParserMatchClass = DPRRegListAsmOperand; 605 let PrintMethod = "printRegisterList"; 606 let DecoderMethod = "DecodeDPRRegListOperand"; 607} 608 609def SPRRegListAsmOperand : AsmOperandClass { 610 let Name = "SPRRegList"; 611 let DiagnosticString = "operand must be a list of registers in range [s0, s31]"; 612} 613def spr_reglist : Operand<i32> { 614 let EncoderMethod = "getRegisterListOpValue"; 615 let ParserMatchClass = SPRRegListAsmOperand; 616 let PrintMethod = "printRegisterList"; 617 let DecoderMethod = "DecodeSPRRegListOperand"; 618} 619 620def FPSRegListWithVPRAsmOperand : AsmOperandClass { let Name = 621 "FPSRegListWithVPR"; } 622def fp_sreglist_with_vpr : Operand<i32> { 623 let EncoderMethod = "getRegisterListOpValue"; 624 let ParserMatchClass = FPSRegListWithVPRAsmOperand; 625 let PrintMethod = "printRegisterList"; 626} 627def FPDRegListWithVPRAsmOperand : AsmOperandClass { let Name = 628 "FPDRegListWithVPR"; } 629def fp_dreglist_with_vpr : Operand<i32> { 630 let EncoderMethod = "getRegisterListOpValue"; 631 let ParserMatchClass = FPDRegListWithVPRAsmOperand; 632 let PrintMethod = "printRegisterList"; 633} 634 635// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 636def cpinst_operand : Operand<i32> { 637 let PrintMethod = "printCPInstOperand"; 638} 639 640// Local PC labels. 641def pclabel : Operand<i32> { 642 let PrintMethod = "printPCLabel"; 643} 644 645// ADR instruction labels. 646def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; } 647def adrlabel : Operand<i32> { 648 let EncoderMethod = "getAdrLabelOpValue"; 649 let ParserMatchClass = AdrLabelAsmOperand; 650 let PrintMethod = "printAdrLabelOperand<0>"; 651} 652 653def neon_vcvt_imm32 : Operand<i32> { 654 let EncoderMethod = "getNEONVcvtImm32OpValue"; 655 let DecoderMethod = "DecodeVCVTImmOperand"; 656} 657 658// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. 659def rot_imm_XFORM: SDNodeXForm<imm, [{ 660 switch (N->getZExtValue()){ 661 default: llvm_unreachable(nullptr); 662 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); 663 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32); 664 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32); 665 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32); 666 } 667}]>; 668def RotImmAsmOperand : AsmOperandClass { 669 let Name = "RotImm"; 670 let ParserMethod = "parseRotImm"; 671} 672def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{ 673 int32_t v = N->getZExtValue(); 674 return v == 8 || v == 16 || v == 24; }], 675 rot_imm_XFORM> { 676 let PrintMethod = "printRotImmOperand"; 677 let ParserMatchClass = RotImmAsmOperand; 678} 679 680// Power-of-two operand for MVE VIDUP and friends, which encode 681// {1,2,4,8} as its log to base 2, i.e. as {0,1,2,3} respectively 682def MVE_VIDUP_imm_asmoperand : AsmOperandClass { 683 let Name = "VIDUP_imm"; 684 let PredicateMethod = "isPowerTwoInRange<1,8>"; 685 let RenderMethod = "addPowerTwoOperands"; 686 let DiagnosticString = "vector increment immediate must be 1, 2, 4 or 8"; 687} 688def MVE_VIDUP_imm : Operand<i32> { 689 let EncoderMethod = "getPowerTwoOpValue"; 690 let DecoderMethod = "DecodePowerTwoOperand<0,3>"; 691 let ParserMatchClass = MVE_VIDUP_imm_asmoperand; 692} 693 694// Pair vector indexing 695class MVEPairVectorIndexOperand<string start, string end> : AsmOperandClass { 696 let Name = "MVEPairVectorIndex"#start; 697 let RenderMethod = "addMVEPairVectorIndexOperands"; 698 let PredicateMethod = "isMVEPairVectorIndex<"#start#", "#end#">"; 699} 700 701class MVEPairVectorIndex<string opval> : Operand<i32> { 702 let PrintMethod = "printVectorIndex"; 703 let EncoderMethod = "getMVEPairVectorIndexOpValue<"#opval#">"; 704 let DecoderMethod = "DecodeMVEPairVectorIndexOperand<"#opval#">"; 705 let MIOperandInfo = (ops i32imm); 706} 707 708def MVEPairVectorIndex0 : MVEPairVectorIndex<"0"> { 709 let ParserMatchClass = MVEPairVectorIndexOperand<"0", "1">; 710} 711 712def MVEPairVectorIndex2 : MVEPairVectorIndex<"2"> { 713 let ParserMatchClass = MVEPairVectorIndexOperand<"2", "3">; 714} 715 716// Vector indexing 717class MVEVectorIndexOperand<int NumLanes> : AsmOperandClass { 718 let Name = "MVEVectorIndex"#NumLanes; 719 let RenderMethod = "addMVEVectorIndexOperands"; 720 let PredicateMethod = "isVectorIndexInRange<"#NumLanes#">"; 721} 722 723class MVEVectorIndex<int NumLanes> : Operand<i32> { 724 let PrintMethod = "printVectorIndex"; 725 let ParserMatchClass = MVEVectorIndexOperand<NumLanes>; 726 let MIOperandInfo = (ops i32imm); 727} 728 729// shift_imm: An integer that encodes a shift amount and the type of shift 730// (asr or lsl). The 6-bit immediate encodes as: 731// {5} 0 ==> lsl 732// 1 asr 733// {4-0} imm5 shift amount. 734// asr #32 encoded as imm5 == 0. 735def ShifterImmAsmOperand : AsmOperandClass { 736 let Name = "ShifterImm"; 737 let ParserMethod = "parseShifterImm"; 738} 739def shift_imm : Operand<i32> { 740 let PrintMethod = "printShiftImmOperand"; 741 let ParserMatchClass = ShifterImmAsmOperand; 742} 743 744// shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm. 745def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; } 746def so_reg_reg : Operand<i32>, // reg reg imm 747 ComplexPattern<i32, 3, "SelectRegShifterOperand", 748 [shl, srl, sra, rotr]> { 749 let EncoderMethod = "getSORegRegOpValue"; 750 let PrintMethod = "printSORegRegOperand"; 751 let DecoderMethod = "DecodeSORegRegOperand"; 752 let ParserMatchClass = ShiftedRegAsmOperand; 753 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm); 754} 755 756def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; } 757def so_reg_imm : Operand<i32>, // reg imm 758 ComplexPattern<i32, 2, "SelectImmShifterOperand", 759 [shl, srl, sra, rotr]> { 760 let EncoderMethod = "getSORegImmOpValue"; 761 let PrintMethod = "printSORegImmOperand"; 762 let DecoderMethod = "DecodeSORegImmOperand"; 763 let ParserMatchClass = ShiftedImmAsmOperand; 764 let MIOperandInfo = (ops GPR, i32imm); 765} 766 767// FIXME: Does this need to be distinct from so_reg? 768def shift_so_reg_reg : Operand<i32>, // reg reg imm 769 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand", 770 [shl,srl,sra,rotr]> { 771 let EncoderMethod = "getSORegRegOpValue"; 772 let PrintMethod = "printSORegRegOperand"; 773 let DecoderMethod = "DecodeSORegRegOperand"; 774 let ParserMatchClass = ShiftedRegAsmOperand; 775 let MIOperandInfo = (ops GPR, GPR, i32imm); 776} 777 778// FIXME: Does this need to be distinct from so_reg? 779def shift_so_reg_imm : Operand<i32>, // reg reg imm 780 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand", 781 [shl,srl,sra,rotr]> { 782 let EncoderMethod = "getSORegImmOpValue"; 783 let PrintMethod = "printSORegImmOperand"; 784 let DecoderMethod = "DecodeSORegImmOperand"; 785 let ParserMatchClass = ShiftedImmAsmOperand; 786 let MIOperandInfo = (ops GPR, i32imm); 787} 788 789// mod_imm: match a 32-bit immediate operand, which can be encoded into 790// a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM 791// - "Modified Immediate Constants"). Within the MC layer we keep this 792// immediate in its encoded form. 793def ModImmAsmOperand: AsmOperandClass { 794 let Name = "ModImm"; 795 let ParserMethod = "parseModImm"; 796} 797def mod_imm : Operand<i32>, ImmLeaf<i32, [{ 798 return ARM_AM::getSOImmVal(Imm) != -1; 799 }]> { 800 let EncoderMethod = "getModImmOpValue"; 801 let PrintMethod = "printModImmOperand"; 802 let ParserMatchClass = ModImmAsmOperand; 803} 804 805// Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder 806// method and such, as they are only used on aliases (Pat<> and InstAlias<>). 807// The actual parsing, encoding, decoding are handled by the destination 808// instructions, which use mod_imm. 809 810def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; } 811def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{ 812 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1; 813 }], imm_not_XFORM> { 814 let ParserMatchClass = ModImmNotAsmOperand; 815} 816 817def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; } 818def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{ 819 unsigned Value = -(unsigned)N->getZExtValue(); 820 return Value && ARM_AM::getSOImmVal(Value) != -1; 821 }], imm_neg_XFORM> { 822 let ParserMatchClass = ModImmNegAsmOperand; 823} 824 825/// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal() 826def arm_i32imm : IntImmLeaf<i32, [{ 827 if (Subtarget->useMovt()) 828 return true; 829 if (ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue())) 830 return true; 831 return ARM_AM::isSOImmTwoPartValNeg(Imm.getZExtValue()); 832}]>; 833 834/// imm0_1 predicate - Immediate in the range [0,1]. 835def Imm0_1AsmOperand: ImmAsmOperand<0,1> { let Name = "Imm0_1"; } 836def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; } 837 838/// imm0_3 predicate - Immediate in the range [0,3]. 839def Imm0_3AsmOperand: ImmAsmOperand<0,3> { let Name = "Imm0_3"; } 840def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; } 841 842/// imm0_7 predicate - Immediate in the range [0,7]. 843def Imm0_7AsmOperand: ImmAsmOperand<0,7> { 844 let Name = "Imm0_7"; 845} 846def imm0_7 : Operand<i32>, ImmLeaf<i32, [{ 847 return Imm >= 0 && Imm < 8; 848}]> { 849 let ParserMatchClass = Imm0_7AsmOperand; 850} 851 852/// imm8_255 predicate - Immediate in the range [8,255]. 853def Imm8_255AsmOperand: ImmAsmOperand<8,255> { let Name = "Imm8_255"; } 854def imm8_255 : Operand<i32>, ImmLeaf<i32, [{ 855 return Imm >= 8 && Imm < 256; 856}]> { 857 let ParserMatchClass = Imm8_255AsmOperand; 858} 859 860/// imm8 predicate - Immediate is exactly 8. 861def Imm8AsmOperand: ImmAsmOperand<8,8> { let Name = "Imm8"; } 862def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> { 863 let ParserMatchClass = Imm8AsmOperand; 864} 865 866/// imm16 predicate - Immediate is exactly 16. 867def Imm16AsmOperand: ImmAsmOperand<16,16> { let Name = "Imm16"; } 868def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> { 869 let ParserMatchClass = Imm16AsmOperand; 870} 871 872/// imm32 predicate - Immediate is exactly 32. 873def Imm32AsmOperand: ImmAsmOperand<32,32> { let Name = "Imm32"; } 874def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> { 875 let ParserMatchClass = Imm32AsmOperand; 876} 877 878def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>; 879 880/// imm1_7 predicate - Immediate in the range [1,7]. 881def Imm1_7AsmOperand: ImmAsmOperand<1,7> { let Name = "Imm1_7"; } 882def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> { 883 let ParserMatchClass = Imm1_7AsmOperand; 884} 885 886/// imm1_15 predicate - Immediate in the range [1,15]. 887def Imm1_15AsmOperand: ImmAsmOperand<1,15> { let Name = "Imm1_15"; } 888def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> { 889 let ParserMatchClass = Imm1_15AsmOperand; 890} 891 892/// imm1_31 predicate - Immediate in the range [1,31]. 893def Imm1_31AsmOperand: ImmAsmOperand<1,31> { let Name = "Imm1_31"; } 894def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> { 895 let ParserMatchClass = Imm1_31AsmOperand; 896} 897 898/// imm0_15 predicate - Immediate in the range [0,15]. 899def Imm0_15AsmOperand: ImmAsmOperand<0,15> { 900 let Name = "Imm0_15"; 901} 902def imm0_15 : Operand<i32>, ImmLeaf<i32, [{ 903 return Imm >= 0 && Imm < 16; 904}]> { 905 let ParserMatchClass = Imm0_15AsmOperand; 906} 907 908/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31]. 909def Imm0_31AsmOperand: ImmAsmOperand<0,31> { let Name = "Imm0_31"; } 910def imm0_31 : Operand<i32>, ImmLeaf<i32, [{ 911 return Imm >= 0 && Imm < 32; 912}]> { 913 let ParserMatchClass = Imm0_31AsmOperand; 914} 915 916/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32]. 917def Imm0_32AsmOperand: ImmAsmOperand<0,32> { let Name = "Imm0_32"; } 918def imm0_32 : Operand<i32>, ImmLeaf<i32, [{ 919 return Imm >= 0 && Imm < 33; 920}]> { 921 let ParserMatchClass = Imm0_32AsmOperand; 922} 923 924/// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63]. 925def Imm0_63AsmOperand: ImmAsmOperand<0,63> { let Name = "Imm0_63"; } 926def imm0_63 : Operand<i32>, ImmLeaf<i32, [{ 927 return Imm >= 0 && Imm < 64; 928}]> { 929 let ParserMatchClass = Imm0_63AsmOperand; 930} 931 932/// imm0_239 predicate - Immediate in the range [0,239]. 933def Imm0_239AsmOperand : ImmAsmOperand<0,239> { 934 let Name = "Imm0_239"; 935} 936def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> { 937 let ParserMatchClass = Imm0_239AsmOperand; 938} 939 940/// imm0_255 predicate - Immediate in the range [0,255]. 941def Imm0_255AsmOperand : ImmAsmOperand<0,255> { let Name = "Imm0_255"; } 942def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> { 943 let ParserMatchClass = Imm0_255AsmOperand; 944} 945 946/// imm0_65535 - An immediate is in the range [0,65535]. 947def Imm0_65535AsmOperand: ImmAsmOperand<0,65535> { let Name = "Imm0_65535"; } 948def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{ 949 return Imm >= 0 && Imm < 65536; 950}]> { 951 let ParserMatchClass = Imm0_65535AsmOperand; 952} 953 954// imm0_65535_neg - An immediate whose negative value is in the range [0.65535]. 955def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{ 956 return -Imm >= 0 && -Imm < 65536; 957}]>; 958 959// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference 960// a relocatable expression. 961// 962// FIXME: This really needs a Thumb version separate from the ARM version. 963// While the range is the same, and can thus use the same match class, 964// the encoding is different so it should have a different encoder method. 965def Imm0_65535ExprAsmOperand: AsmOperandClass { 966 let Name = "Imm0_65535Expr"; 967 let RenderMethod = "addImmOperands"; 968 let DiagnosticString = "operand must be an immediate in the range [0,0xffff] or a relocatable expression"; 969} 970 971def imm0_65535_expr : Operand<i32> { 972 let EncoderMethod = "getHiLo16ImmOpValue"; 973 let ParserMatchClass = Imm0_65535ExprAsmOperand; 974} 975 976def Imm256_65535ExprAsmOperand: ImmAsmOperand<256,65535> { let Name = "Imm256_65535Expr"; } 977def imm256_65535_expr : Operand<i32> { 978 let ParserMatchClass = Imm256_65535ExprAsmOperand; 979} 980 981/// imm24b - True if the 32-bit immediate is encodable in 24 bits. 982def Imm24bitAsmOperand: ImmAsmOperand<0,0xffffff> { 983 let Name = "Imm24bit"; 984 let DiagnosticString = "operand must be an immediate in the range [0,0xffffff]"; 985} 986def imm24b : Operand<i32>, ImmLeaf<i32, [{ 987 return Imm >= 0 && Imm <= 0xffffff; 988}]> { 989 let ParserMatchClass = Imm24bitAsmOperand; 990} 991 992 993/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield 994/// e.g., 0xf000ffff 995def BitfieldAsmOperand : AsmOperandClass { 996 let Name = "Bitfield"; 997 let ParserMethod = "parseBitfield"; 998} 999 1000def bf_inv_mask_imm : Operand<i32>, 1001 PatLeaf<(imm), [{ 1002 return ARM::isBitFieldInvertedMask(N->getZExtValue()); 1003}] > { 1004 let EncoderMethod = "getBitfieldInvertedMaskOpValue"; 1005 let PrintMethod = "printBitfieldInvMaskImmOperand"; 1006 let DecoderMethod = "DecodeBitfieldMaskOperand"; 1007 let ParserMatchClass = BitfieldAsmOperand; 1008 let GISelPredicateCode = [{ 1009 // There's better methods of implementing this check. IntImmLeaf<> would be 1010 // equivalent and have less boilerplate but we need a test for C++ 1011 // predicates and this one causes new rules to be imported into GlobalISel 1012 // without requiring additional features first. 1013 const auto &MO = MI.getOperand(1); 1014 if (!MO.isCImm()) 1015 return false; 1016 return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue()); 1017 }]; 1018} 1019 1020def imm1_32_XFORM: SDNodeXForm<imm, [{ 1021 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 1022 MVT::i32); 1023}]>; 1024def Imm1_32AsmOperand: ImmAsmOperandMinusOne<1,32> { 1025 let Name = "Imm1_32"; 1026} 1027def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ 1028 uint64_t Imm = N->getZExtValue(); 1029 return Imm > 0 && Imm <= 32; 1030 }], 1031 imm1_32_XFORM> { 1032 let PrintMethod = "printImmPlusOneOperand"; 1033 let ParserMatchClass = Imm1_32AsmOperand; 1034} 1035 1036def imm1_16_XFORM: SDNodeXForm<imm, [{ 1037 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 1038 MVT::i32); 1039}]>; 1040def Imm1_16AsmOperand: ImmAsmOperandMinusOne<1,16> { let Name = "Imm1_16"; } 1041def imm1_16 : Operand<i32>, ImmLeaf<i32, [{ 1042 return Imm > 0 && Imm <= 16; 1043 }], 1044 imm1_16_XFORM> { 1045 let PrintMethod = "printImmPlusOneOperand"; 1046 let ParserMatchClass = Imm1_16AsmOperand; 1047} 1048 1049def MVEShiftImm1_7AsmOperand: ImmAsmOperand<1,7> { 1050 let Name = "MVEShiftImm1_7"; 1051 // Reason we're doing this is because instruction vshll.s8 t1 encoding 1052 // accepts 1,7 but the t2 encoding accepts 8. By doing this we can get a 1053 // better diagnostic message if someone uses bigger immediate than the t1/t2 1054 // encodings allow. 1055 let DiagnosticString = "operand must be an immediate in the range [1,8]"; 1056} 1057def mve_shift_imm1_7 : Operand<i32>, 1058 // SelectImmediateInRange / isScaledConstantInRange uses a 1059 // half-open interval, so the parameters <1,8> mean 1-7 inclusive 1060 ComplexPattern<i32, 1, "SelectImmediateInRange<1,8>", [], []> { 1061 let ParserMatchClass = MVEShiftImm1_7AsmOperand; 1062 let EncoderMethod = "getMVEShiftImmOpValue"; 1063} 1064 1065def MVEShiftImm1_15AsmOperand: ImmAsmOperand<1,15> { 1066 let Name = "MVEShiftImm1_15"; 1067 // Reason we're doing this is because instruction vshll.s16 t1 encoding 1068 // accepts 1,15 but the t2 encoding accepts 16. By doing this we can get a 1069 // better diagnostic message if someone uses bigger immediate than the t1/t2 1070 // encodings allow. 1071 let DiagnosticString = "operand must be an immediate in the range [1,16]"; 1072} 1073def mve_shift_imm1_15 : Operand<i32>, 1074 // SelectImmediateInRange / isScaledConstantInRange uses a 1075 // half-open interval, so the parameters <1,16> mean 1-15 inclusive 1076 ComplexPattern<i32, 1, "SelectImmediateInRange<1,16>", [], []> { 1077 let ParserMatchClass = MVEShiftImm1_15AsmOperand; 1078 let EncoderMethod = "getMVEShiftImmOpValue"; 1079} 1080 1081// Define ARM specific addressing modes. 1082// addrmode_imm12 := reg +/- imm12 1083// 1084def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; } 1085class AddrMode_Imm12 : MemOperand, 1086 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> { 1087 // 12-bit immediate operand. Note that instructions using this encode 1088 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other 1089 // immediate values are as normal. 1090 1091 let EncoderMethod = "getAddrModeImm12OpValue"; 1092 let DecoderMethod = "DecodeAddrModeImm12Operand"; 1093 let ParserMatchClass = MemImm12OffsetAsmOperand; 1094 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 1095} 1096 1097def addrmode_imm12 : AddrMode_Imm12 { 1098 let PrintMethod = "printAddrModeImm12Operand<false>"; 1099} 1100 1101def addrmode_imm12_pre : AddrMode_Imm12 { 1102 let PrintMethod = "printAddrModeImm12Operand<true>"; 1103} 1104 1105// ldst_so_reg := reg +/- reg shop imm 1106// 1107def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; } 1108def ldst_so_reg : MemOperand, 1109 ComplexPattern<i32, 3, "SelectLdStSOReg", []> { 1110 let EncoderMethod = "getLdStSORegOpValue"; 1111 // FIXME: Simplify the printer 1112 let PrintMethod = "printAddrMode2Operand"; 1113 let DecoderMethod = "DecodeSORegMemOperand"; 1114 let ParserMatchClass = MemRegOffsetAsmOperand; 1115 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift); 1116} 1117 1118// postidx_imm8 := +/- [0,255] 1119// 1120// 9 bit value: 1121// {8} 1 is imm8 is non-negative. 0 otherwise. 1122// {7-0} [0,255] imm8 value. 1123def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; } 1124def postidx_imm8 : MemOperand { 1125 let PrintMethod = "printPostIdxImm8Operand"; 1126 let ParserMatchClass = PostIdxImm8AsmOperand; 1127 let MIOperandInfo = (ops i32imm); 1128} 1129 1130// postidx_imm8s4 := +/- [0,1020] 1131// 1132// 9 bit value: 1133// {8} 1 is imm8 is non-negative. 0 otherwise. 1134// {7-0} [0,255] imm8 value, scaled by 4. 1135def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; } 1136def postidx_imm8s4 : MemOperand { 1137 let PrintMethod = "printPostIdxImm8s4Operand"; 1138 let ParserMatchClass = PostIdxImm8s4AsmOperand; 1139 let MIOperandInfo = (ops i32imm); 1140} 1141 1142 1143// postidx_reg := +/- reg 1144// 1145def PostIdxRegAsmOperand : AsmOperandClass { 1146 let Name = "PostIdxReg"; 1147 let ParserMethod = "parsePostIdxReg"; 1148} 1149def postidx_reg : MemOperand { 1150 let EncoderMethod = "getPostIdxRegOpValue"; 1151 let DecoderMethod = "DecodePostIdxReg"; 1152 let PrintMethod = "printPostIdxRegOperand"; 1153 let ParserMatchClass = PostIdxRegAsmOperand; 1154 let MIOperandInfo = (ops GPRnopc, i32imm); 1155} 1156 1157def PostIdxRegShiftedAsmOperand : AsmOperandClass { 1158 let Name = "PostIdxRegShifted"; 1159 let ParserMethod = "parsePostIdxReg"; 1160} 1161def am2offset_reg : MemOperand, 1162 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg", 1163 [], [SDNPWantRoot]> { 1164 let EncoderMethod = "getAddrMode2OffsetOpValue"; 1165 let PrintMethod = "printAddrMode2OffsetOperand"; 1166 // When using this for assembly, it's always as a post-index offset. 1167 let ParserMatchClass = PostIdxRegShiftedAsmOperand; 1168 let MIOperandInfo = (ops GPRnopc, i32imm); 1169} 1170 1171// FIXME: am2offset_imm should only need the immediate, not the GPR. Having 1172// the GPR is purely vestigal at this point. 1173def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; } 1174def am2offset_imm : MemOperand, 1175 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm", 1176 [], [SDNPWantRoot]> { 1177 let EncoderMethod = "getAddrMode2OffsetOpValue"; 1178 let PrintMethod = "printAddrMode2OffsetOperand"; 1179 let ParserMatchClass = AM2OffsetImmAsmOperand; 1180 let MIOperandInfo = (ops GPRnopc, i32imm); 1181} 1182 1183 1184// addrmode3 := reg +/- reg 1185// addrmode3 := reg +/- imm8 1186// 1187// FIXME: split into imm vs. reg versions. 1188def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; } 1189class AddrMode3 : MemOperand, 1190 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 1191 let EncoderMethod = "getAddrMode3OpValue"; 1192 let ParserMatchClass = AddrMode3AsmOperand; 1193 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 1194} 1195 1196def addrmode3 : AddrMode3 1197{ 1198 let PrintMethod = "printAddrMode3Operand<false>"; 1199} 1200 1201def addrmode3_pre : AddrMode3 1202{ 1203 let PrintMethod = "printAddrMode3Operand<true>"; 1204} 1205 1206// FIXME: split into imm vs. reg versions. 1207// FIXME: parser method to handle +/- register. 1208def AM3OffsetAsmOperand : AsmOperandClass { 1209 let Name = "AM3Offset"; 1210 let ParserMethod = "parseAM3Offset"; 1211} 1212def am3offset : MemOperand, 1213 ComplexPattern<i32, 2, "SelectAddrMode3Offset", 1214 [], [SDNPWantRoot]> { 1215 let EncoderMethod = "getAddrMode3OffsetOpValue"; 1216 let PrintMethod = "printAddrMode3OffsetOperand"; 1217 let ParserMatchClass = AM3OffsetAsmOperand; 1218 let MIOperandInfo = (ops GPR, i32imm); 1219} 1220 1221// ldstm_mode := {ia, ib, da, db} 1222// 1223def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> { 1224 let EncoderMethod = "getLdStmModeOpValue"; 1225 let PrintMethod = "printLdStmModeOperand"; 1226} 1227 1228// addrmode5 := reg +/- imm8*4 1229// 1230def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; } 1231class AddrMode5 : MemOperand, 1232 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 1233 let EncoderMethod = "getAddrMode5OpValue"; 1234 let DecoderMethod = "DecodeAddrMode5Operand"; 1235 let ParserMatchClass = AddrMode5AsmOperand; 1236 let MIOperandInfo = (ops GPR:$base, i32imm); 1237} 1238 1239def addrmode5 : AddrMode5 { 1240 let PrintMethod = "printAddrMode5Operand<false>"; 1241} 1242 1243def addrmode5_pre : AddrMode5 { 1244 let PrintMethod = "printAddrMode5Operand<true>"; 1245} 1246 1247// addrmode5fp16 := reg +/- imm8*2 1248// 1249def AddrMode5FP16AsmOperand : AsmOperandClass { let Name = "AddrMode5FP16"; } 1250class AddrMode5FP16 : Operand<i32>, 1251 ComplexPattern<i32, 2, "SelectAddrMode5FP16", []> { 1252 let EncoderMethod = "getAddrMode5FP16OpValue"; 1253 let DecoderMethod = "DecodeAddrMode5FP16Operand"; 1254 let ParserMatchClass = AddrMode5FP16AsmOperand; 1255 let MIOperandInfo = (ops GPR:$base, i32imm); 1256} 1257 1258def addrmode5fp16 : AddrMode5FP16 { 1259 let PrintMethod = "printAddrMode5FP16Operand<false>"; 1260} 1261 1262// addrmode6 := reg with optional alignment 1263// 1264def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; } 1265def addrmode6 : MemOperand, 1266 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1267 let PrintMethod = "printAddrMode6Operand"; 1268 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1269 let EncoderMethod = "getAddrMode6AddressOpValue"; 1270 let DecoderMethod = "DecodeAddrMode6Operand"; 1271 let ParserMatchClass = AddrMode6AsmOperand; 1272} 1273 1274def am6offset : MemOperand, 1275 ComplexPattern<i32, 1, "SelectAddrMode6Offset", 1276 [], [SDNPWantRoot]> { 1277 let PrintMethod = "printAddrMode6OffsetOperand"; 1278 let MIOperandInfo = (ops GPR); 1279 let EncoderMethod = "getAddrMode6OffsetOpValue"; 1280 let DecoderMethod = "DecodeGPRRegisterClass"; 1281} 1282 1283// Special version of addrmode6 to handle alignment encoding for VST1/VLD1 1284// (single element from one lane) for size 32. 1285def addrmode6oneL32 : MemOperand, 1286 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1287 let PrintMethod = "printAddrMode6Operand"; 1288 let MIOperandInfo = (ops GPR:$addr, i32imm); 1289 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue"; 1290} 1291 1292// Base class for addrmode6 with specific alignment restrictions. 1293class AddrMode6Align : MemOperand, 1294 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1295 let PrintMethod = "printAddrMode6Operand"; 1296 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1297 let EncoderMethod = "getAddrMode6AddressOpValue"; 1298 let DecoderMethod = "DecodeAddrMode6Operand"; 1299} 1300 1301// Special version of addrmode6 to handle no allowed alignment encoding for 1302// VLD/VST instructions and checking the alignment is not specified. 1303def AddrMode6AlignNoneAsmOperand : AsmOperandClass { 1304 let Name = "AlignedMemoryNone"; 1305 let DiagnosticString = "alignment must be omitted"; 1306} 1307def addrmode6alignNone : AddrMode6Align { 1308 // The alignment specifier can only be omitted. 1309 let ParserMatchClass = AddrMode6AlignNoneAsmOperand; 1310} 1311 1312// Special version of addrmode6 to handle 16-bit alignment encoding for 1313// VLD/VST instructions and checking the alignment value. 1314def AddrMode6Align16AsmOperand : AsmOperandClass { 1315 let Name = "AlignedMemory16"; 1316 let DiagnosticString = "alignment must be 16 or omitted"; 1317} 1318def addrmode6align16 : AddrMode6Align { 1319 // The alignment specifier can only be 16 or omitted. 1320 let ParserMatchClass = AddrMode6Align16AsmOperand; 1321} 1322 1323// Special version of addrmode6 to handle 32-bit alignment encoding for 1324// VLD/VST instructions and checking the alignment value. 1325def AddrMode6Align32AsmOperand : AsmOperandClass { 1326 let Name = "AlignedMemory32"; 1327 let DiagnosticString = "alignment must be 32 or omitted"; 1328} 1329def addrmode6align32 : AddrMode6Align { 1330 // The alignment specifier can only be 32 or omitted. 1331 let ParserMatchClass = AddrMode6Align32AsmOperand; 1332} 1333 1334// Special version of addrmode6 to handle 64-bit alignment encoding for 1335// VLD/VST instructions and checking the alignment value. 1336def AddrMode6Align64AsmOperand : AsmOperandClass { 1337 let Name = "AlignedMemory64"; 1338 let DiagnosticString = "alignment must be 64 or omitted"; 1339} 1340def addrmode6align64 : AddrMode6Align { 1341 // The alignment specifier can only be 64 or omitted. 1342 let ParserMatchClass = AddrMode6Align64AsmOperand; 1343} 1344 1345// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1346// for VLD/VST instructions and checking the alignment value. 1347def AddrMode6Align64or128AsmOperand : AsmOperandClass { 1348 let Name = "AlignedMemory64or128"; 1349 let DiagnosticString = "alignment must be 64, 128 or omitted"; 1350} 1351def addrmode6align64or128 : AddrMode6Align { 1352 // The alignment specifier can only be 64, 128 or omitted. 1353 let ParserMatchClass = AddrMode6Align64or128AsmOperand; 1354} 1355 1356// Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment 1357// encoding for VLD/VST instructions and checking the alignment value. 1358def AddrMode6Align64or128or256AsmOperand : AsmOperandClass { 1359 let Name = "AlignedMemory64or128or256"; 1360 let DiagnosticString = "alignment must be 64, 128, 256 or omitted"; 1361} 1362def addrmode6align64or128or256 : AddrMode6Align { 1363 // The alignment specifier can only be 64, 128, 256 or omitted. 1364 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand; 1365} 1366 1367// Special version of addrmode6 to handle alignment encoding for VLD-dup 1368// instructions, specifically VLD4-dup. 1369def addrmode6dup : MemOperand, 1370 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1371 let PrintMethod = "printAddrMode6Operand"; 1372 let MIOperandInfo = (ops GPR:$addr, i32imm); 1373 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1374 // FIXME: This is close, but not quite right. The alignment specifier is 1375 // different. 1376 let ParserMatchClass = AddrMode6AsmOperand; 1377} 1378 1379// Base class for addrmode6dup with specific alignment restrictions. 1380class AddrMode6DupAlign : MemOperand, 1381 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1382 let PrintMethod = "printAddrMode6Operand"; 1383 let MIOperandInfo = (ops GPR:$addr, i32imm); 1384 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1385} 1386 1387// Special version of addrmode6 to handle no allowed alignment encoding for 1388// VLD-dup instruction and checking the alignment is not specified. 1389def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass { 1390 let Name = "DupAlignedMemoryNone"; 1391 let DiagnosticString = "alignment must be omitted"; 1392} 1393def addrmode6dupalignNone : AddrMode6DupAlign { 1394 // The alignment specifier can only be omitted. 1395 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand; 1396} 1397 1398// Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup 1399// instruction and checking the alignment value. 1400def AddrMode6dupAlign16AsmOperand : AsmOperandClass { 1401 let Name = "DupAlignedMemory16"; 1402 let DiagnosticString = "alignment must be 16 or omitted"; 1403} 1404def addrmode6dupalign16 : AddrMode6DupAlign { 1405 // The alignment specifier can only be 16 or omitted. 1406 let ParserMatchClass = AddrMode6dupAlign16AsmOperand; 1407} 1408 1409// Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup 1410// instruction and checking the alignment value. 1411def AddrMode6dupAlign32AsmOperand : AsmOperandClass { 1412 let Name = "DupAlignedMemory32"; 1413 let DiagnosticString = "alignment must be 32 or omitted"; 1414} 1415def addrmode6dupalign32 : AddrMode6DupAlign { 1416 // The alignment specifier can only be 32 or omitted. 1417 let ParserMatchClass = AddrMode6dupAlign32AsmOperand; 1418} 1419 1420// Special version of addrmode6 to handle 64-bit alignment encoding for VLD 1421// instructions and checking the alignment value. 1422def AddrMode6dupAlign64AsmOperand : AsmOperandClass { 1423 let Name = "DupAlignedMemory64"; 1424 let DiagnosticString = "alignment must be 64 or omitted"; 1425} 1426def addrmode6dupalign64 : AddrMode6DupAlign { 1427 // The alignment specifier can only be 64 or omitted. 1428 let ParserMatchClass = AddrMode6dupAlign64AsmOperand; 1429} 1430 1431// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1432// for VLD instructions and checking the alignment value. 1433def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass { 1434 let Name = "DupAlignedMemory64or128"; 1435 let DiagnosticString = "alignment must be 64, 128 or omitted"; 1436} 1437def addrmode6dupalign64or128 : AddrMode6DupAlign { 1438 // The alignment specifier can only be 64, 128 or omitted. 1439 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand; 1440} 1441 1442// addrmodepc := pc + reg 1443// 1444def addrmodepc : MemOperand, 1445 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 1446 let PrintMethod = "printAddrModePCOperand"; 1447 let MIOperandInfo = (ops GPR, i32imm); 1448} 1449 1450// addr_offset_none := reg 1451// 1452def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; } 1453def addr_offset_none : MemOperand, 1454 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> { 1455 let PrintMethod = "printAddrMode7Operand"; 1456 let DecoderMethod = "DecodeAddrMode7Operand"; 1457 let ParserMatchClass = MemNoOffsetAsmOperand; 1458 let MIOperandInfo = (ops GPR:$base); 1459} 1460 1461// t_addr_offset_none := reg [r0-r7] 1462def MemNoOffsetTAsmOperand : AsmOperandClass { let Name = "MemNoOffsetT"; } 1463def t_addr_offset_none : MemOperand { 1464 let PrintMethod = "printAddrMode7Operand"; 1465 let DecoderMethod = "DecodetGPRRegisterClass"; 1466 let ParserMatchClass = MemNoOffsetTAsmOperand; 1467 let MIOperandInfo = (ops tGPR:$base); 1468} 1469 1470def nohash_imm : Operand<i32> { 1471 let PrintMethod = "printNoHashImmediate"; 1472} 1473 1474def CoprocNumAsmOperand : AsmOperandClass { 1475 let Name = "CoprocNum"; 1476 let ParserMethod = "parseCoprocNumOperand"; 1477} 1478def p_imm : Operand<i32> { 1479 let PrintMethod = "printPImmediate"; 1480 let ParserMatchClass = CoprocNumAsmOperand; 1481 let DecoderMethod = "DecodeCoprocessor"; 1482} 1483 1484def CoprocRegAsmOperand : AsmOperandClass { 1485 let Name = "CoprocReg"; 1486 let ParserMethod = "parseCoprocRegOperand"; 1487} 1488def c_imm : Operand<i32> { 1489 let PrintMethod = "printCImmediate"; 1490 let ParserMatchClass = CoprocRegAsmOperand; 1491} 1492def CoprocOptionAsmOperand : AsmOperandClass { 1493 let Name = "CoprocOption"; 1494 let ParserMethod = "parseCoprocOptionOperand"; 1495} 1496def coproc_option_imm : Operand<i32> { 1497 let PrintMethod = "printCoprocOptionImm"; 1498 let ParserMatchClass = CoprocOptionAsmOperand; 1499} 1500 1501//===----------------------------------------------------------------------===// 1502 1503include "ARMInstrFormats.td" 1504 1505//===----------------------------------------------------------------------===// 1506// Multiclass helpers... 1507// 1508 1509/// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a 1510/// binop that produces a value. 1511let TwoOperandAliasConstraint = "$Rn = $Rd" in 1512multiclass AsI1_bin_irs<bits<4> opcod, string opc, 1513 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1514 SDPatternOperator opnode, bit Commutable = 0> { 1515 // The register-immediate version is re-materializable. This is useful 1516 // in particular for taking the address of a local. 1517 let isReMaterializable = 1 in { 1518 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1519 iii, opc, "\t$Rd, $Rn, $imm", 1520 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>, 1521 Sched<[WriteALU, ReadALU]> { 1522 bits<4> Rd; 1523 bits<4> Rn; 1524 bits<12> imm; 1525 let Inst{25} = 1; 1526 let Inst{19-16} = Rn; 1527 let Inst{15-12} = Rd; 1528 let Inst{11-0} = imm; 1529 } 1530 } 1531 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1532 iir, opc, "\t$Rd, $Rn, $Rm", 1533 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, 1534 Sched<[WriteALU, ReadALU, ReadALU]> { 1535 bits<4> Rd; 1536 bits<4> Rn; 1537 bits<4> Rm; 1538 let Inst{25} = 0; 1539 let isCommutable = Commutable; 1540 let Inst{19-16} = Rn; 1541 let Inst{15-12} = Rd; 1542 let Inst{11-4} = 0b00000000; 1543 let Inst{3-0} = Rm; 1544 } 1545 1546 def rsi : AsI1<opcod, (outs GPR:$Rd), 1547 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1548 iis, opc, "\t$Rd, $Rn, $shift", 1549 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>, 1550 Sched<[WriteALUsi, ReadALU]> { 1551 bits<4> Rd; 1552 bits<4> Rn; 1553 bits<12> shift; 1554 let Inst{25} = 0; 1555 let Inst{19-16} = Rn; 1556 let Inst{15-12} = Rd; 1557 let Inst{11-5} = shift{11-5}; 1558 let Inst{4} = 0; 1559 let Inst{3-0} = shift{3-0}; 1560 } 1561 1562 def rsr : AsI1<opcod, (outs GPR:$Rd), 1563 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1564 iis, opc, "\t$Rd, $Rn, $shift", 1565 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>, 1566 Sched<[WriteALUsr, ReadALUsr]> { 1567 bits<4> Rd; 1568 bits<4> Rn; 1569 bits<12> shift; 1570 let Inst{25} = 0; 1571 let Inst{19-16} = Rn; 1572 let Inst{15-12} = Rd; 1573 let Inst{11-8} = shift{11-8}; 1574 let Inst{7} = 0; 1575 let Inst{6-5} = shift{6-5}; 1576 let Inst{4} = 1; 1577 let Inst{3-0} = shift{3-0}; 1578 } 1579} 1580 1581/// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are 1582/// reversed. The 'rr' form is only defined for the disassembler; for codegen 1583/// it is equivalent to the AsI1_bin_irs counterpart. 1584let TwoOperandAliasConstraint = "$Rn = $Rd" in 1585multiclass AsI1_rbin_irs<bits<4> opcod, string opc, 1586 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1587 SDNode opnode, bit Commutable = 0> { 1588 // The register-immediate version is re-materializable. This is useful 1589 // in particular for taking the address of a local. 1590 let isReMaterializable = 1 in { 1591 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1592 iii, opc, "\t$Rd, $Rn, $imm", 1593 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>, 1594 Sched<[WriteALU, ReadALU]> { 1595 bits<4> Rd; 1596 bits<4> Rn; 1597 bits<12> imm; 1598 let Inst{25} = 1; 1599 let Inst{19-16} = Rn; 1600 let Inst{15-12} = Rd; 1601 let Inst{11-0} = imm; 1602 } 1603 } 1604 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1605 iir, opc, "\t$Rd, $Rn, $Rm", 1606 [/* pattern left blank */]>, 1607 Sched<[WriteALU, ReadALU, ReadALU]> { 1608 bits<4> Rd; 1609 bits<4> Rn; 1610 bits<4> Rm; 1611 let Inst{11-4} = 0b00000000; 1612 let Inst{25} = 0; 1613 let Inst{3-0} = Rm; 1614 let Inst{15-12} = Rd; 1615 let Inst{19-16} = Rn; 1616 } 1617 1618 def rsi : AsI1<opcod, (outs GPR:$Rd), 1619 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1620 iis, opc, "\t$Rd, $Rn, $shift", 1621 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>, 1622 Sched<[WriteALUsi, ReadALU]> { 1623 bits<4> Rd; 1624 bits<4> Rn; 1625 bits<12> shift; 1626 let Inst{25} = 0; 1627 let Inst{19-16} = Rn; 1628 let Inst{15-12} = Rd; 1629 let Inst{11-5} = shift{11-5}; 1630 let Inst{4} = 0; 1631 let Inst{3-0} = shift{3-0}; 1632 } 1633 1634 def rsr : AsI1<opcod, (outs GPR:$Rd), 1635 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1636 iis, opc, "\t$Rd, $Rn, $shift", 1637 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>, 1638 Sched<[WriteALUsr, ReadALUsr]> { 1639 bits<4> Rd; 1640 bits<4> Rn; 1641 bits<12> shift; 1642 let Inst{25} = 0; 1643 let Inst{19-16} = Rn; 1644 let Inst{15-12} = Rd; 1645 let Inst{11-8} = shift{11-8}; 1646 let Inst{7} = 0; 1647 let Inst{6-5} = shift{6-5}; 1648 let Inst{4} = 1; 1649 let Inst{3-0} = shift{3-0}; 1650 } 1651} 1652 1653/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default. 1654/// 1655/// These opcodes will be converted to the real non-S opcodes by 1656/// AdjustInstrPostInstrSelection after giving them an optional CPSR operand. 1657let hasPostISelHook = 1, Defs = [CPSR] in { 1658multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir, 1659 InstrItinClass iis, SDNode opnode, 1660 bit Commutable = 0> { 1661 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1662 4, iii, 1663 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>, 1664 Sched<[WriteALU, ReadALU]>; 1665 1666 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p), 1667 4, iir, 1668 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>, 1669 Sched<[WriteALU, ReadALU, ReadALU]> { 1670 let isCommutable = Commutable; 1671 } 1672 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1673 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1674 4, iis, 1675 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1676 so_reg_imm:$shift))]>, 1677 Sched<[WriteALUsi, ReadALU]>; 1678 1679 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1680 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1681 4, iis, 1682 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1683 so_reg_reg:$shift))]>, 1684 Sched<[WriteALUSsr, ReadALUsr]>; 1685} 1686} 1687 1688/// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG 1689/// operands are reversed. 1690let hasPostISelHook = 1, Defs = [CPSR] in { 1691multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir, 1692 InstrItinClass iis, SDNode opnode, 1693 bit Commutable = 0> { 1694 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1695 4, iii, 1696 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>, 1697 Sched<[WriteALU, ReadALU]>; 1698 1699 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1700 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1701 4, iis, 1702 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, 1703 GPR:$Rn))]>, 1704 Sched<[WriteALUsi, ReadALU]>; 1705 1706 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1707 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1708 4, iis, 1709 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, 1710 GPR:$Rn))]>, 1711 Sched<[WriteALUSsr, ReadALUsr]>; 1712} 1713} 1714 1715/// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test 1716/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 1717/// a explicit result, only implicitly set CPSR. 1718let isCompare = 1, Defs = [CPSR] in { 1719multiclass AI1_cmp_irs<bits<4> opcod, string opc, 1720 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1721 SDPatternOperator opnode, bit Commutable = 0, 1722 string rrDecoderMethod = ""> { 1723 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii, 1724 opc, "\t$Rn, $imm", 1725 [(opnode GPR:$Rn, mod_imm:$imm)]>, 1726 Sched<[WriteCMP, ReadALU]> { 1727 bits<4> Rn; 1728 bits<12> imm; 1729 let Inst{25} = 1; 1730 let Inst{20} = 1; 1731 let Inst{19-16} = Rn; 1732 let Inst{15-12} = 0b0000; 1733 let Inst{11-0} = imm; 1734 1735 let Unpredictable{15-12} = 0b1111; 1736 } 1737 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir, 1738 opc, "\t$Rn, $Rm", 1739 [(opnode GPR:$Rn, GPR:$Rm)]>, 1740 Sched<[WriteCMP, ReadALU, ReadALU]> { 1741 bits<4> Rn; 1742 bits<4> Rm; 1743 let isCommutable = Commutable; 1744 let Inst{25} = 0; 1745 let Inst{20} = 1; 1746 let Inst{19-16} = Rn; 1747 let Inst{15-12} = 0b0000; 1748 let Inst{11-4} = 0b00000000; 1749 let Inst{3-0} = Rm; 1750 let DecoderMethod = rrDecoderMethod; 1751 1752 let Unpredictable{15-12} = 0b1111; 1753 } 1754 def rsi : AI1<opcod, (outs), 1755 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis, 1756 opc, "\t$Rn, $shift", 1757 [(opnode GPR:$Rn, so_reg_imm:$shift)]>, 1758 Sched<[WriteCMPsi, ReadALU]> { 1759 bits<4> Rn; 1760 bits<12> shift; 1761 let Inst{25} = 0; 1762 let Inst{20} = 1; 1763 let Inst{19-16} = Rn; 1764 let Inst{15-12} = 0b0000; 1765 let Inst{11-5} = shift{11-5}; 1766 let Inst{4} = 0; 1767 let Inst{3-0} = shift{3-0}; 1768 1769 let Unpredictable{15-12} = 0b1111; 1770 } 1771 def rsr : AI1<opcod, (outs), 1772 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis, 1773 opc, "\t$Rn, $shift", 1774 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>, 1775 Sched<[WriteCMPsr, ReadALU]> { 1776 bits<4> Rn; 1777 bits<12> shift; 1778 let Inst{25} = 0; 1779 let Inst{20} = 1; 1780 let Inst{19-16} = Rn; 1781 let Inst{15-12} = 0b0000; 1782 let Inst{11-8} = shift{11-8}; 1783 let Inst{7} = 0; 1784 let Inst{6-5} = shift{6-5}; 1785 let Inst{4} = 1; 1786 let Inst{3-0} = shift{3-0}; 1787 1788 let Unpredictable{15-12} = 0b1111; 1789 } 1790 1791} 1792} 1793 1794/// AI_ext_rrot - A unary operation with two forms: one whose operand is a 1795/// register and one whose operand is a register rotated by 8/16/24. 1796/// FIXME: Remove the 'r' variant. Its rot_imm is zero. 1797class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> 1798 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1799 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", 1800 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1801 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1802 bits<4> Rd; 1803 bits<4> Rm; 1804 bits<2> rot; 1805 let Inst{19-16} = 0b1111; 1806 let Inst{15-12} = Rd; 1807 let Inst{11-10} = rot; 1808 let Inst{3-0} = Rm; 1809} 1810 1811class AI_ext_rrot_np<bits<8> opcod, string opc> 1812 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1813 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>, 1814 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1815 bits<2> rot; 1816 let Inst{19-16} = 0b1111; 1817 let Inst{11-10} = rot; 1818 } 1819 1820/// AI_exta_rrot - A binary operation with two forms: one whose operand is a 1821/// register and one whose operand is a register rotated by 8/16/24. 1822class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> 1823 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1824 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", 1825 [(set GPRnopc:$Rd, (opnode GPR:$Rn, 1826 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1827 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1828 bits<4> Rd; 1829 bits<4> Rm; 1830 bits<4> Rn; 1831 bits<2> rot; 1832 let Inst{19-16} = Rn; 1833 let Inst{15-12} = Rd; 1834 let Inst{11-10} = rot; 1835 let Inst{9-4} = 0b000111; 1836 let Inst{3-0} = Rm; 1837} 1838 1839class AI_exta_rrot_np<bits<8> opcod, string opc> 1840 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1841 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>, 1842 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1843 bits<4> Rn; 1844 bits<2> rot; 1845 let Inst{19-16} = Rn; 1846 let Inst{11-10} = rot; 1847} 1848 1849/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. 1850let TwoOperandAliasConstraint = "$Rn = $Rd" in 1851multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode, 1852 bit Commutable = 0> { 1853 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1854 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1855 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1856 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>, 1857 Requires<[IsARM]>, 1858 Sched<[WriteALU, ReadALU]> { 1859 bits<4> Rd; 1860 bits<4> Rn; 1861 bits<12> imm; 1862 let Inst{25} = 1; 1863 let Inst{15-12} = Rd; 1864 let Inst{19-16} = Rn; 1865 let Inst{11-0} = imm; 1866 } 1867 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1868 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1869 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>, 1870 Requires<[IsARM]>, 1871 Sched<[WriteALU, ReadALU, ReadALU]> { 1872 bits<4> Rd; 1873 bits<4> Rn; 1874 bits<4> Rm; 1875 let Inst{11-4} = 0b00000000; 1876 let Inst{25} = 0; 1877 let isCommutable = Commutable; 1878 let Inst{3-0} = Rm; 1879 let Inst{15-12} = Rd; 1880 let Inst{19-16} = Rn; 1881 } 1882 def rsi : AsI1<opcod, (outs GPR:$Rd), 1883 (ins GPR:$Rn, so_reg_imm:$shift), 1884 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1885 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>, 1886 Requires<[IsARM]>, 1887 Sched<[WriteALUsi, ReadALU]> { 1888 bits<4> Rd; 1889 bits<4> Rn; 1890 bits<12> shift; 1891 let Inst{25} = 0; 1892 let Inst{19-16} = Rn; 1893 let Inst{15-12} = Rd; 1894 let Inst{11-5} = shift{11-5}; 1895 let Inst{4} = 0; 1896 let Inst{3-0} = shift{3-0}; 1897 } 1898 def rsr : AsI1<opcod, (outs GPRnopc:$Rd), 1899 (ins GPRnopc:$Rn, so_reg_reg:$shift), 1900 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1901 [(set GPRnopc:$Rd, CPSR, 1902 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>, 1903 Requires<[IsARM]>, 1904 Sched<[WriteALUsr, ReadALUsr]> { 1905 bits<4> Rd; 1906 bits<4> Rn; 1907 bits<12> shift; 1908 let Inst{25} = 0; 1909 let Inst{19-16} = Rn; 1910 let Inst{15-12} = Rd; 1911 let Inst{11-8} = shift{11-8}; 1912 let Inst{7} = 0; 1913 let Inst{6-5} = shift{6-5}; 1914 let Inst{4} = 1; 1915 let Inst{3-0} = shift{3-0}; 1916 } 1917 } 1918} 1919 1920/// AI1_rsc_irs - Define instructions and patterns for rsc 1921let TwoOperandAliasConstraint = "$Rn = $Rd" in 1922multiclass AI1_rsc_irs<bits<4> opcod, string opc, SDNode opnode> { 1923 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1924 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1925 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1926 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>, 1927 Requires<[IsARM]>, 1928 Sched<[WriteALU, ReadALU]> { 1929 bits<4> Rd; 1930 bits<4> Rn; 1931 bits<12> imm; 1932 let Inst{25} = 1; 1933 let Inst{15-12} = Rd; 1934 let Inst{19-16} = Rn; 1935 let Inst{11-0} = imm; 1936 } 1937 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1938 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1939 [/* pattern left blank */]>, 1940 Sched<[WriteALU, ReadALU, ReadALU]> { 1941 bits<4> Rd; 1942 bits<4> Rn; 1943 bits<4> Rm; 1944 let Inst{11-4} = 0b00000000; 1945 let Inst{25} = 0; 1946 let Inst{3-0} = Rm; 1947 let Inst{15-12} = Rd; 1948 let Inst{19-16} = Rn; 1949 } 1950 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), 1951 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1952 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>, 1953 Requires<[IsARM]>, 1954 Sched<[WriteALUsi, ReadALU]> { 1955 bits<4> Rd; 1956 bits<4> Rn; 1957 bits<12> shift; 1958 let Inst{25} = 0; 1959 let Inst{19-16} = Rn; 1960 let Inst{15-12} = Rd; 1961 let Inst{11-5} = shift{11-5}; 1962 let Inst{4} = 0; 1963 let Inst{3-0} = shift{3-0}; 1964 } 1965 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), 1966 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1967 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>, 1968 Requires<[IsARM]>, 1969 Sched<[WriteALUsr, ReadALUsr]> { 1970 bits<4> Rd; 1971 bits<4> Rn; 1972 bits<12> shift; 1973 let Inst{25} = 0; 1974 let Inst{19-16} = Rn; 1975 let Inst{15-12} = Rd; 1976 let Inst{11-8} = shift{11-8}; 1977 let Inst{7} = 0; 1978 let Inst{6-5} = shift{6-5}; 1979 let Inst{4} = 1; 1980 let Inst{3-0} = shift{3-0}; 1981 } 1982 } 1983} 1984 1985let canFoldAsLoad = 1, isReMaterializable = 1 in { 1986multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii, 1987 InstrItinClass iir, PatFrag opnode> { 1988 // Note: We use the complex addrmode_imm12 rather than just an input 1989 // GPR and a constrained immediate so that we can use this to match 1990 // frame index references and avoid matching constant pool references. 1991 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 1992 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1993 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { 1994 bits<4> Rt; 1995 bits<17> addr; 1996 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1997 let Inst{19-16} = addr{16-13}; // Rn 1998 let Inst{15-12} = Rt; 1999 let Inst{11-0} = addr{11-0}; // imm12 2000 } 2001 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift), 2002 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 2003 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { 2004 bits<4> Rt; 2005 bits<17> shift; 2006 let shift{4} = 0; // Inst{4} = 0 2007 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2008 let Inst{19-16} = shift{16-13}; // Rn 2009 let Inst{15-12} = Rt; 2010 let Inst{11-0} = shift{11-0}; 2011 } 2012} 2013} 2014 2015let canFoldAsLoad = 1, isReMaterializable = 1 in { 2016multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii, 2017 InstrItinClass iir, PatFrag opnode> { 2018 // Note: We use the complex addrmode_imm12 rather than just an input 2019 // GPR and a constrained immediate so that we can use this to match 2020 // frame index references and avoid matching constant pool references. 2021 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), 2022 (ins addrmode_imm12:$addr), 2023 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 2024 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> { 2025 bits<4> Rt; 2026 bits<17> addr; 2027 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2028 let Inst{19-16} = addr{16-13}; // Rn 2029 let Inst{15-12} = Rt; 2030 let Inst{11-0} = addr{11-0}; // imm12 2031 } 2032 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), 2033 (ins ldst_so_reg:$shift), 2034 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 2035 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> { 2036 bits<4> Rt; 2037 bits<17> shift; 2038 let shift{4} = 0; // Inst{4} = 0 2039 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2040 let Inst{19-16} = shift{16-13}; // Rn 2041 let Inst{15-12} = Rt; 2042 let Inst{11-0} = shift{11-0}; 2043 } 2044} 2045} 2046 2047 2048multiclass AI_str1<bit isByte, string opc, InstrItinClass iii, 2049 InstrItinClass iir, PatFrag opnode> { 2050 // Note: We use the complex addrmode_imm12 rather than just an input 2051 // GPR and a constrained immediate so that we can use this to match 2052 // frame index references and avoid matching constant pool references. 2053 def i12 : AI2ldst<0b010, 0, isByte, (outs), 2054 (ins GPR:$Rt, addrmode_imm12:$addr), 2055 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 2056 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> { 2057 bits<4> Rt; 2058 bits<17> addr; 2059 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2060 let Inst{19-16} = addr{16-13}; // Rn 2061 let Inst{15-12} = Rt; 2062 let Inst{11-0} = addr{11-0}; // imm12 2063 } 2064 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift), 2065 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 2066 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> { 2067 bits<4> Rt; 2068 bits<17> shift; 2069 let shift{4} = 0; // Inst{4} = 0 2070 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2071 let Inst{19-16} = shift{16-13}; // Rn 2072 let Inst{15-12} = Rt; 2073 let Inst{11-0} = shift{11-0}; 2074 } 2075} 2076 2077multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii, 2078 InstrItinClass iir, PatFrag opnode> { 2079 // Note: We use the complex addrmode_imm12 rather than just an input 2080 // GPR and a constrained immediate so that we can use this to match 2081 // frame index references and avoid matching constant pool references. 2082 def i12 : AI2ldst<0b010, 0, isByte, (outs), 2083 (ins GPRnopc:$Rt, addrmode_imm12:$addr), 2084 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 2085 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> { 2086 bits<4> Rt; 2087 bits<17> addr; 2088 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2089 let Inst{19-16} = addr{16-13}; // Rn 2090 let Inst{15-12} = Rt; 2091 let Inst{11-0} = addr{11-0}; // imm12 2092 } 2093 def rs : AI2ldst<0b011, 0, isByte, (outs), 2094 (ins GPRnopc:$Rt, ldst_so_reg:$shift), 2095 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 2096 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> { 2097 bits<4> Rt; 2098 bits<17> shift; 2099 let shift{4} = 0; // Inst{4} = 0 2100 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2101 let Inst{19-16} = shift{16-13}; // Rn 2102 let Inst{15-12} = Rt; 2103 let Inst{11-0} = shift{11-0}; 2104 } 2105} 2106 2107 2108//===----------------------------------------------------------------------===// 2109// Instructions 2110//===----------------------------------------------------------------------===// 2111 2112//===----------------------------------------------------------------------===// 2113// Miscellaneous Instructions. 2114// 2115 2116/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 2117/// the function. The first operand is the ID# for this instruction, the second 2118/// is the index into the MachineConstantPool that this is, the third is the 2119/// size in bytes of this constant pool entry. 2120let hasSideEffects = 0, isNotDuplicable = 1, hasNoSchedulingInfo = 1 in 2121def CONSTPOOL_ENTRY : 2122PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2123 i32imm:$size), NoItinerary, []>; 2124 2125/// A jumptable consisting of direct 32-bit addresses of the destination basic 2126/// blocks (either absolute, or relative to the start of the jump-table in PIC 2127/// mode). Used mostly in ARM and Thumb-1 modes. 2128def JUMPTABLE_ADDRS : 2129PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2130 i32imm:$size), NoItinerary, []>; 2131 2132/// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables 2133/// that cannot be optimised to use TBB or TBH. 2134def JUMPTABLE_INSTS : 2135PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2136 i32imm:$size), NoItinerary, []>; 2137 2138/// A jumptable consisting of 8-bit unsigned integers representing offsets from 2139/// a TBB instruction. 2140def JUMPTABLE_TBB : 2141PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2142 i32imm:$size), NoItinerary, []>; 2143 2144/// A jumptable consisting of 16-bit unsigned integers representing offsets from 2145/// a TBH instruction. 2146def JUMPTABLE_TBH : 2147PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2148 i32imm:$size), NoItinerary, []>; 2149 2150 2151// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 2152// from removing one half of the matched pairs. That breaks PEI, which assumes 2153// these will always be in pairs, and asserts if it finds otherwise. Better way? 2154let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 2155def ADJCALLSTACKUP : 2156PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, 2157 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; 2158 2159def ADJCALLSTACKDOWN : 2160PseudoInst<(outs), (ins i32imm:$amt, i32imm:$amt2, pred:$p), NoItinerary, 2161 [(ARMcallseq_start timm:$amt, timm:$amt2)]>; 2162} 2163 2164def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary, 2165 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>, 2166 Requires<[IsARM, HasV6]> { 2167 bits<8> imm; 2168 let Inst{27-8} = 0b00110010000011110000; 2169 let Inst{7-0} = imm; 2170 let DecoderMethod = "DecodeHINTInstruction"; 2171} 2172 2173def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>; 2174def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>; 2175def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>; 2176def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>; 2177def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>; 2178def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>; 2179def : InstAlias<"esb$p", (HINT 16, pred:$p)>, Requires<[IsARM, HasRAS]>; 2180def : InstAlias<"csdb$p", (HINT 20, pred:$p)>, Requires<[IsARM, HasV6K]>; 2181 2182def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel", 2183 "\t$Rd, $Rn, $Rm", 2184 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>, 2185 Requires<[IsARM, HasV6]> { 2186 bits<4> Rd; 2187 bits<4> Rn; 2188 bits<4> Rm; 2189 let Inst{3-0} = Rm; 2190 let Inst{15-12} = Rd; 2191 let Inst{19-16} = Rn; 2192 let Inst{27-20} = 0b01101000; 2193 let Inst{7-4} = 0b1011; 2194 let Inst{11-8} = 0b1111; 2195 let Unpredictable{11-8} = 0b1111; 2196} 2197 2198// The 16-bit operand $val can be used by a debugger to store more information 2199// about the breakpoint. 2200def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 2201 "bkpt", "\t$val", []>, Requires<[IsARM]> { 2202 bits<16> val; 2203 let Inst{3-0} = val{3-0}; 2204 let Inst{19-8} = val{15-4}; 2205 let Inst{27-20} = 0b00010010; 2206 let Inst{31-28} = 0xe; // AL 2207 let Inst{7-4} = 0b0111; 2208} 2209// default immediate for breakpoint mnemonic 2210def : InstAlias<"bkpt", (BKPT 0), 0>, Requires<[IsARM]>; 2211 2212def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 2213 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> { 2214 bits<16> val; 2215 let Inst{3-0} = val{3-0}; 2216 let Inst{19-8} = val{15-4}; 2217 let Inst{27-20} = 0b00010000; 2218 let Inst{31-28} = 0xe; // AL 2219 let Inst{7-4} = 0b0111; 2220} 2221 2222// Change Processor State 2223// FIXME: We should use InstAlias to handle the optional operands. 2224class CPS<dag iops, string asm_ops> 2225 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops), 2226 []>, Requires<[IsARM]> { 2227 bits<2> imod; 2228 bits<3> iflags; 2229 bits<5> mode; 2230 bit M; 2231 2232 let Inst{31-28} = 0b1111; 2233 let Inst{27-20} = 0b00010000; 2234 let Inst{19-18} = imod; 2235 let Inst{17} = M; // Enabled if mode is set; 2236 let Inst{16-9} = 0b00000000; 2237 let Inst{8-6} = iflags; 2238 let Inst{5} = 0; 2239 let Inst{4-0} = mode; 2240} 2241 2242let DecoderMethod = "DecodeCPSInstruction" in { 2243let M = 1 in 2244 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode), 2245 "$imod\t$iflags, $mode">; 2246let mode = 0, M = 0 in 2247 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">; 2248 2249let imod = 0, iflags = 0, M = 1 in 2250 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">; 2251} 2252 2253// Preload signals the memory system of possible future data/instruction access. 2254multiclass APreLoad<bits<1> read, bits<1> data, string opc> { 2255 2256 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm, 2257 IIC_Preload, !strconcat(opc, "\t$addr"), 2258 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>, 2259 Sched<[WritePreLd]> { 2260 bits<4> Rt; 2261 bits<17> addr; 2262 let Inst{31-26} = 0b111101; 2263 let Inst{25} = 0; // 0 for immediate form 2264 let Inst{24} = data; 2265 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2266 let Inst{22} = read; 2267 let Inst{21-20} = 0b01; 2268 let Inst{19-16} = addr{16-13}; // Rn 2269 let Inst{15-12} = 0b1111; 2270 let Inst{11-0} = addr{11-0}; // imm12 2271 } 2272 2273 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, 2274 !strconcat(opc, "\t$shift"), 2275 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>, 2276 Sched<[WritePreLd]> { 2277 bits<17> shift; 2278 let Inst{31-26} = 0b111101; 2279 let Inst{25} = 1; // 1 for register form 2280 let Inst{24} = data; 2281 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2282 let Inst{22} = read; 2283 let Inst{21-20} = 0b01; 2284 let Inst{19-16} = shift{16-13}; // Rn 2285 let Inst{15-12} = 0b1111; 2286 let Inst{11-0} = shift{11-0}; 2287 let Inst{4} = 0; 2288 } 2289} 2290 2291defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>; 2292defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>; 2293defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>; 2294 2295def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary, 2296 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> { 2297 bits<1> end; 2298 let Inst{31-10} = 0b1111000100000001000000; 2299 let Inst{9} = end; 2300 let Inst{8-0} = 0; 2301} 2302 2303def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", 2304 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> { 2305 bits<4> opt; 2306 let Inst{27-4} = 0b001100100000111100001111; 2307 let Inst{3-0} = opt; 2308} 2309 2310// A8.8.247 UDF - Undefined (Encoding A1) 2311def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary, 2312 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> { 2313 bits<16> imm16; 2314 let Inst{31-28} = 0b1110; // AL 2315 let Inst{27-25} = 0b011; 2316 let Inst{24-20} = 0b11111; 2317 let Inst{19-8} = imm16{15-4}; 2318 let Inst{7-4} = 0b1111; 2319 let Inst{3-0} = imm16{3-0}; 2320} 2321 2322/* 2323 * A5.4 Permanently UNDEFINED instructions. 2324 * 2325 * For most targets use UDF #65006, for which the OS will generate SIGTRAP. 2326 * Other UDF encodings generate SIGILL. 2327 * 2328 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb. 2329 * Encoding A1: 2330 * 1110 0111 1111 iiii iiii iiii 1111 iiii 2331 * Encoding T1: 2332 * 1101 1110 iiii iiii 2333 * It uses the following encoding: 2334 * 1110 0111 1111 1110 1101 1110 1111 0000 2335 * - In ARM: UDF #60896; 2336 * - In Thumb: UDF #254 followed by a branch-to-self. 2337 */ 2338let isBarrier = 1, isTerminator = 1 in 2339def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary, 2340 "trap", [(trap)]>, 2341 Requires<[IsARM,UseNaClTrap]> { 2342 let Inst = 0xe7fedef0; 2343} 2344let isBarrier = 1, isTerminator = 1 in 2345def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, 2346 "trap", [(trap)]>, 2347 Requires<[IsARM,DontUseNaClTrap]> { 2348 let Inst = 0xe7ffdefe; 2349} 2350 2351def : Pat<(debugtrap), (BKPT 0)>, Requires<[IsARM, HasV5T]>; 2352def : Pat<(debugtrap), (UDF 254)>, Requires<[IsARM, NoV5T]>; 2353 2354// Address computation and loads and stores in PIC mode. 2355let isNotDuplicable = 1 in { 2356def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 2357 4, IIC_iALUr, 2358 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>, 2359 Sched<[WriteALU, ReadALU]>; 2360 2361let AddedComplexity = 10 in { 2362def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 2363 4, IIC_iLoad_r, 2364 [(set GPR:$dst, (load addrmodepc:$addr))]>; 2365 2366def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2367 4, IIC_iLoad_bh_r, 2368 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>; 2369 2370def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2371 4, IIC_iLoad_bh_r, 2372 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>; 2373 2374def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2375 4, IIC_iLoad_bh_r, 2376 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>; 2377 2378def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2379 4, IIC_iLoad_bh_r, 2380 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>; 2381} 2382let AddedComplexity = 10 in { 2383def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2384 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>; 2385 2386def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2387 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, 2388 addrmodepc:$addr)]>; 2389 2390def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2391 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 2392} 2393} // isNotDuplicable = 1 2394 2395 2396// LEApcrel - Load a pc-relative address into a register without offending the 2397// assembler. 2398let hasSideEffects = 0, isReMaterializable = 1 in 2399// The 'adr' mnemonic encodes differently if the label is before or after 2400// the instruction. The {24-21} opcode bits are set by the fixup, as we don't 2401// know until then which form of the instruction will be used. 2402def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), 2403 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>, 2404 Sched<[WriteALU, ReadALU]> { 2405 bits<4> Rd; 2406 bits<14> label; 2407 let Inst{27-25} = 0b001; 2408 let Inst{24} = 0; 2409 let Inst{23-22} = label{13-12}; 2410 let Inst{21} = 0; 2411 let Inst{20} = 0; 2412 let Inst{19-16} = 0b1111; 2413 let Inst{15-12} = Rd; 2414 let Inst{11-0} = label{11-0}; 2415} 2416 2417let hasSideEffects = 1 in { 2418def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 2419 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2420 2421def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd), 2422 (ins i32imm:$label, pred:$p), 2423 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2424} 2425 2426//===----------------------------------------------------------------------===// 2427// Control Flow Instructions. 2428// 2429 2430let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 2431 // ARMV4T and above 2432 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2433 "bx", "\tlr", [(ARMretflag)]>, 2434 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2435 let Inst{27-0} = 0b0001001011111111111100011110; 2436 } 2437 2438 // ARMV4 only 2439 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2440 "mov", "\tpc, lr", [(ARMretflag)]>, 2441 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> { 2442 let Inst{27-0} = 0b0001101000001111000000001110; 2443 } 2444 2445 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets 2446 // the user-space one). 2447 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p), 2448 4, IIC_Br, 2449 [(ARMintretflag imm:$offset)]>; 2450} 2451 2452// Indirect branches 2453let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 2454 // ARMV4T and above 2455 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst", 2456 [(brind GPR:$dst)]>, 2457 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2458 bits<4> dst; 2459 let Inst{31-4} = 0b1110000100101111111111110001; 2460 let Inst{3-0} = dst; 2461 } 2462 2463 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, 2464 "bx", "\t$dst", [/* pattern left blank */]>, 2465 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2466 bits<4> dst; 2467 let Inst{27-4} = 0b000100101111111111110001; 2468 let Inst{3-0} = dst; 2469 } 2470} 2471 2472// SP is marked as a use to prevent stack-pointer assignments that appear 2473// immediately before calls from potentially appearing dead. 2474let isCall = 1, 2475 // FIXME: Do we really need a non-predicated version? If so, it should 2476 // at least be a pseudo instruction expanding to the predicated version 2477 // at MC lowering time. 2478 Defs = [LR], Uses = [SP] in { 2479 def BL : ABXI<0b1011, (outs), (ins arm_bl_target:$func), 2480 IIC_Br, "bl\t$func", 2481 [(ARMcall tglobaladdr:$func)]>, 2482 Requires<[IsARM]>, Sched<[WriteBrL]> { 2483 let Inst{31-28} = 0b1110; 2484 bits<24> func; 2485 let Inst{23-0} = func; 2486 let DecoderMethod = "DecodeBranchImmInstruction"; 2487 } 2488 2489 def BL_pred : ABI<0b1011, (outs), (ins arm_bl_target:$func), 2490 IIC_Br, "bl", "\t$func", 2491 [(ARMcall_pred tglobaladdr:$func)]>, 2492 Requires<[IsARM]>, Sched<[WriteBrL]> { 2493 bits<24> func; 2494 let Inst{23-0} = func; 2495 let DecoderMethod = "DecodeBranchImmInstruction"; 2496 } 2497 2498 // ARMv5T and above 2499 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm, IIC_Br, "blx\t$func", []>, 2500 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2501 bits<4> func; 2502 let Inst{31-4} = 0b1110000100101111111111110011; 2503 let Inst{3-0} = func; 2504 } 2505 def BLX_noip : ARMPseudoExpand<(outs), (ins GPRnoip:$func), 2506 4, IIC_Br, [], (BLX GPR:$func)>, 2507 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]>; 2508 2509 2510 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm, 2511 IIC_Br, "blx", "\t$func", []>, 2512 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2513 bits<4> func; 2514 let Inst{27-4} = 0b000100101111111111110011; 2515 let Inst{3-0} = func; 2516 } 2517 def BLX_pred_noip : ARMPseudoExpand<(outs), (ins GPRnoip:$func), 2518 4, IIC_Br, [], 2519 (BLX_pred GPR:$func, (ops 14, zero_reg))>, 2520 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]>; 2521 2522 2523 // ARMv4T 2524 // Note: Restrict $func to the tGPR regclass to prevent it being in LR. 2525 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2526 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2527 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>; 2528 2529 // ARMv4 2530 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2531 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2532 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 2533 2534 // mov lr, pc; b if callee is marked noreturn to avoid confusing the 2535 // return stack predictor. 2536 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins arm_bl_target:$func), 2537 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>, 2538 Requires<[IsARM]>, Sched<[WriteBr]>; 2539 2540 // push lr before the call 2541 def BL_PUSHLR : ARMPseudoInst<(outs), (ins GPRlr:$ra, arm_bl_target:$func), 2542 4, IIC_Br, 2543 []>, 2544 Requires<[IsARM]>, Sched<[WriteBr]>; 2545} 2546 2547def : ARMPat<(ARMcall GPR:$func), (BLX $func)>, 2548 Requires<[IsARM, HasV5T, NoSLSBLRMitigation]>; 2549def : ARMPat<(ARMcall GPRnoip:$func), (BLX_noip $func)>, 2550 Requires<[IsARM, HasV5T, SLSBLRMitigation]>; 2551def : ARMPat<(ARMcall_pred GPR:$func), (BLX_pred $func)>, 2552 Requires<[IsARM, HasV5T, NoSLSBLRMitigation]>; 2553def : ARMPat<(ARMcall_pred GPRnoip:$func), (BLX_pred_noip $func)>, 2554 Requires<[IsARM, HasV5T, SLSBLRMitigation]>; 2555 2556 2557let isBranch = 1, isTerminator = 1 in { 2558 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 2559 // a two-value operand where a dag node expects two operands. :( 2560 def Bcc : ABI<0b1010, (outs), (ins arm_br_target:$target), 2561 IIC_Br, "b", "\t$target", 2562 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>, 2563 Sched<[WriteBr]> { 2564 bits<24> target; 2565 let Inst{23-0} = target; 2566 let DecoderMethod = "DecodeBranchImmInstruction"; 2567 } 2568 2569 let isBarrier = 1 in { 2570 // B is "predicable" since it's just a Bcc with an 'always' condition. 2571 let isPredicable = 1 in 2572 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly 2573 // should be sufficient. 2574 // FIXME: Is B really a Barrier? That doesn't seem right. 2575 def B : ARMPseudoExpand<(outs), (ins arm_br_target:$target), 4, IIC_Br, 2576 [(br bb:$target)], (Bcc arm_br_target:$target, 2577 (ops 14, zero_reg))>, 2578 Sched<[WriteBr]>; 2579 2580 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in { 2581 def BR_JTr : ARMPseudoInst<(outs), 2582 (ins GPR:$target, i32imm:$jt), 2583 0, IIC_Br, 2584 [(ARMbrjt GPR:$target, tjumptable:$jt)]>, 2585 Sched<[WriteBr]>; 2586 def BR_JTm_i12 : ARMPseudoInst<(outs), 2587 (ins addrmode_imm12:$target, i32imm:$jt), 2588 0, IIC_Br, 2589 [(ARMbrjt (i32 (load addrmode_imm12:$target)), 2590 tjumptable:$jt)]>, Sched<[WriteBrTbl]>; 2591 def BR_JTm_rs : ARMPseudoInst<(outs), 2592 (ins ldst_so_reg:$target, i32imm:$jt), 2593 0, IIC_Br, 2594 [(ARMbrjt (i32 (load ldst_so_reg:$target)), 2595 tjumptable:$jt)]>, Sched<[WriteBrTbl]>; 2596 def BR_JTadd : ARMPseudoInst<(outs), 2597 (ins GPR:$target, GPR:$idx, i32imm:$jt), 2598 0, IIC_Br, 2599 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>, 2600 Sched<[WriteBrTbl]>; 2601 } // isNotDuplicable = 1, isIndirectBranch = 1 2602 } // isBarrier = 1 2603 2604} 2605 2606// BLX (immediate) 2607def BLXi : AXI<(outs), (ins arm_blx_target:$target), BrMiscFrm, NoItinerary, 2608 "blx\t$target", []>, 2609 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2610 let Inst{31-25} = 0b1111101; 2611 bits<25> target; 2612 let Inst{23-0} = target{24-1}; 2613 let Inst{24} = target{0}; 2614 let isCall = 1; 2615} 2616 2617// Branch and Exchange Jazelle 2618def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", 2619 [/* pattern left blank */]>, Sched<[WriteBr]> { 2620 bits<4> func; 2621 let Inst{23-20} = 0b0010; 2622 let Inst{19-8} = 0xfff; 2623 let Inst{7-4} = 0b0010; 2624 let Inst{3-0} = func; 2625 let isBranch = 1; 2626 let isIndirectBranch = 1; 2627} 2628 2629// Tail calls. 2630 2631let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { 2632 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>, 2633 Sched<[WriteBr]>; 2634 2635 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>, 2636 Sched<[WriteBr]>; 2637 2638 def TAILJMPd : ARMPseudoExpand<(outs), (ins arm_br_target:$dst), 2639 4, IIC_Br, [], 2640 (Bcc arm_br_target:$dst, (ops 14, zero_reg))>, 2641 Requires<[IsARM]>, Sched<[WriteBr]>; 2642 2643 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst), 2644 4, IIC_Br, [], 2645 (BX GPR:$dst)>, Sched<[WriteBr]>, 2646 Requires<[IsARM, HasV4T]>; 2647} 2648 2649// Secure Monitor Call is a system instruction. 2650def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", 2651 []>, Requires<[IsARM, HasTrustZone]> { 2652 bits<4> opt; 2653 let Inst{23-4} = 0b01100000000000000111; 2654 let Inst{3-0} = opt; 2655} 2656def : MnemonicAlias<"smi", "smc">; 2657 2658// Supervisor Call (Software Interrupt) 2659let isCall = 1, Uses = [SP] in { 2660def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>, 2661 Sched<[WriteBr]> { 2662 bits<24> svc; 2663 let Inst{23-0} = svc; 2664} 2665} 2666 2667// Store Return State 2668class SRSI<bit wb, string asm> 2669 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm, 2670 NoItinerary, asm, "", []> { 2671 bits<5> mode; 2672 let Inst{31-28} = 0b1111; 2673 let Inst{27-25} = 0b100; 2674 let Inst{22} = 1; 2675 let Inst{21} = wb; 2676 let Inst{20} = 0; 2677 let Inst{19-16} = 0b1101; // SP 2678 let Inst{15-5} = 0b00000101000; 2679 let Inst{4-0} = mode; 2680} 2681 2682def SRSDA : SRSI<0, "srsda\tsp, $mode"> { 2683 let Inst{24-23} = 0; 2684} 2685def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> { 2686 let Inst{24-23} = 0; 2687} 2688def SRSDB : SRSI<0, "srsdb\tsp, $mode"> { 2689 let Inst{24-23} = 0b10; 2690} 2691def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> { 2692 let Inst{24-23} = 0b10; 2693} 2694def SRSIA : SRSI<0, "srsia\tsp, $mode"> { 2695 let Inst{24-23} = 0b01; 2696} 2697def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> { 2698 let Inst{24-23} = 0b01; 2699} 2700def SRSIB : SRSI<0, "srsib\tsp, $mode"> { 2701 let Inst{24-23} = 0b11; 2702} 2703def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> { 2704 let Inst{24-23} = 0b11; 2705} 2706 2707def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>; 2708def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>; 2709 2710def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>; 2711def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>; 2712 2713def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>; 2714def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>; 2715 2716def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>; 2717def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>; 2718 2719// Return From Exception 2720class RFEI<bit wb, string asm> 2721 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm, 2722 NoItinerary, asm, "", []> { 2723 bits<4> Rn; 2724 let Inst{31-28} = 0b1111; 2725 let Inst{27-25} = 0b100; 2726 let Inst{22} = 0; 2727 let Inst{21} = wb; 2728 let Inst{20} = 1; 2729 let Inst{19-16} = Rn; 2730 let Inst{15-0} = 0xa00; 2731} 2732 2733def RFEDA : RFEI<0, "rfeda\t$Rn"> { 2734 let Inst{24-23} = 0; 2735} 2736def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> { 2737 let Inst{24-23} = 0; 2738} 2739def RFEDB : RFEI<0, "rfedb\t$Rn"> { 2740 let Inst{24-23} = 0b10; 2741} 2742def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> { 2743 let Inst{24-23} = 0b10; 2744} 2745def RFEIA : RFEI<0, "rfeia\t$Rn"> { 2746 let Inst{24-23} = 0b01; 2747} 2748def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> { 2749 let Inst{24-23} = 0b01; 2750} 2751def RFEIB : RFEI<0, "rfeib\t$Rn"> { 2752 let Inst{24-23} = 0b11; 2753} 2754def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> { 2755 let Inst{24-23} = 0b11; 2756} 2757 2758// Hypervisor Call is a system instruction 2759let isCall = 1 in { 2760def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary, 2761 "hvc", "\t$imm", []>, 2762 Requires<[IsARM, HasVirtualization]> { 2763 bits<16> imm; 2764 2765 // Even though HVC isn't predicable, it's encoding includes a condition field. 2766 // The instruction is undefined if the condition field is 0xf otherwise it is 2767 // unpredictable if it isn't condition AL (0xe). 2768 let Inst{31-28} = 0b1110; 2769 let Unpredictable{31-28} = 0b1111; 2770 let Inst{27-24} = 0b0001; 2771 let Inst{23-20} = 0b0100; 2772 let Inst{19-8} = imm{15-4}; 2773 let Inst{7-4} = 0b0111; 2774 let Inst{3-0} = imm{3-0}; 2775} 2776} 2777 2778// Return from exception in Hypervisor mode. 2779let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in 2780def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>, 2781 Requires<[IsARM, HasVirtualization]> { 2782 let Inst{23-0} = 0b011000000000000001101110; 2783} 2784 2785//===----------------------------------------------------------------------===// 2786// Load / Store Instructions. 2787// 2788 2789// Load 2790 2791 2792defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si, load>; 2793defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si, 2794 zextloadi8>; 2795defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si, store>; 2796defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si, 2797 truncstorei8>; 2798 2799// Special LDR for loads from non-pc-relative constpools. 2800let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0, 2801 isReMaterializable = 1, isCodeGenOnly = 1 in 2802def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 2803 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", 2804 []> { 2805 bits<4> Rt; 2806 bits<17> addr; 2807 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2808 let Inst{19-16} = 0b1111; 2809 let Inst{15-12} = Rt; 2810 let Inst{11-0} = addr{11-0}; // imm12 2811} 2812 2813// Loads with zero extension 2814def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2815 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr", 2816 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>; 2817 2818// Loads with sign extension 2819def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2820 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr", 2821 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>; 2822 2823def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2824 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr", 2825 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>; 2826 2827let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in { 2828 // Load doubleword 2829 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr), 2830 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>, 2831 Requires<[IsARM, HasV5TE]>; 2832} 2833 2834let mayLoad = 1, hasSideEffects = 0, hasNoSchedulingInfo = 1 in { 2835def LOADDUAL : ARMPseudoInst<(outs GPRPairOp:$Rt), (ins addrmode3:$addr), 2836 64, IIC_iLoad_d_r, []>, 2837 Requires<[IsARM, HasV5TE]> { 2838 let AM = AddrMode3; 2839} 2840} 2841 2842def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2843 NoItinerary, "lda", "\t$Rt, $addr", []>; 2844def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2845 NoItinerary, "ldab", "\t$Rt, $addr", []>; 2846def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2847 NoItinerary, "ldah", "\t$Rt, $addr", []>; 2848 2849// Indexed loads 2850multiclass AI2_ldridx<bit isByte, string opc, 2851 InstrItinClass iii, InstrItinClass iir> { 2852 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2853 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii, 2854 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2855 bits<17> addr; 2856 let Inst{25} = 0; 2857 let Inst{23} = addr{12}; 2858 let Inst{19-16} = addr{16-13}; 2859 let Inst{11-0} = addr{11-0}; 2860 let DecoderMethod = "DecodeLDRPreImm"; 2861 } 2862 2863 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2864 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir, 2865 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2866 bits<17> addr; 2867 let Inst{25} = 1; 2868 let Inst{23} = addr{12}; 2869 let Inst{19-16} = addr{16-13}; 2870 let Inst{11-0} = addr{11-0}; 2871 let Inst{4} = 0; 2872 let DecoderMethod = "DecodeLDRPreReg"; 2873 } 2874 2875 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2876 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2877 IndexModePost, LdFrm, iir, 2878 opc, "\t$Rt, $addr, $offset", 2879 "$addr.base = $Rn_wb", []> { 2880 // {12} isAdd 2881 // {11-0} imm12/Rm 2882 bits<14> offset; 2883 bits<4> addr; 2884 let Inst{25} = 1; 2885 let Inst{23} = offset{12}; 2886 let Inst{19-16} = addr; 2887 let Inst{11-0} = offset{11-0}; 2888 let Inst{4} = 0; 2889 2890 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2891 } 2892 2893 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2894 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2895 IndexModePost, LdFrm, iii, 2896 opc, "\t$Rt, $addr, $offset", 2897 "$addr.base = $Rn_wb", []> { 2898 // {12} isAdd 2899 // {11-0} imm12/Rm 2900 bits<14> offset; 2901 bits<4> addr; 2902 let Inst{25} = 0; 2903 let Inst{23} = offset{12}; 2904 let Inst{19-16} = addr; 2905 let Inst{11-0} = offset{11-0}; 2906 2907 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2908 } 2909 2910} 2911 2912let mayLoad = 1, hasSideEffects = 0 in { 2913// FIXME: for LDR_PRE_REG etc. the itinerary should be either IIC_iLoad_ru or 2914// IIC_iLoad_siu depending on whether it the offset register is shifted. 2915defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>; 2916defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>; 2917} 2918 2919multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> { 2920 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2921 (ins addrmode3_pre:$addr), IndexModePre, 2922 LdMiscFrm, itin, 2923 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2924 bits<14> addr; 2925 let Inst{23} = addr{8}; // U bit 2926 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2927 let Inst{19-16} = addr{12-9}; // Rn 2928 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2929 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2930 let DecoderMethod = "DecodeAddrMode3Instruction"; 2931 } 2932 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2933 (ins addr_offset_none:$addr, am3offset:$offset), 2934 IndexModePost, LdMiscFrm, itin, 2935 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2936 []> { 2937 bits<10> offset; 2938 bits<4> addr; 2939 let Inst{23} = offset{8}; // U bit 2940 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2941 let Inst{19-16} = addr; 2942 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2943 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2944 let DecoderMethod = "DecodeAddrMode3Instruction"; 2945 } 2946} 2947 2948let mayLoad = 1, hasSideEffects = 0 in { 2949defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>; 2950defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>; 2951defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>; 2952let hasExtraDefRegAllocReq = 1 in { 2953def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2954 (ins addrmode3_pre:$addr), IndexModePre, 2955 LdMiscFrm, IIC_iLoad_d_ru, 2956 "ldrd", "\t$Rt, $Rt2, $addr!", 2957 "$addr.base = $Rn_wb", []> { 2958 bits<14> addr; 2959 let Inst{23} = addr{8}; // U bit 2960 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2961 let Inst{19-16} = addr{12-9}; // Rn 2962 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2963 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2964 let DecoderMethod = "DecodeAddrMode3Instruction"; 2965} 2966def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2967 (ins addr_offset_none:$addr, am3offset:$offset), 2968 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru, 2969 "ldrd", "\t$Rt, $Rt2, $addr, $offset", 2970 "$addr.base = $Rn_wb", []> { 2971 bits<10> offset; 2972 bits<4> addr; 2973 let Inst{23} = offset{8}; // U bit 2974 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2975 let Inst{19-16} = addr; 2976 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2977 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2978 let DecoderMethod = "DecodeAddrMode3Instruction"; 2979} 2980} // hasExtraDefRegAllocReq = 1 2981} // mayLoad = 1, hasSideEffects = 0 2982 2983// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT. 2984let mayLoad = 1, hasSideEffects = 0 in { 2985def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2986 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2987 IndexModePost, LdFrm, IIC_iLoad_ru, 2988 "ldrt", "\t$Rt, $addr, $offset", 2989 "$addr.base = $Rn_wb", []> { 2990 // {12} isAdd 2991 // {11-0} imm12/Rm 2992 bits<14> offset; 2993 bits<4> addr; 2994 let Inst{25} = 1; 2995 let Inst{23} = offset{12}; 2996 let Inst{21} = 1; // overwrite 2997 let Inst{19-16} = addr; 2998 let Inst{11-5} = offset{11-5}; 2999 let Inst{4} = 0; 3000 let Inst{3-0} = offset{3-0}; 3001 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3002} 3003 3004def LDRT_POST_IMM 3005 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 3006 (ins addr_offset_none:$addr, am2offset_imm:$offset), 3007 IndexModePost, LdFrm, IIC_iLoad_ru, 3008 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3009 // {12} isAdd 3010 // {11-0} imm12/Rm 3011 bits<14> offset; 3012 bits<4> addr; 3013 let Inst{25} = 0; 3014 let Inst{23} = offset{12}; 3015 let Inst{21} = 1; // overwrite 3016 let Inst{19-16} = addr; 3017 let Inst{11-0} = offset{11-0}; 3018 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3019} 3020 3021def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 3022 (ins addr_offset_none:$addr, am2offset_reg:$offset), 3023 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 3024 "ldrbt", "\t$Rt, $addr, $offset", 3025 "$addr.base = $Rn_wb", []> { 3026 // {12} isAdd 3027 // {11-0} imm12/Rm 3028 bits<14> offset; 3029 bits<4> addr; 3030 let Inst{25} = 1; 3031 let Inst{23} = offset{12}; 3032 let Inst{21} = 1; // overwrite 3033 let Inst{19-16} = addr; 3034 let Inst{11-5} = offset{11-5}; 3035 let Inst{4} = 0; 3036 let Inst{3-0} = offset{3-0}; 3037 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3038} 3039 3040def LDRBT_POST_IMM 3041 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 3042 (ins addr_offset_none:$addr, am2offset_imm:$offset), 3043 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 3044 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3045 // {12} isAdd 3046 // {11-0} imm12/Rm 3047 bits<14> offset; 3048 bits<4> addr; 3049 let Inst{25} = 0; 3050 let Inst{23} = offset{12}; 3051 let Inst{21} = 1; // overwrite 3052 let Inst{19-16} = addr; 3053 let Inst{11-0} = offset{11-0}; 3054 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3055} 3056 3057multiclass AI3ldrT<bits<4> op, string opc> { 3058 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb), 3059 (ins addr_offset_none:$addr, postidx_imm8:$offset), 3060 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 3061 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 3062 bits<9> offset; 3063 let Inst{23} = offset{8}; 3064 let Inst{22} = 1; 3065 let Inst{11-8} = offset{7-4}; 3066 let Inst{3-0} = offset{3-0}; 3067 } 3068 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb), 3069 (ins addr_offset_none:$addr, postidx_reg:$Rm), 3070 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 3071 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 3072 bits<5> Rm; 3073 let Inst{23} = Rm{4}; 3074 let Inst{22} = 0; 3075 let Inst{11-8} = 0; 3076 let Unpredictable{11-8} = 0b1111; 3077 let Inst{3-0} = Rm{3-0}; 3078 let DecoderMethod = "DecodeLDR"; 3079 } 3080 3081 def ii : ARMAsmPseudo<!strconcat(opc, "${p} $Rt, $addr"), 3082 (ins addr_offset_none:$addr, pred:$p), (outs GPR:$Rt)>; 3083} 3084 3085defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">; 3086defm LDRHT : AI3ldrT<0b1011, "ldrht">; 3087defm LDRSHT : AI3ldrT<0b1111, "ldrsht">; 3088} 3089 3090def LDRT_POST 3091 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 3092 (outs GPR:$Rt)>; 3093 3094def LDRBT_POST 3095 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 3096 (outs GPR:$Rt)>; 3097 3098// Pseudo instruction ldr Rt, =immediate 3099def LDRConstPool 3100 : ARMAsmPseudo<"ldr${q} $Rt, $immediate", 3101 (ins const_pool_asm_imm:$immediate, pred:$q), 3102 (outs GPR:$Rt)>; 3103 3104// Store 3105 3106// Stores with truncate 3107def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, 3108 IIC_iStore_bh_r, "strh", "\t$Rt, $addr", 3109 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>; 3110 3111// Store doubleword 3112let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 3113 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr), 3114 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>, 3115 Requires<[IsARM, HasV5TE]> { 3116 let Inst{21} = 0; 3117 } 3118} 3119 3120let mayStore = 1, hasSideEffects = 0, hasNoSchedulingInfo = 1 in { 3121def STOREDUAL : ARMPseudoInst<(outs), (ins GPRPairOp:$Rt, addrmode3:$addr), 3122 64, IIC_iStore_d_r, []>, 3123 Requires<[IsARM, HasV5TE]> { 3124 let AM = AddrMode3; 3125} 3126} 3127 3128// Indexed stores 3129multiclass AI2_stridx<bit isByte, string opc, 3130 InstrItinClass iii, InstrItinClass iir> { 3131 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 3132 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre, 3133 StFrm, iii, 3134 opc, "\t$Rt, $addr!", 3135 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3136 bits<17> addr; 3137 let Inst{25} = 0; 3138 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 3139 let Inst{19-16} = addr{16-13}; // Rn 3140 let Inst{11-0} = addr{11-0}; // imm12 3141 let DecoderMethod = "DecodeSTRPreImm"; 3142 } 3143 3144 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 3145 (ins GPR:$Rt, ldst_so_reg:$addr), 3146 IndexModePre, StFrm, iir, 3147 opc, "\t$Rt, $addr!", 3148 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3149 bits<17> addr; 3150 let Inst{25} = 1; 3151 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 3152 let Inst{19-16} = addr{16-13}; // Rn 3153 let Inst{11-0} = addr{11-0}; 3154 let Inst{4} = 0; // Inst{4} = 0 3155 let DecoderMethod = "DecodeSTRPreReg"; 3156 } 3157 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 3158 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3159 IndexModePost, StFrm, iir, 3160 opc, "\t$Rt, $addr, $offset", 3161 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3162 // {12} isAdd 3163 // {11-0} imm12/Rm 3164 bits<14> offset; 3165 bits<4> addr; 3166 let Inst{25} = 1; 3167 let Inst{23} = offset{12}; 3168 let Inst{19-16} = addr; 3169 let Inst{11-0} = offset{11-0}; 3170 let Inst{4} = 0; 3171 3172 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3173 } 3174 3175 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 3176 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3177 IndexModePost, StFrm, iii, 3178 opc, "\t$Rt, $addr, $offset", 3179 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3180 // {12} isAdd 3181 // {11-0} imm12/Rm 3182 bits<14> offset; 3183 bits<4> addr; 3184 let Inst{25} = 0; 3185 let Inst{23} = offset{12}; 3186 let Inst{19-16} = addr; 3187 let Inst{11-0} = offset{11-0}; 3188 3189 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3190 } 3191} 3192 3193let mayStore = 1, hasSideEffects = 0 in { 3194// FIXME: for STR_PRE_REG etc. the itinerary should be either IIC_iStore_ru or 3195// IIC_iStore_siu depending on whether it the offset register is shifted. 3196defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>; 3197defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>; 3198} 3199 3200def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 3201 am2offset_reg:$offset), 3202 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr, 3203 am2offset_reg:$offset)>; 3204def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 3205 am2offset_imm:$offset), 3206 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr, 3207 am2offset_imm:$offset)>; 3208def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 3209 am2offset_reg:$offset), 3210 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr, 3211 am2offset_reg:$offset)>; 3212def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 3213 am2offset_imm:$offset), 3214 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr, 3215 am2offset_imm:$offset)>; 3216 3217// Pseudo-instructions for pattern matching the pre-indexed stores. We can't 3218// put the patterns on the instruction definitions directly as ISel wants 3219// the address base and offset to be separate operands, not a single 3220// complex operand like we represent the instructions themselves. The 3221// pseudos map between the two. 3222let usesCustomInserter = 1, 3223 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 3224def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3225 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 3226 4, IIC_iStore_ru, 3227 [(set GPR:$Rn_wb, 3228 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 3229def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3230 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 3231 4, IIC_iStore_ru, 3232 [(set GPR:$Rn_wb, 3233 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 3234def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3235 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 3236 4, IIC_iStore_ru, 3237 [(set GPR:$Rn_wb, 3238 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 3239def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3240 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 3241 4, IIC_iStore_ru, 3242 [(set GPR:$Rn_wb, 3243 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 3244def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3245 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p), 3246 4, IIC_iStore_ru, 3247 [(set GPR:$Rn_wb, 3248 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>; 3249} 3250 3251 3252 3253def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb), 3254 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre, 3255 StMiscFrm, IIC_iStore_bh_ru, 3256 "strh", "\t$Rt, $addr!", 3257 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3258 bits<14> addr; 3259 let Inst{23} = addr{8}; // U bit 3260 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 3261 let Inst{19-16} = addr{12-9}; // Rn 3262 let Inst{11-8} = addr{7-4}; // imm7_4/zero 3263 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 3264 let DecoderMethod = "DecodeAddrMode3Instruction"; 3265} 3266 3267def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb), 3268 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset), 3269 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, 3270 "strh", "\t$Rt, $addr, $offset", 3271 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", 3272 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt, 3273 addr_offset_none:$addr, 3274 am3offset:$offset))]> { 3275 bits<10> offset; 3276 bits<4> addr; 3277 let Inst{23} = offset{8}; // U bit 3278 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 3279 let Inst{19-16} = addr; 3280 let Inst{11-8} = offset{7-4}; // imm7_4/zero 3281 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 3282 let DecoderMethod = "DecodeAddrMode3Instruction"; 3283} 3284 3285let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 3286def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb), 3287 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr), 3288 IndexModePre, StMiscFrm, IIC_iStore_d_ru, 3289 "strd", "\t$Rt, $Rt2, $addr!", 3290 "$addr.base = $Rn_wb", []> { 3291 bits<14> addr; 3292 let Inst{23} = addr{8}; // U bit 3293 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 3294 let Inst{19-16} = addr{12-9}; // Rn 3295 let Inst{11-8} = addr{7-4}; // imm7_4/zero 3296 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 3297 let DecoderMethod = "DecodeAddrMode3Instruction"; 3298} 3299 3300def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb), 3301 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr, 3302 am3offset:$offset), 3303 IndexModePost, StMiscFrm, IIC_iStore_d_ru, 3304 "strd", "\t$Rt, $Rt2, $addr, $offset", 3305 "$addr.base = $Rn_wb", []> { 3306 bits<10> offset; 3307 bits<4> addr; 3308 let Inst{23} = offset{8}; // U bit 3309 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 3310 let Inst{19-16} = addr; 3311 let Inst{11-8} = offset{7-4}; // imm7_4/zero 3312 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 3313 let DecoderMethod = "DecodeAddrMode3Instruction"; 3314} 3315} // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 3316 3317// STRT, STRBT, and STRHT 3318 3319def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3320 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3321 IndexModePost, StFrm, IIC_iStore_bh_ru, 3322 "strbt", "\t$Rt, $addr, $offset", 3323 "$addr.base = $Rn_wb", []> { 3324 // {12} isAdd 3325 // {11-0} imm12/Rm 3326 bits<14> offset; 3327 bits<4> addr; 3328 let Inst{25} = 1; 3329 let Inst{23} = offset{12}; 3330 let Inst{21} = 1; // overwrite 3331 let Inst{19-16} = addr; 3332 let Inst{11-5} = offset{11-5}; 3333 let Inst{4} = 0; 3334 let Inst{3-0} = offset{3-0}; 3335 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3336} 3337 3338def STRBT_POST_IMM 3339 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3340 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3341 IndexModePost, StFrm, IIC_iStore_bh_ru, 3342 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3343 // {12} isAdd 3344 // {11-0} imm12/Rm 3345 bits<14> offset; 3346 bits<4> addr; 3347 let Inst{25} = 0; 3348 let Inst{23} = offset{12}; 3349 let Inst{21} = 1; // overwrite 3350 let Inst{19-16} = addr; 3351 let Inst{11-0} = offset{11-0}; 3352 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3353} 3354 3355def STRBT_POST 3356 : ARMAsmPseudo<"strbt${q} $Rt, $addr", 3357 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3358 3359let mayStore = 1, hasSideEffects = 0 in { 3360def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3361 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3362 IndexModePost, StFrm, IIC_iStore_ru, 3363 "strt", "\t$Rt, $addr, $offset", 3364 "$addr.base = $Rn_wb", []> { 3365 // {12} isAdd 3366 // {11-0} imm12/Rm 3367 bits<14> offset; 3368 bits<4> addr; 3369 let Inst{25} = 1; 3370 let Inst{23} = offset{12}; 3371 let Inst{21} = 1; // overwrite 3372 let Inst{19-16} = addr; 3373 let Inst{11-5} = offset{11-5}; 3374 let Inst{4} = 0; 3375 let Inst{3-0} = offset{3-0}; 3376 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3377} 3378 3379def STRT_POST_IMM 3380 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3381 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3382 IndexModePost, StFrm, IIC_iStore_ru, 3383 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3384 // {12} isAdd 3385 // {11-0} imm12/Rm 3386 bits<14> offset; 3387 bits<4> addr; 3388 let Inst{25} = 0; 3389 let Inst{23} = offset{12}; 3390 let Inst{21} = 1; // overwrite 3391 let Inst{19-16} = addr; 3392 let Inst{11-0} = offset{11-0}; 3393 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3394} 3395} 3396 3397def STRT_POST 3398 : ARMAsmPseudo<"strt${q} $Rt, $addr", 3399 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3400 3401multiclass AI3strT<bits<4> op, string opc> { 3402 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3403 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset), 3404 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3405 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 3406 bits<9> offset; 3407 let Inst{23} = offset{8}; 3408 let Inst{22} = 1; 3409 let Inst{11-8} = offset{7-4}; 3410 let Inst{3-0} = offset{3-0}; 3411 } 3412 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3413 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm), 3414 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3415 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 3416 bits<5> Rm; 3417 let Inst{23} = Rm{4}; 3418 let Inst{22} = 0; 3419 let Inst{11-8} = 0; 3420 let Inst{3-0} = Rm{3-0}; 3421 } 3422} 3423 3424 3425defm STRHT : AI3strT<0b1011, "strht">; 3426 3427def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3428 NoItinerary, "stl", "\t$Rt, $addr", []>; 3429def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3430 NoItinerary, "stlb", "\t$Rt, $addr", []>; 3431def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3432 NoItinerary, "stlh", "\t$Rt, $addr", []>; 3433 3434//===----------------------------------------------------------------------===// 3435// Load / store multiple Instructions. 3436// 3437 3438multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f, 3439 InstrItinClass itin, InstrItinClass itin_upd> { 3440 // IA is the default, so no need for an explicit suffix on the 3441 // mnemonic here. Without it is the canonical spelling. 3442 def IA : 3443 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3444 IndexModeNone, f, itin, 3445 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> { 3446 let Inst{24-23} = 0b01; // Increment After 3447 let Inst{22} = P_bit; 3448 let Inst{21} = 0; // No writeback 3449 let Inst{20} = L_bit; 3450 } 3451 def IA_UPD : 3452 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3453 IndexModeUpd, f, itin_upd, 3454 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3455 let Inst{24-23} = 0b01; // Increment After 3456 let Inst{22} = P_bit; 3457 let Inst{21} = 1; // Writeback 3458 let Inst{20} = L_bit; 3459 3460 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3461 } 3462 def DA : 3463 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3464 IndexModeNone, f, itin, 3465 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> { 3466 let Inst{24-23} = 0b00; // Decrement After 3467 let Inst{22} = P_bit; 3468 let Inst{21} = 0; // No writeback 3469 let Inst{20} = L_bit; 3470 } 3471 def DA_UPD : 3472 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3473 IndexModeUpd, f, itin_upd, 3474 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3475 let Inst{24-23} = 0b00; // Decrement After 3476 let Inst{22} = P_bit; 3477 let Inst{21} = 1; // Writeback 3478 let Inst{20} = L_bit; 3479 3480 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3481 } 3482 def DB : 3483 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3484 IndexModeNone, f, itin, 3485 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> { 3486 let Inst{24-23} = 0b10; // Decrement Before 3487 let Inst{22} = P_bit; 3488 let Inst{21} = 0; // No writeback 3489 let Inst{20} = L_bit; 3490 } 3491 def DB_UPD : 3492 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3493 IndexModeUpd, f, itin_upd, 3494 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3495 let Inst{24-23} = 0b10; // Decrement Before 3496 let Inst{22} = P_bit; 3497 let Inst{21} = 1; // Writeback 3498 let Inst{20} = L_bit; 3499 3500 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3501 } 3502 def IB : 3503 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3504 IndexModeNone, f, itin, 3505 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> { 3506 let Inst{24-23} = 0b11; // Increment Before 3507 let Inst{22} = P_bit; 3508 let Inst{21} = 0; // No writeback 3509 let Inst{20} = L_bit; 3510 } 3511 def IB_UPD : 3512 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3513 IndexModeUpd, f, itin_upd, 3514 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3515 let Inst{24-23} = 0b11; // Increment Before 3516 let Inst{22} = P_bit; 3517 let Inst{21} = 1; // Writeback 3518 let Inst{20} = L_bit; 3519 3520 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3521 } 3522} 3523 3524let hasSideEffects = 0 in { 3525 3526let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in 3527defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m, 3528 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">; 3529 3530let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3531defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m, 3532 IIC_iStore_mu>, 3533 ComplexDeprecationPredicate<"ARMStore">; 3534 3535} // hasSideEffects 3536 3537// FIXME: remove when we have a way to marking a MI with these properties. 3538// FIXME: Should pc be an implicit operand like PICADD, etc? 3539let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 3540 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 3541def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 3542 reglist:$regs, variable_ops), 3543 4, IIC_iLoad_mBr, [], 3544 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 3545 RegConstraint<"$Rn = $wb">; 3546 3547let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 3548defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m, 3549 IIC_iLoad_mu>; 3550 3551let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3552defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m, 3553 IIC_iStore_mu>; 3554 3555 3556 3557//===----------------------------------------------------------------------===// 3558// Move Instructions. 3559// 3560 3561let hasSideEffects = 0, isMoveReg = 1 in 3562def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr, 3563 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3564 bits<4> Rd; 3565 bits<4> Rm; 3566 3567 let Inst{19-16} = 0b0000; 3568 let Inst{11-4} = 0b00000000; 3569 let Inst{25} = 0; 3570 let Inst{3-0} = Rm; 3571 let Inst{15-12} = Rd; 3572} 3573 3574// A version for the smaller set of tail call registers. 3575let hasSideEffects = 0 in 3576def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, 3577 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3578 bits<4> Rd; 3579 bits<4> Rm; 3580 3581 let Inst{11-4} = 0b00000000; 3582 let Inst{25} = 0; 3583 let Inst{3-0} = Rm; 3584 let Inst{15-12} = Rd; 3585} 3586 3587def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src), 3588 DPSoRegRegFrm, IIC_iMOVsr, 3589 "mov", "\t$Rd, $src", 3590 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP, 3591 Sched<[WriteALU]> { 3592 bits<4> Rd; 3593 bits<12> src; 3594 let Inst{15-12} = Rd; 3595 let Inst{19-16} = 0b0000; 3596 let Inst{11-8} = src{11-8}; 3597 let Inst{7} = 0; 3598 let Inst{6-5} = src{6-5}; 3599 let Inst{4} = 1; 3600 let Inst{3-0} = src{3-0}; 3601 let Inst{25} = 0; 3602} 3603 3604def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src), 3605 DPSoRegImmFrm, IIC_iMOVsr, 3606 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>, 3607 UnaryDP, Sched<[WriteALU]> { 3608 bits<4> Rd; 3609 bits<12> src; 3610 let Inst{15-12} = Rd; 3611 let Inst{19-16} = 0b0000; 3612 let Inst{11-5} = src{11-5}; 3613 let Inst{4} = 0; 3614 let Inst{3-0} = src{3-0}; 3615 let Inst{25} = 0; 3616} 3617 3618let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3619def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi, 3620 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP, 3621 Sched<[WriteALU]> { 3622 bits<4> Rd; 3623 bits<12> imm; 3624 let Inst{25} = 1; 3625 let Inst{15-12} = Rd; 3626 let Inst{19-16} = 0b0000; 3627 let Inst{11-0} = imm; 3628} 3629 3630let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3631def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm), 3632 DPFrm, IIC_iMOVi, 3633 "movw", "\t$Rd, $imm", 3634 [(set GPR:$Rd, imm0_65535:$imm)]>, 3635 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> { 3636 bits<4> Rd; 3637 bits<16> imm; 3638 let Inst{15-12} = Rd; 3639 let Inst{11-0} = imm{11-0}; 3640 let Inst{19-16} = imm{15-12}; 3641 let Inst{20} = 0; 3642 let Inst{25} = 1; 3643 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3644} 3645 3646def : InstAlias<"mov${p} $Rd, $imm", 3647 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p), 0>, 3648 Requires<[IsARM, HasV6T2]>; 3649 3650def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3651 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3652 Sched<[WriteALU]>; 3653 3654let Constraints = "$src = $Rd" in { 3655def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd), 3656 (ins GPR:$src, imm0_65535_expr:$imm), 3657 DPFrm, IIC_iMOVi, 3658 "movt", "\t$Rd, $imm", 3659 [(set GPRnopc:$Rd, 3660 (or (and GPR:$src, 0xffff), 3661 lo16AllZero:$imm))]>, UnaryDP, 3662 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> { 3663 bits<4> Rd; 3664 bits<16> imm; 3665 let Inst{15-12} = Rd; 3666 let Inst{11-0} = imm{11-0}; 3667 let Inst{19-16} = imm{15-12}; 3668 let Inst{20} = 0; 3669 let Inst{25} = 1; 3670 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3671} 3672 3673def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3674 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3675 Sched<[WriteALU]>; 3676 3677} // Constraints 3678 3679def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>, 3680 Requires<[IsARM, HasV6T2]>; 3681 3682let Uses = [CPSR] in 3683def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, 3684 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP, 3685 Requires<[IsARM]>, Sched<[WriteALU]>; 3686 3687// These aren't really mov instructions, but we have to define them this way 3688// due to flag operands. 3689 3690let Defs = [CPSR] in { 3691def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3692 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP, 3693 Sched<[WriteALU]>, Requires<[IsARM]>; 3694def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3695 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP, 3696 Sched<[WriteALU]>, Requires<[IsARM]>; 3697} 3698 3699//===----------------------------------------------------------------------===// 3700// Extend Instructions. 3701// 3702 3703// Sign extenders 3704 3705def SXTB : AI_ext_rrot<0b01101010, 3706 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 3707def SXTH : AI_ext_rrot<0b01101011, 3708 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 3709 3710def SXTAB : AI_exta_rrot<0b01101010, 3711 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 3712def SXTAH : AI_exta_rrot<0b01101011, 3713 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 3714 3715def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8)), 3716 (SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3717def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot), 3718 i16)), 3719 (SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3720 3721def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; 3722def : ARMV6Pat<(int_arm_sxtb16 GPR:$Src), 3723 (SXTB16 GPR:$Src, 0)>; 3724def : ARMV6Pat<(int_arm_sxtb16 (rotr GPR:$Src, rot_imm:$rot)), 3725 (SXTB16 GPR:$Src, rot_imm:$rot)>; 3726 3727def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; 3728def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, GPR:$RHS), 3729 (SXTAB16 GPR:$LHS, GPR:$RHS, 0)>; 3730def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)), 3731 (SXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>; 3732 3733// Zero extenders 3734 3735let AddedComplexity = 16 in { 3736def UXTB : AI_ext_rrot<0b01101110, 3737 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 3738def UXTH : AI_ext_rrot<0b01101111, 3739 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 3740def UXTB16 : AI_ext_rrot<0b01101100, 3741 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 3742 3743// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 3744// The transformation should probably be done as a combiner action 3745// instead so we can include a check for masking back in the upper 3746// eight bits of the source into the lower eight bits of the result. 3747//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 3748// (UXTB16r_rot GPR:$Src, 3)>; 3749def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 3750 (UXTB16 GPR:$Src, 1)>; 3751def : ARMV6Pat<(int_arm_uxtb16 GPR:$Src), 3752 (UXTB16 GPR:$Src, 0)>; 3753def : ARMV6Pat<(int_arm_uxtb16 (rotr GPR:$Src, rot_imm:$rot)), 3754 (UXTB16 GPR:$Src, rot_imm:$rot)>; 3755 3756def UXTAB : AI_exta_rrot<0b01101110, "uxtab", 3757 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 3758def UXTAH : AI_exta_rrot<0b01101111, "uxtah", 3759 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 3760 3761def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 0xFF)), 3762 (UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3763def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 0xFFFF)), 3764 (UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3765} 3766 3767// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 3768def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; 3769def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, GPR:$RHS), 3770 (UXTAB16 GPR:$LHS, GPR:$RHS, 0)>; 3771def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)), 3772 (UXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>; 3773 3774 3775def SBFX : I<(outs GPRnopc:$Rd), 3776 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3777 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3778 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3779 Requires<[IsARM, HasV6T2]> { 3780 bits<4> Rd; 3781 bits<4> Rn; 3782 bits<5> lsb; 3783 bits<5> width; 3784 let Inst{27-21} = 0b0111101; 3785 let Inst{6-4} = 0b101; 3786 let Inst{20-16} = width; 3787 let Inst{15-12} = Rd; 3788 let Inst{11-7} = lsb; 3789 let Inst{3-0} = Rn; 3790} 3791 3792def UBFX : I<(outs GPRnopc:$Rd), 3793 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3794 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3795 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3796 Requires<[IsARM, HasV6T2]> { 3797 bits<4> Rd; 3798 bits<4> Rn; 3799 bits<5> lsb; 3800 bits<5> width; 3801 let Inst{27-21} = 0b0111111; 3802 let Inst{6-4} = 0b101; 3803 let Inst{20-16} = width; 3804 let Inst{15-12} = Rd; 3805 let Inst{11-7} = lsb; 3806 let Inst{3-0} = Rn; 3807} 3808 3809//===----------------------------------------------------------------------===// 3810// Arithmetic Instructions. 3811// 3812 3813let isAdd = 1 in 3814defm ADD : AsI1_bin_irs<0b0100, "add", 3815 IIC_iALUi, IIC_iALUr, IIC_iALUsr, add, 1>; 3816defm SUB : AsI1_bin_irs<0b0010, "sub", 3817 IIC_iALUi, IIC_iALUr, IIC_iALUsr, sub>; 3818 3819// ADD and SUB with 's' bit set. 3820// 3821// Currently, ADDS/SUBS are pseudo opcodes that exist only in the 3822// selection DAG. They are "lowered" to real ADD/SUB opcodes by 3823// AdjustInstrPostInstrSelection where we determine whether or not to 3824// set the "s" bit based on CPSR liveness. 3825// 3826// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen 3827// support for an optional CPSR definition that corresponds to the DAG 3828// node's second value. We can then eliminate the implicit def of CPSR. 3829let isAdd = 1 in 3830defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMaddc, 1>; 3831defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>; 3832 3833def : ARMPat<(ARMsubs GPR:$Rn, mod_imm:$imm), (SUBSri $Rn, mod_imm:$imm)>; 3834def : ARMPat<(ARMsubs GPR:$Rn, GPR:$Rm), (SUBSrr $Rn, $Rm)>; 3835def : ARMPat<(ARMsubs GPR:$Rn, so_reg_imm:$shift), 3836 (SUBSrsi $Rn, so_reg_imm:$shift)>; 3837def : ARMPat<(ARMsubs GPR:$Rn, so_reg_reg:$shift), 3838 (SUBSrsr $Rn, so_reg_reg:$shift)>; 3839 3840 3841let isAdd = 1 in 3842defm ADC : AI1_adde_sube_irs<0b0101, "adc", ARMadde, 1>; 3843defm SBC : AI1_adde_sube_irs<0b0110, "sbc", ARMsube>; 3844 3845defm RSB : AsI1_rbin_irs<0b0011, "rsb", 3846 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3847 sub>; 3848 3849// FIXME: Eliminate them if we can write def : Pat patterns which defines 3850// CPSR and the implicit def of CPSR is not needed. 3851defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>; 3852 3853defm RSC : AI1_rsc_irs<0b0111, "rsc", ARMsube>; 3854 3855// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 3856// The assume-no-carry-in form uses the negation of the input since add/sub 3857// assume opposite meanings of the carry flag (i.e., carry == !borrow). 3858// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 3859// details. 3860def : ARMPat<(add GPR:$src, mod_imm_neg:$imm), 3861 (SUBri GPR:$src, mod_imm_neg:$imm)>; 3862def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm), 3863 (SUBSri GPR:$src, mod_imm_neg:$imm)>; 3864 3865def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm), 3866 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3867 Requires<[IsARM, HasV6T2]>; 3868def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm), 3869 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3870 Requires<[IsARM, HasV6T2]>; 3871 3872// The with-carry-in form matches bitwise not instead of the negation. 3873// Effectively, the inverse interpretation of the carry flag already accounts 3874// for part of the negation. 3875def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR), 3876 (SBCri GPR:$src, mod_imm_not:$imm)>; 3877def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR), 3878 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>, 3879 Requires<[IsARM, HasV6T2]>; 3880 3881// Note: These are implemented in C++ code, because they have to generate 3882// ADD/SUBrs instructions, which use a complex pattern that a xform function 3883// cannot produce. 3884// (mul X, 2^n+1) -> (add (X << n), X) 3885// (mul X, 2^n-1) -> (rsb X, (X << n)) 3886 3887// ARM Arithmetic Instruction 3888// GPR:$dst = GPR:$a op GPR:$b 3889class AAI<bits<8> op27_20, bits<8> op11_4, string opc, 3890 list<dag> pattern = [], 3891 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm), 3892 string asm = "\t$Rd, $Rn, $Rm"> 3893 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>, 3894 Sched<[WriteALU, ReadALU, ReadALU]> { 3895 bits<4> Rn; 3896 bits<4> Rd; 3897 bits<4> Rm; 3898 let Inst{27-20} = op27_20; 3899 let Inst{11-4} = op11_4; 3900 let Inst{19-16} = Rn; 3901 let Inst{15-12} = Rd; 3902 let Inst{3-0} = Rm; 3903 3904 let Unpredictable{11-8} = 0b1111; 3905} 3906 3907// Wrappers around the AAI class 3908class AAIRevOpr<bits<8> op27_20, bits<8> op11_4, string opc, 3909 list<dag> pattern = []> 3910 : AAI<op27_20, op11_4, opc, 3911 pattern, 3912 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3913 "\t$Rd, $Rm, $Rn">; 3914 3915class AAIIntrinsic<bits<8> op27_20, bits<8> op11_4, string opc, 3916 Intrinsic intrinsic> 3917 : AAI<op27_20, op11_4, opc, 3918 [(set GPRnopc:$Rd, (intrinsic GPRnopc:$Rn, GPRnopc:$Rm))]>; 3919 3920// Saturating add/subtract 3921let hasSideEffects = 1 in { 3922def QADD8 : AAIIntrinsic<0b01100010, 0b11111001, "qadd8", int_arm_qadd8>; 3923def QADD16 : AAIIntrinsic<0b01100010, 0b11110001, "qadd16", int_arm_qadd16>; 3924def QSUB16 : AAIIntrinsic<0b01100010, 0b11110111, "qsub16", int_arm_qsub16>; 3925def QSUB8 : AAIIntrinsic<0b01100010, 0b11111111, "qsub8", int_arm_qsub8>; 3926 3927def QDADD : AAIRevOpr<0b00010100, 0b00000101, "qdadd", 3928 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, 3929 (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>; 3930def QDSUB : AAIRevOpr<0b00010110, 0b00000101, "qdsub", 3931 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, 3932 (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>; 3933def QSUB : AAIRevOpr<0b00010010, 0b00000101, "qsub", 3934 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))]>; 3935let DecoderMethod = "DecodeQADDInstruction" in 3936 def QADD : AAIRevOpr<0b00010000, 0b00000101, "qadd", 3937 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))]>; 3938} 3939 3940def : ARMV5TEPat<(saddsat GPR:$a, GPR:$b), 3941 (QADD GPR:$a, GPR:$b)>; 3942def : ARMV5TEPat<(ssubsat GPR:$a, GPR:$b), 3943 (QSUB GPR:$a, GPR:$b)>; 3944def : ARMV5TEPat<(saddsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)), 3945 (QDADD rGPR:$Rm, rGPR:$Rn)>; 3946def : ARMV5TEPat<(ssubsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)), 3947 (QDSUB rGPR:$Rm, rGPR:$Rn)>; 3948def : ARMV6Pat<(ARMqadd8b rGPR:$Rm, rGPR:$Rn), 3949 (QADD8 rGPR:$Rm, rGPR:$Rn)>; 3950def : ARMV6Pat<(ARMqsub8b rGPR:$Rm, rGPR:$Rn), 3951 (QSUB8 rGPR:$Rm, rGPR:$Rn)>; 3952def : ARMV6Pat<(ARMqadd16b rGPR:$Rm, rGPR:$Rn), 3953 (QADD16 rGPR:$Rm, rGPR:$Rn)>; 3954def : ARMV6Pat<(ARMqsub16b rGPR:$Rm, rGPR:$Rn), 3955 (QSUB16 rGPR:$Rm, rGPR:$Rn)>; 3956 3957def UQADD16 : AAIIntrinsic<0b01100110, 0b11110001, "uqadd16", int_arm_uqadd16>; 3958def UQADD8 : AAIIntrinsic<0b01100110, 0b11111001, "uqadd8", int_arm_uqadd8>; 3959def UQSUB16 : AAIIntrinsic<0b01100110, 0b11110111, "uqsub16", int_arm_uqsub16>; 3960def UQSUB8 : AAIIntrinsic<0b01100110, 0b11111111, "uqsub8", int_arm_uqsub8>; 3961def QASX : AAIIntrinsic<0b01100010, 0b11110011, "qasx", int_arm_qasx>; 3962def QSAX : AAIIntrinsic<0b01100010, 0b11110101, "qsax", int_arm_qsax>; 3963def UQASX : AAIIntrinsic<0b01100110, 0b11110011, "uqasx", int_arm_uqasx>; 3964def UQSAX : AAIIntrinsic<0b01100110, 0b11110101, "uqsax", int_arm_uqsax>; 3965 3966// Signed/Unsigned add/subtract 3967 3968def SASX : AAIIntrinsic<0b01100001, 0b11110011, "sasx", int_arm_sasx>; 3969def SADD16 : AAIIntrinsic<0b01100001, 0b11110001, "sadd16", int_arm_sadd16>; 3970def SADD8 : AAIIntrinsic<0b01100001, 0b11111001, "sadd8", int_arm_sadd8>; 3971def SSAX : AAIIntrinsic<0b01100001, 0b11110101, "ssax", int_arm_ssax>; 3972def SSUB16 : AAIIntrinsic<0b01100001, 0b11110111, "ssub16", int_arm_ssub16>; 3973def SSUB8 : AAIIntrinsic<0b01100001, 0b11111111, "ssub8", int_arm_ssub8>; 3974def UASX : AAIIntrinsic<0b01100101, 0b11110011, "uasx", int_arm_uasx>; 3975def UADD16 : AAIIntrinsic<0b01100101, 0b11110001, "uadd16", int_arm_uadd16>; 3976def UADD8 : AAIIntrinsic<0b01100101, 0b11111001, "uadd8", int_arm_uadd8>; 3977def USAX : AAIIntrinsic<0b01100101, 0b11110101, "usax", int_arm_usax>; 3978def USUB16 : AAIIntrinsic<0b01100101, 0b11110111, "usub16", int_arm_usub16>; 3979def USUB8 : AAIIntrinsic<0b01100101, 0b11111111, "usub8", int_arm_usub8>; 3980 3981// Signed/Unsigned halving add/subtract 3982 3983def SHASX : AAIIntrinsic<0b01100011, 0b11110011, "shasx", int_arm_shasx>; 3984def SHADD16 : AAIIntrinsic<0b01100011, 0b11110001, "shadd16", int_arm_shadd16>; 3985def SHADD8 : AAIIntrinsic<0b01100011, 0b11111001, "shadd8", int_arm_shadd8>; 3986def SHSAX : AAIIntrinsic<0b01100011, 0b11110101, "shsax", int_arm_shsax>; 3987def SHSUB16 : AAIIntrinsic<0b01100011, 0b11110111, "shsub16", int_arm_shsub16>; 3988def SHSUB8 : AAIIntrinsic<0b01100011, 0b11111111, "shsub8", int_arm_shsub8>; 3989def UHASX : AAIIntrinsic<0b01100111, 0b11110011, "uhasx", int_arm_uhasx>; 3990def UHADD16 : AAIIntrinsic<0b01100111, 0b11110001, "uhadd16", int_arm_uhadd16>; 3991def UHADD8 : AAIIntrinsic<0b01100111, 0b11111001, "uhadd8", int_arm_uhadd8>; 3992def UHSAX : AAIIntrinsic<0b01100111, 0b11110101, "uhsax", int_arm_uhsax>; 3993def UHSUB16 : AAIIntrinsic<0b01100111, 0b11110111, "uhsub16", int_arm_uhsub16>; 3994def UHSUB8 : AAIIntrinsic<0b01100111, 0b11111111, "uhsub8", int_arm_uhsub8>; 3995 3996// Unsigned Sum of Absolute Differences [and Accumulate]. 3997 3998def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3999 MulFrm /* for convenience */, NoItinerary, "usad8", 4000 "\t$Rd, $Rn, $Rm", 4001 [(set GPR:$Rd, (int_arm_usad8 GPR:$Rn, GPR:$Rm))]>, 4002 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> { 4003 bits<4> Rd; 4004 bits<4> Rn; 4005 bits<4> Rm; 4006 let Inst{27-20} = 0b01111000; 4007 let Inst{15-12} = 0b1111; 4008 let Inst{7-4} = 0b0001; 4009 let Inst{19-16} = Rd; 4010 let Inst{11-8} = Rm; 4011 let Inst{3-0} = Rn; 4012} 4013def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4014 MulFrm /* for convenience */, NoItinerary, "usada8", 4015 "\t$Rd, $Rn, $Rm, $Ra", 4016 [(set GPR:$Rd, (int_arm_usada8 GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 4017 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{ 4018 bits<4> Rd; 4019 bits<4> Rn; 4020 bits<4> Rm; 4021 bits<4> Ra; 4022 let Inst{27-20} = 0b01111000; 4023 let Inst{7-4} = 0b0001; 4024 let Inst{19-16} = Rd; 4025 let Inst{15-12} = Ra; 4026 let Inst{11-8} = Rm; 4027 let Inst{3-0} = Rn; 4028} 4029 4030// Signed/Unsigned saturate 4031def SSAT : AI<(outs GPRnopc:$Rd), 4032 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 4033 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>, 4034 Requires<[IsARM,HasV6]>{ 4035 bits<4> Rd; 4036 bits<5> sat_imm; 4037 bits<4> Rn; 4038 bits<8> sh; 4039 let Inst{27-21} = 0b0110101; 4040 let Inst{5-4} = 0b01; 4041 let Inst{20-16} = sat_imm; 4042 let Inst{15-12} = Rd; 4043 let Inst{11-7} = sh{4-0}; 4044 let Inst{6} = sh{5}; 4045 let Inst{3-0} = Rn; 4046} 4047 4048def SSAT16 : AI<(outs GPRnopc:$Rd), 4049 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm, 4050 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []>, 4051 Requires<[IsARM,HasV6]>{ 4052 bits<4> Rd; 4053 bits<4> sat_imm; 4054 bits<4> Rn; 4055 let Inst{27-20} = 0b01101010; 4056 let Inst{11-4} = 0b11110011; 4057 let Inst{15-12} = Rd; 4058 let Inst{19-16} = sat_imm; 4059 let Inst{3-0} = Rn; 4060} 4061 4062def USAT : AI<(outs GPRnopc:$Rd), 4063 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 4064 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>, 4065 Requires<[IsARM,HasV6]> { 4066 bits<4> Rd; 4067 bits<5> sat_imm; 4068 bits<4> Rn; 4069 bits<8> sh; 4070 let Inst{27-21} = 0b0110111; 4071 let Inst{5-4} = 0b01; 4072 let Inst{15-12} = Rd; 4073 let Inst{11-7} = sh{4-0}; 4074 let Inst{6} = sh{5}; 4075 let Inst{20-16} = sat_imm; 4076 let Inst{3-0} = Rn; 4077} 4078 4079def USAT16 : AI<(outs GPRnopc:$Rd), 4080 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm, 4081 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []>, 4082 Requires<[IsARM,HasV6]>{ 4083 bits<4> Rd; 4084 bits<4> sat_imm; 4085 bits<4> Rn; 4086 let Inst{27-20} = 0b01101110; 4087 let Inst{11-4} = 0b11110011; 4088 let Inst{15-12} = Rd; 4089 let Inst{19-16} = sat_imm; 4090 let Inst{3-0} = Rn; 4091} 4092 4093def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos), 4094 (SSAT imm1_32:$pos, GPRnopc:$a, 0)>; 4095def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos), 4096 (USAT imm0_31:$pos, GPRnopc:$a, 0)>; 4097def : ARMPat<(ARMssat GPRnopc:$Rn, imm0_31:$imm), 4098 (SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 4099def : ARMPat<(ARMusat GPRnopc:$Rn, imm0_31:$imm), 4100 (USAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 4101def : ARMV6Pat<(int_arm_ssat16 GPRnopc:$a, imm1_16:$pos), 4102 (SSAT16 imm1_16:$pos, GPRnopc:$a)>; 4103def : ARMV6Pat<(int_arm_usat16 GPRnopc:$a, imm0_15:$pos), 4104 (USAT16 imm0_15:$pos, GPRnopc:$a)>; 4105def : ARMV6Pat<(int_arm_ssat (shl GPRnopc:$a, imm0_31:$shft), imm1_32:$pos), 4106 (SSAT imm1_32:$pos, GPRnopc:$a, imm0_31:$shft)>; 4107def : ARMV6Pat<(int_arm_ssat (sra GPRnopc:$a, asr_imm:$shft), imm1_32:$pos), 4108 (SSAT imm1_32:$pos, GPRnopc:$a, asr_imm:$shft)>; 4109def : ARMV6Pat<(int_arm_usat (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos), 4110 (USAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>; 4111def : ARMV6Pat<(int_arm_usat (sra GPRnopc:$a, asr_imm:$shft), imm0_31:$pos), 4112 (USAT imm0_31:$pos, GPRnopc:$a, asr_imm:$shft)>; 4113def : ARMPat<(ARMssat (shl GPRnopc:$Rn, imm0_31:$shft), imm0_31:$pos), 4114 (SSAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>; 4115def : ARMPat<(ARMssat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos), 4116 (SSAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>; 4117def : ARMPat<(ARMusat (shl GPRnopc:$Rn, imm0_31:$shft), imm0_31:$pos), 4118 (USAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>; 4119def : ARMPat<(ARMusat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos), 4120 (USAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>; 4121 4122 4123//===----------------------------------------------------------------------===// 4124// Bitwise Instructions. 4125// 4126 4127defm AND : AsI1_bin_irs<0b0000, "and", 4128 IIC_iBITi, IIC_iBITr, IIC_iBITsr, and, 1>; 4129defm ORR : AsI1_bin_irs<0b1100, "orr", 4130 IIC_iBITi, IIC_iBITr, IIC_iBITsr, or, 1>; 4131defm EOR : AsI1_bin_irs<0b0001, "eor", 4132 IIC_iBITi, IIC_iBITr, IIC_iBITsr, xor, 1>; 4133defm BIC : AsI1_bin_irs<0b1110, "bic", 4134 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 4135 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 4136 4137// FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just 4138// like in the actual instruction encoding. The complexity of mapping the mask 4139// to the lsb/msb pair should be handled by ISel, not encapsulated in the 4140// instruction description. 4141def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), 4142 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 4143 "bfc", "\t$Rd, $imm", "$src = $Rd", 4144 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>, 4145 Requires<[IsARM, HasV6T2]> { 4146 bits<4> Rd; 4147 bits<10> imm; 4148 let Inst{27-21} = 0b0111110; 4149 let Inst{6-0} = 0b0011111; 4150 let Inst{15-12} = Rd; 4151 let Inst{11-7} = imm{4-0}; // lsb 4152 let Inst{20-16} = imm{9-5}; // msb 4153} 4154 4155// A8.6.18 BFI - Bitfield insert (Encoding A1) 4156def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm), 4157 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 4158 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd", 4159 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn, 4160 bf_inv_mask_imm:$imm))]>, 4161 Requires<[IsARM, HasV6T2]> { 4162 bits<4> Rd; 4163 bits<4> Rn; 4164 bits<10> imm; 4165 let Inst{27-21} = 0b0111110; 4166 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 4167 let Inst{15-12} = Rd; 4168 let Inst{11-7} = imm{4-0}; // lsb 4169 let Inst{20-16} = imm{9-5}; // width 4170 let Inst{3-0} = Rn; 4171} 4172 4173def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr, 4174 "mvn", "\t$Rd, $Rm", 4175 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> { 4176 bits<4> Rd; 4177 bits<4> Rm; 4178 let Inst{25} = 0; 4179 let Inst{19-16} = 0b0000; 4180 let Inst{11-4} = 0b00000000; 4181 let Inst{15-12} = Rd; 4182 let Inst{3-0} = Rm; 4183 4184 let Unpredictable{19-16} = 0b1111; 4185} 4186def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift), 4187 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 4188 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP, 4189 Sched<[WriteALU]> { 4190 bits<4> Rd; 4191 bits<12> shift; 4192 let Inst{25} = 0; 4193 let Inst{19-16} = 0b0000; 4194 let Inst{15-12} = Rd; 4195 let Inst{11-5} = shift{11-5}; 4196 let Inst{4} = 0; 4197 let Inst{3-0} = shift{3-0}; 4198 4199 let Unpredictable{19-16} = 0b1111; 4200} 4201def MVNsr : AsI1<0b1111, (outs GPRnopc:$Rd), (ins so_reg_reg:$shift), 4202 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 4203 [(set GPRnopc:$Rd, (not so_reg_reg:$shift))]>, UnaryDP, 4204 Sched<[WriteALU]> { 4205 bits<4> Rd; 4206 bits<12> shift; 4207 let Inst{25} = 0; 4208 let Inst{19-16} = 0b0000; 4209 let Inst{15-12} = Rd; 4210 let Inst{11-8} = shift{11-8}; 4211 let Inst{7} = 0; 4212 let Inst{6-5} = shift{6-5}; 4213 let Inst{4} = 1; 4214 let Inst{3-0} = shift{3-0}; 4215 4216 let Unpredictable{19-16} = 0b1111; 4217} 4218let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 4219def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, 4220 IIC_iMVNi, "mvn", "\t$Rd, $imm", 4221 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> { 4222 bits<4> Rd; 4223 bits<12> imm; 4224 let Inst{25} = 1; 4225 let Inst{19-16} = 0b0000; 4226 let Inst{15-12} = Rd; 4227 let Inst{11-0} = imm; 4228} 4229 4230let AddedComplexity = 1 in 4231def : ARMPat<(and GPR:$src, mod_imm_not:$imm), 4232 (BICri GPR:$src, mod_imm_not:$imm)>; 4233 4234//===----------------------------------------------------------------------===// 4235// Multiply Instructions. 4236// 4237class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4238 string opc, string asm, list<dag> pattern> 4239 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4240 bits<4> Rd; 4241 bits<4> Rm; 4242 bits<4> Rn; 4243 let Inst{19-16} = Rd; 4244 let Inst{11-8} = Rm; 4245 let Inst{3-0} = Rn; 4246} 4247class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4248 string opc, string asm, list<dag> pattern> 4249 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4250 bits<4> RdLo; 4251 bits<4> RdHi; 4252 bits<4> Rm; 4253 bits<4> Rn; 4254 let Inst{19-16} = RdHi; 4255 let Inst{15-12} = RdLo; 4256 let Inst{11-8} = Rm; 4257 let Inst{3-0} = Rn; 4258} 4259class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4260 string opc, string asm, list<dag> pattern> 4261 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4262 bits<4> RdLo; 4263 bits<4> RdHi; 4264 bits<4> Rm; 4265 bits<4> Rn; 4266 let Inst{19-16} = RdHi; 4267 let Inst{15-12} = RdLo; 4268 let Inst{11-8} = Rm; 4269 let Inst{3-0} = Rn; 4270} 4271 4272// FIXME: The v5 pseudos are only necessary for the additional Constraint 4273// property. Remove them when it's possible to add those properties 4274// on an individual MachineInstr, not just an instruction description. 4275let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in { 4276def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), 4277 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4278 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", 4279 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>, 4280 Requires<[IsARM, HasV6]>, 4281 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4282 let Inst{15-12} = 0b0000; 4283 let Unpredictable{15-12} = 0b1111; 4284} 4285 4286let Constraints = "@earlyclobber $Rd" in 4287def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, 4288 pred:$p, cc_out:$s), 4289 4, IIC_iMUL32, 4290 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))], 4291 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 4292 Requires<[IsARM, NoV6, UseMulOps]>, 4293 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4294} 4295 4296def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd), 4297 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra), 4298 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra", 4299 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>, 4300 Requires<[IsARM, HasV6, UseMulOps]>, 4301 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 4302 bits<4> Ra; 4303 let Inst{15-12} = Ra; 4304} 4305 4306let Constraints = "@earlyclobber $Rd" in 4307def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd), 4308 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 4309 pred:$p, cc_out:$s), 4, IIC_iMAC32, 4310 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))], 4311 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>, 4312 Requires<[IsARM, NoV6]>, 4313 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4314 4315def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4316 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra", 4317 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>, 4318 Requires<[IsARM, HasV6T2, UseMulOps]>, 4319 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 4320 bits<4> Rd; 4321 bits<4> Rm; 4322 bits<4> Rn; 4323 bits<4> Ra; 4324 let Inst{19-16} = Rd; 4325 let Inst{15-12} = Ra; 4326 let Inst{11-8} = Rm; 4327 let Inst{3-0} = Rn; 4328} 4329 4330// Extra precision multiplies with low / high results 4331let hasSideEffects = 0 in { 4332let isCommutable = 1 in { 4333def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi), 4334 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 4335 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", 4336 [(set GPR:$RdLo, GPR:$RdHi, 4337 (smullohi GPR:$Rn, GPR:$Rm))]>, 4338 Requires<[IsARM, HasV6]>, 4339 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4340 4341def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), 4342 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 4343 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", 4344 [(set GPR:$RdLo, GPR:$RdHi, 4345 (umullohi GPR:$Rn, GPR:$Rm))]>, 4346 Requires<[IsARM, HasV6]>, 4347 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL]>; 4348 4349let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { 4350def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4351 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 4352 4, IIC_iMUL64, 4353 [(set GPR:$RdLo, GPR:$RdHi, 4354 (smullohi GPR:$Rn, GPR:$Rm))], 4355 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 4356 Requires<[IsARM, NoV6]>, 4357 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4358 4359def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4360 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 4361 4, IIC_iMUL64, 4362 [(set GPR:$RdLo, GPR:$RdHi, 4363 (umullohi GPR:$Rn, GPR:$Rm))], 4364 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 4365 Requires<[IsARM, NoV6]>, 4366 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4367} 4368} 4369 4370// Multiply + accumulate 4371def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi), 4372 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4373 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4374 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4375 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4376def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi), 4377 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4378 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4379 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4380 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4381 4382def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi), 4383 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4384 IIC_iMAC64, 4385 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4386 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4387 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> { 4388 bits<4> RdLo; 4389 bits<4> RdHi; 4390 bits<4> Rm; 4391 bits<4> Rn; 4392 let Inst{19-16} = RdHi; 4393 let Inst{15-12} = RdLo; 4394 let Inst{11-8} = Rm; 4395 let Inst{3-0} = Rn; 4396} 4397 4398let Constraints = 4399 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in { 4400def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4401 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4402 4, IIC_iMAC64, [], 4403 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4404 pred:$p, cc_out:$s)>, 4405 Requires<[IsARM, NoV6]>, 4406 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4407def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4408 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4409 4, IIC_iMAC64, [], 4410 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4411 pred:$p, cc_out:$s)>, 4412 Requires<[IsARM, NoV6]>, 4413 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4414} 4415 4416} // hasSideEffects 4417 4418// Most significant word multiply 4419def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4420 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm", 4421 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>, 4422 Requires<[IsARM, HasV6]>, 4423 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4424 let Inst{15-12} = 0b1111; 4425} 4426 4427def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4428 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", 4429 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, (i32 0)))]>, 4430 Requires<[IsARM, HasV6]>, 4431 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4432 let Inst{15-12} = 0b1111; 4433} 4434 4435def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd), 4436 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4437 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra", 4438 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, 4439 Requires<[IsARM, HasV6, UseMulOps]>, 4440 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4441 4442def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd), 4443 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4444 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", 4445 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 4446 Requires<[IsARM, HasV6]>, 4447 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4448 4449def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd), 4450 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4451 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>, 4452 Requires<[IsARM, HasV6, UseMulOps]>, 4453 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4454 4455def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd), 4456 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4457 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", 4458 [(set GPR:$Rd, (ARMsmmlsr GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 4459 Requires<[IsARM, HasV6]>, 4460 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4461 4462multiclass AI_smul<string opc> { 4463 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4464 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 4465 [(set GPR:$Rd, (bb_mul GPR:$Rn, GPR:$Rm))]>, 4466 Requires<[IsARM, HasV5TE]>, 4467 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4468 4469 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4470 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 4471 [(set GPR:$Rd, (bt_mul GPR:$Rn, GPR:$Rm))]>, 4472 Requires<[IsARM, HasV5TE]>, 4473 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4474 4475 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4476 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 4477 [(set GPR:$Rd, (tb_mul GPR:$Rn, GPR:$Rm))]>, 4478 Requires<[IsARM, HasV5TE]>, 4479 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4480 4481 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4482 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 4483 [(set GPR:$Rd, (tt_mul GPR:$Rn, GPR:$Rm))]>, 4484 Requires<[IsARM, HasV5TE]>, 4485 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4486 4487 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4488 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 4489 [(set GPR:$Rd, (ARMsmulwb GPR:$Rn, GPR:$Rm))]>, 4490 Requires<[IsARM, HasV5TE]>, 4491 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4492 4493 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4494 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 4495 [(set GPR:$Rd, (ARMsmulwt GPR:$Rn, GPR:$Rm))]>, 4496 Requires<[IsARM, HasV5TE]>, 4497 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4498} 4499 4500 4501multiclass AI_smla<string opc> { 4502 let DecoderMethod = "DecodeSMLAInstruction" in { 4503 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd), 4504 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4505 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 4506 [(set GPRnopc:$Rd, (add GPR:$Ra, 4507 (bb_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4508 Requires<[IsARM, HasV5TE, UseMulOps]>, 4509 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4510 4511 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd), 4512 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4513 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 4514 [(set GPRnopc:$Rd, (add GPR:$Ra, 4515 (bt_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4516 Requires<[IsARM, HasV5TE, UseMulOps]>, 4517 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4518 4519 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd), 4520 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4521 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 4522 [(set GPRnopc:$Rd, (add GPR:$Ra, 4523 (tb_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4524 Requires<[IsARM, HasV5TE, UseMulOps]>, 4525 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4526 4527 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd), 4528 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4529 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 4530 [(set GPRnopc:$Rd, (add GPR:$Ra, 4531 (tt_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4532 Requires<[IsARM, HasV5TE, UseMulOps]>, 4533 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4534 4535 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd), 4536 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4537 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 4538 [(set GPRnopc:$Rd, 4539 (add GPR:$Ra, (ARMsmulwb GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4540 Requires<[IsARM, HasV5TE, UseMulOps]>, 4541 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4542 4543 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd), 4544 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4545 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 4546 [(set GPRnopc:$Rd, 4547 (add GPR:$Ra, (ARMsmulwt GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4548 Requires<[IsARM, HasV5TE, UseMulOps]>, 4549 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4550 } 4551} 4552 4553defm SMUL : AI_smul<"smul">; 4554defm SMLA : AI_smla<"smla">; 4555 4556// Halfword multiply accumulate long: SMLAL<x><y>. 4557class SMLAL<bits<2> opc1, string asm> 4558 : AMulxyI64<0b0001010, opc1, 4559 (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4560 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4561 IIC_iMAC64, asm, "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4562 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4563 Requires<[IsARM, HasV5TE]>, 4564 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4565 4566def SMLALBB : SMLAL<0b00, "smlalbb">; 4567def SMLALBT : SMLAL<0b10, "smlalbt">; 4568def SMLALTB : SMLAL<0b01, "smlaltb">; 4569def SMLALTT : SMLAL<0b11, "smlaltt">; 4570 4571def : ARMV5TEPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4572 (SMLALBB $Rn, $Rm, $RLo, $RHi)>; 4573def : ARMV5TEPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4574 (SMLALBT $Rn, $Rm, $RLo, $RHi)>; 4575def : ARMV5TEPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4576 (SMLALTB $Rn, $Rm, $RLo, $RHi)>; 4577def : ARMV5TEPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4578 (SMLALTT $Rn, $Rm, $RLo, $RHi)>; 4579 4580// Helper class for AI_smld. 4581class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops, 4582 InstrItinClass itin, string opc, string asm> 4583 : AI<oops, iops, MulFrm, itin, opc, asm, []>, 4584 Requires<[IsARM, HasV6]> { 4585 bits<4> Rn; 4586 bits<4> Rm; 4587 let Inst{27-23} = 0b01110; 4588 let Inst{22} = long; 4589 let Inst{21-20} = 0b00; 4590 let Inst{11-8} = Rm; 4591 let Inst{7} = 0; 4592 let Inst{6} = sub; 4593 let Inst{5} = swap; 4594 let Inst{4} = 1; 4595 let Inst{3-0} = Rn; 4596} 4597class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops, 4598 InstrItinClass itin, string opc, string asm> 4599 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4600 bits<4> Rd; 4601 let Inst{15-12} = 0b1111; 4602 let Inst{19-16} = Rd; 4603} 4604class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops, 4605 InstrItinClass itin, string opc, string asm> 4606 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4607 bits<4> Ra; 4608 bits<4> Rd; 4609 let Inst{19-16} = Rd; 4610 let Inst{15-12} = Ra; 4611} 4612class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops, 4613 InstrItinClass itin, string opc, string asm> 4614 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4615 bits<4> RdLo; 4616 bits<4> RdHi; 4617 let Inst{19-16} = RdHi; 4618 let Inst{15-12} = RdLo; 4619} 4620 4621multiclass AI_smld<bit sub, string opc> { 4622 4623 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd), 4624 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4625 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">, 4626 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4627 4628 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd), 4629 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4630 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">, 4631 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4632 4633 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4634 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4635 NoItinerary, 4636 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">, 4637 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4638 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4639 4640 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4641 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4642 NoItinerary, 4643 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">, 4644 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4645 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4646} 4647 4648defm SMLA : AI_smld<0, "smla">; 4649defm SMLS : AI_smld<1, "smls">; 4650 4651def : ARMV6Pat<(int_arm_smlad GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4652 (SMLAD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4653def : ARMV6Pat<(int_arm_smladx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4654 (SMLADX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4655def : ARMV6Pat<(int_arm_smlsd GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4656 (SMLSD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4657def : ARMV6Pat<(int_arm_smlsdx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4658 (SMLSDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4659def : ARMV6Pat<(ARMSmlald GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4660 (SMLALD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4661def : ARMV6Pat<(ARMSmlaldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4662 (SMLALDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4663def : ARMV6Pat<(ARMSmlsld GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4664 (SMLSLD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4665def : ARMV6Pat<(ARMSmlsldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4666 (SMLSLDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4667 4668multiclass AI_sdml<bit sub, string opc> { 4669 4670 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), 4671 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">, 4672 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4673 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm), 4674 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">, 4675 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4676} 4677 4678defm SMUA : AI_sdml<0, "smua">; 4679defm SMUS : AI_sdml<1, "smus">; 4680 4681def : ARMV6Pat<(int_arm_smuad GPRnopc:$Rn, GPRnopc:$Rm), 4682 (SMUAD GPRnopc:$Rn, GPRnopc:$Rm)>; 4683def : ARMV6Pat<(int_arm_smuadx GPRnopc:$Rn, GPRnopc:$Rm), 4684 (SMUADX GPRnopc:$Rn, GPRnopc:$Rm)>; 4685def : ARMV6Pat<(int_arm_smusd GPRnopc:$Rn, GPRnopc:$Rm), 4686 (SMUSD GPRnopc:$Rn, GPRnopc:$Rm)>; 4687def : ARMV6Pat<(int_arm_smusdx GPRnopc:$Rn, GPRnopc:$Rm), 4688 (SMUSDX GPRnopc:$Rn, GPRnopc:$Rm)>; 4689 4690//===----------------------------------------------------------------------===// 4691// Division Instructions (ARMv7-A with virtualization extension) 4692// 4693def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4694 "sdiv", "\t$Rd, $Rn, $Rm", 4695 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>, 4696 Requires<[IsARM, HasDivideInARM]>, 4697 Sched<[WriteDIV]>; 4698 4699def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4700 "udiv", "\t$Rd, $Rn, $Rm", 4701 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>, 4702 Requires<[IsARM, HasDivideInARM]>, 4703 Sched<[WriteDIV]>; 4704 4705//===----------------------------------------------------------------------===// 4706// Misc. Arithmetic Instructions. 4707// 4708 4709def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm), 4710 IIC_iUNAr, "clz", "\t$Rd, $Rm", 4711 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>, 4712 Sched<[WriteALU]>; 4713 4714def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4715 IIC_iUNAr, "rbit", "\t$Rd, $Rm", 4716 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>, 4717 Requires<[IsARM, HasV6T2]>, 4718 Sched<[WriteALU]>; 4719 4720def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4721 IIC_iUNAr, "rev", "\t$Rd, $Rm", 4722 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>, 4723 Sched<[WriteALU]>; 4724 4725let AddedComplexity = 5 in 4726def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4727 IIC_iUNAr, "rev16", "\t$Rd, $Rm", 4728 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>, 4729 Requires<[IsARM, HasV6]>, 4730 Sched<[WriteALU]>; 4731 4732def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)), 4733 (REV16 (LDRH addrmode3:$addr))>; 4734def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr), 4735 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>; 4736 4737let AddedComplexity = 5 in 4738def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4739 IIC_iUNAr, "revsh", "\t$Rd, $Rm", 4740 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>, 4741 Requires<[IsARM, HasV6]>, 4742 Sched<[WriteALU]>; 4743 4744def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)), 4745 (and (srl GPR:$Rm, (i32 8)), 0xFF)), 4746 (REVSH GPR:$Rm)>; 4747 4748def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd), 4749 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh), 4750 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 4751 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF), 4752 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh), 4753 0xFFFF0000)))]>, 4754 Requires<[IsARM, HasV6]>, 4755 Sched<[WriteALUsi, ReadALU]>; 4756 4757// Alternate cases for PKHBT where identities eliminate some nodes. 4758def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)), 4759 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>; 4760def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)), 4761 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>; 4762 4763// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 4764// will match the pattern below. 4765def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd), 4766 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh), 4767 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 4768 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000), 4769 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh), 4770 0xFFFF)))]>, 4771 Requires<[IsARM, HasV6]>, 4772 Sched<[WriteALUsi, ReadALU]>; 4773 4774// Alternate cases for PKHTB where identities eliminate some nodes. Note that 4775// a shift amount of 0 is *not legal* here, it is PKHBT instead. 4776// We also can not replace a srl (17..31) by an arithmetic shift we would use in 4777// pkhtb src1, src2, asr (17..31). 4778def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4779 (srl GPRnopc:$src2, imm16:$sh)), 4780 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>; 4781def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4782 (sra GPRnopc:$src2, imm16_31:$sh)), 4783 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>; 4784def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4785 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)), 4786 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>; 4787 4788//===----------------------------------------------------------------------===// 4789// CRC Instructions 4790// 4791// Polynomials: 4792// + CRC32{B,H,W} 0x04C11DB7 4793// + CRC32C{B,H,W} 0x1EDC6F41 4794// 4795 4796class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin> 4797 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary, 4798 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm", 4799 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>, 4800 Requires<[IsARM, HasV8, HasCRC]> { 4801 bits<4> Rd; 4802 bits<4> Rn; 4803 bits<4> Rm; 4804 4805 let Inst{31-28} = 0b1110; 4806 let Inst{27-23} = 0b00010; 4807 let Inst{22-21} = sz; 4808 let Inst{20} = 0; 4809 let Inst{19-16} = Rn; 4810 let Inst{15-12} = Rd; 4811 let Inst{11-10} = 0b00; 4812 let Inst{9} = C; 4813 let Inst{8} = 0; 4814 let Inst{7-4} = 0b0100; 4815 let Inst{3-0} = Rm; 4816 4817 let Unpredictable{11-8} = 0b1101; 4818} 4819 4820def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>; 4821def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>; 4822def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>; 4823def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>; 4824def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>; 4825def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>; 4826 4827//===----------------------------------------------------------------------===// 4828// ARMv8.1a Privilege Access Never extension 4829// 4830// SETPAN #imm1 4831 4832def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan", 4833 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> { 4834 bits<1> imm; 4835 4836 let Inst{31-28} = 0b1111; 4837 let Inst{27-20} = 0b00010001; 4838 let Inst{19-16} = 0b0000; 4839 let Inst{15-10} = 0b000000; 4840 let Inst{9} = imm; 4841 let Inst{8} = 0b0; 4842 let Inst{7-4} = 0b0000; 4843 let Inst{3-0} = 0b0000; 4844 4845 let Unpredictable{19-16} = 0b1111; 4846 let Unpredictable{15-10} = 0b111111; 4847 let Unpredictable{8} = 0b1; 4848 let Unpredictable{3-0} = 0b1111; 4849} 4850 4851//===----------------------------------------------------------------------===// 4852// Comparison Instructions... 4853// 4854 4855defm CMP : AI1_cmp_irs<0b1010, "cmp", 4856 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, ARMcmp>; 4857 4858// ARMcmpZ can re-use the above instruction definitions. 4859def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm), 4860 (CMPri GPR:$src, mod_imm:$imm)>; 4861def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs), 4862 (CMPrr GPR:$src, GPR:$rhs)>; 4863def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs), 4864 (CMPrsi GPR:$src, so_reg_imm:$rhs)>; 4865def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs), 4866 (CMPrsr GPR:$src, so_reg_reg:$rhs)>; 4867 4868// CMN register-integer 4869let isCompare = 1, Defs = [CPSR] in { 4870def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi, 4871 "cmn", "\t$Rn, $imm", 4872 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>, 4873 Sched<[WriteCMP, ReadALU]> { 4874 bits<4> Rn; 4875 bits<12> imm; 4876 let Inst{25} = 1; 4877 let Inst{20} = 1; 4878 let Inst{19-16} = Rn; 4879 let Inst{15-12} = 0b0000; 4880 let Inst{11-0} = imm; 4881 4882 let Unpredictable{15-12} = 0b1111; 4883} 4884 4885// CMN register-register/shift 4886def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr, 4887 "cmn", "\t$Rn, $Rm", 4888 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4889 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> { 4890 bits<4> Rn; 4891 bits<4> Rm; 4892 let isCommutable = 1; 4893 let Inst{25} = 0; 4894 let Inst{20} = 1; 4895 let Inst{19-16} = Rn; 4896 let Inst{15-12} = 0b0000; 4897 let Inst{11-4} = 0b00000000; 4898 let Inst{3-0} = Rm; 4899 4900 let Unpredictable{15-12} = 0b1111; 4901} 4902 4903def CMNzrsi : AI1<0b1011, (outs), 4904 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr, 4905 "cmn", "\t$Rn, $shift", 4906 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4907 GPR:$Rn, so_reg_imm:$shift)]>, 4908 Sched<[WriteCMPsi, ReadALU]> { 4909 bits<4> Rn; 4910 bits<12> shift; 4911 let Inst{25} = 0; 4912 let Inst{20} = 1; 4913 let Inst{19-16} = Rn; 4914 let Inst{15-12} = 0b0000; 4915 let Inst{11-5} = shift{11-5}; 4916 let Inst{4} = 0; 4917 let Inst{3-0} = shift{3-0}; 4918 4919 let Unpredictable{15-12} = 0b1111; 4920} 4921 4922def CMNzrsr : AI1<0b1011, (outs), 4923 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr, 4924 "cmn", "\t$Rn, $shift", 4925 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4926 GPRnopc:$Rn, so_reg_reg:$shift)]>, 4927 Sched<[WriteCMPsr, ReadALU]> { 4928 bits<4> Rn; 4929 bits<12> shift; 4930 let Inst{25} = 0; 4931 let Inst{20} = 1; 4932 let Inst{19-16} = Rn; 4933 let Inst{15-12} = 0b0000; 4934 let Inst{11-8} = shift{11-8}; 4935 let Inst{7} = 0; 4936 let Inst{6-5} = shift{6-5}; 4937 let Inst{4} = 1; 4938 let Inst{3-0} = shift{3-0}; 4939 4940 let Unpredictable{15-12} = 0b1111; 4941} 4942 4943} 4944 4945def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm), 4946 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4947 4948def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm), 4949 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4950 4951// Note that TST/TEQ don't set all the same flags that CMP does! 4952defm TST : AI1_cmp_irs<0b1000, "tst", 4953 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4954 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1, 4955 "DecodeTSTInstruction">; 4956defm TEQ : AI1_cmp_irs<0b1001, "teq", 4957 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4958 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>; 4959 4960// Pseudo i64 compares for some floating point compares. 4961let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, 4962 Defs = [CPSR] in { 4963def BCCi64 : PseudoInst<(outs), 4964 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst), 4965 IIC_Br, 4966 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>, 4967 Sched<[WriteBr]>; 4968 4969def BCCZi64 : PseudoInst<(outs), 4970 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, 4971 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>, 4972 Sched<[WriteBr]>; 4973} // usesCustomInserter 4974 4975 4976// Conditional moves 4977let hasSideEffects = 0 in { 4978 4979let isCommutable = 1, isSelect = 1 in 4980def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), 4981 (ins GPR:$false, GPR:$Rm, cmovpred:$p), 4982 4, IIC_iCMOVr, 4983 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, 4984 cmovpred:$p))]>, 4985 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4986 4987def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd), 4988 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p), 4989 4, IIC_iCMOVsr, 4990 [(set GPR:$Rd, 4991 (ARMcmov GPR:$false, so_reg_imm:$shift, 4992 cmovpred:$p))]>, 4993 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4994def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd), 4995 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p), 4996 4, IIC_iCMOVsr, 4997 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift, 4998 cmovpred:$p))]>, 4999 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 5000 5001 5002let isMoveImm = 1 in 5003def MOVCCi16 5004 : ARMPseudoInst<(outs GPR:$Rd), 5005 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p), 5006 4, IIC_iMOVi, 5007 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm, 5008 cmovpred:$p))]>, 5009 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>, 5010 Sched<[WriteALU]>; 5011 5012let isMoveImm = 1 in 5013def MOVCCi : ARMPseudoInst<(outs GPR:$Rd), 5014 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 5015 4, IIC_iCMOVi, 5016 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm, 5017 cmovpred:$p))]>, 5018 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 5019 5020// Two instruction predicate mov immediate. 5021let isMoveImm = 1 in 5022def MOVCCi32imm 5023 : ARMPseudoInst<(outs GPR:$Rd), 5024 (ins GPR:$false, i32imm:$src, cmovpred:$p), 5025 8, IIC_iCMOVix2, 5026 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src, 5027 cmovpred:$p))]>, 5028 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>; 5029 5030let isMoveImm = 1 in 5031def MVNCCi : ARMPseudoInst<(outs GPR:$Rd), 5032 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 5033 4, IIC_iCMOVi, 5034 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm, 5035 cmovpred:$p))]>, 5036 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 5037 5038} // hasSideEffects 5039 5040 5041//===----------------------------------------------------------------------===// 5042// Atomic operations intrinsics 5043// 5044 5045def MemBarrierOptOperand : AsmOperandClass { 5046 let Name = "MemBarrierOpt"; 5047 let ParserMethod = "parseMemBarrierOptOperand"; 5048} 5049def memb_opt : Operand<i32> { 5050 let PrintMethod = "printMemBOption"; 5051 let ParserMatchClass = MemBarrierOptOperand; 5052 let DecoderMethod = "DecodeMemBarrierOption"; 5053} 5054 5055def InstSyncBarrierOptOperand : AsmOperandClass { 5056 let Name = "InstSyncBarrierOpt"; 5057 let ParserMethod = "parseInstSyncBarrierOptOperand"; 5058} 5059def instsyncb_opt : Operand<i32> { 5060 let PrintMethod = "printInstSyncBOption"; 5061 let ParserMatchClass = InstSyncBarrierOptOperand; 5062 let DecoderMethod = "DecodeInstSyncBarrierOption"; 5063} 5064 5065def TraceSyncBarrierOptOperand : AsmOperandClass { 5066 let Name = "TraceSyncBarrierOpt"; 5067 let ParserMethod = "parseTraceSyncBarrierOptOperand"; 5068} 5069def tsb_opt : Operand<i32> { 5070 let PrintMethod = "printTraceSyncBOption"; 5071 let ParserMatchClass = TraceSyncBarrierOptOperand; 5072} 5073 5074// Memory barriers protect the atomic sequences 5075let hasSideEffects = 1 in { 5076def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 5077 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>, 5078 Requires<[IsARM, HasDB]> { 5079 bits<4> opt; 5080 let Inst{31-4} = 0xf57ff05; 5081 let Inst{3-0} = opt; 5082} 5083 5084def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 5085 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>, 5086 Requires<[IsARM, HasDB]> { 5087 bits<4> opt; 5088 let Inst{31-4} = 0xf57ff04; 5089 let Inst{3-0} = opt; 5090} 5091 5092// ISB has only full system option 5093def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary, 5094 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>, 5095 Requires<[IsARM, HasDB]> { 5096 bits<4> opt; 5097 let Inst{31-4} = 0xf57ff06; 5098 let Inst{3-0} = opt; 5099} 5100 5101let hasNoSchedulingInfo = 1 in 5102def TSB : AInoP<(outs), (ins tsb_opt:$opt), MiscFrm, NoItinerary, 5103 "tsb", "\t$opt", []>, Requires<[IsARM, HasV8_4a]> { 5104 let Inst{31-0} = 0xe320f012; 5105} 5106 5107} 5108 5109// Armv8.5-A speculation barrier 5110def SB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "sb", "", []>, 5111 Requires<[IsARM, HasSB]>, Sched<[]> { 5112 let Inst{31-0} = 0xf57ff070; 5113 let Unpredictable = 0x000fff0f; 5114 let hasSideEffects = 1; 5115} 5116 5117let usesCustomInserter = 1, Defs = [CPSR], hasNoSchedulingInfo = 1 in { 5118 // Pseudo instruction that combines movs + predicated rsbmi 5119 // to implement integer ABS 5120 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>; 5121} 5122 5123let usesCustomInserter = 1, Defs = [CPSR], hasNoSchedulingInfo = 1 in { 5124 def COPY_STRUCT_BYVAL_I32 : PseudoInst< 5125 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment), 5126 NoItinerary, 5127 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>; 5128} 5129 5130let hasPostISelHook = 1, Constraints = "$newdst = $dst, $newsrc = $src" in { 5131 // %newsrc, %newdst = MEMCPY %dst, %src, N, ...N scratch regs... 5132 // Copies N registers worth of memory from address %src to address %dst 5133 // and returns the incremented addresses. N scratch register will 5134 // be attached for the copy to use. 5135 def MEMCPY : PseudoInst< 5136 (outs GPR:$newdst, GPR:$newsrc), 5137 (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops), 5138 NoItinerary, 5139 [(set GPR:$newdst, GPR:$newsrc, 5140 (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>; 5141} 5142 5143def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 5144 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 5145}]>; 5146 5147def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 5148 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 5149}]>; 5150 5151def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 5152 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 5153}]>; 5154 5155def strex_1 : PatFrag<(ops node:$val, node:$ptr), 5156 (int_arm_strex node:$val, node:$ptr), [{ 5157 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 5158}]>; 5159 5160def strex_2 : PatFrag<(ops node:$val, node:$ptr), 5161 (int_arm_strex node:$val, node:$ptr), [{ 5162 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 5163}]>; 5164 5165def strex_4 : PatFrag<(ops node:$val, node:$ptr), 5166 (int_arm_strex node:$val, node:$ptr), [{ 5167 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 5168}]>; 5169 5170def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 5171 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 5172}]>; 5173 5174def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 5175 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 5176}]>; 5177 5178def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 5179 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 5180}]>; 5181 5182def stlex_1 : PatFrag<(ops node:$val, node:$ptr), 5183 (int_arm_stlex node:$val, node:$ptr), [{ 5184 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 5185}]>; 5186 5187def stlex_2 : PatFrag<(ops node:$val, node:$ptr), 5188 (int_arm_stlex node:$val, node:$ptr), [{ 5189 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 5190}]>; 5191 5192def stlex_4 : PatFrag<(ops node:$val, node:$ptr), 5193 (int_arm_stlex node:$val, node:$ptr), [{ 5194 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 5195}]>; 5196 5197let mayLoad = 1 in { 5198def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5199 NoItinerary, "ldrexb", "\t$Rt, $addr", 5200 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>; 5201def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5202 NoItinerary, "ldrexh", "\t$Rt, $addr", 5203 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>; 5204def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5205 NoItinerary, "ldrex", "\t$Rt, $addr", 5206 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>; 5207let hasExtraDefRegAllocReq = 1 in 5208def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 5209 NoItinerary, "ldrexd", "\t$Rt, $addr", []> { 5210 let DecoderMethod = "DecodeDoubleRegLoad"; 5211} 5212 5213def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5214 NoItinerary, "ldaexb", "\t$Rt, $addr", 5215 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>; 5216def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5217 NoItinerary, "ldaexh", "\t$Rt, $addr", 5218 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>; 5219def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5220 NoItinerary, "ldaex", "\t$Rt, $addr", 5221 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>; 5222let hasExtraDefRegAllocReq = 1 in 5223def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 5224 NoItinerary, "ldaexd", "\t$Rt, $addr", []> { 5225 let DecoderMethod = "DecodeDoubleRegLoad"; 5226} 5227} 5228 5229let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 5230def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5231 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", 5232 [(set GPR:$Rd, (strex_1 GPR:$Rt, 5233 addr_offset_none:$addr))]>; 5234def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5235 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", 5236 [(set GPR:$Rd, (strex_2 GPR:$Rt, 5237 addr_offset_none:$addr))]>; 5238def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5239 NoItinerary, "strex", "\t$Rd, $Rt, $addr", 5240 [(set GPR:$Rd, (strex_4 GPR:$Rt, 5241 addr_offset_none:$addr))]>; 5242let hasExtraSrcRegAllocReq = 1 in 5243def STREXD : AIstrex<0b01, (outs GPR:$Rd), 5244 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 5245 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> { 5246 let DecoderMethod = "DecodeDoubleRegStore"; 5247} 5248def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5249 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr", 5250 [(set GPR:$Rd, 5251 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>; 5252def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5253 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr", 5254 [(set GPR:$Rd, 5255 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>; 5256def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5257 NoItinerary, "stlex", "\t$Rd, $Rt, $addr", 5258 [(set GPR:$Rd, 5259 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>; 5260let hasExtraSrcRegAllocReq = 1 in 5261def STLEXD : AIstlex<0b01, (outs GPR:$Rd), 5262 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 5263 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> { 5264 let DecoderMethod = "DecodeDoubleRegStore"; 5265} 5266} 5267 5268def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", 5269 [(int_arm_clrex)]>, 5270 Requires<[IsARM, HasV6K]> { 5271 let Inst{31-0} = 0b11110101011111111111000000011111; 5272} 5273 5274def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 5275 (STREXB GPR:$Rt, addr_offset_none:$addr)>; 5276def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 5277 (STREXH GPR:$Rt, addr_offset_none:$addr)>; 5278 5279def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 5280 (STLEXB GPR:$Rt, addr_offset_none:$addr)>; 5281def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 5282 (STLEXH GPR:$Rt, addr_offset_none:$addr)>; 5283 5284class acquiring_load<PatFrag base> 5285 : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 5286 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 5287 return isAcquireOrStronger(Ordering); 5288}]>; 5289 5290def atomic_load_acquire_8 : acquiring_load<atomic_load_8>; 5291def atomic_load_acquire_16 : acquiring_load<atomic_load_16>; 5292def atomic_load_acquire_32 : acquiring_load<atomic_load_32>; 5293 5294class releasing_store<PatFrag base> 5295 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 5296 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 5297 return isReleaseOrStronger(Ordering); 5298}]>; 5299 5300def atomic_store_release_8 : releasing_store<atomic_store_8>; 5301def atomic_store_release_16 : releasing_store<atomic_store_16>; 5302def atomic_store_release_32 : releasing_store<atomic_store_32>; 5303 5304let AddedComplexity = 8 in { 5305 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>; 5306 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>; 5307 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>; 5308 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>; 5309 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>; 5310 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>; 5311} 5312 5313// SWP/SWPB are deprecated in V6/V7 and optional in v7VE. 5314// FIXME Use InstAlias to generate LDREX/STREX pairs instead. 5315let mayLoad = 1, mayStore = 1 in { 5316def SWP : AIswp<0, (outs GPRnopc:$Rt), 5317 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>, 5318 Requires<[IsARM,PreV8]>; 5319def SWPB: AIswp<1, (outs GPRnopc:$Rt), 5320 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>, 5321 Requires<[IsARM,PreV8]>; 5322} 5323 5324//===----------------------------------------------------------------------===// 5325// Coprocessor Instructions. 5326// 5327 5328def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5329 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5330 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5331 [(int_arm_cdp timm:$cop, timm:$opc1, timm:$CRd, timm:$CRn, 5332 timm:$CRm, timm:$opc2)]>, 5333 Requires<[IsARM,PreV8]> { 5334 bits<4> opc1; 5335 bits<4> CRn; 5336 bits<4> CRd; 5337 bits<4> cop; 5338 bits<3> opc2; 5339 bits<4> CRm; 5340 5341 let Inst{3-0} = CRm; 5342 let Inst{4} = 0; 5343 let Inst{7-5} = opc2; 5344 let Inst{11-8} = cop; 5345 let Inst{15-12} = CRd; 5346 let Inst{19-16} = CRn; 5347 let Inst{23-20} = opc1; 5348 5349 let DecoderNamespace = "CoProc"; 5350} 5351 5352def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5353 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5354 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5355 [(int_arm_cdp2 timm:$cop, timm:$opc1, timm:$CRd, timm:$CRn, 5356 timm:$CRm, timm:$opc2)]>, 5357 Requires<[IsARM,PreV8]> { 5358 let Inst{31-28} = 0b1111; 5359 bits<4> opc1; 5360 bits<4> CRn; 5361 bits<4> CRd; 5362 bits<4> cop; 5363 bits<3> opc2; 5364 bits<4> CRm; 5365 5366 let Inst{3-0} = CRm; 5367 let Inst{4} = 0; 5368 let Inst{7-5} = opc2; 5369 let Inst{11-8} = cop; 5370 let Inst{15-12} = CRd; 5371 let Inst{19-16} = CRn; 5372 let Inst{23-20} = opc1; 5373 5374 let DecoderNamespace = "CoProc"; 5375} 5376 5377class ACI<dag oops, dag iops, string opc, string asm, 5378 list<dag> pattern, IndexMode im = IndexModeNone> 5379 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 5380 opc, asm, "", pattern> { 5381 let Inst{27-25} = 0b110; 5382} 5383class ACInoP<dag oops, dag iops, string opc, string asm, 5384 list<dag> pattern, IndexMode im = IndexModeNone> 5385 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 5386 opc, asm, "", pattern> { 5387 let Inst{31-28} = 0b1111; 5388 let Inst{27-25} = 0b110; 5389} 5390 5391let DecoderNamespace = "CoProc" in { 5392multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> { 5393 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 5394 asm, "\t$cop, $CRd, $addr", pattern> { 5395 bits<13> addr; 5396 bits<4> cop; 5397 bits<4> CRd; 5398 let Inst{24} = 1; // P = 1 5399 let Inst{23} = addr{8}; 5400 let Inst{22} = Dbit; 5401 let Inst{21} = 0; // W = 0 5402 let Inst{20} = load; 5403 let Inst{19-16} = addr{12-9}; 5404 let Inst{15-12} = CRd; 5405 let Inst{11-8} = cop; 5406 let Inst{7-0} = addr{7-0}; 5407 let DecoderMethod = "DecodeCopMemInstruction"; 5408 } 5409 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 5410 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { 5411 bits<13> addr; 5412 bits<4> cop; 5413 bits<4> CRd; 5414 let Inst{24} = 1; // P = 1 5415 let Inst{23} = addr{8}; 5416 let Inst{22} = Dbit; 5417 let Inst{21} = 1; // W = 1 5418 let Inst{20} = load; 5419 let Inst{19-16} = addr{12-9}; 5420 let Inst{15-12} = CRd; 5421 let Inst{11-8} = cop; 5422 let Inst{7-0} = addr{7-0}; 5423 let DecoderMethod = "DecodeCopMemInstruction"; 5424 } 5425 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5426 postidx_imm8s4:$offset), 5427 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { 5428 bits<9> offset; 5429 bits<4> addr; 5430 bits<4> cop; 5431 bits<4> CRd; 5432 let Inst{24} = 0; // P = 0 5433 let Inst{23} = offset{8}; 5434 let Inst{22} = Dbit; 5435 let Inst{21} = 1; // W = 1 5436 let Inst{20} = load; 5437 let Inst{19-16} = addr; 5438 let Inst{15-12} = CRd; 5439 let Inst{11-8} = cop; 5440 let Inst{7-0} = offset{7-0}; 5441 let DecoderMethod = "DecodeCopMemInstruction"; 5442 } 5443 def _OPTION : ACI<(outs), 5444 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5445 coproc_option_imm:$option), 5446 asm, "\t$cop, $CRd, $addr, $option", []> { 5447 bits<8> option; 5448 bits<4> addr; 5449 bits<4> cop; 5450 bits<4> CRd; 5451 let Inst{24} = 0; // P = 0 5452 let Inst{23} = 1; // U = 1 5453 let Inst{22} = Dbit; 5454 let Inst{21} = 0; // W = 0 5455 let Inst{20} = load; 5456 let Inst{19-16} = addr; 5457 let Inst{15-12} = CRd; 5458 let Inst{11-8} = cop; 5459 let Inst{7-0} = option; 5460 let DecoderMethod = "DecodeCopMemInstruction"; 5461 } 5462} 5463multiclass LdSt2Cop<bit load, bit Dbit, string asm, list<dag> pattern> { 5464 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 5465 asm, "\t$cop, $CRd, $addr", pattern> { 5466 bits<13> addr; 5467 bits<4> cop; 5468 bits<4> CRd; 5469 let Inst{24} = 1; // P = 1 5470 let Inst{23} = addr{8}; 5471 let Inst{22} = Dbit; 5472 let Inst{21} = 0; // W = 0 5473 let Inst{20} = load; 5474 let Inst{19-16} = addr{12-9}; 5475 let Inst{15-12} = CRd; 5476 let Inst{11-8} = cop; 5477 let Inst{7-0} = addr{7-0}; 5478 let DecoderMethod = "DecodeCopMemInstruction"; 5479 } 5480 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 5481 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { 5482 bits<13> addr; 5483 bits<4> cop; 5484 bits<4> CRd; 5485 let Inst{24} = 1; // P = 1 5486 let Inst{23} = addr{8}; 5487 let Inst{22} = Dbit; 5488 let Inst{21} = 1; // W = 1 5489 let Inst{20} = load; 5490 let Inst{19-16} = addr{12-9}; 5491 let Inst{15-12} = CRd; 5492 let Inst{11-8} = cop; 5493 let Inst{7-0} = addr{7-0}; 5494 let DecoderMethod = "DecodeCopMemInstruction"; 5495 } 5496 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5497 postidx_imm8s4:$offset), 5498 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { 5499 bits<9> offset; 5500 bits<4> addr; 5501 bits<4> cop; 5502 bits<4> CRd; 5503 let Inst{24} = 0; // P = 0 5504 let Inst{23} = offset{8}; 5505 let Inst{22} = Dbit; 5506 let Inst{21} = 1; // W = 1 5507 let Inst{20} = load; 5508 let Inst{19-16} = addr; 5509 let Inst{15-12} = CRd; 5510 let Inst{11-8} = cop; 5511 let Inst{7-0} = offset{7-0}; 5512 let DecoderMethod = "DecodeCopMemInstruction"; 5513 } 5514 def _OPTION : ACInoP<(outs), 5515 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5516 coproc_option_imm:$option), 5517 asm, "\t$cop, $CRd, $addr, $option", []> { 5518 bits<8> option; 5519 bits<4> addr; 5520 bits<4> cop; 5521 bits<4> CRd; 5522 let Inst{24} = 0; // P = 0 5523 let Inst{23} = 1; // U = 1 5524 let Inst{22} = Dbit; 5525 let Inst{21} = 0; // W = 0 5526 let Inst{20} = load; 5527 let Inst{19-16} = addr; 5528 let Inst{15-12} = CRd; 5529 let Inst{11-8} = cop; 5530 let Inst{7-0} = option; 5531 let DecoderMethod = "DecodeCopMemInstruction"; 5532 } 5533} 5534 5535defm LDC : LdStCop <1, 0, "ldc", [(int_arm_ldc timm:$cop, timm:$CRd, addrmode5:$addr)]>; 5536defm LDCL : LdStCop <1, 1, "ldcl", [(int_arm_ldcl timm:$cop, timm:$CRd, addrmode5:$addr)]>; 5537defm LDC2 : LdSt2Cop<1, 0, "ldc2", [(int_arm_ldc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5538defm LDC2L : LdSt2Cop<1, 1, "ldc2l", [(int_arm_ldc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5539 5540defm STC : LdStCop <0, 0, "stc", [(int_arm_stc timm:$cop, timm:$CRd, addrmode5:$addr)]>; 5541defm STCL : LdStCop <0, 1, "stcl", [(int_arm_stcl timm:$cop, timm:$CRd, addrmode5:$addr)]>; 5542defm STC2 : LdSt2Cop<0, 0, "stc2", [(int_arm_stc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5543defm STC2L : LdSt2Cop<0, 1, "stc2l", [(int_arm_stc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5544 5545} // DecoderNamespace = "CoProc" 5546 5547//===----------------------------------------------------------------------===// 5548// Move between coprocessor and ARM core register. 5549// 5550 5551class MovRCopro<string opc, bit direction, dag oops, dag iops, 5552 list<dag> pattern> 5553 : ABI<0b1110, oops, iops, NoItinerary, opc, 5554 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> { 5555 let Inst{20} = direction; 5556 let Inst{4} = 1; 5557 5558 bits<4> Rt; 5559 bits<4> cop; 5560 bits<3> opc1; 5561 bits<3> opc2; 5562 bits<4> CRm; 5563 bits<4> CRn; 5564 5565 let Inst{15-12} = Rt; 5566 let Inst{11-8} = cop; 5567 let Inst{23-21} = opc1; 5568 let Inst{7-5} = opc2; 5569 let Inst{3-0} = CRm; 5570 let Inst{19-16} = CRn; 5571 5572 let DecoderNamespace = "CoProc"; 5573} 5574 5575def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */, 5576 (outs), 5577 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5578 c_imm:$CRm, imm0_7:$opc2), 5579 [(int_arm_mcr timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn, 5580 timm:$CRm, timm:$opc2)]>, 5581 ComplexDeprecationPredicate<"MCR">; 5582def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 5583 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5584 c_imm:$CRm, 0, pred:$p)>; 5585def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, 5586 (outs GPRwithAPSR:$Rt), 5587 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5588 imm0_7:$opc2), []>, 5589 ComplexDeprecationPredicate<"MRC">; 5590def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", 5591 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5592 c_imm:$CRm, 0, pred:$p)>; 5593 5594def : ARMPat<(int_arm_mrc timm:$cop, timm:$opc1, timm:$CRn, timm:$CRm, timm:$opc2), 5595 (MRC p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2)>; 5596 5597class MovRCopro2<string opc, bit direction, dag oops, dag iops, 5598 list<dag> pattern> 5599 : ABXI<0b1110, oops, iops, NoItinerary, 5600 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> { 5601 let Inst{31-24} = 0b11111110; 5602 let Inst{20} = direction; 5603 let Inst{4} = 1; 5604 5605 bits<4> Rt; 5606 bits<4> cop; 5607 bits<3> opc1; 5608 bits<3> opc2; 5609 bits<4> CRm; 5610 bits<4> CRn; 5611 5612 let Inst{15-12} = Rt; 5613 let Inst{11-8} = cop; 5614 let Inst{23-21} = opc1; 5615 let Inst{7-5} = opc2; 5616 let Inst{3-0} = CRm; 5617 let Inst{19-16} = CRn; 5618 5619 let DecoderNamespace = "CoProc"; 5620} 5621 5622def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */, 5623 (outs), 5624 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5625 c_imm:$CRm, imm0_7:$opc2), 5626 [(int_arm_mcr2 timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn, 5627 timm:$CRm, timm:$opc2)]>, 5628 Requires<[IsARM,PreV8]>; 5629def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm", 5630 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5631 c_imm:$CRm, 0)>; 5632def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, 5633 (outs GPRwithAPSR:$Rt), 5634 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5635 imm0_7:$opc2), []>, 5636 Requires<[IsARM,PreV8]>; 5637def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm", 5638 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5639 c_imm:$CRm, 0)>; 5640 5641def : ARMV5TPat<(int_arm_mrc2 timm:$cop, timm:$opc1, timm:$CRn, 5642 timm:$CRm, timm:$opc2), 5643 (MRC2 p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2)>; 5644 5645class MovRRCopro<string opc, bit direction, dag oops, dag iops, list<dag> 5646 pattern = []> 5647 : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", 5648 pattern> { 5649 5650 let Inst{23-21} = 0b010; 5651 let Inst{20} = direction; 5652 5653 bits<4> Rt; 5654 bits<4> Rt2; 5655 bits<4> cop; 5656 bits<4> opc1; 5657 bits<4> CRm; 5658 5659 let Inst{15-12} = Rt; 5660 let Inst{19-16} = Rt2; 5661 let Inst{11-8} = cop; 5662 let Inst{7-4} = opc1; 5663 let Inst{3-0} = CRm; 5664} 5665 5666def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */, 5667 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5668 GPRnopc:$Rt2, c_imm:$CRm), 5669 [(int_arm_mcrr timm:$cop, timm:$opc1, GPRnopc:$Rt, 5670 GPRnopc:$Rt2, timm:$CRm)]>; 5671def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */, 5672 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5673 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5674 5675class MovRRCopro2<string opc, bit direction, dag oops, dag iops, 5676 list<dag> pattern = []> 5677 : ABXI<0b1100, oops, iops, NoItinerary, 5678 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>, 5679 Requires<[IsARM,PreV8]> { 5680 let Inst{31-28} = 0b1111; 5681 let Inst{23-21} = 0b010; 5682 let Inst{20} = direction; 5683 5684 bits<4> Rt; 5685 bits<4> Rt2; 5686 bits<4> cop; 5687 bits<4> opc1; 5688 bits<4> CRm; 5689 5690 let Inst{15-12} = Rt; 5691 let Inst{19-16} = Rt2; 5692 let Inst{11-8} = cop; 5693 let Inst{7-4} = opc1; 5694 let Inst{3-0} = CRm; 5695 5696 let DecoderMethod = "DecoderForMRRC2AndMCRR2"; 5697} 5698 5699def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */, 5700 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5701 GPRnopc:$Rt2, c_imm:$CRm), 5702 [(int_arm_mcrr2 timm:$cop, timm:$opc1, GPRnopc:$Rt, 5703 GPRnopc:$Rt2, timm:$CRm)]>; 5704 5705def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */, 5706 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5707 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5708 5709//===----------------------------------------------------------------------===// 5710// Move between special register and ARM core register 5711// 5712 5713// Move to ARM core register from Special Register 5714def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5715 "mrs", "\t$Rd, apsr", []> { 5716 bits<4> Rd; 5717 let Inst{23-16} = 0b00001111; 5718 let Unpredictable{19-17} = 0b111; 5719 5720 let Inst{15-12} = Rd; 5721 5722 let Inst{11-0} = 0b000000000000; 5723 let Unpredictable{11-0} = 0b110100001111; 5724} 5725 5726def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p), 0>, 5727 Requires<[IsARM]>; 5728 5729// The MRSsys instruction is the MRS instruction from the ARM ARM, 5730// section B9.3.9, with the R bit set to 1. 5731def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5732 "mrs", "\t$Rd, spsr", []> { 5733 bits<4> Rd; 5734 let Inst{23-16} = 0b01001111; 5735 let Unpredictable{19-16} = 0b1111; 5736 5737 let Inst{15-12} = Rd; 5738 5739 let Inst{11-0} = 0b000000000000; 5740 let Unpredictable{11-0} = 0b110100001111; 5741} 5742 5743// However, the MRS (banked register) system instruction (ARMv7VE) *does* have a 5744// separate encoding (distinguished by bit 5. 5745def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked), 5746 NoItinerary, "mrs", "\t$Rd, $banked", []>, 5747 Requires<[IsARM, HasVirtualization]> { 5748 bits<6> banked; 5749 bits<4> Rd; 5750 5751 let Inst{23} = 0; 5752 let Inst{22} = banked{5}; // R bit 5753 let Inst{21-20} = 0b00; 5754 let Inst{19-16} = banked{3-0}; 5755 let Inst{15-12} = Rd; 5756 let Inst{11-9} = 0b001; 5757 let Inst{8} = banked{4}; 5758 let Inst{7-0} = 0b00000000; 5759} 5760 5761// Move from ARM core register to Special Register 5762// 5763// No need to have both system and application versions of MSR (immediate) or 5764// MSR (register), the encodings are the same and the assembly parser has no way 5765// to distinguish between them. The mask operand contains the special register 5766// (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be 5767// accessed in the special register. 5768let Defs = [CPSR] in 5769def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, 5770 "msr", "\t$mask, $Rn", []> { 5771 bits<5> mask; 5772 bits<4> Rn; 5773 5774 let Inst{23} = 0; 5775 let Inst{22} = mask{4}; // R bit 5776 let Inst{21-20} = 0b10; 5777 let Inst{19-16} = mask{3-0}; 5778 let Inst{15-12} = 0b1111; 5779 let Inst{11-4} = 0b00000000; 5780 let Inst{3-0} = Rn; 5781} 5782 5783let Defs = [CPSR] in 5784def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary, 5785 "msr", "\t$mask, $imm", []> { 5786 bits<5> mask; 5787 bits<12> imm; 5788 5789 let Inst{23} = 0; 5790 let Inst{22} = mask{4}; // R bit 5791 let Inst{21-20} = 0b10; 5792 let Inst{19-16} = mask{3-0}; 5793 let Inst{15-12} = 0b1111; 5794 let Inst{11-0} = imm; 5795} 5796 5797// However, the MSR (banked register) system instruction (ARMv7VE) *does* have a 5798// separate encoding (distinguished by bit 5. 5799def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn), 5800 NoItinerary, "msr", "\t$banked, $Rn", []>, 5801 Requires<[IsARM, HasVirtualization]> { 5802 bits<6> banked; 5803 bits<4> Rn; 5804 5805 let Inst{23} = 0; 5806 let Inst{22} = banked{5}; // R bit 5807 let Inst{21-20} = 0b10; 5808 let Inst{19-16} = banked{3-0}; 5809 let Inst{15-12} = 0b1111; 5810 let Inst{11-9} = 0b001; 5811 let Inst{8} = banked{4}; 5812 let Inst{7-4} = 0b0000; 5813 let Inst{3-0} = Rn; 5814} 5815 5816// Dynamic stack allocation yields a _chkstk for Windows targets. These calls 5817// are needed to probe the stack when allocating more than 5818// 4k bytes in one go. Touching the stack at 4K increments is necessary to 5819// ensure that the guard pages used by the OS virtual memory manager are 5820// allocated in correct sequence. 5821// The main point of having separate instruction are extra unmodelled effects 5822// (compared to ordinary calls) like stack pointer change. 5823 5824def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone, 5825 [SDNPHasChain, SDNPSideEffect]>; 5826let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP], hasNoSchedulingInfo = 1 in 5827 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>; 5828 5829def win__dbzchk : SDNode<"ARMISD::WIN__DBZCHK", SDT_WIN__DBZCHK, 5830 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 5831let usesCustomInserter = 1, Defs = [CPSR], hasNoSchedulingInfo = 1 in 5832 def WIN__DBZCHK : PseudoInst<(outs), (ins tGPR:$divisor), NoItinerary, 5833 [(win__dbzchk tGPR:$divisor)]>; 5834 5835//===----------------------------------------------------------------------===// 5836// TLS Instructions 5837// 5838 5839// __aeabi_read_tp preserves the registers r1-r3. 5840// This is a pseudo inst so that we can get the encoding right, 5841// complete with fixup for the aeabi_read_tp function. 5842// TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern 5843// is defined in "ARMInstrThumb.td". 5844let isCall = 1, 5845 Defs = [R0, R12, LR, CPSR], Uses = [SP] in { 5846 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br, 5847 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>, 5848 Requires<[IsARM, IsReadTPSoft]>; 5849} 5850 5851// Reading thread pointer from coprocessor register 5852def : ARMPat<(ARMthread_pointer), (MRC 15, 0, 13, 0, 3)>, 5853 Requires<[IsARM, IsReadTPHard]>; 5854 5855//===----------------------------------------------------------------------===// 5856// SJLJ Exception handling intrinsics 5857// eh_sjlj_setjmp() is an instruction sequence to store the return 5858// address and save #0 in R0 for the non-longjmp case. 5859// Since by its nature we may be coming from some other function to get 5860// here, and we're using the stack frame for the containing function to 5861// save/restore registers, we can't keep anything live in regs across 5862// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 5863// when we get here from a longjmp(). We force everything out of registers 5864// except for our own input by listing the relevant registers in Defs. By 5865// doing so, we also cause the prologue/epilogue code to actively preserve 5866// all of the callee-saved registers, which is exactly what we want. 5867// A constant value is passed in $val, and we use the location as a scratch. 5868// 5869// These are pseudo-instructions and are lowered to individual MC-insts, so 5870// no encoding information is necessary. 5871let Defs = 5872 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 5873 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ], 5874 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5875 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5876 NoItinerary, 5877 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5878 Requires<[IsARM, HasVFP2]>; 5879} 5880 5881let Defs = 5882 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 5883 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5884 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5885 NoItinerary, 5886 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5887 Requires<[IsARM, NoVFP]>; 5888} 5889 5890// FIXME: Non-IOS version(s) 5891let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, 5892 Defs = [ R7, LR, SP ] in { 5893def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch), 5894 NoItinerary, 5895 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 5896 Requires<[IsARM]>; 5897} 5898 5899let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in 5900def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary, 5901 [(ARMeh_sjlj_setup_dispatch)]>; 5902 5903// eh.sjlj.dispatchsetup pseudo-instruction. 5904// This pseudo is used for both ARM and Thumb. Any differences are handled when 5905// the pseudo is expanded (which happens before any passes that need the 5906// instruction size). 5907let isBarrier = 1 in 5908def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>; 5909 5910 5911//===----------------------------------------------------------------------===// 5912// Non-Instruction Patterns 5913// 5914 5915// ARMv4 indirect branch using (MOVr PC, dst) 5916let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in 5917 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst), 5918 4, IIC_Br, [(brind GPR:$dst)], 5919 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5920 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5921 5922let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in 5923 def TAILJMPr4 : ARMPseudoExpand<(outs), (ins GPR:$dst), 5924 4, IIC_Br, [], 5925 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5926 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5927 5928// Large immediate handling. 5929 5930// 32-bit immediate using two piece mod_imms or movw + movt. 5931// This is a single pseudo instruction, the benefit is that it can be remat'd 5932// as a single unit instead of having to handle reg inputs. 5933// FIXME: Remove this when we can do generalized remat. 5934let isReMaterializable = 1, isMoveImm = 1 in 5935def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 5936 [(set GPR:$dst, (arm_i32imm:$src))]>, 5937 Requires<[IsARM]>; 5938 5939def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i, 5940 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>, 5941 Requires<[IsARM, DontUseMovt]>; 5942 5943// Pseudo instruction that combines movw + movt + add pc (if PIC). 5944// It also makes it possible to rematerialize the instructions. 5945// FIXME: Remove this when we can do generalized remat and when machine licm 5946// can properly the instructions. 5947let isReMaterializable = 1 in { 5948def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5949 IIC_iMOVix2addpc, 5950 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 5951 Requires<[IsARM, UseMovtInPic]>; 5952 5953def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5954 IIC_iLoadiALU, 5955 [(set GPR:$dst, 5956 (ARMWrapperPIC tglobaladdr:$addr))]>, 5957 Requires<[IsARM, DontUseMovtInPic]>; 5958 5959let AddedComplexity = 10 in 5960def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5961 NoItinerary, 5962 [(set GPR:$dst, 5963 (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5964 Requires<[IsARM, DontUseMovtInPic]>; 5965 5966let AddedComplexity = 10 in 5967def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5968 IIC_iMOVix2ld, 5969 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5970 Requires<[IsARM, UseMovtInPic]>; 5971} // isReMaterializable 5972 5973// The many different faces of TLS access. 5974def : ARMPat<(ARMWrapper tglobaltlsaddr :$dst), 5975 (MOVi32imm tglobaltlsaddr :$dst)>, 5976 Requires<[IsARM, UseMovt]>; 5977 5978def : Pat<(ARMWrapper tglobaltlsaddr:$src), 5979 (LDRLIT_ga_abs tglobaltlsaddr:$src)>, 5980 Requires<[IsARM, DontUseMovt]>; 5981 5982def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5983 (MOV_ga_pcrel tglobaltlsaddr:$addr)>, Requires<[IsARM, UseMovtInPic]>; 5984 5985def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5986 (LDRLIT_ga_pcrel tglobaltlsaddr:$addr)>, 5987 Requires<[IsARM, DontUseMovtInPic]>; 5988let AddedComplexity = 10 in 5989def : Pat<(load (ARMWrapperPIC tglobaltlsaddr:$addr)), 5990 (MOV_ga_pcrel_ldr tglobaltlsaddr:$addr)>, 5991 Requires<[IsARM, UseMovtInPic]>; 5992 5993 5994// ConstantPool, GlobalAddress, and JumpTable 5995def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 5996def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>, 5997 Requires<[IsARM, UseMovt]>; 5998def : ARMPat<(ARMWrapper texternalsym :$dst), (MOVi32imm texternalsym :$dst)>, 5999 Requires<[IsARM, UseMovt]>; 6000def : ARMPat<(ARMWrapperJT tjumptable:$dst), 6001 (LEApcrelJT tjumptable:$dst)>; 6002 6003// TODO: add,sub,and, 3-instr forms? 6004 6005// Tail calls. These patterns also apply to Thumb mode. 6006def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>; 6007def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>; 6008def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>; 6009 6010// Direct calls 6011def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; 6012def : ARMPat<(ARMcall_nolink texternalsym:$func), 6013 (BMOVPCB_CALL texternalsym:$func)>; 6014 6015// zextload i1 -> zextload i8 6016def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 6017def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 6018 6019// extload -> zextload 6020def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 6021def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 6022def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 6023def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 6024 6025def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 6026 6027def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; 6028def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; 6029 6030// smul* and smla* 6031def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 6032 (SMULBB GPR:$a, GPR:$b)>; 6033def : ARMV5TEPat<(mul sext_16_node:$a, (sext_bottom_16 GPR:$b)), 6034 (SMULBB GPR:$a, GPR:$b)>; 6035def : ARMV5TEPat<(mul sext_16_node:$a, (sext_top_16 GPR:$b)), 6036 (SMULBT GPR:$a, GPR:$b)>; 6037def : ARMV5TEPat<(mul (sext_top_16 GPR:$a), sext_16_node:$b), 6038 (SMULTB GPR:$a, GPR:$b)>; 6039def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, sext_16_node:$b)), 6040 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 6041def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, (sext_bottom_16 GPR:$b))), 6042 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 6043def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, (sext_top_16 GPR:$b))), 6044 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 6045def : ARMV5MOPat<(add GPR:$acc, (mul (sext_top_16 GPR:$a), sext_16_node:$b)), 6046 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 6047 6048def : ARMV5TEPat<(int_arm_smulbb GPR:$a, GPR:$b), 6049 (SMULBB GPR:$a, GPR:$b)>; 6050def : ARMV5TEPat<(int_arm_smulbt GPR:$a, GPR:$b), 6051 (SMULBT GPR:$a, GPR:$b)>; 6052def : ARMV5TEPat<(int_arm_smultb GPR:$a, GPR:$b), 6053 (SMULTB GPR:$a, GPR:$b)>; 6054def : ARMV5TEPat<(int_arm_smultt GPR:$a, GPR:$b), 6055 (SMULTT GPR:$a, GPR:$b)>; 6056def : ARMV5TEPat<(int_arm_smulwb GPR:$a, GPR:$b), 6057 (SMULWB GPR:$a, GPR:$b)>; 6058def : ARMV5TEPat<(int_arm_smulwt GPR:$a, GPR:$b), 6059 (SMULWT GPR:$a, GPR:$b)>; 6060 6061def : ARMV5TEPat<(int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc), 6062 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 6063def : ARMV5TEPat<(int_arm_smlabt GPR:$a, GPR:$b, GPR:$acc), 6064 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 6065def : ARMV5TEPat<(int_arm_smlatb GPR:$a, GPR:$b, GPR:$acc), 6066 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 6067def : ARMV5TEPat<(int_arm_smlatt GPR:$a, GPR:$b, GPR:$acc), 6068 (SMLATT GPR:$a, GPR:$b, GPR:$acc)>; 6069def : ARMV5TEPat<(int_arm_smlawb GPR:$a, GPR:$b, GPR:$acc), 6070 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 6071def : ARMV5TEPat<(int_arm_smlawt GPR:$a, GPR:$b, GPR:$acc), 6072 (SMLAWT GPR:$a, GPR:$b, GPR:$acc)>; 6073 6074// Pre-v7 uses MCR for synchronization barriers. 6075def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>, 6076 Requires<[IsARM, HasV6]>; 6077 6078// SXT/UXT with no rotate 6079let AddedComplexity = 16 in { 6080def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>; 6081def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>; 6082def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>; 6083def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)), 6084 (UXTAB GPR:$Rn, GPR:$Rm, 0)>; 6085def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)), 6086 (UXTAH GPR:$Rn, GPR:$Rm, 0)>; 6087} 6088 6089def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>; 6090def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; 6091 6092def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)), 6093 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>; 6094def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)), 6095 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>; 6096 6097// Atomic load/store patterns 6098def : ARMPat<(atomic_load_8 ldst_so_reg:$src), 6099 (LDRBrs ldst_so_reg:$src)>; 6100def : ARMPat<(atomic_load_8 addrmode_imm12:$src), 6101 (LDRBi12 addrmode_imm12:$src)>; 6102def : ARMPat<(atomic_load_16 addrmode3:$src), 6103 (LDRH addrmode3:$src)>; 6104def : ARMPat<(atomic_load_32 ldst_so_reg:$src), 6105 (LDRrs ldst_so_reg:$src)>; 6106def : ARMPat<(atomic_load_32 addrmode_imm12:$src), 6107 (LDRi12 addrmode_imm12:$src)>; 6108def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val), 6109 (STRBrs GPR:$val, ldst_so_reg:$ptr)>; 6110def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val), 6111 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>; 6112def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val), 6113 (STRH GPR:$val, addrmode3:$ptr)>; 6114def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val), 6115 (STRrs GPR:$val, ldst_so_reg:$ptr)>; 6116def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val), 6117 (STRi12 GPR:$val, addrmode_imm12:$ptr)>; 6118 6119 6120//===----------------------------------------------------------------------===// 6121// Thumb Support 6122// 6123 6124include "ARMInstrThumb.td" 6125 6126//===----------------------------------------------------------------------===// 6127// Thumb2 Support 6128// 6129 6130include "ARMInstrThumb2.td" 6131 6132//===----------------------------------------------------------------------===// 6133// Floating Point Support 6134// 6135 6136include "ARMInstrVFP.td" 6137 6138//===----------------------------------------------------------------------===// 6139// Advanced SIMD (NEON) Support 6140// 6141 6142include "ARMInstrNEON.td" 6143 6144//===----------------------------------------------------------------------===// 6145// MVE Support 6146// 6147 6148include "ARMInstrMVE.td" 6149 6150//===----------------------------------------------------------------------===// 6151// CDE (Custom Datapath Extension) 6152// 6153 6154include "ARMInstrCDE.td" 6155 6156//===----------------------------------------------------------------------===// 6157// Assembler aliases 6158// 6159 6160// Memory barriers 6161def : InstAlias<"dmb", (DMB 0xf), 0>, Requires<[IsARM, HasDB]>; 6162def : InstAlias<"dsb", (DSB 0xf), 0>, Requires<[IsARM, HasDB]>; 6163def : InstAlias<"ssbb", (DSB 0x0), 1>, Requires<[IsARM, HasDB]>; 6164def : InstAlias<"pssbb", (DSB 0x4), 1>, Requires<[IsARM, HasDB]>; 6165def : InstAlias<"isb", (ISB 0xf), 0>, Requires<[IsARM, HasDB]>; 6166// Armv8-R 'Data Full Barrier' 6167def : InstAlias<"dfb", (DSB 0xc), 1>, Requires<[IsARM, HasDFB]>; 6168 6169// System instructions 6170def : MnemonicAlias<"swi", "svc">; 6171 6172// Load / Store Multiple 6173def : MnemonicAlias<"ldmfd", "ldm">; 6174def : MnemonicAlias<"ldmia", "ldm">; 6175def : MnemonicAlias<"ldmea", "ldmdb">; 6176def : MnemonicAlias<"stmfd", "stmdb">; 6177def : MnemonicAlias<"stmia", "stm">; 6178def : MnemonicAlias<"stmea", "stm">; 6179 6180// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the 6181// input operands swapped when the shift amount is zero (i.e., unspecified). 6182def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 6183 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p), 0>, 6184 Requires<[IsARM, HasV6]>; 6185def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 6186 (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p), 0>, 6187 Requires<[IsARM, HasV6]>; 6188 6189// PUSH/POP aliases for STM/LDM 6190def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>; 6191def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>; 6192 6193// SSAT/USAT optional shift operand. 6194def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 6195 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 6196def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn", 6197 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 6198 6199 6200// Extend instruction optional rotate operand. 6201def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm", 6202 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6203def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm", 6204 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6205def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 6206 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6207def : ARMInstAlias<"sxtb${p} $Rd, $Rm", 6208 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6209def : ARMInstAlias<"sxtb16${p} $Rd, $Rm", 6210 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6211def : ARMInstAlias<"sxth${p} $Rd, $Rm", 6212 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6213 6214def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm", 6215 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6216def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm", 6217 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6218def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 6219 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6220def : ARMInstAlias<"uxtb${p} $Rd, $Rm", 6221 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6222def : ARMInstAlias<"uxtb16${p} $Rd, $Rm", 6223 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6224def : ARMInstAlias<"uxth${p} $Rd, $Rm", 6225 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6226 6227 6228// RFE aliases 6229def : MnemonicAlias<"rfefa", "rfeda">; 6230def : MnemonicAlias<"rfeea", "rfedb">; 6231def : MnemonicAlias<"rfefd", "rfeia">; 6232def : MnemonicAlias<"rfeed", "rfeib">; 6233def : MnemonicAlias<"rfe", "rfeia">; 6234 6235// SRS aliases 6236def : MnemonicAlias<"srsfa", "srsib">; 6237def : MnemonicAlias<"srsea", "srsia">; 6238def : MnemonicAlias<"srsfd", "srsdb">; 6239def : MnemonicAlias<"srsed", "srsda">; 6240def : MnemonicAlias<"srs", "srsia">; 6241 6242// QSAX == QSUBADDX 6243def : MnemonicAlias<"qsubaddx", "qsax">; 6244// SASX == SADDSUBX 6245def : MnemonicAlias<"saddsubx", "sasx">; 6246// SHASX == SHADDSUBX 6247def : MnemonicAlias<"shaddsubx", "shasx">; 6248// SHSAX == SHSUBADDX 6249def : MnemonicAlias<"shsubaddx", "shsax">; 6250// SSAX == SSUBADDX 6251def : MnemonicAlias<"ssubaddx", "ssax">; 6252// UASX == UADDSUBX 6253def : MnemonicAlias<"uaddsubx", "uasx">; 6254// UHASX == UHADDSUBX 6255def : MnemonicAlias<"uhaddsubx", "uhasx">; 6256// UHSAX == UHSUBADDX 6257def : MnemonicAlias<"uhsubaddx", "uhsax">; 6258// UQASX == UQADDSUBX 6259def : MnemonicAlias<"uqaddsubx", "uqasx">; 6260// UQSAX == UQSUBADDX 6261def : MnemonicAlias<"uqsubaddx", "uqsax">; 6262// USAX == USUBADDX 6263def : MnemonicAlias<"usubaddx", "usax">; 6264 6265// "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like 6266// for isel. 6267def : ARMInstSubst<"mov${s}${p} $Rd, $imm", 6268 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6269def : ARMInstSubst<"mvn${s}${p} $Rd, $imm", 6270 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6271// Same for AND <--> BIC 6272def : ARMInstSubst<"bic${s}${p} $Rd, $Rn, $imm", 6273 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 6274 pred:$p, cc_out:$s)>; 6275def : ARMInstSubst<"bic${s}${p} $Rdn, $imm", 6276 (ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 6277 pred:$p, cc_out:$s)>; 6278def : ARMInstSubst<"and${s}${p} $Rd, $Rn, $imm", 6279 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 6280 pred:$p, cc_out:$s)>; 6281def : ARMInstSubst<"and${s}${p} $Rdn, $imm", 6282 (BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 6283 pred:$p, cc_out:$s)>; 6284 6285// Likewise, "add Rd, mod_imm_neg" -> sub 6286def : ARMInstSubst<"add${s}${p} $Rd, $Rn, $imm", 6287 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6288def : ARMInstSubst<"add${s}${p} $Rd, $imm", 6289 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6290// Likewise, "sub Rd, mod_imm_neg" -> add 6291def : ARMInstSubst<"sub${s}${p} $Rd, $Rn, $imm", 6292 (ADDri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6293def : ARMInstSubst<"sub${s}${p} $Rd, $imm", 6294 (ADDri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6295 6296 6297def : ARMInstSubst<"adc${s}${p} $Rd, $Rn, $imm", 6298 (SBCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6299def : ARMInstSubst<"adc${s}${p} $Rdn, $imm", 6300 (SBCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6301def : ARMInstSubst<"sbc${s}${p} $Rd, $Rn, $imm", 6302 (ADCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6303def : ARMInstSubst<"sbc${s}${p} $Rdn, $imm", 6304 (ADCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6305 6306// Same for CMP <--> CMN via mod_imm_neg 6307def : ARMInstSubst<"cmp${p} $Rd, $imm", 6308 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 6309def : ARMInstSubst<"cmn${p} $Rd, $imm", 6310 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 6311 6312// The shifter forms of the MOV instruction are aliased to the ASR, LSL, 6313// LSR, ROR, and RRX instructions. 6314// FIXME: We need C++ parser hooks to map the alias to the MOV 6315// encoding. It seems we should be able to do that sort of thing 6316// in tblgen, but it could get ugly. 6317let TwoOperandAliasConstraint = "$Rm = $Rd" in { 6318def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm", 6319 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 6320 cc_out:$s)>; 6321def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm", 6322 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 6323 cc_out:$s)>; 6324def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm", 6325 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 6326 cc_out:$s)>; 6327def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm", 6328 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 6329 cc_out:$s)>; 6330} 6331def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm", 6332 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>; 6333let TwoOperandAliasConstraint = "$Rn = $Rd" in { 6334def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm", 6335 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6336 cc_out:$s)>; 6337def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm", 6338 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6339 cc_out:$s)>; 6340def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm", 6341 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6342 cc_out:$s)>; 6343def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm", 6344 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6345 cc_out:$s)>; 6346} 6347 6348// "neg" is and alias for "rsb rd, rn, #0" 6349def : ARMInstAlias<"neg${s}${p} $Rd, $Rm", 6350 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>; 6351 6352// Pre-v6, 'mov r0, r0' was used as a NOP encoding. 6353def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>, 6354 Requires<[IsARM, NoV6]>; 6355 6356// MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but 6357// the instruction definitions need difference constraints pre-v6. 6358// Use these aliases for the assembly parsing on pre-v6. 6359def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm", 6360 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s), 0>, 6361 Requires<[IsARM, NoV6]>; 6362def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra", 6363 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 6364 pred:$p, cc_out:$s), 0>, 6365 Requires<[IsARM, NoV6]>; 6366def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6367 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6368 Requires<[IsARM, NoV6]>; 6369def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6370 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6371 Requires<[IsARM, NoV6]>; 6372def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6373 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6374 Requires<[IsARM, NoV6]>; 6375def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6376 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6377 Requires<[IsARM, NoV6]>; 6378 6379// 'it' blocks in ARM mode just validate the predicates. The IT itself 6380// is discarded. 6381def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>, 6382 ComplexDeprecationPredicate<"IT">; 6383 6384let mayLoad = 1, mayStore =1, hasSideEffects = 1, hasNoSchedulingInfo = 1 in 6385def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn), 6386 NoItinerary, 6387 [(set GPR:$Rd, (int_arm_space timm:$size, GPR:$Rn))]>; 6388 6389// SpeculationBarrierEndBB must only be used after an unconditional control 6390// flow, i.e. after a terminator for which isBarrier is True. 6391let hasSideEffects = 1, isCodeGenOnly = 1, isTerminator = 1, isBarrier = 1 in { 6392 def SpeculationBarrierISBDSBEndBB 6393 : PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>; 6394 def SpeculationBarrierSBEndBB 6395 : PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>; 6396} 6397 6398//===---------------------------------- 6399// Atomic cmpxchg for -O0 6400//===---------------------------------- 6401 6402// The fast register allocator used during -O0 inserts spills to cover any VRegs 6403// live across basic block boundaries. When this happens between an LDXR and an 6404// STXR it can clear the exclusive monitor, causing all cmpxchg attempts to 6405// fail. 6406 6407// Unfortunately, this means we have to have an alternative (expanded 6408// post-regalloc) path for -O0 compilations. Fortunately this path can be 6409// significantly more naive than the standard expansion: we conservatively 6410// assume seq_cst, strong cmpxchg and omit clrex on failure. 6411 6412let Constraints = "@earlyclobber $Rd,@earlyclobber $temp", 6413 mayLoad = 1, mayStore = 1 in { 6414def CMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6415 (ins GPR:$addr, GPR:$desired, GPR:$new), 6416 NoItinerary, []>, Sched<[]>; 6417 6418def CMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6419 (ins GPR:$addr, GPR:$desired, GPR:$new), 6420 NoItinerary, []>, Sched<[]>; 6421 6422def CMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6423 (ins GPR:$addr, GPR:$desired, GPR:$new), 6424 NoItinerary, []>, Sched<[]>; 6425 6426def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$temp), 6427 (ins GPR:$addr, GPRPair:$desired, GPRPair:$new), 6428 NoItinerary, []>, Sched<[]>; 6429} 6430 6431def CompilerBarrier : PseudoInst<(outs), (ins i32imm:$ordering), NoItinerary, 6432 [(atomic_fence timm:$ordering, 0)]> { 6433 let hasSideEffects = 1; 6434 let Size = 0; 6435 let AsmString = "@ COMPILER BARRIER"; 6436 let hasNoSchedulingInfo = 1; 6437} 6438