1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// ARM specific DAG Nodes. 16// 17 18// Type profiles. 19def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 20def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 21def SDT_ARMStructByVal : SDTypeProfile<0, 4, 22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 24 25def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 26 27def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 28 29def SDT_ARMCMov : SDTypeProfile<1, 3, 30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 31 SDTCisVT<3, i32>]>; 32 33def SDT_ARMBrcond : SDTypeProfile<0, 2, 34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 35 36def SDT_ARMBrJT : SDTypeProfile<0, 2, 37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 38 39def SDT_ARMBr2JT : SDTypeProfile<0, 3, 40 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 41 SDTCisVT<2, i32>]>; 42 43def SDT_ARMBCC_i64 : SDTypeProfile<0, 6, 44 [SDTCisVT<0, i32>, 45 SDTCisVT<1, i32>, SDTCisVT<2, i32>, 46 SDTCisVT<3, i32>, SDTCisVT<4, i32>, 47 SDTCisVT<5, OtherVT>]>; 48 49def SDT_ARMAnd : SDTypeProfile<1, 2, 50 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 51 SDTCisVT<2, i32>]>; 52 53def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 54 55def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 56 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 57 58def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 59def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, 60 SDTCisInt<2>]>; 61def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 62def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>; 63 64def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 65 66def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, 67 SDTCisInt<1>]>; 68 69def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 70 71def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 73 74def SDT_WIN__DBZCHK : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 75 76def SDT_ARMMEMCPY : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 77 SDTCisVT<2, i32>, SDTCisVT<3, i32>, 78 SDTCisVT<4, i32>]>; 79 80def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 81 [SDTCisSameAs<0, 2>, 82 SDTCisSameAs<0, 3>, 83 SDTCisInt<0>, SDTCisVT<1, i32>]>; 84 85// SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR 86def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 87 [SDTCisSameAs<0, 2>, 88 SDTCisSameAs<0, 3>, 89 SDTCisInt<0>, 90 SDTCisVT<1, i32>, 91 SDTCisVT<4, i32>]>; 92 93def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>, 94 SDTCisVT<2, i32>, SDTCisVT<3, i32>, 95 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >; 96def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>; 97def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>; 98 99// Node definitions. 100def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 101def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>; 102def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>; 103 104def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 105 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 106def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 107 [SDNPHasChain, SDNPSideEffect, 108 SDNPOptInGlue, SDNPOutGlue]>; 109def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" , 110 SDT_ARMStructByVal, 111 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 112 SDNPMayStore, SDNPMayLoad]>; 113 114def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 116 SDNPVariadic]>; 117def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 119 SDNPVariadic]>; 120def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 121 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 122 SDNPVariadic]>; 123 124def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, 125 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 126def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall, 127 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 128def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 129 [SDNPInGlue]>; 130 131def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 132 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 133 134def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 135 [SDNPHasChain]>; 136def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, 137 [SDNPHasChain]>; 138 139def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64, 140 [SDNPHasChain]>; 141 142def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 143 [SDNPOutGlue]>; 144 145def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp, 146 [SDNPOutGlue]>; 147 148def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, 149 [SDNPOutGlue, SDNPCommutative]>; 150 151def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 152 153def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 154def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 155def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>; 156 157def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags, 158 [SDNPCommutative]>; 159def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>; 160def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>; 161def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>; 162 163def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 164def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", 165 SDT_ARMEH_SJLJ_Setjmp, 166 [SDNPHasChain, SDNPSideEffect]>; 167def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP", 168 SDT_ARMEH_SJLJ_Longjmp, 169 [SDNPHasChain, SDNPSideEffect]>; 170def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH", 171 SDT_ARMEH_SJLJ_SetupDispatch, 172 [SDNPHasChain, SDNPSideEffect]>; 173 174def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER, 175 [SDNPHasChain, SDNPSideEffect]>; 176def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH, 177 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 178 179def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET, 180 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 181 182def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; 183 184def ARMmemcopy : SDNode<"ARMISD::MEMCPY", SDT_ARMMEMCPY, 185 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 186 SDNPMayStore, SDNPMayLoad]>; 187 188//===----------------------------------------------------------------------===// 189// ARM Instruction Predicate Definitions. 190// 191def HasV4T : Predicate<"Subtarget->hasV4TOps()">, 192 AssemblerPredicate<"HasV4TOps", "armv4t">; 193def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; 194def HasV5T : Predicate<"Subtarget->hasV5TOps()">, 195 AssemblerPredicate<"HasV5TOps", "armv5t">; 196def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, 197 AssemblerPredicate<"HasV5TEOps", "armv5te">; 198def HasV6 : Predicate<"Subtarget->hasV6Ops()">, 199 AssemblerPredicate<"HasV6Ops", "armv6">; 200def NoV6 : Predicate<"!Subtarget->hasV6Ops()">; 201def HasV6M : Predicate<"Subtarget->hasV6MOps()">, 202 AssemblerPredicate<"HasV6MOps", 203 "armv6m or armv6t2">; 204def HasV8MBaseline : Predicate<"Subtarget->hasV8MBaselineOps()">, 205 AssemblerPredicate<"HasV8MBaselineOps", 206 "armv8m.base">; 207def HasV8MMainline : Predicate<"Subtarget->hasV8MMainlineOps()">, 208 AssemblerPredicate<"HasV8MMainlineOps", 209 "armv8m.main">; 210def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, 211 AssemblerPredicate<"HasV6T2Ops", "armv6t2">; 212def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; 213def HasV6K : Predicate<"Subtarget->hasV6KOps()">, 214 AssemblerPredicate<"HasV6KOps", "armv6k">; 215def NoV6K : Predicate<"!Subtarget->hasV6KOps()">; 216def HasV7 : Predicate<"Subtarget->hasV7Ops()">, 217 AssemblerPredicate<"HasV7Ops", "armv7">; 218def HasV8 : Predicate<"Subtarget->hasV8Ops()">, 219 AssemblerPredicate<"HasV8Ops", "armv8">; 220def PreV8 : Predicate<"!Subtarget->hasV8Ops()">, 221 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">; 222def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">, 223 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">; 224def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">, 225 AssemblerPredicate<"HasV8_2aOps", "armv8.2a">; 226def NoVFP : Predicate<"!Subtarget->hasVFP2()">; 227def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, 228 AssemblerPredicate<"FeatureVFP2", "VFP2">; 229def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, 230 AssemblerPredicate<"FeatureVFP3", "VFP3">; 231def HasVFP4 : Predicate<"Subtarget->hasVFP4()">, 232 AssemblerPredicate<"FeatureVFP4", "VFP4">; 233def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">, 234 AssemblerPredicate<"!FeatureVFPOnlySP", 235 "double precision VFP">; 236def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, 237 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">; 238def HasNEON : Predicate<"Subtarget->hasNEON()">, 239 AssemblerPredicate<"FeatureNEON", "NEON">; 240def HasCrypto : Predicate<"Subtarget->hasCrypto()">, 241 AssemblerPredicate<"FeatureCrypto", "crypto">; 242def HasCRC : Predicate<"Subtarget->hasCRC()">, 243 AssemblerPredicate<"FeatureCRC", "crc">; 244def HasFP16 : Predicate<"Subtarget->hasFP16()">, 245 AssemblerPredicate<"FeatureFP16","half-float conversions">; 246def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">, 247 AssemblerPredicate<"FeatureFullFP16","full half-float">; 248def HasDivide : Predicate<"Subtarget->hasDivide()">, 249 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">; 250def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">, 251 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">; 252def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">, 253 AssemblerPredicate<"FeatureT2XtPk", 254 "pack/extract">; 255def HasDSP : Predicate<"Subtarget->hasDSP()">, 256 AssemblerPredicate<"FeatureDSP", "dsp">; 257def HasDB : Predicate<"Subtarget->hasDataBarrier()">, 258 AssemblerPredicate<"FeatureDB", 259 "data-barriers">; 260def HasV7Clrex : Predicate<"Subtarget->hasV7Clrex()">, 261 AssemblerPredicate<"FeatureV7Clrex", 262 "v7 clrex">; 263def HasAcquireRelease : Predicate<"Subtarget->hasAcquireRelease()">, 264 AssemblerPredicate<"FeatureAcquireRelease", 265 "acquire/release">; 266def HasMP : Predicate<"Subtarget->hasMPExtension()">, 267 AssemblerPredicate<"FeatureMP", 268 "mp-extensions">; 269def HasVirtualization: Predicate<"false">, 270 AssemblerPredicate<"FeatureVirtualization", 271 "virtualization-extensions">; 272def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">, 273 AssemblerPredicate<"FeatureTrustZone", 274 "TrustZone">; 275def Has8MSecExt : Predicate<"Subtarget->has8MSecExt()">, 276 AssemblerPredicate<"Feature8MSecExt", 277 "ARMv8-M Security Extensions">; 278def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">; 279def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; 280def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; 281def IsThumb : Predicate<"Subtarget->isThumb()">, 282 AssemblerPredicate<"ModeThumb", "thumb">; 283def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; 284def IsThumb2 : Predicate<"Subtarget->isThumb2()">, 285 AssemblerPredicate<"ModeThumb,FeatureThumb2", 286 "thumb2">; 287def IsMClass : Predicate<"Subtarget->isMClass()">, 288 AssemblerPredicate<"FeatureMClass", "armv*m">; 289def IsNotMClass : Predicate<"!Subtarget->isMClass()">, 290 AssemblerPredicate<"!FeatureMClass", 291 "!armv*m">; 292def IsARM : Predicate<"!Subtarget->isThumb()">, 293 AssemblerPredicate<"!ModeThumb", "arm-mode">; 294def IsMachO : Predicate<"Subtarget->isTargetMachO()">; 295def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">; 296def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 297def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">, 298 AssemblerPredicate<"FeatureNaClTrap", "NaCl">; 299def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">; 300 301// FIXME: Eventually this will be just "hasV6T2Ops". 302def UseMovt : Predicate<"Subtarget->useMovt(*MF)">; 303def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">; 304def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">; 305def UseMulOps : Predicate<"Subtarget->useMulOps()">; 306 307// Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available. 308// But only select them if more precision in FP computation is allowed. 309// Do not use them for Darwin platforms. 310def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion ==" 311 " FPOpFusion::Fast && " 312 " Subtarget->hasVFP4()) && " 313 "!Subtarget->isTargetDarwin()">; 314def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion ==" 315 " FPOpFusion::Fast &&" 316 " Subtarget->hasVFP4()) || " 317 "Subtarget->isTargetDarwin()">; 318 319// VGETLNi32 is microcoded on Swift - prefer VMOV. 320def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">; 321def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">; 322 323// VDUP.32 is microcoded on Swift - prefer VMOV. 324def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">; 325def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">; 326 327// Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as 328// this allows more effective execution domain optimization. See 329// setExecutionDomain(). 330def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">; 331def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">; 332 333def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">; 334def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">; 335 336//===----------------------------------------------------------------------===// 337// ARM Flag Definitions. 338 339class RegConstraint<string C> { 340 string Constraints = C; 341} 342 343//===----------------------------------------------------------------------===// 344// ARM specific transformation functions and pattern fragments. 345// 346 347// imm_neg_XFORM - Return the negation of an i32 immediate value. 348def imm_neg_XFORM : SDNodeXForm<imm, [{ 349 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32); 350}]>; 351 352// imm_not_XFORM - Return the complement of a i32 immediate value. 353def imm_not_XFORM : SDNodeXForm<imm, [{ 354 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32); 355}]>; 356 357/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 358def imm16_31 : ImmLeaf<i32, [{ 359 return (int32_t)Imm >= 16 && (int32_t)Imm < 32; 360}]>; 361 362// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 363def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 364 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; 365}]>; 366 367/// Split a 32-bit immediate into two 16 bit parts. 368def hi16 : SDNodeXForm<imm, [{ 369 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N), 370 MVT::i32); 371}]>; 372 373def lo16AllZero : PatLeaf<(i32 imm), [{ 374 // Returns true if all low 16-bits are 0. 375 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 376}], hi16>; 377 378class BinOpWithFlagFrag<dag res> : 379 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>; 380class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 381class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 382 383// An 'and' node with a single use. 384def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 385 return N->hasOneUse(); 386}]>; 387 388// An 'xor' node with a single use. 389def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{ 390 return N->hasOneUse(); 391}]>; 392 393// An 'fmul' node with a single use. 394def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{ 395 return N->hasOneUse(); 396}]>; 397 398// An 'fadd' node which checks for single non-hazardous use. 399def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{ 400 return hasNoVMLxHazardUse(N); 401}]>; 402 403// An 'fsub' node which checks for single non-hazardous use. 404def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{ 405 return hasNoVMLxHazardUse(N); 406}]>; 407 408//===----------------------------------------------------------------------===// 409// Operand Definitions. 410// 411 412// Immediate operands with a shared generic asm render method. 413class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; } 414 415// Operands that are part of a memory addressing mode. 416class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; } 417 418// Branch target. 419// FIXME: rename brtarget to t2_brtarget 420def brtarget : Operand<OtherVT> { 421 let EncoderMethod = "getBranchTargetOpValue"; 422 let OperandType = "OPERAND_PCREL"; 423 let DecoderMethod = "DecodeT2BROperand"; 424} 425 426// FIXME: get rid of this one? 427def uncondbrtarget : Operand<OtherVT> { 428 let EncoderMethod = "getUnconditionalBranchTargetOpValue"; 429 let OperandType = "OPERAND_PCREL"; 430} 431 432// Branch target for ARM. Handles conditional/unconditional 433def br_target : Operand<OtherVT> { 434 let EncoderMethod = "getARMBranchTargetOpValue"; 435 let OperandType = "OPERAND_PCREL"; 436} 437 438// Call target. 439// FIXME: rename bltarget to t2_bl_target? 440def bltarget : Operand<i32> { 441 // Encoded the same as branch targets. 442 let EncoderMethod = "getBranchTargetOpValue"; 443 let OperandType = "OPERAND_PCREL"; 444} 445 446// Call target for ARM. Handles conditional/unconditional 447// FIXME: rename bl_target to t2_bltarget? 448def bl_target : Operand<i32> { 449 let EncoderMethod = "getARMBLTargetOpValue"; 450 let OperandType = "OPERAND_PCREL"; 451} 452 453def blx_target : Operand<i32> { 454 let EncoderMethod = "getARMBLXTargetOpValue"; 455 let OperandType = "OPERAND_PCREL"; 456} 457 458// A list of registers separated by comma. Used by load/store multiple. 459def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; } 460def reglist : Operand<i32> { 461 let EncoderMethod = "getRegisterListOpValue"; 462 let ParserMatchClass = RegListAsmOperand; 463 let PrintMethod = "printRegisterList"; 464 let DecoderMethod = "DecodeRegListOperand"; 465} 466 467def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">; 468 469def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; } 470def dpr_reglist : Operand<i32> { 471 let EncoderMethod = "getRegisterListOpValue"; 472 let ParserMatchClass = DPRRegListAsmOperand; 473 let PrintMethod = "printRegisterList"; 474 let DecoderMethod = "DecodeDPRRegListOperand"; 475} 476 477def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; } 478def spr_reglist : Operand<i32> { 479 let EncoderMethod = "getRegisterListOpValue"; 480 let ParserMatchClass = SPRRegListAsmOperand; 481 let PrintMethod = "printRegisterList"; 482 let DecoderMethod = "DecodeSPRRegListOperand"; 483} 484 485// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 486def cpinst_operand : Operand<i32> { 487 let PrintMethod = "printCPInstOperand"; 488} 489 490// Local PC labels. 491def pclabel : Operand<i32> { 492 let PrintMethod = "printPCLabel"; 493} 494 495// ADR instruction labels. 496def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; } 497def adrlabel : Operand<i32> { 498 let EncoderMethod = "getAdrLabelOpValue"; 499 let ParserMatchClass = AdrLabelAsmOperand; 500 let PrintMethod = "printAdrLabelOperand<0>"; 501} 502 503def neon_vcvt_imm32 : Operand<i32> { 504 let EncoderMethod = "getNEONVcvtImm32OpValue"; 505 let DecoderMethod = "DecodeVCVTImmOperand"; 506} 507 508// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. 509def rot_imm_XFORM: SDNodeXForm<imm, [{ 510 switch (N->getZExtValue()){ 511 default: llvm_unreachable(nullptr); 512 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); 513 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32); 514 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32); 515 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32); 516 } 517}]>; 518def RotImmAsmOperand : AsmOperandClass { 519 let Name = "RotImm"; 520 let ParserMethod = "parseRotImm"; 521} 522def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{ 523 int32_t v = N->getZExtValue(); 524 return v == 8 || v == 16 || v == 24; }], 525 rot_imm_XFORM> { 526 let PrintMethod = "printRotImmOperand"; 527 let ParserMatchClass = RotImmAsmOperand; 528} 529 530// shift_imm: An integer that encodes a shift amount and the type of shift 531// (asr or lsl). The 6-bit immediate encodes as: 532// {5} 0 ==> lsl 533// 1 asr 534// {4-0} imm5 shift amount. 535// asr #32 encoded as imm5 == 0. 536def ShifterImmAsmOperand : AsmOperandClass { 537 let Name = "ShifterImm"; 538 let ParserMethod = "parseShifterImm"; 539} 540def shift_imm : Operand<i32> { 541 let PrintMethod = "printShiftImmOperand"; 542 let ParserMatchClass = ShifterImmAsmOperand; 543} 544 545// shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm. 546def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; } 547def so_reg_reg : Operand<i32>, // reg reg imm 548 ComplexPattern<i32, 3, "SelectRegShifterOperand", 549 [shl, srl, sra, rotr]> { 550 let EncoderMethod = "getSORegRegOpValue"; 551 let PrintMethod = "printSORegRegOperand"; 552 let DecoderMethod = "DecodeSORegRegOperand"; 553 let ParserMatchClass = ShiftedRegAsmOperand; 554 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm); 555} 556 557def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; } 558def so_reg_imm : Operand<i32>, // reg imm 559 ComplexPattern<i32, 2, "SelectImmShifterOperand", 560 [shl, srl, sra, rotr]> { 561 let EncoderMethod = "getSORegImmOpValue"; 562 let PrintMethod = "printSORegImmOperand"; 563 let DecoderMethod = "DecodeSORegImmOperand"; 564 let ParserMatchClass = ShiftedImmAsmOperand; 565 let MIOperandInfo = (ops GPR, i32imm); 566} 567 568// FIXME: Does this need to be distinct from so_reg? 569def shift_so_reg_reg : Operand<i32>, // reg reg imm 570 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand", 571 [shl,srl,sra,rotr]> { 572 let EncoderMethod = "getSORegRegOpValue"; 573 let PrintMethod = "printSORegRegOperand"; 574 let DecoderMethod = "DecodeSORegRegOperand"; 575 let ParserMatchClass = ShiftedRegAsmOperand; 576 let MIOperandInfo = (ops GPR, GPR, i32imm); 577} 578 579// FIXME: Does this need to be distinct from so_reg? 580def shift_so_reg_imm : Operand<i32>, // reg reg imm 581 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand", 582 [shl,srl,sra,rotr]> { 583 let EncoderMethod = "getSORegImmOpValue"; 584 let PrintMethod = "printSORegImmOperand"; 585 let DecoderMethod = "DecodeSORegImmOperand"; 586 let ParserMatchClass = ShiftedImmAsmOperand; 587 let MIOperandInfo = (ops GPR, i32imm); 588} 589 590// mod_imm: match a 32-bit immediate operand, which can be encoded into 591// a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM 592// - "Modified Immediate Constants"). Within the MC layer we keep this 593// immediate in its encoded form. 594def ModImmAsmOperand: AsmOperandClass { 595 let Name = "ModImm"; 596 let ParserMethod = "parseModImm"; 597} 598def mod_imm : Operand<i32>, ImmLeaf<i32, [{ 599 return ARM_AM::getSOImmVal(Imm) != -1; 600 }]> { 601 let EncoderMethod = "getModImmOpValue"; 602 let PrintMethod = "printModImmOperand"; 603 let ParserMatchClass = ModImmAsmOperand; 604} 605 606// Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder 607// method and such, as they are only used on aliases (Pat<> and InstAlias<>). 608// The actual parsing, encoding, decoding are handled by the destination 609// instructions, which use mod_imm. 610 611def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; } 612def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{ 613 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1; 614 }], imm_not_XFORM> { 615 let ParserMatchClass = ModImmNotAsmOperand; 616} 617 618def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; } 619def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{ 620 unsigned Value = -(unsigned)N->getZExtValue(); 621 return Value && ARM_AM::getSOImmVal(Value) != -1; 622 }], imm_neg_XFORM> { 623 let ParserMatchClass = ModImmNegAsmOperand; 624} 625 626/// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal() 627def arm_i32imm : PatLeaf<(imm), [{ 628 if (Subtarget->useMovt(*MF)) 629 return true; 630 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 631}]>; 632 633/// imm0_1 predicate - Immediate in the range [0,1]. 634def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; } 635def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; } 636 637/// imm0_3 predicate - Immediate in the range [0,3]. 638def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; } 639def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; } 640 641/// imm0_7 predicate - Immediate in the range [0,7]. 642def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; } 643def imm0_7 : Operand<i32>, ImmLeaf<i32, [{ 644 return Imm >= 0 && Imm < 8; 645}]> { 646 let ParserMatchClass = Imm0_7AsmOperand; 647} 648 649/// imm8 predicate - Immediate is exactly 8. 650def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; } 651def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> { 652 let ParserMatchClass = Imm8AsmOperand; 653} 654 655/// imm16 predicate - Immediate is exactly 16. 656def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; } 657def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> { 658 let ParserMatchClass = Imm16AsmOperand; 659} 660 661/// imm32 predicate - Immediate is exactly 32. 662def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; } 663def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> { 664 let ParserMatchClass = Imm32AsmOperand; 665} 666 667def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>; 668 669/// imm1_7 predicate - Immediate in the range [1,7]. 670def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; } 671def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> { 672 let ParserMatchClass = Imm1_7AsmOperand; 673} 674 675/// imm1_15 predicate - Immediate in the range [1,15]. 676def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; } 677def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> { 678 let ParserMatchClass = Imm1_15AsmOperand; 679} 680 681/// imm1_31 predicate - Immediate in the range [1,31]. 682def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; } 683def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> { 684 let ParserMatchClass = Imm1_31AsmOperand; 685} 686 687/// imm0_15 predicate - Immediate in the range [0,15]. 688def Imm0_15AsmOperand: ImmAsmOperand { 689 let Name = "Imm0_15"; 690 let DiagnosticType = "ImmRange0_15"; 691} 692def imm0_15 : Operand<i32>, ImmLeaf<i32, [{ 693 return Imm >= 0 && Imm < 16; 694}]> { 695 let ParserMatchClass = Imm0_15AsmOperand; 696} 697 698/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31]. 699def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; } 700def imm0_31 : Operand<i32>, ImmLeaf<i32, [{ 701 return Imm >= 0 && Imm < 32; 702}]> { 703 let ParserMatchClass = Imm0_31AsmOperand; 704} 705 706/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32]. 707def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; } 708def imm0_32 : Operand<i32>, ImmLeaf<i32, [{ 709 return Imm >= 0 && Imm < 32; 710}]> { 711 let ParserMatchClass = Imm0_32AsmOperand; 712} 713 714/// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63]. 715def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; } 716def imm0_63 : Operand<i32>, ImmLeaf<i32, [{ 717 return Imm >= 0 && Imm < 64; 718}]> { 719 let ParserMatchClass = Imm0_63AsmOperand; 720} 721 722/// imm0_239 predicate - Immediate in the range [0,239]. 723def Imm0_239AsmOperand : ImmAsmOperand { 724 let Name = "Imm0_239"; 725 let DiagnosticType = "ImmRange0_239"; 726} 727def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> { 728 let ParserMatchClass = Imm0_239AsmOperand; 729} 730 731/// imm0_255 predicate - Immediate in the range [0,255]. 732def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; } 733def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> { 734 let ParserMatchClass = Imm0_255AsmOperand; 735} 736 737/// imm0_65535 - An immediate is in the range [0.65535]. 738def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; } 739def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{ 740 return Imm >= 0 && Imm < 65536; 741}]> { 742 let ParserMatchClass = Imm0_65535AsmOperand; 743} 744 745// imm0_65535_neg - An immediate whose negative value is in the range [0.65535]. 746def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{ 747 return -Imm >= 0 && -Imm < 65536; 748}]>; 749 750// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference 751// a relocatable expression. 752// 753// FIXME: This really needs a Thumb version separate from the ARM version. 754// While the range is the same, and can thus use the same match class, 755// the encoding is different so it should have a different encoder method. 756def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; } 757def imm0_65535_expr : Operand<i32> { 758 let EncoderMethod = "getHiLo16ImmOpValue"; 759 let ParserMatchClass = Imm0_65535ExprAsmOperand; 760} 761 762def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; } 763def imm256_65535_expr : Operand<i32> { 764 let ParserMatchClass = Imm256_65535ExprAsmOperand; 765} 766 767/// imm24b - True if the 32-bit immediate is encodable in 24 bits. 768def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; } 769def imm24b : Operand<i32>, ImmLeaf<i32, [{ 770 return Imm >= 0 && Imm <= 0xffffff; 771}]> { 772 let ParserMatchClass = Imm24bitAsmOperand; 773} 774 775 776/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield 777/// e.g., 0xf000ffff 778def BitfieldAsmOperand : AsmOperandClass { 779 let Name = "Bitfield"; 780 let ParserMethod = "parseBitfield"; 781} 782 783def bf_inv_mask_imm : Operand<i32>, 784 PatLeaf<(imm), [{ 785 return ARM::isBitFieldInvertedMask(N->getZExtValue()); 786}] > { 787 let EncoderMethod = "getBitfieldInvertedMaskOpValue"; 788 let PrintMethod = "printBitfieldInvMaskImmOperand"; 789 let DecoderMethod = "DecodeBitfieldMaskOperand"; 790 let ParserMatchClass = BitfieldAsmOperand; 791} 792 793def imm1_32_XFORM: SDNodeXForm<imm, [{ 794 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 795 MVT::i32); 796}]>; 797def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; } 798def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ 799 uint64_t Imm = N->getZExtValue(); 800 return Imm > 0 && Imm <= 32; 801 }], 802 imm1_32_XFORM> { 803 let PrintMethod = "printImmPlusOneOperand"; 804 let ParserMatchClass = Imm1_32AsmOperand; 805} 806 807def imm1_16_XFORM: SDNodeXForm<imm, [{ 808 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 809 MVT::i32); 810}]>; 811def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; } 812def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }], 813 imm1_16_XFORM> { 814 let PrintMethod = "printImmPlusOneOperand"; 815 let ParserMatchClass = Imm1_16AsmOperand; 816} 817 818// Define ARM specific addressing modes. 819// addrmode_imm12 := reg +/- imm12 820// 821def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; } 822class AddrMode_Imm12 : MemOperand, 823 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> { 824 // 12-bit immediate operand. Note that instructions using this encode 825 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other 826 // immediate values are as normal. 827 828 let EncoderMethod = "getAddrModeImm12OpValue"; 829 let DecoderMethod = "DecodeAddrModeImm12Operand"; 830 let ParserMatchClass = MemImm12OffsetAsmOperand; 831 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 832} 833 834def addrmode_imm12 : AddrMode_Imm12 { 835 let PrintMethod = "printAddrModeImm12Operand<false>"; 836} 837 838def addrmode_imm12_pre : AddrMode_Imm12 { 839 let PrintMethod = "printAddrModeImm12Operand<true>"; 840} 841 842// ldst_so_reg := reg +/- reg shop imm 843// 844def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; } 845def ldst_so_reg : MemOperand, 846 ComplexPattern<i32, 3, "SelectLdStSOReg", []> { 847 let EncoderMethod = "getLdStSORegOpValue"; 848 // FIXME: Simplify the printer 849 let PrintMethod = "printAddrMode2Operand"; 850 let DecoderMethod = "DecodeSORegMemOperand"; 851 let ParserMatchClass = MemRegOffsetAsmOperand; 852 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift); 853} 854 855// postidx_imm8 := +/- [0,255] 856// 857// 9 bit value: 858// {8} 1 is imm8 is non-negative. 0 otherwise. 859// {7-0} [0,255] imm8 value. 860def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; } 861def postidx_imm8 : MemOperand { 862 let PrintMethod = "printPostIdxImm8Operand"; 863 let ParserMatchClass = PostIdxImm8AsmOperand; 864 let MIOperandInfo = (ops i32imm); 865} 866 867// postidx_imm8s4 := +/- [0,1020] 868// 869// 9 bit value: 870// {8} 1 is imm8 is non-negative. 0 otherwise. 871// {7-0} [0,255] imm8 value, scaled by 4. 872def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; } 873def postidx_imm8s4 : MemOperand { 874 let PrintMethod = "printPostIdxImm8s4Operand"; 875 let ParserMatchClass = PostIdxImm8s4AsmOperand; 876 let MIOperandInfo = (ops i32imm); 877} 878 879 880// postidx_reg := +/- reg 881// 882def PostIdxRegAsmOperand : AsmOperandClass { 883 let Name = "PostIdxReg"; 884 let ParserMethod = "parsePostIdxReg"; 885} 886def postidx_reg : MemOperand { 887 let EncoderMethod = "getPostIdxRegOpValue"; 888 let DecoderMethod = "DecodePostIdxReg"; 889 let PrintMethod = "printPostIdxRegOperand"; 890 let ParserMatchClass = PostIdxRegAsmOperand; 891 let MIOperandInfo = (ops GPRnopc, i32imm); 892} 893 894 895// addrmode2 := reg +/- imm12 896// := reg +/- reg shop imm 897// 898// FIXME: addrmode2 should be refactored the rest of the way to always 899// use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg). 900def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; } 901def addrmode2 : MemOperand, 902 ComplexPattern<i32, 3, "SelectAddrMode2", []> { 903 let EncoderMethod = "getAddrMode2OpValue"; 904 let PrintMethod = "printAddrMode2Operand"; 905 let ParserMatchClass = AddrMode2AsmOperand; 906 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 907} 908 909def PostIdxRegShiftedAsmOperand : AsmOperandClass { 910 let Name = "PostIdxRegShifted"; 911 let ParserMethod = "parsePostIdxReg"; 912} 913def am2offset_reg : MemOperand, 914 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg", 915 [], [SDNPWantRoot]> { 916 let EncoderMethod = "getAddrMode2OffsetOpValue"; 917 let PrintMethod = "printAddrMode2OffsetOperand"; 918 // When using this for assembly, it's always as a post-index offset. 919 let ParserMatchClass = PostIdxRegShiftedAsmOperand; 920 let MIOperandInfo = (ops GPRnopc, i32imm); 921} 922 923// FIXME: am2offset_imm should only need the immediate, not the GPR. Having 924// the GPR is purely vestigal at this point. 925def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; } 926def am2offset_imm : MemOperand, 927 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm", 928 [], [SDNPWantRoot]> { 929 let EncoderMethod = "getAddrMode2OffsetOpValue"; 930 let PrintMethod = "printAddrMode2OffsetOperand"; 931 let ParserMatchClass = AM2OffsetImmAsmOperand; 932 let MIOperandInfo = (ops GPRnopc, i32imm); 933} 934 935 936// addrmode3 := reg +/- reg 937// addrmode3 := reg +/- imm8 938// 939// FIXME: split into imm vs. reg versions. 940def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; } 941class AddrMode3 : MemOperand, 942 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 943 let EncoderMethod = "getAddrMode3OpValue"; 944 let ParserMatchClass = AddrMode3AsmOperand; 945 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 946} 947 948def addrmode3 : AddrMode3 949{ 950 let PrintMethod = "printAddrMode3Operand<false>"; 951} 952 953def addrmode3_pre : AddrMode3 954{ 955 let PrintMethod = "printAddrMode3Operand<true>"; 956} 957 958// FIXME: split into imm vs. reg versions. 959// FIXME: parser method to handle +/- register. 960def AM3OffsetAsmOperand : AsmOperandClass { 961 let Name = "AM3Offset"; 962 let ParserMethod = "parseAM3Offset"; 963} 964def am3offset : MemOperand, 965 ComplexPattern<i32, 2, "SelectAddrMode3Offset", 966 [], [SDNPWantRoot]> { 967 let EncoderMethod = "getAddrMode3OffsetOpValue"; 968 let PrintMethod = "printAddrMode3OffsetOperand"; 969 let ParserMatchClass = AM3OffsetAsmOperand; 970 let MIOperandInfo = (ops GPR, i32imm); 971} 972 973// ldstm_mode := {ia, ib, da, db} 974// 975def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> { 976 let EncoderMethod = "getLdStmModeOpValue"; 977 let PrintMethod = "printLdStmModeOperand"; 978} 979 980// addrmode5 := reg +/- imm8*4 981// 982def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; } 983class AddrMode5 : MemOperand, 984 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 985 let EncoderMethod = "getAddrMode5OpValue"; 986 let DecoderMethod = "DecodeAddrMode5Operand"; 987 let ParserMatchClass = AddrMode5AsmOperand; 988 let MIOperandInfo = (ops GPR:$base, i32imm); 989} 990 991def addrmode5 : AddrMode5 { 992 let PrintMethod = "printAddrMode5Operand<false>"; 993} 994 995def addrmode5_pre : AddrMode5 { 996 let PrintMethod = "printAddrMode5Operand<true>"; 997} 998 999// addrmode5fp16 := reg +/- imm8*2 1000// 1001def AddrMode5FP16AsmOperand : AsmOperandClass { let Name = "AddrMode5FP16"; } 1002class AddrMode5FP16 : Operand<i32>, 1003 ComplexPattern<i32, 2, "SelectAddrMode5FP16", []> { 1004 let EncoderMethod = "getAddrMode5FP16OpValue"; 1005 let DecoderMethod = "DecodeAddrMode5FP16Operand"; 1006 let ParserMatchClass = AddrMode5FP16AsmOperand; 1007 let MIOperandInfo = (ops GPR:$base, i32imm); 1008} 1009 1010def addrmode5fp16 : AddrMode5FP16 { 1011 let PrintMethod = "printAddrMode5FP16Operand<false>"; 1012} 1013 1014// addrmode6 := reg with optional alignment 1015// 1016def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; } 1017def addrmode6 : MemOperand, 1018 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1019 let PrintMethod = "printAddrMode6Operand"; 1020 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1021 let EncoderMethod = "getAddrMode6AddressOpValue"; 1022 let DecoderMethod = "DecodeAddrMode6Operand"; 1023 let ParserMatchClass = AddrMode6AsmOperand; 1024} 1025 1026def am6offset : MemOperand, 1027 ComplexPattern<i32, 1, "SelectAddrMode6Offset", 1028 [], [SDNPWantRoot]> { 1029 let PrintMethod = "printAddrMode6OffsetOperand"; 1030 let MIOperandInfo = (ops GPR); 1031 let EncoderMethod = "getAddrMode6OffsetOpValue"; 1032 let DecoderMethod = "DecodeGPRRegisterClass"; 1033} 1034 1035// Special version of addrmode6 to handle alignment encoding for VST1/VLD1 1036// (single element from one lane) for size 32. 1037def addrmode6oneL32 : MemOperand, 1038 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1039 let PrintMethod = "printAddrMode6Operand"; 1040 let MIOperandInfo = (ops GPR:$addr, i32imm); 1041 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue"; 1042} 1043 1044// Base class for addrmode6 with specific alignment restrictions. 1045class AddrMode6Align : MemOperand, 1046 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1047 let PrintMethod = "printAddrMode6Operand"; 1048 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1049 let EncoderMethod = "getAddrMode6AddressOpValue"; 1050 let DecoderMethod = "DecodeAddrMode6Operand"; 1051} 1052 1053// Special version of addrmode6 to handle no allowed alignment encoding for 1054// VLD/VST instructions and checking the alignment is not specified. 1055def AddrMode6AlignNoneAsmOperand : AsmOperandClass { 1056 let Name = "AlignedMemoryNone"; 1057 let DiagnosticType = "AlignedMemoryRequiresNone"; 1058} 1059def addrmode6alignNone : AddrMode6Align { 1060 // The alignment specifier can only be omitted. 1061 let ParserMatchClass = AddrMode6AlignNoneAsmOperand; 1062} 1063 1064// Special version of addrmode6 to handle 16-bit alignment encoding for 1065// VLD/VST instructions and checking the alignment value. 1066def AddrMode6Align16AsmOperand : AsmOperandClass { 1067 let Name = "AlignedMemory16"; 1068 let DiagnosticType = "AlignedMemoryRequires16"; 1069} 1070def addrmode6align16 : AddrMode6Align { 1071 // The alignment specifier can only be 16 or omitted. 1072 let ParserMatchClass = AddrMode6Align16AsmOperand; 1073} 1074 1075// Special version of addrmode6 to handle 32-bit alignment encoding for 1076// VLD/VST instructions and checking the alignment value. 1077def AddrMode6Align32AsmOperand : AsmOperandClass { 1078 let Name = "AlignedMemory32"; 1079 let DiagnosticType = "AlignedMemoryRequires32"; 1080} 1081def addrmode6align32 : AddrMode6Align { 1082 // The alignment specifier can only be 32 or omitted. 1083 let ParserMatchClass = AddrMode6Align32AsmOperand; 1084} 1085 1086// Special version of addrmode6 to handle 64-bit alignment encoding for 1087// VLD/VST instructions and checking the alignment value. 1088def AddrMode6Align64AsmOperand : AsmOperandClass { 1089 let Name = "AlignedMemory64"; 1090 let DiagnosticType = "AlignedMemoryRequires64"; 1091} 1092def addrmode6align64 : AddrMode6Align { 1093 // The alignment specifier can only be 64 or omitted. 1094 let ParserMatchClass = AddrMode6Align64AsmOperand; 1095} 1096 1097// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1098// for VLD/VST instructions and checking the alignment value. 1099def AddrMode6Align64or128AsmOperand : AsmOperandClass { 1100 let Name = "AlignedMemory64or128"; 1101 let DiagnosticType = "AlignedMemoryRequires64or128"; 1102} 1103def addrmode6align64or128 : AddrMode6Align { 1104 // The alignment specifier can only be 64, 128 or omitted. 1105 let ParserMatchClass = AddrMode6Align64or128AsmOperand; 1106} 1107 1108// Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment 1109// encoding for VLD/VST instructions and checking the alignment value. 1110def AddrMode6Align64or128or256AsmOperand : AsmOperandClass { 1111 let Name = "AlignedMemory64or128or256"; 1112 let DiagnosticType = "AlignedMemoryRequires64or128or256"; 1113} 1114def addrmode6align64or128or256 : AddrMode6Align { 1115 // The alignment specifier can only be 64, 128, 256 or omitted. 1116 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand; 1117} 1118 1119// Special version of addrmode6 to handle alignment encoding for VLD-dup 1120// instructions, specifically VLD4-dup. 1121def addrmode6dup : MemOperand, 1122 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1123 let PrintMethod = "printAddrMode6Operand"; 1124 let MIOperandInfo = (ops GPR:$addr, i32imm); 1125 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1126 // FIXME: This is close, but not quite right. The alignment specifier is 1127 // different. 1128 let ParserMatchClass = AddrMode6AsmOperand; 1129} 1130 1131// Base class for addrmode6dup with specific alignment restrictions. 1132class AddrMode6DupAlign : MemOperand, 1133 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1134 let PrintMethod = "printAddrMode6Operand"; 1135 let MIOperandInfo = (ops GPR:$addr, i32imm); 1136 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1137} 1138 1139// Special version of addrmode6 to handle no allowed alignment encoding for 1140// VLD-dup instruction and checking the alignment is not specified. 1141def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass { 1142 let Name = "DupAlignedMemoryNone"; 1143 let DiagnosticType = "DupAlignedMemoryRequiresNone"; 1144} 1145def addrmode6dupalignNone : AddrMode6DupAlign { 1146 // The alignment specifier can only be omitted. 1147 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand; 1148} 1149 1150// Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup 1151// instruction and checking the alignment value. 1152def AddrMode6dupAlign16AsmOperand : AsmOperandClass { 1153 let Name = "DupAlignedMemory16"; 1154 let DiagnosticType = "DupAlignedMemoryRequires16"; 1155} 1156def addrmode6dupalign16 : AddrMode6DupAlign { 1157 // The alignment specifier can only be 16 or omitted. 1158 let ParserMatchClass = AddrMode6dupAlign16AsmOperand; 1159} 1160 1161// Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup 1162// instruction and checking the alignment value. 1163def AddrMode6dupAlign32AsmOperand : AsmOperandClass { 1164 let Name = "DupAlignedMemory32"; 1165 let DiagnosticType = "DupAlignedMemoryRequires32"; 1166} 1167def addrmode6dupalign32 : AddrMode6DupAlign { 1168 // The alignment specifier can only be 32 or omitted. 1169 let ParserMatchClass = AddrMode6dupAlign32AsmOperand; 1170} 1171 1172// Special version of addrmode6 to handle 64-bit alignment encoding for VLD 1173// instructions and checking the alignment value. 1174def AddrMode6dupAlign64AsmOperand : AsmOperandClass { 1175 let Name = "DupAlignedMemory64"; 1176 let DiagnosticType = "DupAlignedMemoryRequires64"; 1177} 1178def addrmode6dupalign64 : AddrMode6DupAlign { 1179 // The alignment specifier can only be 64 or omitted. 1180 let ParserMatchClass = AddrMode6dupAlign64AsmOperand; 1181} 1182 1183// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1184// for VLD instructions and checking the alignment value. 1185def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass { 1186 let Name = "DupAlignedMemory64or128"; 1187 let DiagnosticType = "DupAlignedMemoryRequires64or128"; 1188} 1189def addrmode6dupalign64or128 : AddrMode6DupAlign { 1190 // The alignment specifier can only be 64, 128 or omitted. 1191 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand; 1192} 1193 1194// addrmodepc := pc + reg 1195// 1196def addrmodepc : MemOperand, 1197 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 1198 let PrintMethod = "printAddrModePCOperand"; 1199 let MIOperandInfo = (ops GPR, i32imm); 1200} 1201 1202// addr_offset_none := reg 1203// 1204def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; } 1205def addr_offset_none : MemOperand, 1206 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> { 1207 let PrintMethod = "printAddrMode7Operand"; 1208 let DecoderMethod = "DecodeAddrMode7Operand"; 1209 let ParserMatchClass = MemNoOffsetAsmOperand; 1210 let MIOperandInfo = (ops GPR:$base); 1211} 1212 1213def nohash_imm : Operand<i32> { 1214 let PrintMethod = "printNoHashImmediate"; 1215} 1216 1217def CoprocNumAsmOperand : AsmOperandClass { 1218 let Name = "CoprocNum"; 1219 let ParserMethod = "parseCoprocNumOperand"; 1220} 1221def p_imm : Operand<i32> { 1222 let PrintMethod = "printPImmediate"; 1223 let ParserMatchClass = CoprocNumAsmOperand; 1224 let DecoderMethod = "DecodeCoprocessor"; 1225} 1226 1227def CoprocRegAsmOperand : AsmOperandClass { 1228 let Name = "CoprocReg"; 1229 let ParserMethod = "parseCoprocRegOperand"; 1230} 1231def c_imm : Operand<i32> { 1232 let PrintMethod = "printCImmediate"; 1233 let ParserMatchClass = CoprocRegAsmOperand; 1234} 1235def CoprocOptionAsmOperand : AsmOperandClass { 1236 let Name = "CoprocOption"; 1237 let ParserMethod = "parseCoprocOptionOperand"; 1238} 1239def coproc_option_imm : Operand<i32> { 1240 let PrintMethod = "printCoprocOptionImm"; 1241 let ParserMatchClass = CoprocOptionAsmOperand; 1242} 1243 1244//===----------------------------------------------------------------------===// 1245 1246include "ARMInstrFormats.td" 1247 1248//===----------------------------------------------------------------------===// 1249// Multiclass helpers... 1250// 1251 1252/// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a 1253/// binop that produces a value. 1254let TwoOperandAliasConstraint = "$Rn = $Rd" in 1255multiclass AsI1_bin_irs<bits<4> opcod, string opc, 1256 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1257 PatFrag opnode, bit Commutable = 0> { 1258 // The register-immediate version is re-materializable. This is useful 1259 // in particular for taking the address of a local. 1260 let isReMaterializable = 1 in { 1261 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1262 iii, opc, "\t$Rd, $Rn, $imm", 1263 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>, 1264 Sched<[WriteALU, ReadALU]> { 1265 bits<4> Rd; 1266 bits<4> Rn; 1267 bits<12> imm; 1268 let Inst{25} = 1; 1269 let Inst{19-16} = Rn; 1270 let Inst{15-12} = Rd; 1271 let Inst{11-0} = imm; 1272 } 1273 } 1274 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1275 iir, opc, "\t$Rd, $Rn, $Rm", 1276 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, 1277 Sched<[WriteALU, ReadALU, ReadALU]> { 1278 bits<4> Rd; 1279 bits<4> Rn; 1280 bits<4> Rm; 1281 let Inst{25} = 0; 1282 let isCommutable = Commutable; 1283 let Inst{19-16} = Rn; 1284 let Inst{15-12} = Rd; 1285 let Inst{11-4} = 0b00000000; 1286 let Inst{3-0} = Rm; 1287 } 1288 1289 def rsi : AsI1<opcod, (outs GPR:$Rd), 1290 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1291 iis, opc, "\t$Rd, $Rn, $shift", 1292 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>, 1293 Sched<[WriteALUsi, ReadALU]> { 1294 bits<4> Rd; 1295 bits<4> Rn; 1296 bits<12> shift; 1297 let Inst{25} = 0; 1298 let Inst{19-16} = Rn; 1299 let Inst{15-12} = Rd; 1300 let Inst{11-5} = shift{11-5}; 1301 let Inst{4} = 0; 1302 let Inst{3-0} = shift{3-0}; 1303 } 1304 1305 def rsr : AsI1<opcod, (outs GPR:$Rd), 1306 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1307 iis, opc, "\t$Rd, $Rn, $shift", 1308 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>, 1309 Sched<[WriteALUsr, ReadALUsr]> { 1310 bits<4> Rd; 1311 bits<4> Rn; 1312 bits<12> shift; 1313 let Inst{25} = 0; 1314 let Inst{19-16} = Rn; 1315 let Inst{15-12} = Rd; 1316 let Inst{11-8} = shift{11-8}; 1317 let Inst{7} = 0; 1318 let Inst{6-5} = shift{6-5}; 1319 let Inst{4} = 1; 1320 let Inst{3-0} = shift{3-0}; 1321 } 1322} 1323 1324/// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are 1325/// reversed. The 'rr' form is only defined for the disassembler; for codegen 1326/// it is equivalent to the AsI1_bin_irs counterpart. 1327let TwoOperandAliasConstraint = "$Rn = $Rd" in 1328multiclass AsI1_rbin_irs<bits<4> opcod, string opc, 1329 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1330 PatFrag opnode, bit Commutable = 0> { 1331 // The register-immediate version is re-materializable. This is useful 1332 // in particular for taking the address of a local. 1333 let isReMaterializable = 1 in { 1334 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1335 iii, opc, "\t$Rd, $Rn, $imm", 1336 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>, 1337 Sched<[WriteALU, ReadALU]> { 1338 bits<4> Rd; 1339 bits<4> Rn; 1340 bits<12> imm; 1341 let Inst{25} = 1; 1342 let Inst{19-16} = Rn; 1343 let Inst{15-12} = Rd; 1344 let Inst{11-0} = imm; 1345 } 1346 } 1347 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1348 iir, opc, "\t$Rd, $Rn, $Rm", 1349 [/* pattern left blank */]>, 1350 Sched<[WriteALU, ReadALU, ReadALU]> { 1351 bits<4> Rd; 1352 bits<4> Rn; 1353 bits<4> Rm; 1354 let Inst{11-4} = 0b00000000; 1355 let Inst{25} = 0; 1356 let Inst{3-0} = Rm; 1357 let Inst{15-12} = Rd; 1358 let Inst{19-16} = Rn; 1359 } 1360 1361 def rsi : AsI1<opcod, (outs GPR:$Rd), 1362 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1363 iis, opc, "\t$Rd, $Rn, $shift", 1364 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>, 1365 Sched<[WriteALUsi, ReadALU]> { 1366 bits<4> Rd; 1367 bits<4> Rn; 1368 bits<12> shift; 1369 let Inst{25} = 0; 1370 let Inst{19-16} = Rn; 1371 let Inst{15-12} = Rd; 1372 let Inst{11-5} = shift{11-5}; 1373 let Inst{4} = 0; 1374 let Inst{3-0} = shift{3-0}; 1375 } 1376 1377 def rsr : AsI1<opcod, (outs GPR:$Rd), 1378 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1379 iis, opc, "\t$Rd, $Rn, $shift", 1380 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>, 1381 Sched<[WriteALUsr, ReadALUsr]> { 1382 bits<4> Rd; 1383 bits<4> Rn; 1384 bits<12> shift; 1385 let Inst{25} = 0; 1386 let Inst{19-16} = Rn; 1387 let Inst{15-12} = Rd; 1388 let Inst{11-8} = shift{11-8}; 1389 let Inst{7} = 0; 1390 let Inst{6-5} = shift{6-5}; 1391 let Inst{4} = 1; 1392 let Inst{3-0} = shift{3-0}; 1393 } 1394} 1395 1396/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default. 1397/// 1398/// These opcodes will be converted to the real non-S opcodes by 1399/// AdjustInstrPostInstrSelection after giving them an optional CPSR operand. 1400let hasPostISelHook = 1, Defs = [CPSR] in { 1401multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir, 1402 InstrItinClass iis, PatFrag opnode, 1403 bit Commutable = 0> { 1404 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1405 4, iii, 1406 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>, 1407 Sched<[WriteALU, ReadALU]>; 1408 1409 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p), 1410 4, iir, 1411 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>, 1412 Sched<[WriteALU, ReadALU, ReadALU]> { 1413 let isCommutable = Commutable; 1414 } 1415 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1416 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1417 4, iis, 1418 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1419 so_reg_imm:$shift))]>, 1420 Sched<[WriteALUsi, ReadALU]>; 1421 1422 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1423 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1424 4, iis, 1425 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1426 so_reg_reg:$shift))]>, 1427 Sched<[WriteALUSsr, ReadALUsr]>; 1428} 1429} 1430 1431/// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG 1432/// operands are reversed. 1433let hasPostISelHook = 1, Defs = [CPSR] in { 1434multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir, 1435 InstrItinClass iis, PatFrag opnode, 1436 bit Commutable = 0> { 1437 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1438 4, iii, 1439 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>, 1440 Sched<[WriteALU, ReadALU]>; 1441 1442 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1443 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1444 4, iis, 1445 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, 1446 GPR:$Rn))]>, 1447 Sched<[WriteALUsi, ReadALU]>; 1448 1449 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1450 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1451 4, iis, 1452 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, 1453 GPR:$Rn))]>, 1454 Sched<[WriteALUSsr, ReadALUsr]>; 1455} 1456} 1457 1458/// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test 1459/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 1460/// a explicit result, only implicitly set CPSR. 1461let isCompare = 1, Defs = [CPSR] in { 1462multiclass AI1_cmp_irs<bits<4> opcod, string opc, 1463 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1464 PatFrag opnode, bit Commutable = 0, 1465 string rrDecoderMethod = ""> { 1466 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii, 1467 opc, "\t$Rn, $imm", 1468 [(opnode GPR:$Rn, mod_imm:$imm)]>, 1469 Sched<[WriteCMP, ReadALU]> { 1470 bits<4> Rn; 1471 bits<12> imm; 1472 let Inst{25} = 1; 1473 let Inst{20} = 1; 1474 let Inst{19-16} = Rn; 1475 let Inst{15-12} = 0b0000; 1476 let Inst{11-0} = imm; 1477 1478 let Unpredictable{15-12} = 0b1111; 1479 } 1480 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir, 1481 opc, "\t$Rn, $Rm", 1482 [(opnode GPR:$Rn, GPR:$Rm)]>, 1483 Sched<[WriteCMP, ReadALU, ReadALU]> { 1484 bits<4> Rn; 1485 bits<4> Rm; 1486 let isCommutable = Commutable; 1487 let Inst{25} = 0; 1488 let Inst{20} = 1; 1489 let Inst{19-16} = Rn; 1490 let Inst{15-12} = 0b0000; 1491 let Inst{11-4} = 0b00000000; 1492 let Inst{3-0} = Rm; 1493 let DecoderMethod = rrDecoderMethod; 1494 1495 let Unpredictable{15-12} = 0b1111; 1496 } 1497 def rsi : AI1<opcod, (outs), 1498 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis, 1499 opc, "\t$Rn, $shift", 1500 [(opnode GPR:$Rn, so_reg_imm:$shift)]>, 1501 Sched<[WriteCMPsi, ReadALU]> { 1502 bits<4> Rn; 1503 bits<12> shift; 1504 let Inst{25} = 0; 1505 let Inst{20} = 1; 1506 let Inst{19-16} = Rn; 1507 let Inst{15-12} = 0b0000; 1508 let Inst{11-5} = shift{11-5}; 1509 let Inst{4} = 0; 1510 let Inst{3-0} = shift{3-0}; 1511 1512 let Unpredictable{15-12} = 0b1111; 1513 } 1514 def rsr : AI1<opcod, (outs), 1515 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis, 1516 opc, "\t$Rn, $shift", 1517 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>, 1518 Sched<[WriteCMPsr, ReadALU]> { 1519 bits<4> Rn; 1520 bits<12> shift; 1521 let Inst{25} = 0; 1522 let Inst{20} = 1; 1523 let Inst{19-16} = Rn; 1524 let Inst{15-12} = 0b0000; 1525 let Inst{11-8} = shift{11-8}; 1526 let Inst{7} = 0; 1527 let Inst{6-5} = shift{6-5}; 1528 let Inst{4} = 1; 1529 let Inst{3-0} = shift{3-0}; 1530 1531 let Unpredictable{15-12} = 0b1111; 1532 } 1533 1534} 1535} 1536 1537/// AI_ext_rrot - A unary operation with two forms: one whose operand is a 1538/// register and one whose operand is a register rotated by 8/16/24. 1539/// FIXME: Remove the 'r' variant. Its rot_imm is zero. 1540class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> 1541 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1542 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", 1543 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1544 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1545 bits<4> Rd; 1546 bits<4> Rm; 1547 bits<2> rot; 1548 let Inst{19-16} = 0b1111; 1549 let Inst{15-12} = Rd; 1550 let Inst{11-10} = rot; 1551 let Inst{3-0} = Rm; 1552} 1553 1554class AI_ext_rrot_np<bits<8> opcod, string opc> 1555 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1556 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>, 1557 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1558 bits<2> rot; 1559 let Inst{19-16} = 0b1111; 1560 let Inst{11-10} = rot; 1561 } 1562 1563/// AI_exta_rrot - A binary operation with two forms: one whose operand is a 1564/// register and one whose operand is a register rotated by 8/16/24. 1565class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> 1566 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1567 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", 1568 [(set GPRnopc:$Rd, (opnode GPR:$Rn, 1569 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1570 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1571 bits<4> Rd; 1572 bits<4> Rm; 1573 bits<4> Rn; 1574 bits<2> rot; 1575 let Inst{19-16} = Rn; 1576 let Inst{15-12} = Rd; 1577 let Inst{11-10} = rot; 1578 let Inst{9-4} = 0b000111; 1579 let Inst{3-0} = Rm; 1580} 1581 1582class AI_exta_rrot_np<bits<8> opcod, string opc> 1583 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1584 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>, 1585 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1586 bits<4> Rn; 1587 bits<2> rot; 1588 let Inst{19-16} = Rn; 1589 let Inst{11-10} = rot; 1590} 1591 1592/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. 1593let TwoOperandAliasConstraint = "$Rn = $Rd" in 1594multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, 1595 bit Commutable = 0> { 1596 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1597 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1598 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1599 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>, 1600 Requires<[IsARM]>, 1601 Sched<[WriteALU, ReadALU]> { 1602 bits<4> Rd; 1603 bits<4> Rn; 1604 bits<12> imm; 1605 let Inst{25} = 1; 1606 let Inst{15-12} = Rd; 1607 let Inst{19-16} = Rn; 1608 let Inst{11-0} = imm; 1609 } 1610 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1611 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1612 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>, 1613 Requires<[IsARM]>, 1614 Sched<[WriteALU, ReadALU, ReadALU]> { 1615 bits<4> Rd; 1616 bits<4> Rn; 1617 bits<4> Rm; 1618 let Inst{11-4} = 0b00000000; 1619 let Inst{25} = 0; 1620 let isCommutable = Commutable; 1621 let Inst{3-0} = Rm; 1622 let Inst{15-12} = Rd; 1623 let Inst{19-16} = Rn; 1624 } 1625 def rsi : AsI1<opcod, (outs GPR:$Rd), 1626 (ins GPR:$Rn, so_reg_imm:$shift), 1627 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1628 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>, 1629 Requires<[IsARM]>, 1630 Sched<[WriteALUsi, ReadALU]> { 1631 bits<4> Rd; 1632 bits<4> Rn; 1633 bits<12> shift; 1634 let Inst{25} = 0; 1635 let Inst{19-16} = Rn; 1636 let Inst{15-12} = Rd; 1637 let Inst{11-5} = shift{11-5}; 1638 let Inst{4} = 0; 1639 let Inst{3-0} = shift{3-0}; 1640 } 1641 def rsr : AsI1<opcod, (outs GPRnopc:$Rd), 1642 (ins GPRnopc:$Rn, so_reg_reg:$shift), 1643 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1644 [(set GPRnopc:$Rd, CPSR, 1645 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>, 1646 Requires<[IsARM]>, 1647 Sched<[WriteALUsr, ReadALUsr]> { 1648 bits<4> Rd; 1649 bits<4> Rn; 1650 bits<12> shift; 1651 let Inst{25} = 0; 1652 let Inst{19-16} = Rn; 1653 let Inst{15-12} = Rd; 1654 let Inst{11-8} = shift{11-8}; 1655 let Inst{7} = 0; 1656 let Inst{6-5} = shift{6-5}; 1657 let Inst{4} = 1; 1658 let Inst{3-0} = shift{3-0}; 1659 } 1660 } 1661} 1662 1663/// AI1_rsc_irs - Define instructions and patterns for rsc 1664let TwoOperandAliasConstraint = "$Rn = $Rd" in 1665multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> { 1666 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1667 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1668 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1669 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>, 1670 Requires<[IsARM]>, 1671 Sched<[WriteALU, ReadALU]> { 1672 bits<4> Rd; 1673 bits<4> Rn; 1674 bits<12> imm; 1675 let Inst{25} = 1; 1676 let Inst{15-12} = Rd; 1677 let Inst{19-16} = Rn; 1678 let Inst{11-0} = imm; 1679 } 1680 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1681 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1682 [/* pattern left blank */]>, 1683 Sched<[WriteALU, ReadALU, ReadALU]> { 1684 bits<4> Rd; 1685 bits<4> Rn; 1686 bits<4> Rm; 1687 let Inst{11-4} = 0b00000000; 1688 let Inst{25} = 0; 1689 let Inst{3-0} = Rm; 1690 let Inst{15-12} = Rd; 1691 let Inst{19-16} = Rn; 1692 } 1693 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), 1694 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1695 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>, 1696 Requires<[IsARM]>, 1697 Sched<[WriteALUsi, ReadALU]> { 1698 bits<4> Rd; 1699 bits<4> Rn; 1700 bits<12> shift; 1701 let Inst{25} = 0; 1702 let Inst{19-16} = Rn; 1703 let Inst{15-12} = Rd; 1704 let Inst{11-5} = shift{11-5}; 1705 let Inst{4} = 0; 1706 let Inst{3-0} = shift{3-0}; 1707 } 1708 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), 1709 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1710 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>, 1711 Requires<[IsARM]>, 1712 Sched<[WriteALUsr, ReadALUsr]> { 1713 bits<4> Rd; 1714 bits<4> Rn; 1715 bits<12> shift; 1716 let Inst{25} = 0; 1717 let Inst{19-16} = Rn; 1718 let Inst{15-12} = Rd; 1719 let Inst{11-8} = shift{11-8}; 1720 let Inst{7} = 0; 1721 let Inst{6-5} = shift{6-5}; 1722 let Inst{4} = 1; 1723 let Inst{3-0} = shift{3-0}; 1724 } 1725 } 1726} 1727 1728let canFoldAsLoad = 1, isReMaterializable = 1 in { 1729multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii, 1730 InstrItinClass iir, PatFrag opnode> { 1731 // Note: We use the complex addrmode_imm12 rather than just an input 1732 // GPR and a constrained immediate so that we can use this to match 1733 // frame index references and avoid matching constant pool references. 1734 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 1735 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1736 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { 1737 bits<4> Rt; 1738 bits<17> addr; 1739 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1740 let Inst{19-16} = addr{16-13}; // Rn 1741 let Inst{15-12} = Rt; 1742 let Inst{11-0} = addr{11-0}; // imm12 1743 } 1744 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift), 1745 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1746 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { 1747 bits<4> Rt; 1748 bits<17> shift; 1749 let shift{4} = 0; // Inst{4} = 0 1750 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1751 let Inst{19-16} = shift{16-13}; // Rn 1752 let Inst{15-12} = Rt; 1753 let Inst{11-0} = shift{11-0}; 1754 } 1755} 1756} 1757 1758let canFoldAsLoad = 1, isReMaterializable = 1 in { 1759multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii, 1760 InstrItinClass iir, PatFrag opnode> { 1761 // Note: We use the complex addrmode_imm12 rather than just an input 1762 // GPR and a constrained immediate so that we can use this to match 1763 // frame index references and avoid matching constant pool references. 1764 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), 1765 (ins addrmode_imm12:$addr), 1766 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1767 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> { 1768 bits<4> Rt; 1769 bits<17> addr; 1770 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1771 let Inst{19-16} = addr{16-13}; // Rn 1772 let Inst{15-12} = Rt; 1773 let Inst{11-0} = addr{11-0}; // imm12 1774 } 1775 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), 1776 (ins ldst_so_reg:$shift), 1777 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1778 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> { 1779 bits<4> Rt; 1780 bits<17> shift; 1781 let shift{4} = 0; // Inst{4} = 0 1782 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1783 let Inst{19-16} = shift{16-13}; // Rn 1784 let Inst{15-12} = Rt; 1785 let Inst{11-0} = shift{11-0}; 1786 } 1787} 1788} 1789 1790 1791multiclass AI_str1<bit isByte, string opc, InstrItinClass iii, 1792 InstrItinClass iir, PatFrag opnode> { 1793 // Note: We use the complex addrmode_imm12 rather than just an input 1794 // GPR and a constrained immediate so that we can use this to match 1795 // frame index references and avoid matching constant pool references. 1796 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1797 (ins GPR:$Rt, addrmode_imm12:$addr), 1798 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1799 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> { 1800 bits<4> Rt; 1801 bits<17> addr; 1802 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1803 let Inst{19-16} = addr{16-13}; // Rn 1804 let Inst{15-12} = Rt; 1805 let Inst{11-0} = addr{11-0}; // imm12 1806 } 1807 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift), 1808 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1809 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> { 1810 bits<4> Rt; 1811 bits<17> shift; 1812 let shift{4} = 0; // Inst{4} = 0 1813 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1814 let Inst{19-16} = shift{16-13}; // Rn 1815 let Inst{15-12} = Rt; 1816 let Inst{11-0} = shift{11-0}; 1817 } 1818} 1819 1820multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii, 1821 InstrItinClass iir, PatFrag opnode> { 1822 // Note: We use the complex addrmode_imm12 rather than just an input 1823 // GPR and a constrained immediate so that we can use this to match 1824 // frame index references and avoid matching constant pool references. 1825 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1826 (ins GPRnopc:$Rt, addrmode_imm12:$addr), 1827 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1828 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> { 1829 bits<4> Rt; 1830 bits<17> addr; 1831 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1832 let Inst{19-16} = addr{16-13}; // Rn 1833 let Inst{15-12} = Rt; 1834 let Inst{11-0} = addr{11-0}; // imm12 1835 } 1836 def rs : AI2ldst<0b011, 0, isByte, (outs), 1837 (ins GPRnopc:$Rt, ldst_so_reg:$shift), 1838 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1839 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> { 1840 bits<4> Rt; 1841 bits<17> shift; 1842 let shift{4} = 0; // Inst{4} = 0 1843 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1844 let Inst{19-16} = shift{16-13}; // Rn 1845 let Inst{15-12} = Rt; 1846 let Inst{11-0} = shift{11-0}; 1847 } 1848} 1849 1850 1851//===----------------------------------------------------------------------===// 1852// Instructions 1853//===----------------------------------------------------------------------===// 1854 1855//===----------------------------------------------------------------------===// 1856// Miscellaneous Instructions. 1857// 1858 1859/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 1860/// the function. The first operand is the ID# for this instruction, the second 1861/// is the index into the MachineConstantPool that this is, the third is the 1862/// size in bytes of this constant pool entry. 1863let hasSideEffects = 0, isNotDuplicable = 1 in 1864def CONSTPOOL_ENTRY : 1865PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1866 i32imm:$size), NoItinerary, []>; 1867 1868/// A jumptable consisting of direct 32-bit addresses of the destination basic 1869/// blocks (either absolute, or relative to the start of the jump-table in PIC 1870/// mode). Used mostly in ARM and Thumb-1 modes. 1871def JUMPTABLE_ADDRS : 1872PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1873 i32imm:$size), NoItinerary, []>; 1874 1875/// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables 1876/// that cannot be optimised to use TBB or TBH. 1877def JUMPTABLE_INSTS : 1878PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1879 i32imm:$size), NoItinerary, []>; 1880 1881/// A jumptable consisting of 8-bit unsigned integers representing offsets from 1882/// a TBB instruction. 1883def JUMPTABLE_TBB : 1884PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1885 i32imm:$size), NoItinerary, []>; 1886 1887/// A jumptable consisting of 16-bit unsigned integers representing offsets from 1888/// a TBH instruction. 1889def JUMPTABLE_TBH : 1890PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1891 i32imm:$size), NoItinerary, []>; 1892 1893 1894// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 1895// from removing one half of the matched pairs. That breaks PEI, which assumes 1896// these will always be in pairs, and asserts if it finds otherwise. Better way? 1897let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 1898def ADJCALLSTACKUP : 1899PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, 1900 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; 1901 1902def ADJCALLSTACKDOWN : 1903PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary, 1904 [(ARMcallseq_start timm:$amt)]>; 1905} 1906 1907def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary, 1908 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>, 1909 Requires<[IsARM, HasV6]> { 1910 bits<8> imm; 1911 let Inst{27-8} = 0b00110010000011110000; 1912 let Inst{7-0} = imm; 1913} 1914 1915def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>; 1916def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>; 1917def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>; 1918def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>; 1919def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>; 1920def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>; 1921 1922def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel", 1923 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> { 1924 bits<4> Rd; 1925 bits<4> Rn; 1926 bits<4> Rm; 1927 let Inst{3-0} = Rm; 1928 let Inst{15-12} = Rd; 1929 let Inst{19-16} = Rn; 1930 let Inst{27-20} = 0b01101000; 1931 let Inst{7-4} = 0b1011; 1932 let Inst{11-8} = 0b1111; 1933 let Unpredictable{11-8} = 0b1111; 1934} 1935 1936// The 16-bit operand $val can be used by a debugger to store more information 1937// about the breakpoint. 1938def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 1939 "bkpt", "\t$val", []>, Requires<[IsARM]> { 1940 bits<16> val; 1941 let Inst{3-0} = val{3-0}; 1942 let Inst{19-8} = val{15-4}; 1943 let Inst{27-20} = 0b00010010; 1944 let Inst{31-28} = 0xe; // AL 1945 let Inst{7-4} = 0b0111; 1946} 1947// default immediate for breakpoint mnemonic 1948def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>; 1949 1950def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 1951 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> { 1952 bits<16> val; 1953 let Inst{3-0} = val{3-0}; 1954 let Inst{19-8} = val{15-4}; 1955 let Inst{27-20} = 0b00010000; 1956 let Inst{31-28} = 0xe; // AL 1957 let Inst{7-4} = 0b0111; 1958} 1959 1960// Change Processor State 1961// FIXME: We should use InstAlias to handle the optional operands. 1962class CPS<dag iops, string asm_ops> 1963 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops), 1964 []>, Requires<[IsARM]> { 1965 bits<2> imod; 1966 bits<3> iflags; 1967 bits<5> mode; 1968 bit M; 1969 1970 let Inst{31-28} = 0b1111; 1971 let Inst{27-20} = 0b00010000; 1972 let Inst{19-18} = imod; 1973 let Inst{17} = M; // Enabled if mode is set; 1974 let Inst{16-9} = 0b00000000; 1975 let Inst{8-6} = iflags; 1976 let Inst{5} = 0; 1977 let Inst{4-0} = mode; 1978} 1979 1980let DecoderMethod = "DecodeCPSInstruction" in { 1981let M = 1 in 1982 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode), 1983 "$imod\t$iflags, $mode">; 1984let mode = 0, M = 0 in 1985 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">; 1986 1987let imod = 0, iflags = 0, M = 1 in 1988 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">; 1989} 1990 1991// Preload signals the memory system of possible future data/instruction access. 1992multiclass APreLoad<bits<1> read, bits<1> data, string opc> { 1993 1994 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm, 1995 IIC_Preload, !strconcat(opc, "\t$addr"), 1996 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>, 1997 Sched<[WritePreLd]> { 1998 bits<4> Rt; 1999 bits<17> addr; 2000 let Inst{31-26} = 0b111101; 2001 let Inst{25} = 0; // 0 for immediate form 2002 let Inst{24} = data; 2003 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2004 let Inst{22} = read; 2005 let Inst{21-20} = 0b01; 2006 let Inst{19-16} = addr{16-13}; // Rn 2007 let Inst{15-12} = 0b1111; 2008 let Inst{11-0} = addr{11-0}; // imm12 2009 } 2010 2011 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, 2012 !strconcat(opc, "\t$shift"), 2013 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>, 2014 Sched<[WritePreLd]> { 2015 bits<17> shift; 2016 let Inst{31-26} = 0b111101; 2017 let Inst{25} = 1; // 1 for register form 2018 let Inst{24} = data; 2019 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2020 let Inst{22} = read; 2021 let Inst{21-20} = 0b01; 2022 let Inst{19-16} = shift{16-13}; // Rn 2023 let Inst{15-12} = 0b1111; 2024 let Inst{11-0} = shift{11-0}; 2025 let Inst{4} = 0; 2026 } 2027} 2028 2029defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>; 2030defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>; 2031defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>; 2032 2033def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary, 2034 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> { 2035 bits<1> end; 2036 let Inst{31-10} = 0b1111000100000001000000; 2037 let Inst{9} = end; 2038 let Inst{8-0} = 0; 2039} 2040 2041def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", 2042 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> { 2043 bits<4> opt; 2044 let Inst{27-4} = 0b001100100000111100001111; 2045 let Inst{3-0} = opt; 2046} 2047 2048// A8.8.247 UDF - Undefined (Encoding A1) 2049def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary, 2050 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> { 2051 bits<16> imm16; 2052 let Inst{31-28} = 0b1110; // AL 2053 let Inst{27-25} = 0b011; 2054 let Inst{24-20} = 0b11111; 2055 let Inst{19-8} = imm16{15-4}; 2056 let Inst{7-4} = 0b1111; 2057 let Inst{3-0} = imm16{3-0}; 2058} 2059 2060/* 2061 * A5.4 Permanently UNDEFINED instructions. 2062 * 2063 * For most targets use UDF #65006, for which the OS will generate SIGTRAP. 2064 * Other UDF encodings generate SIGILL. 2065 * 2066 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb. 2067 * Encoding A1: 2068 * 1110 0111 1111 iiii iiii iiii 1111 iiii 2069 * Encoding T1: 2070 * 1101 1110 iiii iiii 2071 * It uses the following encoding: 2072 * 1110 0111 1111 1110 1101 1110 1111 0000 2073 * - In ARM: UDF #60896; 2074 * - In Thumb: UDF #254 followed by a branch-to-self. 2075 */ 2076let isBarrier = 1, isTerminator = 1 in 2077def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary, 2078 "trap", [(trap)]>, 2079 Requires<[IsARM,UseNaClTrap]> { 2080 let Inst = 0xe7fedef0; 2081} 2082let isBarrier = 1, isTerminator = 1 in 2083def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, 2084 "trap", [(trap)]>, 2085 Requires<[IsARM,DontUseNaClTrap]> { 2086 let Inst = 0xe7ffdefe; 2087} 2088 2089// Address computation and loads and stores in PIC mode. 2090let isNotDuplicable = 1 in { 2091def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 2092 4, IIC_iALUr, 2093 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>, 2094 Sched<[WriteALU, ReadALU]>; 2095 2096let AddedComplexity = 10 in { 2097def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 2098 4, IIC_iLoad_r, 2099 [(set GPR:$dst, (load addrmodepc:$addr))]>; 2100 2101def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2102 4, IIC_iLoad_bh_r, 2103 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>; 2104 2105def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2106 4, IIC_iLoad_bh_r, 2107 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>; 2108 2109def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2110 4, IIC_iLoad_bh_r, 2111 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>; 2112 2113def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2114 4, IIC_iLoad_bh_r, 2115 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>; 2116} 2117let AddedComplexity = 10 in { 2118def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2119 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>; 2120 2121def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2122 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, 2123 addrmodepc:$addr)]>; 2124 2125def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2126 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 2127} 2128} // isNotDuplicable = 1 2129 2130 2131// LEApcrel - Load a pc-relative address into a register without offending the 2132// assembler. 2133let hasSideEffects = 0, isReMaterializable = 1 in 2134// The 'adr' mnemonic encodes differently if the label is before or after 2135// the instruction. The {24-21} opcode bits are set by the fixup, as we don't 2136// know until then which form of the instruction will be used. 2137def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), 2138 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>, 2139 Sched<[WriteALU, ReadALU]> { 2140 bits<4> Rd; 2141 bits<14> label; 2142 let Inst{27-25} = 0b001; 2143 let Inst{24} = 0; 2144 let Inst{23-22} = label{13-12}; 2145 let Inst{21} = 0; 2146 let Inst{20} = 0; 2147 let Inst{19-16} = 0b1111; 2148 let Inst{15-12} = Rd; 2149 let Inst{11-0} = label{11-0}; 2150} 2151 2152let hasSideEffects = 1 in { 2153def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 2154 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2155 2156def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd), 2157 (ins i32imm:$label, pred:$p), 2158 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2159} 2160 2161//===----------------------------------------------------------------------===// 2162// Control Flow Instructions. 2163// 2164 2165let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 2166 // ARMV4T and above 2167 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2168 "bx", "\tlr", [(ARMretflag)]>, 2169 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2170 let Inst{27-0} = 0b0001001011111111111100011110; 2171 } 2172 2173 // ARMV4 only 2174 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2175 "mov", "\tpc, lr", [(ARMretflag)]>, 2176 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> { 2177 let Inst{27-0} = 0b0001101000001111000000001110; 2178 } 2179 2180 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets 2181 // the user-space one). 2182 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p), 2183 4, IIC_Br, 2184 [(ARMintretflag imm:$offset)]>; 2185} 2186 2187// Indirect branches 2188let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 2189 // ARMV4T and above 2190 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst", 2191 [(brind GPR:$dst)]>, 2192 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2193 bits<4> dst; 2194 let Inst{31-4} = 0b1110000100101111111111110001; 2195 let Inst{3-0} = dst; 2196 } 2197 2198 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, 2199 "bx", "\t$dst", [/* pattern left blank */]>, 2200 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2201 bits<4> dst; 2202 let Inst{27-4} = 0b000100101111111111110001; 2203 let Inst{3-0} = dst; 2204 } 2205} 2206 2207// SP is marked as a use to prevent stack-pointer assignments that appear 2208// immediately before calls from potentially appearing dead. 2209let isCall = 1, 2210 // FIXME: Do we really need a non-predicated version? If so, it should 2211 // at least be a pseudo instruction expanding to the predicated version 2212 // at MC lowering time. 2213 Defs = [LR], Uses = [SP] in { 2214 def BL : ABXI<0b1011, (outs), (ins bl_target:$func), 2215 IIC_Br, "bl\t$func", 2216 [(ARMcall tglobaladdr:$func)]>, 2217 Requires<[IsARM]>, Sched<[WriteBrL]> { 2218 let Inst{31-28} = 0b1110; 2219 bits<24> func; 2220 let Inst{23-0} = func; 2221 let DecoderMethod = "DecodeBranchImmInstruction"; 2222 } 2223 2224 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func), 2225 IIC_Br, "bl", "\t$func", 2226 [(ARMcall_pred tglobaladdr:$func)]>, 2227 Requires<[IsARM]>, Sched<[WriteBrL]> { 2228 bits<24> func; 2229 let Inst{23-0} = func; 2230 let DecoderMethod = "DecodeBranchImmInstruction"; 2231 } 2232 2233 // ARMv5T and above 2234 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm, 2235 IIC_Br, "blx\t$func", 2236 [(ARMcall GPR:$func)]>, 2237 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2238 bits<4> func; 2239 let Inst{31-4} = 0b1110000100101111111111110011; 2240 let Inst{3-0} = func; 2241 } 2242 2243 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm, 2244 IIC_Br, "blx", "\t$func", 2245 [(ARMcall_pred GPR:$func)]>, 2246 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2247 bits<4> func; 2248 let Inst{27-4} = 0b000100101111111111110011; 2249 let Inst{3-0} = func; 2250 } 2251 2252 // ARMv4T 2253 // Note: Restrict $func to the tGPR regclass to prevent it being in LR. 2254 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2255 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2256 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>; 2257 2258 // ARMv4 2259 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2260 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2261 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 2262 2263 // mov lr, pc; b if callee is marked noreturn to avoid confusing the 2264 // return stack predictor. 2265 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func), 2266 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>, 2267 Requires<[IsARM]>, Sched<[WriteBr]>; 2268} 2269 2270let isBranch = 1, isTerminator = 1 in { 2271 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 2272 // a two-value operand where a dag node expects two operands. :( 2273 def Bcc : ABI<0b1010, (outs), (ins br_target:$target), 2274 IIC_Br, "b", "\t$target", 2275 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>, 2276 Sched<[WriteBr]> { 2277 bits<24> target; 2278 let Inst{23-0} = target; 2279 let DecoderMethod = "DecodeBranchImmInstruction"; 2280 } 2281 2282 let isBarrier = 1 in { 2283 // B is "predicable" since it's just a Bcc with an 'always' condition. 2284 let isPredicable = 1 in 2285 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly 2286 // should be sufficient. 2287 // FIXME: Is B really a Barrier? That doesn't seem right. 2288 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br, 2289 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>, 2290 Sched<[WriteBr]>; 2291 2292 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in { 2293 def BR_JTr : ARMPseudoInst<(outs), 2294 (ins GPR:$target, i32imm:$jt), 2295 0, IIC_Br, 2296 [(ARMbrjt GPR:$target, tjumptable:$jt)]>, 2297 Sched<[WriteBr]>; 2298 // FIXME: This shouldn't use the generic "addrmode2," but rather be split 2299 // into i12 and rs suffixed versions. 2300 def BR_JTm : ARMPseudoInst<(outs), 2301 (ins addrmode2:$target, i32imm:$jt), 2302 0, IIC_Br, 2303 [(ARMbrjt (i32 (load addrmode2:$target)), 2304 tjumptable:$jt)]>, Sched<[WriteBrTbl]>; 2305 def BR_JTadd : ARMPseudoInst<(outs), 2306 (ins GPR:$target, GPR:$idx, i32imm:$jt), 2307 0, IIC_Br, 2308 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>, 2309 Sched<[WriteBrTbl]>; 2310 } // isNotDuplicable = 1, isIndirectBranch = 1 2311 } // isBarrier = 1 2312 2313} 2314 2315// BLX (immediate) 2316def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary, 2317 "blx\t$target", []>, 2318 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2319 let Inst{31-25} = 0b1111101; 2320 bits<25> target; 2321 let Inst{23-0} = target{24-1}; 2322 let Inst{24} = target{0}; 2323 let isCall = 1; 2324} 2325 2326// Branch and Exchange Jazelle 2327def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", 2328 [/* pattern left blank */]>, Sched<[WriteBr]> { 2329 bits<4> func; 2330 let Inst{23-20} = 0b0010; 2331 let Inst{19-8} = 0xfff; 2332 let Inst{7-4} = 0b0010; 2333 let Inst{3-0} = func; 2334 let isBranch = 1; 2335} 2336 2337// Tail calls. 2338 2339let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { 2340 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>, 2341 Sched<[WriteBr]>; 2342 2343 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>, 2344 Sched<[WriteBr]>; 2345 2346 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst), 2347 4, IIC_Br, [], 2348 (Bcc br_target:$dst, (ops 14, zero_reg))>, 2349 Requires<[IsARM]>, Sched<[WriteBr]>; 2350 2351 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst), 2352 4, IIC_Br, [], 2353 (BX GPR:$dst)>, Sched<[WriteBr]>, 2354 Requires<[IsARM]>; 2355} 2356 2357// Secure Monitor Call is a system instruction. 2358def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", 2359 []>, Requires<[IsARM, HasTrustZone]> { 2360 bits<4> opt; 2361 let Inst{23-4} = 0b01100000000000000111; 2362 let Inst{3-0} = opt; 2363} 2364def : MnemonicAlias<"smi", "smc">; 2365 2366// Supervisor Call (Software Interrupt) 2367let isCall = 1, Uses = [SP] in { 2368def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>, 2369 Sched<[WriteBr]> { 2370 bits<24> svc; 2371 let Inst{23-0} = svc; 2372} 2373} 2374 2375// Store Return State 2376class SRSI<bit wb, string asm> 2377 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm, 2378 NoItinerary, asm, "", []> { 2379 bits<5> mode; 2380 let Inst{31-28} = 0b1111; 2381 let Inst{27-25} = 0b100; 2382 let Inst{22} = 1; 2383 let Inst{21} = wb; 2384 let Inst{20} = 0; 2385 let Inst{19-16} = 0b1101; // SP 2386 let Inst{15-5} = 0b00000101000; 2387 let Inst{4-0} = mode; 2388} 2389 2390def SRSDA : SRSI<0, "srsda\tsp, $mode"> { 2391 let Inst{24-23} = 0; 2392} 2393def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> { 2394 let Inst{24-23} = 0; 2395} 2396def SRSDB : SRSI<0, "srsdb\tsp, $mode"> { 2397 let Inst{24-23} = 0b10; 2398} 2399def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> { 2400 let Inst{24-23} = 0b10; 2401} 2402def SRSIA : SRSI<0, "srsia\tsp, $mode"> { 2403 let Inst{24-23} = 0b01; 2404} 2405def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> { 2406 let Inst{24-23} = 0b01; 2407} 2408def SRSIB : SRSI<0, "srsib\tsp, $mode"> { 2409 let Inst{24-23} = 0b11; 2410} 2411def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> { 2412 let Inst{24-23} = 0b11; 2413} 2414 2415def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>; 2416def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>; 2417 2418def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>; 2419def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>; 2420 2421def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>; 2422def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>; 2423 2424def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>; 2425def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>; 2426 2427// Return From Exception 2428class RFEI<bit wb, string asm> 2429 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm, 2430 NoItinerary, asm, "", []> { 2431 bits<4> Rn; 2432 let Inst{31-28} = 0b1111; 2433 let Inst{27-25} = 0b100; 2434 let Inst{22} = 0; 2435 let Inst{21} = wb; 2436 let Inst{20} = 1; 2437 let Inst{19-16} = Rn; 2438 let Inst{15-0} = 0xa00; 2439} 2440 2441def RFEDA : RFEI<0, "rfeda\t$Rn"> { 2442 let Inst{24-23} = 0; 2443} 2444def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> { 2445 let Inst{24-23} = 0; 2446} 2447def RFEDB : RFEI<0, "rfedb\t$Rn"> { 2448 let Inst{24-23} = 0b10; 2449} 2450def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> { 2451 let Inst{24-23} = 0b10; 2452} 2453def RFEIA : RFEI<0, "rfeia\t$Rn"> { 2454 let Inst{24-23} = 0b01; 2455} 2456def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> { 2457 let Inst{24-23} = 0b01; 2458} 2459def RFEIB : RFEI<0, "rfeib\t$Rn"> { 2460 let Inst{24-23} = 0b11; 2461} 2462def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> { 2463 let Inst{24-23} = 0b11; 2464} 2465 2466// Hypervisor Call is a system instruction 2467let isCall = 1 in { 2468def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary, 2469 "hvc", "\t$imm", []>, 2470 Requires<[IsARM, HasVirtualization]> { 2471 bits<16> imm; 2472 2473 // Even though HVC isn't predicable, it's encoding includes a condition field. 2474 // The instruction is undefined if the condition field is 0xf otherwise it is 2475 // unpredictable if it isn't condition AL (0xe). 2476 let Inst{31-28} = 0b1110; 2477 let Unpredictable{31-28} = 0b1111; 2478 let Inst{27-24} = 0b0001; 2479 let Inst{23-20} = 0b0100; 2480 let Inst{19-8} = imm{15-4}; 2481 let Inst{7-4} = 0b0111; 2482 let Inst{3-0} = imm{3-0}; 2483} 2484} 2485 2486// Return from exception in Hypervisor mode. 2487let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in 2488def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>, 2489 Requires<[IsARM, HasVirtualization]> { 2490 let Inst{23-0} = 0b011000000000000001101110; 2491} 2492 2493//===----------------------------------------------------------------------===// 2494// Load / Store Instructions. 2495// 2496 2497// Load 2498 2499 2500defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si, 2501 UnOpFrag<(load node:$Src)>>; 2502defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si, 2503 UnOpFrag<(zextloadi8 node:$Src)>>; 2504defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si, 2505 BinOpFrag<(store node:$LHS, node:$RHS)>>; 2506defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si, 2507 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 2508 2509// Special LDR for loads from non-pc-relative constpools. 2510let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0, 2511 isReMaterializable = 1, isCodeGenOnly = 1 in 2512def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 2513 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", 2514 []> { 2515 bits<4> Rt; 2516 bits<17> addr; 2517 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2518 let Inst{19-16} = 0b1111; 2519 let Inst{15-12} = Rt; 2520 let Inst{11-0} = addr{11-0}; // imm12 2521} 2522 2523// Loads with zero extension 2524def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2525 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr", 2526 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>; 2527 2528// Loads with sign extension 2529def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2530 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr", 2531 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>; 2532 2533def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2534 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr", 2535 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>; 2536 2537let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in { 2538 // Load doubleword 2539 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr), 2540 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>, 2541 Requires<[IsARM, HasV5TE]>; 2542} 2543 2544def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2545 NoItinerary, "lda", "\t$Rt, $addr", []>; 2546def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2547 NoItinerary, "ldab", "\t$Rt, $addr", []>; 2548def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2549 NoItinerary, "ldah", "\t$Rt, $addr", []>; 2550 2551// Indexed loads 2552multiclass AI2_ldridx<bit isByte, string opc, 2553 InstrItinClass iii, InstrItinClass iir> { 2554 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2555 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii, 2556 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2557 bits<17> addr; 2558 let Inst{25} = 0; 2559 let Inst{23} = addr{12}; 2560 let Inst{19-16} = addr{16-13}; 2561 let Inst{11-0} = addr{11-0}; 2562 let DecoderMethod = "DecodeLDRPreImm"; 2563 } 2564 2565 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2566 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir, 2567 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2568 bits<17> addr; 2569 let Inst{25} = 1; 2570 let Inst{23} = addr{12}; 2571 let Inst{19-16} = addr{16-13}; 2572 let Inst{11-0} = addr{11-0}; 2573 let Inst{4} = 0; 2574 let DecoderMethod = "DecodeLDRPreReg"; 2575 } 2576 2577 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2578 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2579 IndexModePost, LdFrm, iir, 2580 opc, "\t$Rt, $addr, $offset", 2581 "$addr.base = $Rn_wb", []> { 2582 // {12} isAdd 2583 // {11-0} imm12/Rm 2584 bits<14> offset; 2585 bits<4> addr; 2586 let Inst{25} = 1; 2587 let Inst{23} = offset{12}; 2588 let Inst{19-16} = addr; 2589 let Inst{11-0} = offset{11-0}; 2590 let Inst{4} = 0; 2591 2592 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2593 } 2594 2595 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2596 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2597 IndexModePost, LdFrm, iii, 2598 opc, "\t$Rt, $addr, $offset", 2599 "$addr.base = $Rn_wb", []> { 2600 // {12} isAdd 2601 // {11-0} imm12/Rm 2602 bits<14> offset; 2603 bits<4> addr; 2604 let Inst{25} = 0; 2605 let Inst{23} = offset{12}; 2606 let Inst{19-16} = addr; 2607 let Inst{11-0} = offset{11-0}; 2608 2609 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2610 } 2611 2612} 2613 2614let mayLoad = 1, hasSideEffects = 0 in { 2615// FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or 2616// IIC_iLoad_siu depending on whether it the offset register is shifted. 2617defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>; 2618defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>; 2619} 2620 2621multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> { 2622 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2623 (ins addrmode3_pre:$addr), IndexModePre, 2624 LdMiscFrm, itin, 2625 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2626 bits<14> addr; 2627 let Inst{23} = addr{8}; // U bit 2628 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2629 let Inst{19-16} = addr{12-9}; // Rn 2630 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2631 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2632 let DecoderMethod = "DecodeAddrMode3Instruction"; 2633 } 2634 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2635 (ins addr_offset_none:$addr, am3offset:$offset), 2636 IndexModePost, LdMiscFrm, itin, 2637 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2638 []> { 2639 bits<10> offset; 2640 bits<4> addr; 2641 let Inst{23} = offset{8}; // U bit 2642 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2643 let Inst{19-16} = addr; 2644 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2645 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2646 let DecoderMethod = "DecodeAddrMode3Instruction"; 2647 } 2648} 2649 2650let mayLoad = 1, hasSideEffects = 0 in { 2651defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>; 2652defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>; 2653defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>; 2654let hasExtraDefRegAllocReq = 1 in { 2655def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2656 (ins addrmode3_pre:$addr), IndexModePre, 2657 LdMiscFrm, IIC_iLoad_d_ru, 2658 "ldrd", "\t$Rt, $Rt2, $addr!", 2659 "$addr.base = $Rn_wb", []> { 2660 bits<14> addr; 2661 let Inst{23} = addr{8}; // U bit 2662 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2663 let Inst{19-16} = addr{12-9}; // Rn 2664 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2665 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2666 let DecoderMethod = "DecodeAddrMode3Instruction"; 2667} 2668def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2669 (ins addr_offset_none:$addr, am3offset:$offset), 2670 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru, 2671 "ldrd", "\t$Rt, $Rt2, $addr, $offset", 2672 "$addr.base = $Rn_wb", []> { 2673 bits<10> offset; 2674 bits<4> addr; 2675 let Inst{23} = offset{8}; // U bit 2676 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2677 let Inst{19-16} = addr; 2678 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2679 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2680 let DecoderMethod = "DecodeAddrMode3Instruction"; 2681} 2682} // hasExtraDefRegAllocReq = 1 2683} // mayLoad = 1, hasSideEffects = 0 2684 2685// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT. 2686let mayLoad = 1, hasSideEffects = 0 in { 2687def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2688 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2689 IndexModePost, LdFrm, IIC_iLoad_ru, 2690 "ldrt", "\t$Rt, $addr, $offset", 2691 "$addr.base = $Rn_wb", []> { 2692 // {12} isAdd 2693 // {11-0} imm12/Rm 2694 bits<14> offset; 2695 bits<4> addr; 2696 let Inst{25} = 1; 2697 let Inst{23} = offset{12}; 2698 let Inst{21} = 1; // overwrite 2699 let Inst{19-16} = addr; 2700 let Inst{11-5} = offset{11-5}; 2701 let Inst{4} = 0; 2702 let Inst{3-0} = offset{3-0}; 2703 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2704} 2705 2706def LDRT_POST_IMM 2707 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2708 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2709 IndexModePost, LdFrm, IIC_iLoad_ru, 2710 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2711 // {12} isAdd 2712 // {11-0} imm12/Rm 2713 bits<14> offset; 2714 bits<4> addr; 2715 let Inst{25} = 0; 2716 let Inst{23} = offset{12}; 2717 let Inst{21} = 1; // overwrite 2718 let Inst{19-16} = addr; 2719 let Inst{11-0} = offset{11-0}; 2720 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2721} 2722 2723def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2724 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2725 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2726 "ldrbt", "\t$Rt, $addr, $offset", 2727 "$addr.base = $Rn_wb", []> { 2728 // {12} isAdd 2729 // {11-0} imm12/Rm 2730 bits<14> offset; 2731 bits<4> addr; 2732 let Inst{25} = 1; 2733 let Inst{23} = offset{12}; 2734 let Inst{21} = 1; // overwrite 2735 let Inst{19-16} = addr; 2736 let Inst{11-5} = offset{11-5}; 2737 let Inst{4} = 0; 2738 let Inst{3-0} = offset{3-0}; 2739 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2740} 2741 2742def LDRBT_POST_IMM 2743 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2744 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2745 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2746 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2747 // {12} isAdd 2748 // {11-0} imm12/Rm 2749 bits<14> offset; 2750 bits<4> addr; 2751 let Inst{25} = 0; 2752 let Inst{23} = offset{12}; 2753 let Inst{21} = 1; // overwrite 2754 let Inst{19-16} = addr; 2755 let Inst{11-0} = offset{11-0}; 2756 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2757} 2758 2759multiclass AI3ldrT<bits<4> op, string opc> { 2760 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb), 2761 (ins addr_offset_none:$addr, postidx_imm8:$offset), 2762 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2763 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 2764 bits<9> offset; 2765 let Inst{23} = offset{8}; 2766 let Inst{22} = 1; 2767 let Inst{11-8} = offset{7-4}; 2768 let Inst{3-0} = offset{3-0}; 2769 } 2770 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb), 2771 (ins addr_offset_none:$addr, postidx_reg:$Rm), 2772 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2773 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 2774 bits<5> Rm; 2775 let Inst{23} = Rm{4}; 2776 let Inst{22} = 0; 2777 let Inst{11-8} = 0; 2778 let Unpredictable{11-8} = 0b1111; 2779 let Inst{3-0} = Rm{3-0}; 2780 let DecoderMethod = "DecodeLDR"; 2781 } 2782} 2783 2784defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">; 2785defm LDRHT : AI3ldrT<0b1011, "ldrht">; 2786defm LDRSHT : AI3ldrT<0b1111, "ldrsht">; 2787} 2788 2789def LDRT_POST 2790 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2791 (outs GPR:$Rt)>; 2792 2793def LDRBT_POST 2794 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2795 (outs GPR:$Rt)>; 2796 2797// Store 2798 2799// Stores with truncate 2800def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, 2801 IIC_iStore_bh_r, "strh", "\t$Rt, $addr", 2802 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>; 2803 2804// Store doubleword 2805let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 2806 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr), 2807 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>, 2808 Requires<[IsARM, HasV5TE]> { 2809 let Inst{21} = 0; 2810 } 2811} 2812 2813// Indexed stores 2814multiclass AI2_stridx<bit isByte, string opc, 2815 InstrItinClass iii, InstrItinClass iir> { 2816 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2817 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre, 2818 StFrm, iii, 2819 opc, "\t$Rt, $addr!", 2820 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2821 bits<17> addr; 2822 let Inst{25} = 0; 2823 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2824 let Inst{19-16} = addr{16-13}; // Rn 2825 let Inst{11-0} = addr{11-0}; // imm12 2826 let DecoderMethod = "DecodeSTRPreImm"; 2827 } 2828 2829 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2830 (ins GPR:$Rt, ldst_so_reg:$addr), 2831 IndexModePre, StFrm, iir, 2832 opc, "\t$Rt, $addr!", 2833 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2834 bits<17> addr; 2835 let Inst{25} = 1; 2836 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2837 let Inst{19-16} = addr{16-13}; // Rn 2838 let Inst{11-0} = addr{11-0}; 2839 let Inst{4} = 0; // Inst{4} = 0 2840 let DecoderMethod = "DecodeSTRPreReg"; 2841 } 2842 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2843 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2844 IndexModePost, StFrm, iir, 2845 opc, "\t$Rt, $addr, $offset", 2846 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2847 // {12} isAdd 2848 // {11-0} imm12/Rm 2849 bits<14> offset; 2850 bits<4> addr; 2851 let Inst{25} = 1; 2852 let Inst{23} = offset{12}; 2853 let Inst{19-16} = addr; 2854 let Inst{11-0} = offset{11-0}; 2855 let Inst{4} = 0; 2856 2857 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2858 } 2859 2860 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2861 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2862 IndexModePost, StFrm, iii, 2863 opc, "\t$Rt, $addr, $offset", 2864 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2865 // {12} isAdd 2866 // {11-0} imm12/Rm 2867 bits<14> offset; 2868 bits<4> addr; 2869 let Inst{25} = 0; 2870 let Inst{23} = offset{12}; 2871 let Inst{19-16} = addr; 2872 let Inst{11-0} = offset{11-0}; 2873 2874 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2875 } 2876} 2877 2878let mayStore = 1, hasSideEffects = 0 in { 2879// FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or 2880// IIC_iStore_siu depending on whether it the offset register is shifted. 2881defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>; 2882defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>; 2883} 2884 2885def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 2886 am2offset_reg:$offset), 2887 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr, 2888 am2offset_reg:$offset)>; 2889def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 2890 am2offset_imm:$offset), 2891 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr, 2892 am2offset_imm:$offset)>; 2893def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 2894 am2offset_reg:$offset), 2895 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr, 2896 am2offset_reg:$offset)>; 2897def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 2898 am2offset_imm:$offset), 2899 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr, 2900 am2offset_imm:$offset)>; 2901 2902// Pseudo-instructions for pattern matching the pre-indexed stores. We can't 2903// put the patterns on the instruction definitions directly as ISel wants 2904// the address base and offset to be separate operands, not a single 2905// complex operand like we represent the instructions themselves. The 2906// pseudos map between the two. 2907let usesCustomInserter = 1, 2908 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 2909def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2910 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 2911 4, IIC_iStore_ru, 2912 [(set GPR:$Rn_wb, 2913 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 2914def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2915 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 2916 4, IIC_iStore_ru, 2917 [(set GPR:$Rn_wb, 2918 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 2919def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2920 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 2921 4, IIC_iStore_ru, 2922 [(set GPR:$Rn_wb, 2923 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 2924def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2925 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 2926 4, IIC_iStore_ru, 2927 [(set GPR:$Rn_wb, 2928 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 2929def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2930 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p), 2931 4, IIC_iStore_ru, 2932 [(set GPR:$Rn_wb, 2933 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>; 2934} 2935 2936 2937 2938def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb), 2939 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre, 2940 StMiscFrm, IIC_iStore_bh_ru, 2941 "strh", "\t$Rt, $addr!", 2942 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2943 bits<14> addr; 2944 let Inst{23} = addr{8}; // U bit 2945 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2946 let Inst{19-16} = addr{12-9}; // Rn 2947 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2948 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2949 let DecoderMethod = "DecodeAddrMode3Instruction"; 2950} 2951 2952def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb), 2953 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset), 2954 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, 2955 "strh", "\t$Rt, $addr, $offset", 2956 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", 2957 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt, 2958 addr_offset_none:$addr, 2959 am3offset:$offset))]> { 2960 bits<10> offset; 2961 bits<4> addr; 2962 let Inst{23} = offset{8}; // U bit 2963 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2964 let Inst{19-16} = addr; 2965 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2966 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2967 let DecoderMethod = "DecodeAddrMode3Instruction"; 2968} 2969 2970let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 2971def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb), 2972 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr), 2973 IndexModePre, StMiscFrm, IIC_iStore_d_ru, 2974 "strd", "\t$Rt, $Rt2, $addr!", 2975 "$addr.base = $Rn_wb", []> { 2976 bits<14> addr; 2977 let Inst{23} = addr{8}; // U bit 2978 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2979 let Inst{19-16} = addr{12-9}; // Rn 2980 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2981 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2982 let DecoderMethod = "DecodeAddrMode3Instruction"; 2983} 2984 2985def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb), 2986 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr, 2987 am3offset:$offset), 2988 IndexModePost, StMiscFrm, IIC_iStore_d_ru, 2989 "strd", "\t$Rt, $Rt2, $addr, $offset", 2990 "$addr.base = $Rn_wb", []> { 2991 bits<10> offset; 2992 bits<4> addr; 2993 let Inst{23} = offset{8}; // U bit 2994 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2995 let Inst{19-16} = addr; 2996 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2997 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2998 let DecoderMethod = "DecodeAddrMode3Instruction"; 2999} 3000} // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 3001 3002// STRT, STRBT, and STRHT 3003 3004def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3005 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3006 IndexModePost, StFrm, IIC_iStore_bh_ru, 3007 "strbt", "\t$Rt, $addr, $offset", 3008 "$addr.base = $Rn_wb", []> { 3009 // {12} isAdd 3010 // {11-0} imm12/Rm 3011 bits<14> offset; 3012 bits<4> addr; 3013 let Inst{25} = 1; 3014 let Inst{23} = offset{12}; 3015 let Inst{21} = 1; // overwrite 3016 let Inst{19-16} = addr; 3017 let Inst{11-5} = offset{11-5}; 3018 let Inst{4} = 0; 3019 let Inst{3-0} = offset{3-0}; 3020 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3021} 3022 3023def STRBT_POST_IMM 3024 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3025 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3026 IndexModePost, StFrm, IIC_iStore_bh_ru, 3027 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3028 // {12} isAdd 3029 // {11-0} imm12/Rm 3030 bits<14> offset; 3031 bits<4> addr; 3032 let Inst{25} = 0; 3033 let Inst{23} = offset{12}; 3034 let Inst{21} = 1; // overwrite 3035 let Inst{19-16} = addr; 3036 let Inst{11-0} = offset{11-0}; 3037 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3038} 3039 3040def STRBT_POST 3041 : ARMAsmPseudo<"strbt${q} $Rt, $addr", 3042 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3043 3044let mayStore = 1, hasSideEffects = 0 in { 3045def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3046 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3047 IndexModePost, StFrm, IIC_iStore_ru, 3048 "strt", "\t$Rt, $addr, $offset", 3049 "$addr.base = $Rn_wb", []> { 3050 // {12} isAdd 3051 // {11-0} imm12/Rm 3052 bits<14> offset; 3053 bits<4> addr; 3054 let Inst{25} = 1; 3055 let Inst{23} = offset{12}; 3056 let Inst{21} = 1; // overwrite 3057 let Inst{19-16} = addr; 3058 let Inst{11-5} = offset{11-5}; 3059 let Inst{4} = 0; 3060 let Inst{3-0} = offset{3-0}; 3061 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3062} 3063 3064def STRT_POST_IMM 3065 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3066 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3067 IndexModePost, StFrm, IIC_iStore_ru, 3068 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3069 // {12} isAdd 3070 // {11-0} imm12/Rm 3071 bits<14> offset; 3072 bits<4> addr; 3073 let Inst{25} = 0; 3074 let Inst{23} = offset{12}; 3075 let Inst{21} = 1; // overwrite 3076 let Inst{19-16} = addr; 3077 let Inst{11-0} = offset{11-0}; 3078 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3079} 3080} 3081 3082def STRT_POST 3083 : ARMAsmPseudo<"strt${q} $Rt, $addr", 3084 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3085 3086multiclass AI3strT<bits<4> op, string opc> { 3087 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3088 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset), 3089 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3090 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 3091 bits<9> offset; 3092 let Inst{23} = offset{8}; 3093 let Inst{22} = 1; 3094 let Inst{11-8} = offset{7-4}; 3095 let Inst{3-0} = offset{3-0}; 3096 } 3097 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3098 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm), 3099 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3100 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 3101 bits<5> Rm; 3102 let Inst{23} = Rm{4}; 3103 let Inst{22} = 0; 3104 let Inst{11-8} = 0; 3105 let Inst{3-0} = Rm{3-0}; 3106 } 3107} 3108 3109 3110defm STRHT : AI3strT<0b1011, "strht">; 3111 3112def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3113 NoItinerary, "stl", "\t$Rt, $addr", []>; 3114def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3115 NoItinerary, "stlb", "\t$Rt, $addr", []>; 3116def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3117 NoItinerary, "stlh", "\t$Rt, $addr", []>; 3118 3119//===----------------------------------------------------------------------===// 3120// Load / store multiple Instructions. 3121// 3122 3123multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f, 3124 InstrItinClass itin, InstrItinClass itin_upd> { 3125 // IA is the default, so no need for an explicit suffix on the 3126 // mnemonic here. Without it is the canonical spelling. 3127 def IA : 3128 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3129 IndexModeNone, f, itin, 3130 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> { 3131 let Inst{24-23} = 0b01; // Increment After 3132 let Inst{22} = P_bit; 3133 let Inst{21} = 0; // No writeback 3134 let Inst{20} = L_bit; 3135 } 3136 def IA_UPD : 3137 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3138 IndexModeUpd, f, itin_upd, 3139 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3140 let Inst{24-23} = 0b01; // Increment After 3141 let Inst{22} = P_bit; 3142 let Inst{21} = 1; // Writeback 3143 let Inst{20} = L_bit; 3144 3145 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3146 } 3147 def DA : 3148 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3149 IndexModeNone, f, itin, 3150 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> { 3151 let Inst{24-23} = 0b00; // Decrement After 3152 let Inst{22} = P_bit; 3153 let Inst{21} = 0; // No writeback 3154 let Inst{20} = L_bit; 3155 } 3156 def DA_UPD : 3157 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3158 IndexModeUpd, f, itin_upd, 3159 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3160 let Inst{24-23} = 0b00; // Decrement After 3161 let Inst{22} = P_bit; 3162 let Inst{21} = 1; // Writeback 3163 let Inst{20} = L_bit; 3164 3165 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3166 } 3167 def DB : 3168 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3169 IndexModeNone, f, itin, 3170 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> { 3171 let Inst{24-23} = 0b10; // Decrement Before 3172 let Inst{22} = P_bit; 3173 let Inst{21} = 0; // No writeback 3174 let Inst{20} = L_bit; 3175 } 3176 def DB_UPD : 3177 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3178 IndexModeUpd, f, itin_upd, 3179 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3180 let Inst{24-23} = 0b10; // Decrement Before 3181 let Inst{22} = P_bit; 3182 let Inst{21} = 1; // Writeback 3183 let Inst{20} = L_bit; 3184 3185 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3186 } 3187 def IB : 3188 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3189 IndexModeNone, f, itin, 3190 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> { 3191 let Inst{24-23} = 0b11; // Increment Before 3192 let Inst{22} = P_bit; 3193 let Inst{21} = 0; // No writeback 3194 let Inst{20} = L_bit; 3195 } 3196 def IB_UPD : 3197 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3198 IndexModeUpd, f, itin_upd, 3199 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3200 let Inst{24-23} = 0b11; // Increment Before 3201 let Inst{22} = P_bit; 3202 let Inst{21} = 1; // Writeback 3203 let Inst{20} = L_bit; 3204 3205 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3206 } 3207} 3208 3209let hasSideEffects = 0 in { 3210 3211let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 3212defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m, 3213 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">; 3214 3215let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3216defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m, 3217 IIC_iStore_mu>, 3218 ComplexDeprecationPredicate<"ARMStore">; 3219 3220} // hasSideEffects 3221 3222// FIXME: remove when we have a way to marking a MI with these properties. 3223// FIXME: Should pc be an implicit operand like PICADD, etc? 3224let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 3225 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 3226def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 3227 reglist:$regs, variable_ops), 3228 4, IIC_iLoad_mBr, [], 3229 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 3230 RegConstraint<"$Rn = $wb">; 3231 3232let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 3233defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m, 3234 IIC_iLoad_mu>; 3235 3236let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3237defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m, 3238 IIC_iStore_mu>; 3239 3240 3241 3242//===----------------------------------------------------------------------===// 3243// Move Instructions. 3244// 3245 3246let hasSideEffects = 0 in 3247def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr, 3248 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3249 bits<4> Rd; 3250 bits<4> Rm; 3251 3252 let Inst{19-16} = 0b0000; 3253 let Inst{11-4} = 0b00000000; 3254 let Inst{25} = 0; 3255 let Inst{3-0} = Rm; 3256 let Inst{15-12} = Rd; 3257} 3258 3259// A version for the smaller set of tail call registers. 3260let hasSideEffects = 0 in 3261def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, 3262 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3263 bits<4> Rd; 3264 bits<4> Rm; 3265 3266 let Inst{11-4} = 0b00000000; 3267 let Inst{25} = 0; 3268 let Inst{3-0} = Rm; 3269 let Inst{15-12} = Rd; 3270} 3271 3272def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src), 3273 DPSoRegRegFrm, IIC_iMOVsr, 3274 "mov", "\t$Rd, $src", 3275 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP, 3276 Sched<[WriteALU]> { 3277 bits<4> Rd; 3278 bits<12> src; 3279 let Inst{15-12} = Rd; 3280 let Inst{19-16} = 0b0000; 3281 let Inst{11-8} = src{11-8}; 3282 let Inst{7} = 0; 3283 let Inst{6-5} = src{6-5}; 3284 let Inst{4} = 1; 3285 let Inst{3-0} = src{3-0}; 3286 let Inst{25} = 0; 3287} 3288 3289def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src), 3290 DPSoRegImmFrm, IIC_iMOVsr, 3291 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>, 3292 UnaryDP, Sched<[WriteALU]> { 3293 bits<4> Rd; 3294 bits<12> src; 3295 let Inst{15-12} = Rd; 3296 let Inst{19-16} = 0b0000; 3297 let Inst{11-5} = src{11-5}; 3298 let Inst{4} = 0; 3299 let Inst{3-0} = src{3-0}; 3300 let Inst{25} = 0; 3301} 3302 3303let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3304def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi, 3305 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP, 3306 Sched<[WriteALU]> { 3307 bits<4> Rd; 3308 bits<12> imm; 3309 let Inst{25} = 1; 3310 let Inst{15-12} = Rd; 3311 let Inst{19-16} = 0b0000; 3312 let Inst{11-0} = imm; 3313} 3314 3315let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3316def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm), 3317 DPFrm, IIC_iMOVi, 3318 "movw", "\t$Rd, $imm", 3319 [(set GPR:$Rd, imm0_65535:$imm)]>, 3320 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> { 3321 bits<4> Rd; 3322 bits<16> imm; 3323 let Inst{15-12} = Rd; 3324 let Inst{11-0} = imm{11-0}; 3325 let Inst{19-16} = imm{15-12}; 3326 let Inst{20} = 0; 3327 let Inst{25} = 1; 3328 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3329} 3330 3331def : InstAlias<"mov${p} $Rd, $imm", 3332 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>, 3333 Requires<[IsARM]>; 3334 3335def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3336 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3337 Sched<[WriteALU]>; 3338 3339let Constraints = "$src = $Rd" in { 3340def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd), 3341 (ins GPR:$src, imm0_65535_expr:$imm), 3342 DPFrm, IIC_iMOVi, 3343 "movt", "\t$Rd, $imm", 3344 [(set GPRnopc:$Rd, 3345 (or (and GPR:$src, 0xffff), 3346 lo16AllZero:$imm))]>, UnaryDP, 3347 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> { 3348 bits<4> Rd; 3349 bits<16> imm; 3350 let Inst{15-12} = Rd; 3351 let Inst{11-0} = imm{11-0}; 3352 let Inst{19-16} = imm{15-12}; 3353 let Inst{20} = 0; 3354 let Inst{25} = 1; 3355 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3356} 3357 3358def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3359 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3360 Sched<[WriteALU]>; 3361 3362} // Constraints 3363 3364def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>, 3365 Requires<[IsARM, HasV6T2]>; 3366 3367let Uses = [CPSR] in 3368def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, 3369 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP, 3370 Requires<[IsARM]>, Sched<[WriteALU]>; 3371 3372// These aren't really mov instructions, but we have to define them this way 3373// due to flag operands. 3374 3375let Defs = [CPSR] in { 3376def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3377 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP, 3378 Sched<[WriteALU]>, Requires<[IsARM]>; 3379def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3380 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP, 3381 Sched<[WriteALU]>, Requires<[IsARM]>; 3382} 3383 3384//===----------------------------------------------------------------------===// 3385// Extend Instructions. 3386// 3387 3388// Sign extenders 3389 3390def SXTB : AI_ext_rrot<0b01101010, 3391 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 3392def SXTH : AI_ext_rrot<0b01101011, 3393 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 3394 3395def SXTAB : AI_exta_rrot<0b01101010, 3396 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 3397def SXTAH : AI_exta_rrot<0b01101011, 3398 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 3399 3400def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; 3401 3402def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; 3403 3404// Zero extenders 3405 3406let AddedComplexity = 16 in { 3407def UXTB : AI_ext_rrot<0b01101110, 3408 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 3409def UXTH : AI_ext_rrot<0b01101111, 3410 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 3411def UXTB16 : AI_ext_rrot<0b01101100, 3412 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 3413 3414// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 3415// The transformation should probably be done as a combiner action 3416// instead so we can include a check for masking back in the upper 3417// eight bits of the source into the lower eight bits of the result. 3418//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 3419// (UXTB16r_rot GPR:$Src, 3)>; 3420def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 3421 (UXTB16 GPR:$Src, 1)>; 3422 3423def UXTAB : AI_exta_rrot<0b01101110, "uxtab", 3424 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 3425def UXTAH : AI_exta_rrot<0b01101111, "uxtah", 3426 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 3427} 3428 3429// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 3430def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; 3431 3432 3433def SBFX : I<(outs GPRnopc:$Rd), 3434 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3435 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3436 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3437 Requires<[IsARM, HasV6T2]> { 3438 bits<4> Rd; 3439 bits<4> Rn; 3440 bits<5> lsb; 3441 bits<5> width; 3442 let Inst{27-21} = 0b0111101; 3443 let Inst{6-4} = 0b101; 3444 let Inst{20-16} = width; 3445 let Inst{15-12} = Rd; 3446 let Inst{11-7} = lsb; 3447 let Inst{3-0} = Rn; 3448} 3449 3450def UBFX : I<(outs GPRnopc:$Rd), 3451 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3452 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3453 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3454 Requires<[IsARM, HasV6T2]> { 3455 bits<4> Rd; 3456 bits<4> Rn; 3457 bits<5> lsb; 3458 bits<5> width; 3459 let Inst{27-21} = 0b0111111; 3460 let Inst{6-4} = 0b101; 3461 let Inst{20-16} = width; 3462 let Inst{15-12} = Rd; 3463 let Inst{11-7} = lsb; 3464 let Inst{3-0} = Rn; 3465} 3466 3467//===----------------------------------------------------------------------===// 3468// Arithmetic Instructions. 3469// 3470 3471defm ADD : AsI1_bin_irs<0b0100, "add", 3472 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3473 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; 3474defm SUB : AsI1_bin_irs<0b0010, "sub", 3475 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3476 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 3477 3478// ADD and SUB with 's' bit set. 3479// 3480// Currently, ADDS/SUBS are pseudo opcodes that exist only in the 3481// selection DAG. They are "lowered" to real ADD/SUB opcodes by 3482// AdjustInstrPostInstrSelection where we determine whether or not to 3483// set the "s" bit based on CPSR liveness. 3484// 3485// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen 3486// support for an optional CPSR definition that corresponds to the DAG 3487// node's second value. We can then eliminate the implicit def of CPSR. 3488defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3489 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>; 3490defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3491 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; 3492 3493defm ADC : AI1_adde_sube_irs<0b0101, "adc", 3494 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>; 3495defm SBC : AI1_adde_sube_irs<0b0110, "sbc", 3496 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>; 3497 3498defm RSB : AsI1_rbin_irs<0b0011, "rsb", 3499 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3500 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 3501 3502// FIXME: Eliminate them if we can write def : Pat patterns which defines 3503// CPSR and the implicit def of CPSR is not needed. 3504defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3505 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; 3506 3507defm RSC : AI1_rsc_irs<0b0111, "rsc", 3508 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>; 3509 3510// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 3511// The assume-no-carry-in form uses the negation of the input since add/sub 3512// assume opposite meanings of the carry flag (i.e., carry == !borrow). 3513// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 3514// details. 3515def : ARMPat<(add GPR:$src, mod_imm_neg:$imm), 3516 (SUBri GPR:$src, mod_imm_neg:$imm)>; 3517def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm), 3518 (SUBSri GPR:$src, mod_imm_neg:$imm)>; 3519 3520def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm), 3521 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3522 Requires<[IsARM, HasV6T2]>; 3523def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm), 3524 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3525 Requires<[IsARM, HasV6T2]>; 3526 3527// The with-carry-in form matches bitwise not instead of the negation. 3528// Effectively, the inverse interpretation of the carry flag already accounts 3529// for part of the negation. 3530def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR), 3531 (SBCri GPR:$src, mod_imm_not:$imm)>; 3532def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR), 3533 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>, 3534 Requires<[IsARM, HasV6T2]>; 3535 3536// Note: These are implemented in C++ code, because they have to generate 3537// ADD/SUBrs instructions, which use a complex pattern that a xform function 3538// cannot produce. 3539// (mul X, 2^n+1) -> (add (X << n), X) 3540// (mul X, 2^n-1) -> (rsb X, (X << n)) 3541 3542// ARM Arithmetic Instruction 3543// GPR:$dst = GPR:$a op GPR:$b 3544class AAI<bits<8> op27_20, bits<8> op11_4, string opc, 3545 list<dag> pattern = [], 3546 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm), 3547 string asm = "\t$Rd, $Rn, $Rm"> 3548 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>, 3549 Sched<[WriteALU, ReadALU, ReadALU]> { 3550 bits<4> Rn; 3551 bits<4> Rd; 3552 bits<4> Rm; 3553 let Inst{27-20} = op27_20; 3554 let Inst{11-4} = op11_4; 3555 let Inst{19-16} = Rn; 3556 let Inst{15-12} = Rd; 3557 let Inst{3-0} = Rm; 3558 3559 let Unpredictable{11-8} = 0b1111; 3560} 3561 3562// Saturating add/subtract 3563 3564let DecoderMethod = "DecodeQADDInstruction" in 3565def QADD : AAI<0b00010000, 0b00000101, "qadd", 3566 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))], 3567 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">; 3568 3569def QSUB : AAI<0b00010010, 0b00000101, "qsub", 3570 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))], 3571 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">; 3572def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], 3573 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3574 "\t$Rd, $Rm, $Rn">; 3575def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], 3576 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3577 "\t$Rd, $Rm, $Rn">; 3578 3579def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">; 3580def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">; 3581def QASX : AAI<0b01100010, 0b11110011, "qasx">; 3582def QSAX : AAI<0b01100010, 0b11110101, "qsax">; 3583def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">; 3584def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">; 3585def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">; 3586def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">; 3587def UQASX : AAI<0b01100110, 0b11110011, "uqasx">; 3588def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">; 3589def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">; 3590def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">; 3591 3592// Signed/Unsigned add/subtract 3593 3594def SASX : AAI<0b01100001, 0b11110011, "sasx">; 3595def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">; 3596def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">; 3597def SSAX : AAI<0b01100001, 0b11110101, "ssax">; 3598def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">; 3599def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">; 3600def UASX : AAI<0b01100101, 0b11110011, "uasx">; 3601def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">; 3602def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">; 3603def USAX : AAI<0b01100101, 0b11110101, "usax">; 3604def USUB16 : AAI<0b01100101, 0b11110111, "usub16">; 3605def USUB8 : AAI<0b01100101, 0b11111111, "usub8">; 3606 3607// Signed/Unsigned halving add/subtract 3608 3609def SHASX : AAI<0b01100011, 0b11110011, "shasx">; 3610def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">; 3611def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">; 3612def SHSAX : AAI<0b01100011, 0b11110101, "shsax">; 3613def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">; 3614def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">; 3615def UHASX : AAI<0b01100111, 0b11110011, "uhasx">; 3616def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">; 3617def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">; 3618def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">; 3619def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">; 3620def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">; 3621 3622// Unsigned Sum of Absolute Differences [and Accumulate]. 3623 3624def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3625 MulFrm /* for convenience */, NoItinerary, "usad8", 3626 "\t$Rd, $Rn, $Rm", []>, 3627 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> { 3628 bits<4> Rd; 3629 bits<4> Rn; 3630 bits<4> Rm; 3631 let Inst{27-20} = 0b01111000; 3632 let Inst{15-12} = 0b1111; 3633 let Inst{7-4} = 0b0001; 3634 let Inst{19-16} = Rd; 3635 let Inst{11-8} = Rm; 3636 let Inst{3-0} = Rn; 3637} 3638def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3639 MulFrm /* for convenience */, NoItinerary, "usada8", 3640 "\t$Rd, $Rn, $Rm, $Ra", []>, 3641 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{ 3642 bits<4> Rd; 3643 bits<4> Rn; 3644 bits<4> Rm; 3645 bits<4> Ra; 3646 let Inst{27-20} = 0b01111000; 3647 let Inst{7-4} = 0b0001; 3648 let Inst{19-16} = Rd; 3649 let Inst{15-12} = Ra; 3650 let Inst{11-8} = Rm; 3651 let Inst{3-0} = Rn; 3652} 3653 3654// Signed/Unsigned saturate 3655 3656def SSAT : AI<(outs GPRnopc:$Rd), 3657 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3658 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> { 3659 bits<4> Rd; 3660 bits<5> sat_imm; 3661 bits<4> Rn; 3662 bits<8> sh; 3663 let Inst{27-21} = 0b0110101; 3664 let Inst{5-4} = 0b01; 3665 let Inst{20-16} = sat_imm; 3666 let Inst{15-12} = Rd; 3667 let Inst{11-7} = sh{4-0}; 3668 let Inst{6} = sh{5}; 3669 let Inst{3-0} = Rn; 3670} 3671 3672def SSAT16 : AI<(outs GPRnopc:$Rd), 3673 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm, 3674 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> { 3675 bits<4> Rd; 3676 bits<4> sat_imm; 3677 bits<4> Rn; 3678 let Inst{27-20} = 0b01101010; 3679 let Inst{11-4} = 0b11110011; 3680 let Inst{15-12} = Rd; 3681 let Inst{19-16} = sat_imm; 3682 let Inst{3-0} = Rn; 3683} 3684 3685def USAT : AI<(outs GPRnopc:$Rd), 3686 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3687 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> { 3688 bits<4> Rd; 3689 bits<5> sat_imm; 3690 bits<4> Rn; 3691 bits<8> sh; 3692 let Inst{27-21} = 0b0110111; 3693 let Inst{5-4} = 0b01; 3694 let Inst{15-12} = Rd; 3695 let Inst{11-7} = sh{4-0}; 3696 let Inst{6} = sh{5}; 3697 let Inst{20-16} = sat_imm; 3698 let Inst{3-0} = Rn; 3699} 3700 3701def USAT16 : AI<(outs GPRnopc:$Rd), 3702 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm, 3703 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> { 3704 bits<4> Rd; 3705 bits<4> sat_imm; 3706 bits<4> Rn; 3707 let Inst{27-20} = 0b01101110; 3708 let Inst{11-4} = 0b11110011; 3709 let Inst{15-12} = Rd; 3710 let Inst{19-16} = sat_imm; 3711 let Inst{3-0} = Rn; 3712} 3713 3714def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos), 3715 (SSAT imm1_32:$pos, GPRnopc:$a, 0)>; 3716def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos), 3717 (USAT imm0_31:$pos, GPRnopc:$a, 0)>; 3718 3719//===----------------------------------------------------------------------===// 3720// Bitwise Instructions. 3721// 3722 3723defm AND : AsI1_bin_irs<0b0000, "and", 3724 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3725 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; 3726defm ORR : AsI1_bin_irs<0b1100, "orr", 3727 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3728 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; 3729defm EOR : AsI1_bin_irs<0b0001, "eor", 3730 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3731 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; 3732defm BIC : AsI1_bin_irs<0b1110, "bic", 3733 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3734 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 3735 3736// FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just 3737// like in the actual instruction encoding. The complexity of mapping the mask 3738// to the lsb/msb pair should be handled by ISel, not encapsulated in the 3739// instruction description. 3740def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), 3741 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3742 "bfc", "\t$Rd, $imm", "$src = $Rd", 3743 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>, 3744 Requires<[IsARM, HasV6T2]> { 3745 bits<4> Rd; 3746 bits<10> imm; 3747 let Inst{27-21} = 0b0111110; 3748 let Inst{6-0} = 0b0011111; 3749 let Inst{15-12} = Rd; 3750 let Inst{11-7} = imm{4-0}; // lsb 3751 let Inst{20-16} = imm{9-5}; // msb 3752} 3753 3754// A8.6.18 BFI - Bitfield insert (Encoding A1) 3755def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm), 3756 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3757 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd", 3758 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn, 3759 bf_inv_mask_imm:$imm))]>, 3760 Requires<[IsARM, HasV6T2]> { 3761 bits<4> Rd; 3762 bits<4> Rn; 3763 bits<10> imm; 3764 let Inst{27-21} = 0b0111110; 3765 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 3766 let Inst{15-12} = Rd; 3767 let Inst{11-7} = imm{4-0}; // lsb 3768 let Inst{20-16} = imm{9-5}; // width 3769 let Inst{3-0} = Rn; 3770} 3771 3772def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr, 3773 "mvn", "\t$Rd, $Rm", 3774 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> { 3775 bits<4> Rd; 3776 bits<4> Rm; 3777 let Inst{25} = 0; 3778 let Inst{19-16} = 0b0000; 3779 let Inst{11-4} = 0b00000000; 3780 let Inst{15-12} = Rd; 3781 let Inst{3-0} = Rm; 3782} 3783def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift), 3784 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3785 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP, 3786 Sched<[WriteALU]> { 3787 bits<4> Rd; 3788 bits<12> shift; 3789 let Inst{25} = 0; 3790 let Inst{19-16} = 0b0000; 3791 let Inst{15-12} = Rd; 3792 let Inst{11-5} = shift{11-5}; 3793 let Inst{4} = 0; 3794 let Inst{3-0} = shift{3-0}; 3795} 3796def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift), 3797 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3798 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP, 3799 Sched<[WriteALU]> { 3800 bits<4> Rd; 3801 bits<12> shift; 3802 let Inst{25} = 0; 3803 let Inst{19-16} = 0b0000; 3804 let Inst{15-12} = Rd; 3805 let Inst{11-8} = shift{11-8}; 3806 let Inst{7} = 0; 3807 let Inst{6-5} = shift{6-5}; 3808 let Inst{4} = 1; 3809 let Inst{3-0} = shift{3-0}; 3810} 3811let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3812def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, 3813 IIC_iMVNi, "mvn", "\t$Rd, $imm", 3814 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> { 3815 bits<4> Rd; 3816 bits<12> imm; 3817 let Inst{25} = 1; 3818 let Inst{19-16} = 0b0000; 3819 let Inst{15-12} = Rd; 3820 let Inst{11-0} = imm; 3821} 3822 3823def : ARMPat<(and GPR:$src, mod_imm_not:$imm), 3824 (BICri GPR:$src, mod_imm_not:$imm)>; 3825 3826//===----------------------------------------------------------------------===// 3827// Multiply Instructions. 3828// 3829class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3830 string opc, string asm, list<dag> pattern> 3831 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3832 bits<4> Rd; 3833 bits<4> Rm; 3834 bits<4> Rn; 3835 let Inst{19-16} = Rd; 3836 let Inst{11-8} = Rm; 3837 let Inst{3-0} = Rn; 3838} 3839class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3840 string opc, string asm, list<dag> pattern> 3841 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3842 bits<4> RdLo; 3843 bits<4> RdHi; 3844 bits<4> Rm; 3845 bits<4> Rn; 3846 let Inst{19-16} = RdHi; 3847 let Inst{15-12} = RdLo; 3848 let Inst{11-8} = Rm; 3849 let Inst{3-0} = Rn; 3850} 3851class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3852 string opc, string asm, list<dag> pattern> 3853 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3854 bits<4> RdLo; 3855 bits<4> RdHi; 3856 bits<4> Rm; 3857 bits<4> Rn; 3858 let Inst{19-16} = RdHi; 3859 let Inst{15-12} = RdLo; 3860 let Inst{11-8} = Rm; 3861 let Inst{3-0} = Rn; 3862} 3863 3864// FIXME: The v5 pseudos are only necessary for the additional Constraint 3865// property. Remove them when it's possible to add those properties 3866// on an individual MachineInstr, not just an instruction description. 3867let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in { 3868def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), 3869 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3870 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", 3871 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>, 3872 Requires<[IsARM, HasV6]> { 3873 let Inst{15-12} = 0b0000; 3874 let Unpredictable{15-12} = 0b1111; 3875} 3876 3877let Constraints = "@earlyclobber $Rd" in 3878def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, 3879 pred:$p, cc_out:$s), 3880 4, IIC_iMUL32, 3881 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))], 3882 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 3883 Requires<[IsARM, NoV6, UseMulOps]>; 3884} 3885 3886def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd), 3887 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra), 3888 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra", 3889 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>, 3890 Requires<[IsARM, HasV6, UseMulOps]> { 3891 bits<4> Ra; 3892 let Inst{15-12} = Ra; 3893} 3894 3895let Constraints = "@earlyclobber $Rd" in 3896def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd), 3897 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 3898 pred:$p, cc_out:$s), 4, IIC_iMAC32, 3899 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))], 3900 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>, 3901 Requires<[IsARM, NoV6]>; 3902 3903def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3904 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra", 3905 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>, 3906 Requires<[IsARM, HasV6T2, UseMulOps]> { 3907 bits<4> Rd; 3908 bits<4> Rm; 3909 bits<4> Rn; 3910 bits<4> Ra; 3911 let Inst{19-16} = Rd; 3912 let Inst{15-12} = Ra; 3913 let Inst{11-8} = Rm; 3914 let Inst{3-0} = Rn; 3915} 3916 3917// Extra precision multiplies with low / high results 3918let hasSideEffects = 0 in { 3919let isCommutable = 1 in { 3920def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi), 3921 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 3922 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3923 Requires<[IsARM, HasV6]>; 3924 3925def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), 3926 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 3927 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3928 Requires<[IsARM, HasV6]>; 3929 3930let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { 3931def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3932 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 3933 4, IIC_iMUL64, [], 3934 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 3935 Requires<[IsARM, NoV6]>; 3936 3937def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3938 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 3939 4, IIC_iMUL64, [], 3940 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 3941 Requires<[IsARM, NoV6]>; 3942} 3943} 3944 3945// Multiply + accumulate 3946def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi), 3947 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 3948 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3949 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>; 3950def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi), 3951 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 3952 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3953 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>; 3954 3955def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi), 3956 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64, 3957 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3958 Requires<[IsARM, HasV6]> { 3959 bits<4> RdLo; 3960 bits<4> RdHi; 3961 bits<4> Rm; 3962 bits<4> Rn; 3963 let Inst{19-16} = RdHi; 3964 let Inst{15-12} = RdLo; 3965 let Inst{11-8} = Rm; 3966 let Inst{3-0} = Rn; 3967} 3968 3969let Constraints = 3970 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in { 3971def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3972 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 3973 4, IIC_iMAC64, [], 3974 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 3975 pred:$p, cc_out:$s)>, 3976 Requires<[IsARM, NoV6]>; 3977def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3978 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 3979 4, IIC_iMAC64, [], 3980 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 3981 pred:$p, cc_out:$s)>, 3982 Requires<[IsARM, NoV6]>; 3983} 3984 3985} // hasSideEffects 3986 3987// Most significant word multiply 3988def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3989 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm", 3990 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>, 3991 Requires<[IsARM, HasV6]> { 3992 let Inst{15-12} = 0b1111; 3993} 3994 3995def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3996 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>, 3997 Requires<[IsARM, HasV6]> { 3998 let Inst{15-12} = 0b1111; 3999} 4000 4001def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd), 4002 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4003 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra", 4004 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, 4005 Requires<[IsARM, HasV6, UseMulOps]>; 4006 4007def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd), 4008 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4009 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>, 4010 Requires<[IsARM, HasV6]>; 4011 4012def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd), 4013 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4014 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>, 4015 Requires<[IsARM, HasV6, UseMulOps]>; 4016 4017def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd), 4018 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4019 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>, 4020 Requires<[IsARM, HasV6]>; 4021 4022multiclass AI_smul<string opc, PatFrag opnode> { 4023 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4024 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 4025 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16), 4026 (sext_inreg GPR:$Rm, i16)))]>, 4027 Requires<[IsARM, HasV5TE]>; 4028 4029 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4030 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 4031 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16), 4032 (sra GPR:$Rm, (i32 16))))]>, 4033 Requires<[IsARM, HasV5TE]>; 4034 4035 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4036 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 4037 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)), 4038 (sext_inreg GPR:$Rm, i16)))]>, 4039 Requires<[IsARM, HasV5TE]>; 4040 4041 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4042 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 4043 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)), 4044 (sra GPR:$Rm, (i32 16))))]>, 4045 Requires<[IsARM, HasV5TE]>; 4046 4047 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4048 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 4049 []>, 4050 Requires<[IsARM, HasV5TE]>; 4051 4052 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4053 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 4054 []>, 4055 Requires<[IsARM, HasV5TE]>; 4056} 4057 4058 4059multiclass AI_smla<string opc, PatFrag opnode> { 4060 let DecoderMethod = "DecodeSMLAInstruction" in { 4061 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd), 4062 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4063 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 4064 [(set GPRnopc:$Rd, (add GPR:$Ra, 4065 (opnode (sext_inreg GPRnopc:$Rn, i16), 4066 (sext_inreg GPRnopc:$Rm, i16))))]>, 4067 Requires<[IsARM, HasV5TE, UseMulOps]>; 4068 4069 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd), 4070 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4071 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 4072 [(set GPRnopc:$Rd, 4073 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16), 4074 (sra GPRnopc:$Rm, (i32 16)))))]>, 4075 Requires<[IsARM, HasV5TE, UseMulOps]>; 4076 4077 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd), 4078 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4079 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 4080 [(set GPRnopc:$Rd, 4081 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)), 4082 (sext_inreg GPRnopc:$Rm, i16))))]>, 4083 Requires<[IsARM, HasV5TE, UseMulOps]>; 4084 4085 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd), 4086 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4087 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 4088 [(set GPRnopc:$Rd, 4089 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)), 4090 (sra GPRnopc:$Rm, (i32 16)))))]>, 4091 Requires<[IsARM, HasV5TE, UseMulOps]>; 4092 4093 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd), 4094 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4095 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 4096 []>, 4097 Requires<[IsARM, HasV5TE, UseMulOps]>; 4098 4099 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd), 4100 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4101 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 4102 []>, 4103 Requires<[IsARM, HasV5TE, UseMulOps]>; 4104 } 4105} 4106 4107defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 4108defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 4109 4110// Halfword multiply accumulate long: SMLAL<x><y>. 4111def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4112 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4113 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4114 Requires<[IsARM, HasV5TE]>; 4115 4116def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4117 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4118 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4119 Requires<[IsARM, HasV5TE]>; 4120 4121def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4122 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4123 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4124 Requires<[IsARM, HasV5TE]>; 4125 4126def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4127 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4128 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4129 Requires<[IsARM, HasV5TE]>; 4130 4131// Helper class for AI_smld. 4132class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops, 4133 InstrItinClass itin, string opc, string asm> 4134 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> { 4135 bits<4> Rn; 4136 bits<4> Rm; 4137 let Inst{27-23} = 0b01110; 4138 let Inst{22} = long; 4139 let Inst{21-20} = 0b00; 4140 let Inst{11-8} = Rm; 4141 let Inst{7} = 0; 4142 let Inst{6} = sub; 4143 let Inst{5} = swap; 4144 let Inst{4} = 1; 4145 let Inst{3-0} = Rn; 4146} 4147class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops, 4148 InstrItinClass itin, string opc, string asm> 4149 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4150 bits<4> Rd; 4151 let Inst{15-12} = 0b1111; 4152 let Inst{19-16} = Rd; 4153} 4154class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops, 4155 InstrItinClass itin, string opc, string asm> 4156 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4157 bits<4> Ra; 4158 bits<4> Rd; 4159 let Inst{19-16} = Rd; 4160 let Inst{15-12} = Ra; 4161} 4162class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops, 4163 InstrItinClass itin, string opc, string asm> 4164 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4165 bits<4> RdLo; 4166 bits<4> RdHi; 4167 let Inst{19-16} = RdHi; 4168 let Inst{15-12} = RdLo; 4169} 4170 4171multiclass AI_smld<bit sub, string opc> { 4172 4173 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd), 4174 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4175 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">; 4176 4177 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd), 4178 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4179 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">; 4180 4181 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4182 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary, 4183 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">; 4184 4185 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4186 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary, 4187 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">; 4188 4189} 4190 4191defm SMLA : AI_smld<0, "smla">; 4192defm SMLS : AI_smld<1, "smls">; 4193 4194multiclass AI_sdml<bit sub, string opc> { 4195 4196 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), 4197 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">; 4198 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm), 4199 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">; 4200} 4201 4202defm SMUA : AI_sdml<0, "smua">; 4203defm SMUS : AI_sdml<1, "smus">; 4204 4205//===----------------------------------------------------------------------===// 4206// Division Instructions (ARMv7-A with virtualization extension) 4207// 4208def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4209 "sdiv", "\t$Rd, $Rn, $Rm", 4210 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>, 4211 Requires<[IsARM, HasDivideInARM]>; 4212 4213def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4214 "udiv", "\t$Rd, $Rn, $Rm", 4215 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>, 4216 Requires<[IsARM, HasDivideInARM]>; 4217 4218//===----------------------------------------------------------------------===// 4219// Misc. Arithmetic Instructions. 4220// 4221 4222def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm), 4223 IIC_iUNAr, "clz", "\t$Rd, $Rm", 4224 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>, 4225 Sched<[WriteALU]>; 4226 4227def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4228 IIC_iUNAr, "rbit", "\t$Rd, $Rm", 4229 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>, 4230 Requires<[IsARM, HasV6T2]>, 4231 Sched<[WriteALU]>; 4232 4233def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4234 IIC_iUNAr, "rev", "\t$Rd, $Rm", 4235 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>, 4236 Sched<[WriteALU]>; 4237 4238let AddedComplexity = 5 in 4239def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4240 IIC_iUNAr, "rev16", "\t$Rd, $Rm", 4241 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>, 4242 Requires<[IsARM, HasV6]>, 4243 Sched<[WriteALU]>; 4244 4245def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)), 4246 (REV16 (LDRH addrmode3:$addr))>; 4247def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr), 4248 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>; 4249 4250let AddedComplexity = 5 in 4251def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4252 IIC_iUNAr, "revsh", "\t$Rd, $Rm", 4253 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>, 4254 Requires<[IsARM, HasV6]>, 4255 Sched<[WriteALU]>; 4256 4257def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)), 4258 (and (srl GPR:$Rm, (i32 8)), 0xFF)), 4259 (REVSH GPR:$Rm)>; 4260 4261def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd), 4262 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh), 4263 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 4264 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF), 4265 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh), 4266 0xFFFF0000)))]>, 4267 Requires<[IsARM, HasV6]>, 4268 Sched<[WriteALUsi, ReadALU]>; 4269 4270// Alternate cases for PKHBT where identities eliminate some nodes. 4271def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)), 4272 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>; 4273def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)), 4274 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>; 4275 4276// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 4277// will match the pattern below. 4278def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd), 4279 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh), 4280 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 4281 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000), 4282 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh), 4283 0xFFFF)))]>, 4284 Requires<[IsARM, HasV6]>, 4285 Sched<[WriteALUsi, ReadALU]>; 4286 4287// Alternate cases for PKHTB where identities eliminate some nodes. Note that 4288// a shift amount of 0 is *not legal* here, it is PKHBT instead. 4289// We also can not replace a srl (17..31) by an arithmetic shift we would use in 4290// pkhtb src1, src2, asr (17..31). 4291def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4292 (srl GPRnopc:$src2, imm16:$sh)), 4293 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>; 4294def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4295 (sra GPRnopc:$src2, imm16_31:$sh)), 4296 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>; 4297def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4298 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)), 4299 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>; 4300 4301//===----------------------------------------------------------------------===// 4302// CRC Instructions 4303// 4304// Polynomials: 4305// + CRC32{B,H,W} 0x04C11DB7 4306// + CRC32C{B,H,W} 0x1EDC6F41 4307// 4308 4309class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin> 4310 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary, 4311 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm", 4312 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>, 4313 Requires<[IsARM, HasV8, HasCRC]> { 4314 bits<4> Rd; 4315 bits<4> Rn; 4316 bits<4> Rm; 4317 4318 let Inst{31-28} = 0b1110; 4319 let Inst{27-23} = 0b00010; 4320 let Inst{22-21} = sz; 4321 let Inst{20} = 0; 4322 let Inst{19-16} = Rn; 4323 let Inst{15-12} = Rd; 4324 let Inst{11-10} = 0b00; 4325 let Inst{9} = C; 4326 let Inst{8} = 0; 4327 let Inst{7-4} = 0b0100; 4328 let Inst{3-0} = Rm; 4329 4330 let Unpredictable{11-8} = 0b1101; 4331} 4332 4333def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>; 4334def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>; 4335def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>; 4336def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>; 4337def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>; 4338def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>; 4339 4340//===----------------------------------------------------------------------===// 4341// ARMv8.1a Privilege Access Never extension 4342// 4343// SETPAN #imm1 4344 4345def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan", 4346 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> { 4347 bits<1> imm; 4348 4349 let Inst{31-28} = 0b1111; 4350 let Inst{27-20} = 0b00010001; 4351 let Inst{19-16} = 0b0000; 4352 let Inst{15-10} = 0b000000; 4353 let Inst{9} = imm; 4354 let Inst{8} = 0b0; 4355 let Inst{7-4} = 0b0000; 4356 let Inst{3-0} = 0b0000; 4357 4358 let Unpredictable{19-16} = 0b1111; 4359 let Unpredictable{15-10} = 0b111111; 4360 let Unpredictable{8} = 0b1; 4361 let Unpredictable{3-0} = 0b1111; 4362} 4363 4364//===----------------------------------------------------------------------===// 4365// Comparison Instructions... 4366// 4367 4368defm CMP : AI1_cmp_irs<0b1010, "cmp", 4369 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, 4370 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; 4371 4372// ARMcmpZ can re-use the above instruction definitions. 4373def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm), 4374 (CMPri GPR:$src, mod_imm:$imm)>; 4375def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs), 4376 (CMPrr GPR:$src, GPR:$rhs)>; 4377def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs), 4378 (CMPrsi GPR:$src, so_reg_imm:$rhs)>; 4379def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs), 4380 (CMPrsr GPR:$src, so_reg_reg:$rhs)>; 4381 4382// CMN register-integer 4383let isCompare = 1, Defs = [CPSR] in { 4384def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi, 4385 "cmn", "\t$Rn, $imm", 4386 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>, 4387 Sched<[WriteCMP, ReadALU]> { 4388 bits<4> Rn; 4389 bits<12> imm; 4390 let Inst{25} = 1; 4391 let Inst{20} = 1; 4392 let Inst{19-16} = Rn; 4393 let Inst{15-12} = 0b0000; 4394 let Inst{11-0} = imm; 4395 4396 let Unpredictable{15-12} = 0b1111; 4397} 4398 4399// CMN register-register/shift 4400def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr, 4401 "cmn", "\t$Rn, $Rm", 4402 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4403 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> { 4404 bits<4> Rn; 4405 bits<4> Rm; 4406 let isCommutable = 1; 4407 let Inst{25} = 0; 4408 let Inst{20} = 1; 4409 let Inst{19-16} = Rn; 4410 let Inst{15-12} = 0b0000; 4411 let Inst{11-4} = 0b00000000; 4412 let Inst{3-0} = Rm; 4413 4414 let Unpredictable{15-12} = 0b1111; 4415} 4416 4417def CMNzrsi : AI1<0b1011, (outs), 4418 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr, 4419 "cmn", "\t$Rn, $shift", 4420 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4421 GPR:$Rn, so_reg_imm:$shift)]>, 4422 Sched<[WriteCMPsi, ReadALU]> { 4423 bits<4> Rn; 4424 bits<12> shift; 4425 let Inst{25} = 0; 4426 let Inst{20} = 1; 4427 let Inst{19-16} = Rn; 4428 let Inst{15-12} = 0b0000; 4429 let Inst{11-5} = shift{11-5}; 4430 let Inst{4} = 0; 4431 let Inst{3-0} = shift{3-0}; 4432 4433 let Unpredictable{15-12} = 0b1111; 4434} 4435 4436def CMNzrsr : AI1<0b1011, (outs), 4437 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr, 4438 "cmn", "\t$Rn, $shift", 4439 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4440 GPRnopc:$Rn, so_reg_reg:$shift)]>, 4441 Sched<[WriteCMPsr, ReadALU]> { 4442 bits<4> Rn; 4443 bits<12> shift; 4444 let Inst{25} = 0; 4445 let Inst{20} = 1; 4446 let Inst{19-16} = Rn; 4447 let Inst{15-12} = 0b0000; 4448 let Inst{11-8} = shift{11-8}; 4449 let Inst{7} = 0; 4450 let Inst{6-5} = shift{6-5}; 4451 let Inst{4} = 1; 4452 let Inst{3-0} = shift{3-0}; 4453 4454 let Unpredictable{15-12} = 0b1111; 4455} 4456 4457} 4458 4459def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm), 4460 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4461 4462def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm), 4463 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4464 4465// Note that TST/TEQ don't set all the same flags that CMP does! 4466defm TST : AI1_cmp_irs<0b1000, "tst", 4467 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4468 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1, 4469 "DecodeTSTInstruction">; 4470defm TEQ : AI1_cmp_irs<0b1001, "teq", 4471 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4472 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>; 4473 4474// Pseudo i64 compares for some floating point compares. 4475let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, 4476 Defs = [CPSR] in { 4477def BCCi64 : PseudoInst<(outs), 4478 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst), 4479 IIC_Br, 4480 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>, 4481 Sched<[WriteBr]>; 4482 4483def BCCZi64 : PseudoInst<(outs), 4484 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, 4485 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>, 4486 Sched<[WriteBr]>; 4487} // usesCustomInserter 4488 4489 4490// Conditional moves 4491let hasSideEffects = 0 in { 4492 4493let isCommutable = 1, isSelect = 1 in 4494def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), 4495 (ins GPR:$false, GPR:$Rm, cmovpred:$p), 4496 4, IIC_iCMOVr, 4497 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, 4498 cmovpred:$p))]>, 4499 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4500 4501def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd), 4502 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p), 4503 4, IIC_iCMOVsr, 4504 [(set GPR:$Rd, 4505 (ARMcmov GPR:$false, so_reg_imm:$shift, 4506 cmovpred:$p))]>, 4507 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4508def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd), 4509 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p), 4510 4, IIC_iCMOVsr, 4511 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift, 4512 cmovpred:$p))]>, 4513 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4514 4515 4516let isMoveImm = 1 in 4517def MOVCCi16 4518 : ARMPseudoInst<(outs GPR:$Rd), 4519 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p), 4520 4, IIC_iMOVi, 4521 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm, 4522 cmovpred:$p))]>, 4523 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>, 4524 Sched<[WriteALU]>; 4525 4526let isMoveImm = 1 in 4527def MOVCCi : ARMPseudoInst<(outs GPR:$Rd), 4528 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 4529 4, IIC_iCMOVi, 4530 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm, 4531 cmovpred:$p))]>, 4532 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4533 4534// Two instruction predicate mov immediate. 4535let isMoveImm = 1 in 4536def MOVCCi32imm 4537 : ARMPseudoInst<(outs GPR:$Rd), 4538 (ins GPR:$false, i32imm:$src, cmovpred:$p), 4539 8, IIC_iCMOVix2, 4540 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src, 4541 cmovpred:$p))]>, 4542 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>; 4543 4544let isMoveImm = 1 in 4545def MVNCCi : ARMPseudoInst<(outs GPR:$Rd), 4546 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 4547 4, IIC_iCMOVi, 4548 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm, 4549 cmovpred:$p))]>, 4550 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4551 4552} // hasSideEffects 4553 4554 4555//===----------------------------------------------------------------------===// 4556// Atomic operations intrinsics 4557// 4558 4559def MemBarrierOptOperand : AsmOperandClass { 4560 let Name = "MemBarrierOpt"; 4561 let ParserMethod = "parseMemBarrierOptOperand"; 4562} 4563def memb_opt : Operand<i32> { 4564 let PrintMethod = "printMemBOption"; 4565 let ParserMatchClass = MemBarrierOptOperand; 4566 let DecoderMethod = "DecodeMemBarrierOption"; 4567} 4568 4569def InstSyncBarrierOptOperand : AsmOperandClass { 4570 let Name = "InstSyncBarrierOpt"; 4571 let ParserMethod = "parseInstSyncBarrierOptOperand"; 4572} 4573def instsyncb_opt : Operand<i32> { 4574 let PrintMethod = "printInstSyncBOption"; 4575 let ParserMatchClass = InstSyncBarrierOptOperand; 4576 let DecoderMethod = "DecodeInstSyncBarrierOption"; 4577} 4578 4579// Memory barriers protect the atomic sequences 4580let hasSideEffects = 1 in { 4581def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4582 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>, 4583 Requires<[IsARM, HasDB]> { 4584 bits<4> opt; 4585 let Inst{31-4} = 0xf57ff05; 4586 let Inst{3-0} = opt; 4587} 4588 4589def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4590 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>, 4591 Requires<[IsARM, HasDB]> { 4592 bits<4> opt; 4593 let Inst{31-4} = 0xf57ff04; 4594 let Inst{3-0} = opt; 4595} 4596 4597// ISB has only full system option 4598def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary, 4599 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>, 4600 Requires<[IsARM, HasDB]> { 4601 bits<4> opt; 4602 let Inst{31-4} = 0xf57ff06; 4603 let Inst{3-0} = opt; 4604} 4605} 4606 4607let usesCustomInserter = 1, Defs = [CPSR] in { 4608 4609// Pseudo instruction that combines movs + predicated rsbmi 4610// to implement integer ABS 4611 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>; 4612} 4613 4614let usesCustomInserter = 1 in { 4615 def COPY_STRUCT_BYVAL_I32 : PseudoInst< 4616 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment), 4617 NoItinerary, 4618 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>; 4619} 4620 4621let hasPostISelHook = 1, Constraints = "$newdst = $dst, $newsrc = $src" in { 4622 // %newsrc, %newdst = MEMCPY %dst, %src, N, ...N scratch regs... 4623 // Copies N registers worth of memory from address %src to address %dst 4624 // and returns the incremented addresses. N scratch register will 4625 // be attached for the copy to use. 4626 def MEMCPY : PseudoInst< 4627 (outs GPR:$newdst, GPR:$newsrc), 4628 (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops), 4629 NoItinerary, 4630 [(set GPR:$newdst, GPR:$newsrc, 4631 (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>; 4632} 4633 4634def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4635 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4636}]>; 4637 4638def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4639 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4640}]>; 4641 4642def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4643 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4644}]>; 4645 4646def strex_1 : PatFrag<(ops node:$val, node:$ptr), 4647 (int_arm_strex node:$val, node:$ptr), [{ 4648 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4649}]>; 4650 4651def strex_2 : PatFrag<(ops node:$val, node:$ptr), 4652 (int_arm_strex node:$val, node:$ptr), [{ 4653 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4654}]>; 4655 4656def strex_4 : PatFrag<(ops node:$val, node:$ptr), 4657 (int_arm_strex node:$val, node:$ptr), [{ 4658 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4659}]>; 4660 4661def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4662 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4663}]>; 4664 4665def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4666 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4667}]>; 4668 4669def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4670 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4671}]>; 4672 4673def stlex_1 : PatFrag<(ops node:$val, node:$ptr), 4674 (int_arm_stlex node:$val, node:$ptr), [{ 4675 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4676}]>; 4677 4678def stlex_2 : PatFrag<(ops node:$val, node:$ptr), 4679 (int_arm_stlex node:$val, node:$ptr), [{ 4680 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4681}]>; 4682 4683def stlex_4 : PatFrag<(ops node:$val, node:$ptr), 4684 (int_arm_stlex node:$val, node:$ptr), [{ 4685 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4686}]>; 4687 4688let mayLoad = 1 in { 4689def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4690 NoItinerary, "ldrexb", "\t$Rt, $addr", 4691 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>; 4692def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4693 NoItinerary, "ldrexh", "\t$Rt, $addr", 4694 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>; 4695def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4696 NoItinerary, "ldrex", "\t$Rt, $addr", 4697 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>; 4698let hasExtraDefRegAllocReq = 1 in 4699def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 4700 NoItinerary, "ldrexd", "\t$Rt, $addr", []> { 4701 let DecoderMethod = "DecodeDoubleRegLoad"; 4702} 4703 4704def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4705 NoItinerary, "ldaexb", "\t$Rt, $addr", 4706 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>; 4707def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4708 NoItinerary, "ldaexh", "\t$Rt, $addr", 4709 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>; 4710def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4711 NoItinerary, "ldaex", "\t$Rt, $addr", 4712 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>; 4713let hasExtraDefRegAllocReq = 1 in 4714def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 4715 NoItinerary, "ldaexd", "\t$Rt, $addr", []> { 4716 let DecoderMethod = "DecodeDoubleRegLoad"; 4717} 4718} 4719 4720let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 4721def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4722 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", 4723 [(set GPR:$Rd, (strex_1 GPR:$Rt, 4724 addr_offset_none:$addr))]>; 4725def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4726 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", 4727 [(set GPR:$Rd, (strex_2 GPR:$Rt, 4728 addr_offset_none:$addr))]>; 4729def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4730 NoItinerary, "strex", "\t$Rd, $Rt, $addr", 4731 [(set GPR:$Rd, (strex_4 GPR:$Rt, 4732 addr_offset_none:$addr))]>; 4733let hasExtraSrcRegAllocReq = 1 in 4734def STREXD : AIstrex<0b01, (outs GPR:$Rd), 4735 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 4736 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> { 4737 let DecoderMethod = "DecodeDoubleRegStore"; 4738} 4739def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4740 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr", 4741 [(set GPR:$Rd, 4742 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>; 4743def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4744 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr", 4745 [(set GPR:$Rd, 4746 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>; 4747def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4748 NoItinerary, "stlex", "\t$Rd, $Rt, $addr", 4749 [(set GPR:$Rd, 4750 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>; 4751let hasExtraSrcRegAllocReq = 1 in 4752def STLEXD : AIstlex<0b01, (outs GPR:$Rd), 4753 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 4754 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> { 4755 let DecoderMethod = "DecodeDoubleRegStore"; 4756} 4757} 4758 4759def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", 4760 [(int_arm_clrex)]>, 4761 Requires<[IsARM, HasV6K]> { 4762 let Inst{31-0} = 0b11110101011111111111000000011111; 4763} 4764 4765def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 4766 (STREXB GPR:$Rt, addr_offset_none:$addr)>; 4767def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 4768 (STREXH GPR:$Rt, addr_offset_none:$addr)>; 4769 4770def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 4771 (STLEXB GPR:$Rt, addr_offset_none:$addr)>; 4772def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 4773 (STLEXH GPR:$Rt, addr_offset_none:$addr)>; 4774 4775class acquiring_load<PatFrag base> 4776 : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 4777 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 4778 return isAtLeastAcquire(Ordering); 4779}]>; 4780 4781def atomic_load_acquire_8 : acquiring_load<atomic_load_8>; 4782def atomic_load_acquire_16 : acquiring_load<atomic_load_16>; 4783def atomic_load_acquire_32 : acquiring_load<atomic_load_32>; 4784 4785class releasing_store<PatFrag base> 4786 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 4787 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 4788 return isAtLeastRelease(Ordering); 4789}]>; 4790 4791def atomic_store_release_8 : releasing_store<atomic_store_8>; 4792def atomic_store_release_16 : releasing_store<atomic_store_16>; 4793def atomic_store_release_32 : releasing_store<atomic_store_32>; 4794 4795let AddedComplexity = 8 in { 4796 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>; 4797 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>; 4798 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>; 4799 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>; 4800 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>; 4801 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>; 4802} 4803 4804// SWP/SWPB are deprecated in V6/V7. 4805let mayLoad = 1, mayStore = 1 in { 4806def SWP : AIswp<0, (outs GPRnopc:$Rt), 4807 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>, 4808 Requires<[PreV8]>; 4809def SWPB: AIswp<1, (outs GPRnopc:$Rt), 4810 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>, 4811 Requires<[PreV8]>; 4812} 4813 4814//===----------------------------------------------------------------------===// 4815// Coprocessor Instructions. 4816// 4817 4818def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4819 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4820 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4821 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4822 imm:$CRm, imm:$opc2)]>, 4823 Requires<[PreV8]> { 4824 bits<4> opc1; 4825 bits<4> CRn; 4826 bits<4> CRd; 4827 bits<4> cop; 4828 bits<3> opc2; 4829 bits<4> CRm; 4830 4831 let Inst{3-0} = CRm; 4832 let Inst{4} = 0; 4833 let Inst{7-5} = opc2; 4834 let Inst{11-8} = cop; 4835 let Inst{15-12} = CRd; 4836 let Inst{19-16} = CRn; 4837 let Inst{23-20} = opc1; 4838} 4839 4840def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4841 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4842 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4843 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4844 imm:$CRm, imm:$opc2)]>, 4845 Requires<[PreV8]> { 4846 let Inst{31-28} = 0b1111; 4847 bits<4> opc1; 4848 bits<4> CRn; 4849 bits<4> CRd; 4850 bits<4> cop; 4851 bits<3> opc2; 4852 bits<4> CRm; 4853 4854 let Inst{3-0} = CRm; 4855 let Inst{4} = 0; 4856 let Inst{7-5} = opc2; 4857 let Inst{11-8} = cop; 4858 let Inst{15-12} = CRd; 4859 let Inst{19-16} = CRn; 4860 let Inst{23-20} = opc1; 4861} 4862 4863class ACI<dag oops, dag iops, string opc, string asm, 4864 IndexMode im = IndexModeNone> 4865 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 4866 opc, asm, "", []> { 4867 let Inst{27-25} = 0b110; 4868} 4869class ACInoP<dag oops, dag iops, string opc, string asm, 4870 IndexMode im = IndexModeNone> 4871 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 4872 opc, asm, "", []> { 4873 let Inst{31-28} = 0b1111; 4874 let Inst{27-25} = 0b110; 4875} 4876multiclass LdStCop<bit load, bit Dbit, string asm> { 4877 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 4878 asm, "\t$cop, $CRd, $addr"> { 4879 bits<13> addr; 4880 bits<4> cop; 4881 bits<4> CRd; 4882 let Inst{24} = 1; // P = 1 4883 let Inst{23} = addr{8}; 4884 let Inst{22} = Dbit; 4885 let Inst{21} = 0; // W = 0 4886 let Inst{20} = load; 4887 let Inst{19-16} = addr{12-9}; 4888 let Inst{15-12} = CRd; 4889 let Inst{11-8} = cop; 4890 let Inst{7-0} = addr{7-0}; 4891 let DecoderMethod = "DecodeCopMemInstruction"; 4892 } 4893 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 4894 asm, "\t$cop, $CRd, $addr!", IndexModePre> { 4895 bits<13> addr; 4896 bits<4> cop; 4897 bits<4> CRd; 4898 let Inst{24} = 1; // P = 1 4899 let Inst{23} = addr{8}; 4900 let Inst{22} = Dbit; 4901 let Inst{21} = 1; // W = 1 4902 let Inst{20} = load; 4903 let Inst{19-16} = addr{12-9}; 4904 let Inst{15-12} = CRd; 4905 let Inst{11-8} = cop; 4906 let Inst{7-0} = addr{7-0}; 4907 let DecoderMethod = "DecodeCopMemInstruction"; 4908 } 4909 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4910 postidx_imm8s4:$offset), 4911 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> { 4912 bits<9> offset; 4913 bits<4> addr; 4914 bits<4> cop; 4915 bits<4> CRd; 4916 let Inst{24} = 0; // P = 0 4917 let Inst{23} = offset{8}; 4918 let Inst{22} = Dbit; 4919 let Inst{21} = 1; // W = 1 4920 let Inst{20} = load; 4921 let Inst{19-16} = addr; 4922 let Inst{15-12} = CRd; 4923 let Inst{11-8} = cop; 4924 let Inst{7-0} = offset{7-0}; 4925 let DecoderMethod = "DecodeCopMemInstruction"; 4926 } 4927 def _OPTION : ACI<(outs), 4928 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4929 coproc_option_imm:$option), 4930 asm, "\t$cop, $CRd, $addr, $option"> { 4931 bits<8> option; 4932 bits<4> addr; 4933 bits<4> cop; 4934 bits<4> CRd; 4935 let Inst{24} = 0; // P = 0 4936 let Inst{23} = 1; // U = 1 4937 let Inst{22} = Dbit; 4938 let Inst{21} = 0; // W = 0 4939 let Inst{20} = load; 4940 let Inst{19-16} = addr; 4941 let Inst{15-12} = CRd; 4942 let Inst{11-8} = cop; 4943 let Inst{7-0} = option; 4944 let DecoderMethod = "DecodeCopMemInstruction"; 4945 } 4946} 4947multiclass LdSt2Cop<bit load, bit Dbit, string asm> { 4948 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 4949 asm, "\t$cop, $CRd, $addr"> { 4950 bits<13> addr; 4951 bits<4> cop; 4952 bits<4> CRd; 4953 let Inst{24} = 1; // P = 1 4954 let Inst{23} = addr{8}; 4955 let Inst{22} = Dbit; 4956 let Inst{21} = 0; // W = 0 4957 let Inst{20} = load; 4958 let Inst{19-16} = addr{12-9}; 4959 let Inst{15-12} = CRd; 4960 let Inst{11-8} = cop; 4961 let Inst{7-0} = addr{7-0}; 4962 let DecoderMethod = "DecodeCopMemInstruction"; 4963 } 4964 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 4965 asm, "\t$cop, $CRd, $addr!", IndexModePre> { 4966 bits<13> addr; 4967 bits<4> cop; 4968 bits<4> CRd; 4969 let Inst{24} = 1; // P = 1 4970 let Inst{23} = addr{8}; 4971 let Inst{22} = Dbit; 4972 let Inst{21} = 1; // W = 1 4973 let Inst{20} = load; 4974 let Inst{19-16} = addr{12-9}; 4975 let Inst{15-12} = CRd; 4976 let Inst{11-8} = cop; 4977 let Inst{7-0} = addr{7-0}; 4978 let DecoderMethod = "DecodeCopMemInstruction"; 4979 } 4980 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4981 postidx_imm8s4:$offset), 4982 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> { 4983 bits<9> offset; 4984 bits<4> addr; 4985 bits<4> cop; 4986 bits<4> CRd; 4987 let Inst{24} = 0; // P = 0 4988 let Inst{23} = offset{8}; 4989 let Inst{22} = Dbit; 4990 let Inst{21} = 1; // W = 1 4991 let Inst{20} = load; 4992 let Inst{19-16} = addr; 4993 let Inst{15-12} = CRd; 4994 let Inst{11-8} = cop; 4995 let Inst{7-0} = offset{7-0}; 4996 let DecoderMethod = "DecodeCopMemInstruction"; 4997 } 4998 def _OPTION : ACInoP<(outs), 4999 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5000 coproc_option_imm:$option), 5001 asm, "\t$cop, $CRd, $addr, $option"> { 5002 bits<8> option; 5003 bits<4> addr; 5004 bits<4> cop; 5005 bits<4> CRd; 5006 let Inst{24} = 0; // P = 0 5007 let Inst{23} = 1; // U = 1 5008 let Inst{22} = Dbit; 5009 let Inst{21} = 0; // W = 0 5010 let Inst{20} = load; 5011 let Inst{19-16} = addr; 5012 let Inst{15-12} = CRd; 5013 let Inst{11-8} = cop; 5014 let Inst{7-0} = option; 5015 let DecoderMethod = "DecodeCopMemInstruction"; 5016 } 5017} 5018 5019defm LDC : LdStCop <1, 0, "ldc">; 5020defm LDCL : LdStCop <1, 1, "ldcl">; 5021defm STC : LdStCop <0, 0, "stc">; 5022defm STCL : LdStCop <0, 1, "stcl">; 5023defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>; 5024defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>; 5025defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>; 5026defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>; 5027 5028//===----------------------------------------------------------------------===// 5029// Move between coprocessor and ARM core register. 5030// 5031 5032class MovRCopro<string opc, bit direction, dag oops, dag iops, 5033 list<dag> pattern> 5034 : ABI<0b1110, oops, iops, NoItinerary, opc, 5035 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> { 5036 let Inst{20} = direction; 5037 let Inst{4} = 1; 5038 5039 bits<4> Rt; 5040 bits<4> cop; 5041 bits<3> opc1; 5042 bits<3> opc2; 5043 bits<4> CRm; 5044 bits<4> CRn; 5045 5046 let Inst{15-12} = Rt; 5047 let Inst{11-8} = cop; 5048 let Inst{23-21} = opc1; 5049 let Inst{7-5} = opc2; 5050 let Inst{3-0} = CRm; 5051 let Inst{19-16} = CRn; 5052} 5053 5054def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */, 5055 (outs), 5056 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5057 c_imm:$CRm, imm0_7:$opc2), 5058 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 5059 imm:$CRm, imm:$opc2)]>, 5060 ComplexDeprecationPredicate<"MCR">; 5061def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 5062 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5063 c_imm:$CRm, 0, pred:$p)>; 5064def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, 5065 (outs GPRwithAPSR:$Rt), 5066 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5067 imm0_7:$opc2), []>; 5068def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", 5069 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5070 c_imm:$CRm, 0, pred:$p)>; 5071 5072def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 5073 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 5074 5075class MovRCopro2<string opc, bit direction, dag oops, dag iops, 5076 list<dag> pattern> 5077 : ABXI<0b1110, oops, iops, NoItinerary, 5078 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> { 5079 let Inst{31-24} = 0b11111110; 5080 let Inst{20} = direction; 5081 let Inst{4} = 1; 5082 5083 bits<4> Rt; 5084 bits<4> cop; 5085 bits<3> opc1; 5086 bits<3> opc2; 5087 bits<4> CRm; 5088 bits<4> CRn; 5089 5090 let Inst{15-12} = Rt; 5091 let Inst{11-8} = cop; 5092 let Inst{23-21} = opc1; 5093 let Inst{7-5} = opc2; 5094 let Inst{3-0} = CRm; 5095 let Inst{19-16} = CRn; 5096} 5097 5098def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */, 5099 (outs), 5100 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5101 c_imm:$CRm, imm0_7:$opc2), 5102 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 5103 imm:$CRm, imm:$opc2)]>, 5104 Requires<[PreV8]>; 5105def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm", 5106 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5107 c_imm:$CRm, 0)>; 5108def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, 5109 (outs GPRwithAPSR:$Rt), 5110 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5111 imm0_7:$opc2), []>, 5112 Requires<[PreV8]>; 5113def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm", 5114 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5115 c_imm:$CRm, 0)>; 5116 5117def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, 5118 imm:$CRm, imm:$opc2), 5119 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 5120 5121class MovRRCopro<string opc, bit direction, dag oops, dag iops, list<dag> 5122 pattern = []> 5123 : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", 5124 pattern> { 5125 5126 let Inst{23-21} = 0b010; 5127 let Inst{20} = direction; 5128 5129 bits<4> Rt; 5130 bits<4> Rt2; 5131 bits<4> cop; 5132 bits<4> opc1; 5133 bits<4> CRm; 5134 5135 let Inst{15-12} = Rt; 5136 let Inst{19-16} = Rt2; 5137 let Inst{11-8} = cop; 5138 let Inst{7-4} = opc1; 5139 let Inst{3-0} = CRm; 5140} 5141 5142def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */, 5143 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5144 GPRnopc:$Rt2, c_imm:$CRm), 5145 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt, 5146 GPRnopc:$Rt2, imm:$CRm)]>; 5147def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */, 5148 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5149 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5150 5151class MovRRCopro2<string opc, bit direction, list<dag> pattern = []> 5152 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5153 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary, 5154 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>, 5155 Requires<[PreV8]> { 5156 let Inst{31-28} = 0b1111; 5157 let Inst{23-21} = 0b010; 5158 let Inst{20} = direction; 5159 5160 bits<4> Rt; 5161 bits<4> Rt2; 5162 bits<4> cop; 5163 bits<4> opc1; 5164 bits<4> CRm; 5165 5166 let Inst{15-12} = Rt; 5167 let Inst{19-16} = Rt2; 5168 let Inst{11-8} = cop; 5169 let Inst{7-4} = opc1; 5170 let Inst{3-0} = CRm; 5171 5172 let DecoderMethod = "DecodeMRRC2"; 5173} 5174 5175def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */, 5176 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt, 5177 GPRnopc:$Rt2, imm:$CRm)]>; 5178def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>; 5179 5180//===----------------------------------------------------------------------===// 5181// Move between special register and ARM core register 5182// 5183 5184// Move to ARM core register from Special Register 5185def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5186 "mrs", "\t$Rd, apsr", []> { 5187 bits<4> Rd; 5188 let Inst{23-16} = 0b00001111; 5189 let Unpredictable{19-17} = 0b111; 5190 5191 let Inst{15-12} = Rd; 5192 5193 let Inst{11-0} = 0b000000000000; 5194 let Unpredictable{11-0} = 0b110100001111; 5195} 5196 5197def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>, 5198 Requires<[IsARM]>; 5199 5200// The MRSsys instruction is the MRS instruction from the ARM ARM, 5201// section B9.3.9, with the R bit set to 1. 5202def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5203 "mrs", "\t$Rd, spsr", []> { 5204 bits<4> Rd; 5205 let Inst{23-16} = 0b01001111; 5206 let Unpredictable{19-16} = 0b1111; 5207 5208 let Inst{15-12} = Rd; 5209 5210 let Inst{11-0} = 0b000000000000; 5211 let Unpredictable{11-0} = 0b110100001111; 5212} 5213 5214// However, the MRS (banked register) system instruction (ARMv7VE) *does* have a 5215// separate encoding (distinguished by bit 5. 5216def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked), 5217 NoItinerary, "mrs", "\t$Rd, $banked", []>, 5218 Requires<[IsARM, HasVirtualization]> { 5219 bits<6> banked; 5220 bits<4> Rd; 5221 5222 let Inst{23} = 0; 5223 let Inst{22} = banked{5}; // R bit 5224 let Inst{21-20} = 0b00; 5225 let Inst{19-16} = banked{3-0}; 5226 let Inst{15-12} = Rd; 5227 let Inst{11-9} = 0b001; 5228 let Inst{8} = banked{4}; 5229 let Inst{7-0} = 0b00000000; 5230} 5231 5232// Move from ARM core register to Special Register 5233// 5234// No need to have both system and application versions of MSR (immediate) or 5235// MSR (register), the encodings are the same and the assembly parser has no way 5236// to distinguish between them. The mask operand contains the special register 5237// (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be 5238// accessed in the special register. 5239def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, 5240 "msr", "\t$mask, $Rn", []> { 5241 bits<5> mask; 5242 bits<4> Rn; 5243 5244 let Inst{23} = 0; 5245 let Inst{22} = mask{4}; // R bit 5246 let Inst{21-20} = 0b10; 5247 let Inst{19-16} = mask{3-0}; 5248 let Inst{15-12} = 0b1111; 5249 let Inst{11-4} = 0b00000000; 5250 let Inst{3-0} = Rn; 5251} 5252 5253def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary, 5254 "msr", "\t$mask, $imm", []> { 5255 bits<5> mask; 5256 bits<12> imm; 5257 5258 let Inst{23} = 0; 5259 let Inst{22} = mask{4}; // R bit 5260 let Inst{21-20} = 0b10; 5261 let Inst{19-16} = mask{3-0}; 5262 let Inst{15-12} = 0b1111; 5263 let Inst{11-0} = imm; 5264} 5265 5266// However, the MSR (banked register) system instruction (ARMv7VE) *does* have a 5267// separate encoding (distinguished by bit 5. 5268def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn), 5269 NoItinerary, "msr", "\t$banked, $Rn", []>, 5270 Requires<[IsARM, HasVirtualization]> { 5271 bits<6> banked; 5272 bits<4> Rn; 5273 5274 let Inst{23} = 0; 5275 let Inst{22} = banked{5}; // R bit 5276 let Inst{21-20} = 0b10; 5277 let Inst{19-16} = banked{3-0}; 5278 let Inst{15-12} = 0b1111; 5279 let Inst{11-9} = 0b001; 5280 let Inst{8} = banked{4}; 5281 let Inst{7-4} = 0b0000; 5282 let Inst{3-0} = Rn; 5283} 5284 5285// Dynamic stack allocation yields a _chkstk for Windows targets. These calls 5286// are needed to probe the stack when allocating more than 5287// 4k bytes in one go. Touching the stack at 4K increments is necessary to 5288// ensure that the guard pages used by the OS virtual memory manager are 5289// allocated in correct sequence. 5290// The main point of having separate instruction are extra unmodelled effects 5291// (compared to ordinary calls) like stack pointer change. 5292 5293def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone, 5294 [SDNPHasChain, SDNPSideEffect]>; 5295let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in 5296 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>; 5297 5298def win__dbzchk : SDNode<"ARMISD::WIN__DBZCHK", SDT_WIN__DBZCHK, 5299 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 5300let usesCustomInserter = 1, Defs = [CPSR] in 5301 def WIN__DBZCHK : PseudoInst<(outs), (ins GPR:$divisor), NoItinerary, 5302 [(win__dbzchk GPR:$divisor)]>; 5303 5304//===----------------------------------------------------------------------===// 5305// TLS Instructions 5306// 5307 5308// __aeabi_read_tp preserves the registers r1-r3. 5309// This is a pseudo inst so that we can get the encoding right, 5310// complete with fixup for the aeabi_read_tp function. 5311// TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern 5312// is defined in "ARMInstrThumb.td". 5313let isCall = 1, 5314 Defs = [R0, R12, LR, CPSR], Uses = [SP] in { 5315 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br, 5316 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>; 5317} 5318 5319//===----------------------------------------------------------------------===// 5320// SJLJ Exception handling intrinsics 5321// eh_sjlj_setjmp() is an instruction sequence to store the return 5322// address and save #0 in R0 for the non-longjmp case. 5323// Since by its nature we may be coming from some other function to get 5324// here, and we're using the stack frame for the containing function to 5325// save/restore registers, we can't keep anything live in regs across 5326// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 5327// when we get here from a longjmp(). We force everything out of registers 5328// except for our own input by listing the relevant registers in Defs. By 5329// doing so, we also cause the prologue/epilogue code to actively preserve 5330// all of the callee-saved resgisters, which is exactly what we want. 5331// A constant value is passed in $val, and we use the location as a scratch. 5332// 5333// These are pseudo-instructions and are lowered to individual MC-insts, so 5334// no encoding information is necessary. 5335let Defs = 5336 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 5337 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ], 5338 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5339 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5340 NoItinerary, 5341 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5342 Requires<[IsARM, HasVFP2]>; 5343} 5344 5345let Defs = 5346 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 5347 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5348 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5349 NoItinerary, 5350 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5351 Requires<[IsARM, NoVFP]>; 5352} 5353 5354// FIXME: Non-IOS version(s) 5355let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, 5356 Defs = [ R7, LR, SP ] in { 5357def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch), 5358 NoItinerary, 5359 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 5360 Requires<[IsARM]>; 5361} 5362 5363let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in 5364def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary, 5365 [(ARMeh_sjlj_setup_dispatch)]>; 5366 5367// eh.sjlj.dispatchsetup pseudo-instruction. 5368// This pseudo is used for both ARM and Thumb. Any differences are handled when 5369// the pseudo is expanded (which happens before any passes that need the 5370// instruction size). 5371let isBarrier = 1 in 5372def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>; 5373 5374 5375//===----------------------------------------------------------------------===// 5376// Non-Instruction Patterns 5377// 5378 5379// ARMv4 indirect branch using (MOVr PC, dst) 5380let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in 5381 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst), 5382 4, IIC_Br, [(brind GPR:$dst)], 5383 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5384 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5385 5386// Large immediate handling. 5387 5388// 32-bit immediate using two piece mod_imms or movw + movt. 5389// This is a single pseudo instruction, the benefit is that it can be remat'd 5390// as a single unit instead of having to handle reg inputs. 5391// FIXME: Remove this when we can do generalized remat. 5392let isReMaterializable = 1, isMoveImm = 1 in 5393def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 5394 [(set GPR:$dst, (arm_i32imm:$src))]>, 5395 Requires<[IsARM]>; 5396 5397def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i, 5398 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>, 5399 Requires<[IsARM, DontUseMovt]>; 5400 5401// Pseudo instruction that combines movw + movt + add pc (if PIC). 5402// It also makes it possible to rematerialize the instructions. 5403// FIXME: Remove this when we can do generalized remat and when machine licm 5404// can properly the instructions. 5405let isReMaterializable = 1 in { 5406def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5407 IIC_iMOVix2addpc, 5408 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 5409 Requires<[IsARM, UseMovt]>; 5410 5411def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5412 IIC_iLoadiALU, 5413 [(set GPR:$dst, 5414 (ARMWrapperPIC tglobaladdr:$addr))]>, 5415 Requires<[IsARM, DontUseMovt]>; 5416 5417let AddedComplexity = 10 in 5418def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5419 NoItinerary, 5420 [(set GPR:$dst, 5421 (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5422 Requires<[IsARM, DontUseMovt]>; 5423 5424let AddedComplexity = 10 in 5425def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5426 IIC_iMOVix2ld, 5427 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5428 Requires<[IsARM, UseMovt]>; 5429} // isReMaterializable 5430 5431// The many different faces of TLS access. 5432def : ARMPat<(ARMWrapper tglobaltlsaddr :$dst), 5433 (MOVi32imm tglobaltlsaddr :$dst)>, 5434 Requires<[IsARM, UseMovt]>; 5435 5436def : Pat<(ARMWrapper tglobaltlsaddr:$src), 5437 (LDRLIT_ga_abs tglobaltlsaddr:$src)>, 5438 Requires<[IsARM, DontUseMovt]>; 5439 5440def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5441 (MOV_ga_pcrel tglobaltlsaddr:$addr)>, Requires<[IsARM, UseMovt]>; 5442 5443def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5444 (LDRLIT_ga_pcrel tglobaltlsaddr:$addr)>, 5445 Requires<[IsARM, DontUseMovt]>; 5446let AddedComplexity = 10 in 5447def : Pat<(load (ARMWrapperPIC tglobaltlsaddr:$addr)), 5448 (MOV_ga_pcrel_ldr tglobaltlsaddr:$addr)>, 5449 Requires<[IsARM, UseMovt]>; 5450 5451 5452// ConstantPool, GlobalAddress, and JumpTable 5453def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 5454def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>, 5455 Requires<[IsARM, UseMovt]>; 5456def : ARMPat<(ARMWrapperJT tjumptable:$dst), 5457 (LEApcrelJT tjumptable:$dst)>; 5458 5459// TODO: add,sub,and, 3-instr forms? 5460 5461// Tail calls. These patterns also apply to Thumb mode. 5462def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>; 5463def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>; 5464def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>; 5465 5466// Direct calls 5467def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; 5468def : ARMPat<(ARMcall_nolink texternalsym:$func), 5469 (BMOVPCB_CALL texternalsym:$func)>; 5470 5471// zextload i1 -> zextload i8 5472def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5473def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5474 5475// extload -> zextload 5476def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5477def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5478def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5479def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5480 5481def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 5482 5483def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; 5484def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; 5485 5486// smul* and smla* 5487def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5488 (sra (shl GPR:$b, (i32 16)), (i32 16))), 5489 (SMULBB GPR:$a, GPR:$b)>; 5490def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 5491 (SMULBB GPR:$a, GPR:$b)>; 5492def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5493 (sra GPR:$b, (i32 16))), 5494 (SMULBT GPR:$a, GPR:$b)>; 5495def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))), 5496 (SMULBT GPR:$a, GPR:$b)>; 5497def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), 5498 (sra (shl GPR:$b, (i32 16)), (i32 16))), 5499 (SMULTB GPR:$a, GPR:$b)>; 5500def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b), 5501 (SMULTB GPR:$a, GPR:$b)>; 5502 5503def : ARMV5MOPat<(add GPR:$acc, 5504 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5505 (sra (shl GPR:$b, (i32 16)), (i32 16)))), 5506 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5507def : ARMV5MOPat<(add GPR:$acc, 5508 (mul sext_16_node:$a, sext_16_node:$b)), 5509 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5510def : ARMV5MOPat<(add GPR:$acc, 5511 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5512 (sra GPR:$b, (i32 16)))), 5513 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5514def : ARMV5MOPat<(add GPR:$acc, 5515 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))), 5516 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5517def : ARMV5MOPat<(add GPR:$acc, 5518 (mul (sra GPR:$a, (i32 16)), 5519 (sra (shl GPR:$b, (i32 16)), (i32 16)))), 5520 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5521def : ARMV5MOPat<(add GPR:$acc, 5522 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)), 5523 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5524 5525 5526// Pre-v7 uses MCR for synchronization barriers. 5527def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>, 5528 Requires<[IsARM, HasV6]>; 5529 5530// SXT/UXT with no rotate 5531let AddedComplexity = 16 in { 5532def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>; 5533def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>; 5534def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>; 5535def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)), 5536 (UXTAB GPR:$Rn, GPR:$Rm, 0)>; 5537def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)), 5538 (UXTAH GPR:$Rn, GPR:$Rm, 0)>; 5539} 5540 5541def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>; 5542def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; 5543 5544def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)), 5545 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>; 5546def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)), 5547 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>; 5548 5549// Atomic load/store patterns 5550def : ARMPat<(atomic_load_8 ldst_so_reg:$src), 5551 (LDRBrs ldst_so_reg:$src)>; 5552def : ARMPat<(atomic_load_8 addrmode_imm12:$src), 5553 (LDRBi12 addrmode_imm12:$src)>; 5554def : ARMPat<(atomic_load_16 addrmode3:$src), 5555 (LDRH addrmode3:$src)>; 5556def : ARMPat<(atomic_load_32 ldst_so_reg:$src), 5557 (LDRrs ldst_so_reg:$src)>; 5558def : ARMPat<(atomic_load_32 addrmode_imm12:$src), 5559 (LDRi12 addrmode_imm12:$src)>; 5560def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val), 5561 (STRBrs GPR:$val, ldst_so_reg:$ptr)>; 5562def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val), 5563 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>; 5564def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val), 5565 (STRH GPR:$val, addrmode3:$ptr)>; 5566def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val), 5567 (STRrs GPR:$val, ldst_so_reg:$ptr)>; 5568def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val), 5569 (STRi12 GPR:$val, addrmode_imm12:$ptr)>; 5570 5571 5572//===----------------------------------------------------------------------===// 5573// Thumb Support 5574// 5575 5576include "ARMInstrThumb.td" 5577 5578//===----------------------------------------------------------------------===// 5579// Thumb2 Support 5580// 5581 5582include "ARMInstrThumb2.td" 5583 5584//===----------------------------------------------------------------------===// 5585// Floating Point Support 5586// 5587 5588include "ARMInstrVFP.td" 5589 5590//===----------------------------------------------------------------------===// 5591// Advanced SIMD (NEON) Support 5592// 5593 5594include "ARMInstrNEON.td" 5595 5596//===----------------------------------------------------------------------===// 5597// Assembler aliases 5598// 5599 5600// Memory barriers 5601def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>; 5602def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>; 5603def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>; 5604 5605// System instructions 5606def : MnemonicAlias<"swi", "svc">; 5607 5608// Load / Store Multiple 5609def : MnemonicAlias<"ldmfd", "ldm">; 5610def : MnemonicAlias<"ldmia", "ldm">; 5611def : MnemonicAlias<"ldmea", "ldmdb">; 5612def : MnemonicAlias<"stmfd", "stmdb">; 5613def : MnemonicAlias<"stmia", "stm">; 5614def : MnemonicAlias<"stmea", "stm">; 5615 5616// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the 5617// input operands swapped when the shift amount is zero (i.e., unspecified). 5618def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 5619 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>, 5620 Requires<[IsARM, HasV6]>; 5621def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 5622 (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p)>, 5623 Requires<[IsARM, HasV6]>; 5624 5625// PUSH/POP aliases for STM/LDM 5626def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>; 5627def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>; 5628 5629// SSAT/USAT optional shift operand. 5630def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 5631 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5632def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn", 5633 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5634 5635 5636// Extend instruction optional rotate operand. 5637def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm", 5638 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5639def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm", 5640 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5641def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 5642 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5643def : ARMInstAlias<"sxtb${p} $Rd, $Rm", 5644 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5645def : ARMInstAlias<"sxtb16${p} $Rd, $Rm", 5646 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5647def : ARMInstAlias<"sxth${p} $Rd, $Rm", 5648 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5649 5650def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm", 5651 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5652def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm", 5653 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5654def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 5655 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5656def : ARMInstAlias<"uxtb${p} $Rd, $Rm", 5657 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5658def : ARMInstAlias<"uxtb16${p} $Rd, $Rm", 5659 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5660def : ARMInstAlias<"uxth${p} $Rd, $Rm", 5661 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5662 5663 5664// RFE aliases 5665def : MnemonicAlias<"rfefa", "rfeda">; 5666def : MnemonicAlias<"rfeea", "rfedb">; 5667def : MnemonicAlias<"rfefd", "rfeia">; 5668def : MnemonicAlias<"rfeed", "rfeib">; 5669def : MnemonicAlias<"rfe", "rfeia">; 5670 5671// SRS aliases 5672def : MnemonicAlias<"srsfa", "srsib">; 5673def : MnemonicAlias<"srsea", "srsia">; 5674def : MnemonicAlias<"srsfd", "srsdb">; 5675def : MnemonicAlias<"srsed", "srsda">; 5676def : MnemonicAlias<"srs", "srsia">; 5677 5678// QSAX == QSUBADDX 5679def : MnemonicAlias<"qsubaddx", "qsax">; 5680// SASX == SADDSUBX 5681def : MnemonicAlias<"saddsubx", "sasx">; 5682// SHASX == SHADDSUBX 5683def : MnemonicAlias<"shaddsubx", "shasx">; 5684// SHSAX == SHSUBADDX 5685def : MnemonicAlias<"shsubaddx", "shsax">; 5686// SSAX == SSUBADDX 5687def : MnemonicAlias<"ssubaddx", "ssax">; 5688// UASX == UADDSUBX 5689def : MnemonicAlias<"uaddsubx", "uasx">; 5690// UHASX == UHADDSUBX 5691def : MnemonicAlias<"uhaddsubx", "uhasx">; 5692// UHSAX == UHSUBADDX 5693def : MnemonicAlias<"uhsubaddx", "uhsax">; 5694// UQASX == UQADDSUBX 5695def : MnemonicAlias<"uqaddsubx", "uqasx">; 5696// UQSAX == UQSUBADDX 5697def : MnemonicAlias<"uqsubaddx", "uqsax">; 5698// USAX == USUBADDX 5699def : MnemonicAlias<"usubaddx", "usax">; 5700 5701// "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like 5702// for isel. 5703def : ARMInstAlias<"mov${s}${p} $Rd, $imm", 5704 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 5705def : ARMInstAlias<"mvn${s}${p} $Rd, $imm", 5706 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 5707// Same for AND <--> BIC 5708def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm", 5709 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 5710 pred:$p, cc_out:$s)>; 5711def : ARMInstAlias<"bic${s}${p} $Rdn, $imm", 5712 (ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 5713 pred:$p, cc_out:$s)>; 5714def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm", 5715 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 5716 pred:$p, cc_out:$s)>; 5717def : ARMInstAlias<"and${s}${p} $Rdn, $imm", 5718 (BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 5719 pred:$p, cc_out:$s)>; 5720 5721// Likewise, "add Rd, mod_imm_neg" -> sub 5722def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm", 5723 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 5724def : ARMInstAlias<"add${s}${p} $Rd, $imm", 5725 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 5726// Same for CMP <--> CMN via mod_imm_neg 5727def : ARMInstAlias<"cmp${p} $Rd, $imm", 5728 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 5729def : ARMInstAlias<"cmn${p} $Rd, $imm", 5730 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 5731 5732// The shifter forms of the MOV instruction are aliased to the ASR, LSL, 5733// LSR, ROR, and RRX instructions. 5734// FIXME: We need C++ parser hooks to map the alias to the MOV 5735// encoding. It seems we should be able to do that sort of thing 5736// in tblgen, but it could get ugly. 5737let TwoOperandAliasConstraint = "$Rm = $Rd" in { 5738def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm", 5739 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 5740 cc_out:$s)>; 5741def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm", 5742 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 5743 cc_out:$s)>; 5744def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm", 5745 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 5746 cc_out:$s)>; 5747def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm", 5748 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 5749 cc_out:$s)>; 5750} 5751def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm", 5752 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>; 5753let TwoOperandAliasConstraint = "$Rn = $Rd" in { 5754def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm", 5755 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5756 cc_out:$s)>; 5757def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm", 5758 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5759 cc_out:$s)>; 5760def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm", 5761 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5762 cc_out:$s)>; 5763def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm", 5764 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5765 cc_out:$s)>; 5766} 5767 5768// "neg" is and alias for "rsb rd, rn, #0" 5769def : ARMInstAlias<"neg${s}${p} $Rd, $Rm", 5770 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>; 5771 5772// Pre-v6, 'mov r0, r0' was used as a NOP encoding. 5773def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>, 5774 Requires<[IsARM, NoV6]>; 5775 5776// MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but 5777// the instruction definitions need difference constraints pre-v6. 5778// Use these aliases for the assembly parsing on pre-v6. 5779def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm", 5780 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 5781 Requires<[IsARM, NoV6]>; 5782def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra", 5783 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 5784 pred:$p, cc_out:$s)>, 5785 Requires<[IsARM, NoV6]>; 5786def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5787 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5788 Requires<[IsARM, NoV6]>; 5789def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5790 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5791 Requires<[IsARM, NoV6]>; 5792def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5793 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5794 Requires<[IsARM, NoV6]>; 5795def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5796 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5797 Requires<[IsARM, NoV6]>; 5798 5799// 'it' blocks in ARM mode just validate the predicates. The IT itself 5800// is discarded. 5801def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>, 5802 ComplexDeprecationPredicate<"IT">; 5803 5804let mayLoad = 1, mayStore =1, hasSideEffects = 1 in 5805def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn), 5806 NoItinerary, 5807 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>; 5808