1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// ARM specific DAG Nodes. 16// 17 18// Type profiles. 19def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 20def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 21def SDT_ARMStructByVal : SDTypeProfile<0, 4, 22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 24 25def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 26 27def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 28 29def SDT_ARMCMov : SDTypeProfile<1, 3, 30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 31 SDTCisVT<3, i32>]>; 32 33def SDT_ARMBrcond : SDTypeProfile<0, 2, 34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 35 36def SDT_ARMBrJT : SDTypeProfile<0, 2, 37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 38 39def SDT_ARMBr2JT : SDTypeProfile<0, 3, 40 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 41 SDTCisVT<2, i32>]>; 42 43def SDT_ARMBCC_i64 : SDTypeProfile<0, 6, 44 [SDTCisVT<0, i32>, 45 SDTCisVT<1, i32>, SDTCisVT<2, i32>, 46 SDTCisVT<3, i32>, SDTCisVT<4, i32>, 47 SDTCisVT<5, OtherVT>]>; 48 49def SDT_ARMAnd : SDTypeProfile<1, 2, 50 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 51 SDTCisVT<2, i32>]>; 52 53def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 54 55def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 56 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 57 58def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 59def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, 60 SDTCisInt<2>]>; 61def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 62def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>; 63 64def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 65 66def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, 67 SDTCisInt<1>]>; 68 69def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 70 71def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 73 74def SDT_WIN__DBZCHK : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 75 76def SDT_ARMMEMCPY : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 77 SDTCisVT<2, i32>, SDTCisVT<3, i32>, 78 SDTCisVT<4, i32>]>; 79 80def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 81 [SDTCisSameAs<0, 2>, 82 SDTCisSameAs<0, 3>, 83 SDTCisInt<0>, SDTCisVT<1, i32>]>; 84 85// SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR 86def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 87 [SDTCisSameAs<0, 2>, 88 SDTCisSameAs<0, 3>, 89 SDTCisInt<0>, 90 SDTCisVT<1, i32>, 91 SDTCisVT<4, i32>]>; 92 93// Node definitions. 94def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 95def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>; 96def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>; 97 98def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 99 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 100def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 101 [SDNPHasChain, SDNPSideEffect, 102 SDNPOptInGlue, SDNPOutGlue]>; 103def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" , 104 SDT_ARMStructByVal, 105 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 106 SDNPMayStore, SDNPMayLoad]>; 107 108def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 109 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 110 SDNPVariadic]>; 111def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 112 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 113 SDNPVariadic]>; 114def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 116 SDNPVariadic]>; 117 118def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, 119 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 120def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall, 121 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 122def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 123 [SDNPInGlue]>; 124 125def ARMssatnoshift : SDNode<"ARMISD::SSAT", SDTIntSatNoShOp, []>; 126 127def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 128 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 129 130def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 131 [SDNPHasChain]>; 132def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, 133 [SDNPHasChain]>; 134 135def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64, 136 [SDNPHasChain]>; 137 138def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 139 [SDNPOutGlue]>; 140 141def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp, 142 [SDNPOutGlue]>; 143 144def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, 145 [SDNPOutGlue, SDNPCommutative]>; 146 147def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 148 149def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 150def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 151def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>; 152 153def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags, 154 [SDNPCommutative]>; 155def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>; 156def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>; 157def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>; 158 159def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 160def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", 161 SDT_ARMEH_SJLJ_Setjmp, 162 [SDNPHasChain, SDNPSideEffect]>; 163def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP", 164 SDT_ARMEH_SJLJ_Longjmp, 165 [SDNPHasChain, SDNPSideEffect]>; 166def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH", 167 SDT_ARMEH_SJLJ_SetupDispatch, 168 [SDNPHasChain, SDNPSideEffect]>; 169 170def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER, 171 [SDNPHasChain, SDNPSideEffect]>; 172def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH, 173 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 174 175def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET, 176 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 177 178def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; 179 180def ARMmemcopy : SDNode<"ARMISD::MEMCPY", SDT_ARMMEMCPY, 181 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 182 SDNPMayStore, SDNPMayLoad]>; 183 184//===----------------------------------------------------------------------===// 185// ARM Instruction Predicate Definitions. 186// 187def HasV4T : Predicate<"Subtarget->hasV4TOps()">, 188 AssemblerPredicate<"HasV4TOps", "armv4t">; 189def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; 190def HasV5T : Predicate<"Subtarget->hasV5TOps()">, 191 AssemblerPredicate<"HasV5TOps", "armv5t">; 192def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, 193 AssemblerPredicate<"HasV5TEOps", "armv5te">; 194def HasV6 : Predicate<"Subtarget->hasV6Ops()">, 195 AssemblerPredicate<"HasV6Ops", "armv6">; 196def NoV6 : Predicate<"!Subtarget->hasV6Ops()">; 197def HasV6M : Predicate<"Subtarget->hasV6MOps()">, 198 AssemblerPredicate<"HasV6MOps", 199 "armv6m or armv6t2">; 200def HasV8MBaseline : Predicate<"Subtarget->hasV8MBaselineOps()">, 201 AssemblerPredicate<"HasV8MBaselineOps", 202 "armv8m.base">; 203def HasV8MMainline : Predicate<"Subtarget->hasV8MMainlineOps()">, 204 AssemblerPredicate<"HasV8MMainlineOps", 205 "armv8m.main">; 206def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, 207 AssemblerPredicate<"HasV6T2Ops", "armv6t2">; 208def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; 209def HasV6K : Predicate<"Subtarget->hasV6KOps()">, 210 AssemblerPredicate<"HasV6KOps", "armv6k">; 211def NoV6K : Predicate<"!Subtarget->hasV6KOps()">; 212def HasV7 : Predicate<"Subtarget->hasV7Ops()">, 213 AssemblerPredicate<"HasV7Ops", "armv7">; 214def HasV8 : Predicate<"Subtarget->hasV8Ops()">, 215 AssemblerPredicate<"HasV8Ops", "armv8">; 216def PreV8 : Predicate<"!Subtarget->hasV8Ops()">, 217 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">; 218def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">, 219 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">; 220def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">, 221 AssemblerPredicate<"HasV8_2aOps", "armv8.2a">; 222def NoVFP : Predicate<"!Subtarget->hasVFP2()">; 223def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, 224 AssemblerPredicate<"FeatureVFP2", "VFP2">; 225def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, 226 AssemblerPredicate<"FeatureVFP3", "VFP3">; 227def HasVFP4 : Predicate<"Subtarget->hasVFP4()">, 228 AssemblerPredicate<"FeatureVFP4", "VFP4">; 229def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">, 230 AssemblerPredicate<"!FeatureVFPOnlySP", 231 "double precision VFP">; 232def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, 233 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">; 234def HasNEON : Predicate<"Subtarget->hasNEON()">, 235 AssemblerPredicate<"FeatureNEON", "NEON">; 236def HasCrypto : Predicate<"Subtarget->hasCrypto()">, 237 AssemblerPredicate<"FeatureCrypto", "crypto">; 238def HasCRC : Predicate<"Subtarget->hasCRC()">, 239 AssemblerPredicate<"FeatureCRC", "crc">; 240def HasRAS : Predicate<"Subtarget->hasRAS()">, 241 AssemblerPredicate<"FeatureRAS", "ras">; 242def HasFP16 : Predicate<"Subtarget->hasFP16()">, 243 AssemblerPredicate<"FeatureFP16","half-float conversions">; 244def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">, 245 AssemblerPredicate<"FeatureFullFP16","full half-float">; 246def HasDivide : Predicate<"Subtarget->hasDivide()">, 247 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">; 248def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">, 249 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">; 250def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">, 251 AssemblerPredicate<"FeatureT2XtPk", 252 "pack/extract">; 253def HasDSP : Predicate<"Subtarget->hasDSP()">, 254 AssemblerPredicate<"FeatureDSP", "dsp">; 255def HasDB : Predicate<"Subtarget->hasDataBarrier()">, 256 AssemblerPredicate<"FeatureDB", 257 "data-barriers">; 258def HasV7Clrex : Predicate<"Subtarget->hasV7Clrex()">, 259 AssemblerPredicate<"FeatureV7Clrex", 260 "v7 clrex">; 261def HasAcquireRelease : Predicate<"Subtarget->hasAcquireRelease()">, 262 AssemblerPredicate<"FeatureAcquireRelease", 263 "acquire/release">; 264def HasMP : Predicate<"Subtarget->hasMPExtension()">, 265 AssemblerPredicate<"FeatureMP", 266 "mp-extensions">; 267def HasVirtualization: Predicate<"false">, 268 AssemblerPredicate<"FeatureVirtualization", 269 "virtualization-extensions">; 270def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">, 271 AssemblerPredicate<"FeatureTrustZone", 272 "TrustZone">; 273def Has8MSecExt : Predicate<"Subtarget->has8MSecExt()">, 274 AssemblerPredicate<"Feature8MSecExt", 275 "ARMv8-M Security Extensions">; 276def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">; 277def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; 278def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; 279def IsThumb : Predicate<"Subtarget->isThumb()">, 280 AssemblerPredicate<"ModeThumb", "thumb">; 281def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; 282def IsThumb2 : Predicate<"Subtarget->isThumb2()">, 283 AssemblerPredicate<"ModeThumb,FeatureThumb2", 284 "thumb2">; 285def IsMClass : Predicate<"Subtarget->isMClass()">, 286 AssemblerPredicate<"FeatureMClass", "armv*m">; 287def IsNotMClass : Predicate<"!Subtarget->isMClass()">, 288 AssemblerPredicate<"!FeatureMClass", 289 "!armv*m">; 290def IsARM : Predicate<"!Subtarget->isThumb()">, 291 AssemblerPredicate<"!ModeThumb", "arm-mode">; 292def IsMachO : Predicate<"Subtarget->isTargetMachO()">; 293def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">; 294def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 295def IsWindows : Predicate<"Subtarget->isTargetWindows()">; 296def IsNotWindows : Predicate<"!Subtarget->isTargetWindows()">; 297def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">, 298 AssemblerPredicate<"FeatureNaClTrap", "NaCl">; 299def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">; 300 301// FIXME: Eventually this will be just "hasV6T2Ops". 302def UseMovt : Predicate<"Subtarget->useMovt(*MF)">; 303def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">; 304def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">; 305def UseMulOps : Predicate<"Subtarget->useMulOps()">; 306 307// Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available. 308// But only select them if more precision in FP computation is allowed. 309// Do not use them for Darwin platforms. 310def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion ==" 311 " FPOpFusion::Fast && " 312 " Subtarget->hasVFP4()) && " 313 "!Subtarget->isTargetDarwin()">; 314def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion ==" 315 " FPOpFusion::Fast &&" 316 " Subtarget->hasVFP4()) || " 317 "Subtarget->isTargetDarwin()">; 318 319def HasFastVGETLNi32 : Predicate<"!Subtarget->hasSlowVGETLNi32()">; 320def HasSlowVGETLNi32 : Predicate<"Subtarget->hasSlowVGETLNi32()">; 321 322def HasFastVDUP32 : Predicate<"!Subtarget->hasSlowVDUP32()">; 323def HasSlowVDUP32 : Predicate<"Subtarget->hasSlowVDUP32()">; 324 325def UseVMOVSR : Predicate<"Subtarget->preferVMOVSR() ||" 326 "!Subtarget->useNEONForSinglePrecisionFP()">; 327def DontUseVMOVSR : Predicate<"!Subtarget->preferVMOVSR() &&" 328 "Subtarget->useNEONForSinglePrecisionFP()">; 329 330def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">; 331def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">; 332 333def GenExecuteOnly : Predicate<"Subtarget->genExecuteOnly()">; 334 335//===----------------------------------------------------------------------===// 336// ARM Flag Definitions. 337 338class RegConstraint<string C> { 339 string Constraints = C; 340} 341 342//===----------------------------------------------------------------------===// 343// ARM specific transformation functions and pattern fragments. 344// 345 346// imm_neg_XFORM - Return the negation of an i32 immediate value. 347def imm_neg_XFORM : SDNodeXForm<imm, [{ 348 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32); 349}]>; 350 351// imm_not_XFORM - Return the complement of a i32 immediate value. 352def imm_not_XFORM : SDNodeXForm<imm, [{ 353 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32); 354}]>; 355 356/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 357def imm16_31 : ImmLeaf<i32, [{ 358 return (int32_t)Imm >= 16 && (int32_t)Imm < 32; 359}]>; 360 361// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 362def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 363 if (CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17) 364 return true; 365 366 if (N->getOpcode() != ISD::SRA) 367 return false; 368 if (N->getOperand(0).getOpcode() != ISD::SHL) 369 return false; 370 371 auto *ShiftVal = dyn_cast<ConstantSDNode>(N->getOperand(1)); 372 if (!ShiftVal || ShiftVal->getZExtValue() != 16) 373 return false; 374 375 ShiftVal = dyn_cast<ConstantSDNode>(N->getOperand(0)->getOperand(1)); 376 if (!ShiftVal || ShiftVal->getZExtValue() != 16) 377 return false; 378 379 return true; 380}]>; 381 382/// Split a 32-bit immediate into two 16 bit parts. 383def hi16 : SDNodeXForm<imm, [{ 384 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N), 385 MVT::i32); 386}]>; 387 388def lo16AllZero : PatLeaf<(i32 imm), [{ 389 // Returns true if all low 16-bits are 0. 390 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 391}], hi16>; 392 393class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 394class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 395 396// An 'and' node with a single use. 397def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 398 return N->hasOneUse(); 399}]>; 400 401// An 'xor' node with a single use. 402def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{ 403 return N->hasOneUse(); 404}]>; 405 406// An 'fmul' node with a single use. 407def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{ 408 return N->hasOneUse(); 409}]>; 410 411// An 'fadd' node which checks for single non-hazardous use. 412def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{ 413 return hasNoVMLxHazardUse(N); 414}]>; 415 416// An 'fsub' node which checks for single non-hazardous use. 417def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{ 418 return hasNoVMLxHazardUse(N); 419}]>; 420 421//===----------------------------------------------------------------------===// 422// Operand Definitions. 423// 424 425// Immediate operands with a shared generic asm render method. 426class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; } 427 428// Operands that are part of a memory addressing mode. 429class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; } 430 431// Branch target. 432// FIXME: rename brtarget to t2_brtarget 433def brtarget : Operand<OtherVT> { 434 let EncoderMethod = "getBranchTargetOpValue"; 435 let OperandType = "OPERAND_PCREL"; 436 let DecoderMethod = "DecodeT2BROperand"; 437} 438 439// Branches targeting ARM-mode must be divisible by 4 if they're a raw 440// immediate. 441def ARMBranchTarget : AsmOperandClass { 442 let Name = "ARMBranchTarget"; 443} 444 445// Branches targeting Thumb-mode must be divisible by 2 if they're a raw 446// immediate. 447def ThumbBranchTarget : AsmOperandClass { 448 let Name = "ThumbBranchTarget"; 449} 450 451def arm_br_target : Operand<OtherVT> { 452 let ParserMatchClass = ARMBranchTarget; 453 let EncoderMethod = "getARMBranchTargetOpValue"; 454 let OperandType = "OPERAND_PCREL"; 455} 456 457// Call target for ARM. Handles conditional/unconditional 458// FIXME: rename bl_target to t2_bltarget? 459def arm_bl_target : Operand<i32> { 460 let ParserMatchClass = ARMBranchTarget; 461 let EncoderMethod = "getARMBLTargetOpValue"; 462 let OperandType = "OPERAND_PCREL"; 463} 464 465// Target for BLX *from* ARM mode. 466def arm_blx_target : Operand<i32> { 467 let ParserMatchClass = ThumbBranchTarget; 468 let EncoderMethod = "getARMBLXTargetOpValue"; 469 let OperandType = "OPERAND_PCREL"; 470} 471 472// A list of registers separated by comma. Used by load/store multiple. 473def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; } 474def reglist : Operand<i32> { 475 let EncoderMethod = "getRegisterListOpValue"; 476 let ParserMatchClass = RegListAsmOperand; 477 let PrintMethod = "printRegisterList"; 478 let DecoderMethod = "DecodeRegListOperand"; 479} 480 481def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">; 482 483def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; } 484def dpr_reglist : Operand<i32> { 485 let EncoderMethod = "getRegisterListOpValue"; 486 let ParserMatchClass = DPRRegListAsmOperand; 487 let PrintMethod = "printRegisterList"; 488 let DecoderMethod = "DecodeDPRRegListOperand"; 489} 490 491def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; } 492def spr_reglist : Operand<i32> { 493 let EncoderMethod = "getRegisterListOpValue"; 494 let ParserMatchClass = SPRRegListAsmOperand; 495 let PrintMethod = "printRegisterList"; 496 let DecoderMethod = "DecodeSPRRegListOperand"; 497} 498 499// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 500def cpinst_operand : Operand<i32> { 501 let PrintMethod = "printCPInstOperand"; 502} 503 504// Local PC labels. 505def pclabel : Operand<i32> { 506 let PrintMethod = "printPCLabel"; 507} 508 509// ADR instruction labels. 510def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; } 511def adrlabel : Operand<i32> { 512 let EncoderMethod = "getAdrLabelOpValue"; 513 let ParserMatchClass = AdrLabelAsmOperand; 514 let PrintMethod = "printAdrLabelOperand<0>"; 515} 516 517def neon_vcvt_imm32 : Operand<i32> { 518 let EncoderMethod = "getNEONVcvtImm32OpValue"; 519 let DecoderMethod = "DecodeVCVTImmOperand"; 520} 521 522// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. 523def rot_imm_XFORM: SDNodeXForm<imm, [{ 524 switch (N->getZExtValue()){ 525 default: llvm_unreachable(nullptr); 526 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); 527 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32); 528 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32); 529 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32); 530 } 531}]>; 532def RotImmAsmOperand : AsmOperandClass { 533 let Name = "RotImm"; 534 let ParserMethod = "parseRotImm"; 535} 536def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{ 537 int32_t v = N->getZExtValue(); 538 return v == 8 || v == 16 || v == 24; }], 539 rot_imm_XFORM> { 540 let PrintMethod = "printRotImmOperand"; 541 let ParserMatchClass = RotImmAsmOperand; 542} 543 544// shift_imm: An integer that encodes a shift amount and the type of shift 545// (asr or lsl). The 6-bit immediate encodes as: 546// {5} 0 ==> lsl 547// 1 asr 548// {4-0} imm5 shift amount. 549// asr #32 encoded as imm5 == 0. 550def ShifterImmAsmOperand : AsmOperandClass { 551 let Name = "ShifterImm"; 552 let ParserMethod = "parseShifterImm"; 553} 554def shift_imm : Operand<i32> { 555 let PrintMethod = "printShiftImmOperand"; 556 let ParserMatchClass = ShifterImmAsmOperand; 557} 558 559// shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm. 560def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; } 561def so_reg_reg : Operand<i32>, // reg reg imm 562 ComplexPattern<i32, 3, "SelectRegShifterOperand", 563 [shl, srl, sra, rotr]> { 564 let EncoderMethod = "getSORegRegOpValue"; 565 let PrintMethod = "printSORegRegOperand"; 566 let DecoderMethod = "DecodeSORegRegOperand"; 567 let ParserMatchClass = ShiftedRegAsmOperand; 568 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm); 569} 570 571def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; } 572def so_reg_imm : Operand<i32>, // reg imm 573 ComplexPattern<i32, 2, "SelectImmShifterOperand", 574 [shl, srl, sra, rotr]> { 575 let EncoderMethod = "getSORegImmOpValue"; 576 let PrintMethod = "printSORegImmOperand"; 577 let DecoderMethod = "DecodeSORegImmOperand"; 578 let ParserMatchClass = ShiftedImmAsmOperand; 579 let MIOperandInfo = (ops GPR, i32imm); 580} 581 582// FIXME: Does this need to be distinct from so_reg? 583def shift_so_reg_reg : Operand<i32>, // reg reg imm 584 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand", 585 [shl,srl,sra,rotr]> { 586 let EncoderMethod = "getSORegRegOpValue"; 587 let PrintMethod = "printSORegRegOperand"; 588 let DecoderMethod = "DecodeSORegRegOperand"; 589 let ParserMatchClass = ShiftedRegAsmOperand; 590 let MIOperandInfo = (ops GPR, GPR, i32imm); 591} 592 593// FIXME: Does this need to be distinct from so_reg? 594def shift_so_reg_imm : Operand<i32>, // reg reg imm 595 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand", 596 [shl,srl,sra,rotr]> { 597 let EncoderMethod = "getSORegImmOpValue"; 598 let PrintMethod = "printSORegImmOperand"; 599 let DecoderMethod = "DecodeSORegImmOperand"; 600 let ParserMatchClass = ShiftedImmAsmOperand; 601 let MIOperandInfo = (ops GPR, i32imm); 602} 603 604// mod_imm: match a 32-bit immediate operand, which can be encoded into 605// a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM 606// - "Modified Immediate Constants"). Within the MC layer we keep this 607// immediate in its encoded form. 608def ModImmAsmOperand: AsmOperandClass { 609 let Name = "ModImm"; 610 let ParserMethod = "parseModImm"; 611} 612def mod_imm : Operand<i32>, ImmLeaf<i32, [{ 613 return ARM_AM::getSOImmVal(Imm) != -1; 614 }]> { 615 let EncoderMethod = "getModImmOpValue"; 616 let PrintMethod = "printModImmOperand"; 617 let ParserMatchClass = ModImmAsmOperand; 618} 619 620// Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder 621// method and such, as they are only used on aliases (Pat<> and InstAlias<>). 622// The actual parsing, encoding, decoding are handled by the destination 623// instructions, which use mod_imm. 624 625def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; } 626def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{ 627 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1; 628 }], imm_not_XFORM> { 629 let ParserMatchClass = ModImmNotAsmOperand; 630} 631 632def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; } 633def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{ 634 unsigned Value = -(unsigned)N->getZExtValue(); 635 return Value && ARM_AM::getSOImmVal(Value) != -1; 636 }], imm_neg_XFORM> { 637 let ParserMatchClass = ModImmNegAsmOperand; 638} 639 640/// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal() 641def arm_i32imm : PatLeaf<(imm), [{ 642 if (Subtarget->useMovt(*MF)) 643 return true; 644 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 645}]>; 646 647/// imm0_1 predicate - Immediate in the range [0,1]. 648def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; } 649def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; } 650 651/// imm0_3 predicate - Immediate in the range [0,3]. 652def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; } 653def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; } 654 655/// imm0_7 predicate - Immediate in the range [0,7]. 656def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; } 657def imm0_7 : Operand<i32>, ImmLeaf<i32, [{ 658 return Imm >= 0 && Imm < 8; 659}]> { 660 let ParserMatchClass = Imm0_7AsmOperand; 661} 662 663/// imm8 predicate - Immediate is exactly 8. 664def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; } 665def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> { 666 let ParserMatchClass = Imm8AsmOperand; 667} 668 669/// imm16 predicate - Immediate is exactly 16. 670def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; } 671def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> { 672 let ParserMatchClass = Imm16AsmOperand; 673} 674 675/// imm32 predicate - Immediate is exactly 32. 676def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; } 677def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> { 678 let ParserMatchClass = Imm32AsmOperand; 679} 680 681def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>; 682 683/// imm1_7 predicate - Immediate in the range [1,7]. 684def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; } 685def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> { 686 let ParserMatchClass = Imm1_7AsmOperand; 687} 688 689/// imm1_15 predicate - Immediate in the range [1,15]. 690def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; } 691def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> { 692 let ParserMatchClass = Imm1_15AsmOperand; 693} 694 695/// imm1_31 predicate - Immediate in the range [1,31]. 696def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; } 697def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> { 698 let ParserMatchClass = Imm1_31AsmOperand; 699} 700 701/// imm0_15 predicate - Immediate in the range [0,15]. 702def Imm0_15AsmOperand: ImmAsmOperand { 703 let Name = "Imm0_15"; 704 let DiagnosticType = "ImmRange0_15"; 705} 706def imm0_15 : Operand<i32>, ImmLeaf<i32, [{ 707 return Imm >= 0 && Imm < 16; 708}]> { 709 let ParserMatchClass = Imm0_15AsmOperand; 710} 711 712/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31]. 713def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; } 714def imm0_31 : Operand<i32>, ImmLeaf<i32, [{ 715 return Imm >= 0 && Imm < 32; 716}]> { 717 let ParserMatchClass = Imm0_31AsmOperand; 718} 719 720/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32]. 721def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; } 722def imm0_32 : Operand<i32>, ImmLeaf<i32, [{ 723 return Imm >= 0 && Imm < 32; 724}]> { 725 let ParserMatchClass = Imm0_32AsmOperand; 726} 727 728/// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63]. 729def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; } 730def imm0_63 : Operand<i32>, ImmLeaf<i32, [{ 731 return Imm >= 0 && Imm < 64; 732}]> { 733 let ParserMatchClass = Imm0_63AsmOperand; 734} 735 736/// imm0_239 predicate - Immediate in the range [0,239]. 737def Imm0_239AsmOperand : ImmAsmOperand { 738 let Name = "Imm0_239"; 739 let DiagnosticType = "ImmRange0_239"; 740} 741def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> { 742 let ParserMatchClass = Imm0_239AsmOperand; 743} 744 745/// imm0_255 predicate - Immediate in the range [0,255]. 746def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; } 747def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> { 748 let ParserMatchClass = Imm0_255AsmOperand; 749} 750 751/// imm0_65535 - An immediate is in the range [0.65535]. 752def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; } 753def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{ 754 return Imm >= 0 && Imm < 65536; 755}]> { 756 let ParserMatchClass = Imm0_65535AsmOperand; 757} 758 759// imm0_65535_neg - An immediate whose negative value is in the range [0.65535]. 760def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{ 761 return -Imm >= 0 && -Imm < 65536; 762}]>; 763 764// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference 765// a relocatable expression. 766// 767// FIXME: This really needs a Thumb version separate from the ARM version. 768// While the range is the same, and can thus use the same match class, 769// the encoding is different so it should have a different encoder method. 770def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; } 771def imm0_65535_expr : Operand<i32> { 772 let EncoderMethod = "getHiLo16ImmOpValue"; 773 let ParserMatchClass = Imm0_65535ExprAsmOperand; 774} 775 776def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; } 777def imm256_65535_expr : Operand<i32> { 778 let ParserMatchClass = Imm256_65535ExprAsmOperand; 779} 780 781/// imm24b - True if the 32-bit immediate is encodable in 24 bits. 782def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; } 783def imm24b : Operand<i32>, ImmLeaf<i32, [{ 784 return Imm >= 0 && Imm <= 0xffffff; 785}]> { 786 let ParserMatchClass = Imm24bitAsmOperand; 787} 788 789 790/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield 791/// e.g., 0xf000ffff 792def BitfieldAsmOperand : AsmOperandClass { 793 let Name = "Bitfield"; 794 let ParserMethod = "parseBitfield"; 795} 796 797def bf_inv_mask_imm : Operand<i32>, 798 PatLeaf<(imm), [{ 799 return ARM::isBitFieldInvertedMask(N->getZExtValue()); 800}] > { 801 let EncoderMethod = "getBitfieldInvertedMaskOpValue"; 802 let PrintMethod = "printBitfieldInvMaskImmOperand"; 803 let DecoderMethod = "DecodeBitfieldMaskOperand"; 804 let ParserMatchClass = BitfieldAsmOperand; 805} 806 807def imm1_32_XFORM: SDNodeXForm<imm, [{ 808 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 809 MVT::i32); 810}]>; 811def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; } 812def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ 813 uint64_t Imm = N->getZExtValue(); 814 return Imm > 0 && Imm <= 32; 815 }], 816 imm1_32_XFORM> { 817 let PrintMethod = "printImmPlusOneOperand"; 818 let ParserMatchClass = Imm1_32AsmOperand; 819} 820 821def imm1_16_XFORM: SDNodeXForm<imm, [{ 822 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 823 MVT::i32); 824}]>; 825def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; } 826def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }], 827 imm1_16_XFORM> { 828 let PrintMethod = "printImmPlusOneOperand"; 829 let ParserMatchClass = Imm1_16AsmOperand; 830} 831 832// Define ARM specific addressing modes. 833// addrmode_imm12 := reg +/- imm12 834// 835def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; } 836class AddrMode_Imm12 : MemOperand, 837 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> { 838 // 12-bit immediate operand. Note that instructions using this encode 839 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other 840 // immediate values are as normal. 841 842 let EncoderMethod = "getAddrModeImm12OpValue"; 843 let DecoderMethod = "DecodeAddrModeImm12Operand"; 844 let ParserMatchClass = MemImm12OffsetAsmOperand; 845 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 846} 847 848def addrmode_imm12 : AddrMode_Imm12 { 849 let PrintMethod = "printAddrModeImm12Operand<false>"; 850} 851 852def addrmode_imm12_pre : AddrMode_Imm12 { 853 let PrintMethod = "printAddrModeImm12Operand<true>"; 854} 855 856// ldst_so_reg := reg +/- reg shop imm 857// 858def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; } 859def ldst_so_reg : MemOperand, 860 ComplexPattern<i32, 3, "SelectLdStSOReg", []> { 861 let EncoderMethod = "getLdStSORegOpValue"; 862 // FIXME: Simplify the printer 863 let PrintMethod = "printAddrMode2Operand"; 864 let DecoderMethod = "DecodeSORegMemOperand"; 865 let ParserMatchClass = MemRegOffsetAsmOperand; 866 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift); 867} 868 869// postidx_imm8 := +/- [0,255] 870// 871// 9 bit value: 872// {8} 1 is imm8 is non-negative. 0 otherwise. 873// {7-0} [0,255] imm8 value. 874def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; } 875def postidx_imm8 : MemOperand { 876 let PrintMethod = "printPostIdxImm8Operand"; 877 let ParserMatchClass = PostIdxImm8AsmOperand; 878 let MIOperandInfo = (ops i32imm); 879} 880 881// postidx_imm8s4 := +/- [0,1020] 882// 883// 9 bit value: 884// {8} 1 is imm8 is non-negative. 0 otherwise. 885// {7-0} [0,255] imm8 value, scaled by 4. 886def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; } 887def postidx_imm8s4 : MemOperand { 888 let PrintMethod = "printPostIdxImm8s4Operand"; 889 let ParserMatchClass = PostIdxImm8s4AsmOperand; 890 let MIOperandInfo = (ops i32imm); 891} 892 893 894// postidx_reg := +/- reg 895// 896def PostIdxRegAsmOperand : AsmOperandClass { 897 let Name = "PostIdxReg"; 898 let ParserMethod = "parsePostIdxReg"; 899} 900def postidx_reg : MemOperand { 901 let EncoderMethod = "getPostIdxRegOpValue"; 902 let DecoderMethod = "DecodePostIdxReg"; 903 let PrintMethod = "printPostIdxRegOperand"; 904 let ParserMatchClass = PostIdxRegAsmOperand; 905 let MIOperandInfo = (ops GPRnopc, i32imm); 906} 907 908 909// addrmode2 := reg +/- imm12 910// := reg +/- reg shop imm 911// 912// FIXME: addrmode2 should be refactored the rest of the way to always 913// use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg). 914def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; } 915def addrmode2 : MemOperand, 916 ComplexPattern<i32, 3, "SelectAddrMode2", []> { 917 let EncoderMethod = "getAddrMode2OpValue"; 918 let PrintMethod = "printAddrMode2Operand"; 919 let ParserMatchClass = AddrMode2AsmOperand; 920 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 921} 922 923def PostIdxRegShiftedAsmOperand : AsmOperandClass { 924 let Name = "PostIdxRegShifted"; 925 let ParserMethod = "parsePostIdxReg"; 926} 927def am2offset_reg : MemOperand, 928 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg", 929 [], [SDNPWantRoot]> { 930 let EncoderMethod = "getAddrMode2OffsetOpValue"; 931 let PrintMethod = "printAddrMode2OffsetOperand"; 932 // When using this for assembly, it's always as a post-index offset. 933 let ParserMatchClass = PostIdxRegShiftedAsmOperand; 934 let MIOperandInfo = (ops GPRnopc, i32imm); 935} 936 937// FIXME: am2offset_imm should only need the immediate, not the GPR. Having 938// the GPR is purely vestigal at this point. 939def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; } 940def am2offset_imm : MemOperand, 941 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm", 942 [], [SDNPWantRoot]> { 943 let EncoderMethod = "getAddrMode2OffsetOpValue"; 944 let PrintMethod = "printAddrMode2OffsetOperand"; 945 let ParserMatchClass = AM2OffsetImmAsmOperand; 946 let MIOperandInfo = (ops GPRnopc, i32imm); 947} 948 949 950// addrmode3 := reg +/- reg 951// addrmode3 := reg +/- imm8 952// 953// FIXME: split into imm vs. reg versions. 954def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; } 955class AddrMode3 : MemOperand, 956 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 957 let EncoderMethod = "getAddrMode3OpValue"; 958 let ParserMatchClass = AddrMode3AsmOperand; 959 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 960} 961 962def addrmode3 : AddrMode3 963{ 964 let PrintMethod = "printAddrMode3Operand<false>"; 965} 966 967def addrmode3_pre : AddrMode3 968{ 969 let PrintMethod = "printAddrMode3Operand<true>"; 970} 971 972// FIXME: split into imm vs. reg versions. 973// FIXME: parser method to handle +/- register. 974def AM3OffsetAsmOperand : AsmOperandClass { 975 let Name = "AM3Offset"; 976 let ParserMethod = "parseAM3Offset"; 977} 978def am3offset : MemOperand, 979 ComplexPattern<i32, 2, "SelectAddrMode3Offset", 980 [], [SDNPWantRoot]> { 981 let EncoderMethod = "getAddrMode3OffsetOpValue"; 982 let PrintMethod = "printAddrMode3OffsetOperand"; 983 let ParserMatchClass = AM3OffsetAsmOperand; 984 let MIOperandInfo = (ops GPR, i32imm); 985} 986 987// ldstm_mode := {ia, ib, da, db} 988// 989def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> { 990 let EncoderMethod = "getLdStmModeOpValue"; 991 let PrintMethod = "printLdStmModeOperand"; 992} 993 994// addrmode5 := reg +/- imm8*4 995// 996def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; } 997class AddrMode5 : MemOperand, 998 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 999 let EncoderMethod = "getAddrMode5OpValue"; 1000 let DecoderMethod = "DecodeAddrMode5Operand"; 1001 let ParserMatchClass = AddrMode5AsmOperand; 1002 let MIOperandInfo = (ops GPR:$base, i32imm); 1003} 1004 1005def addrmode5 : AddrMode5 { 1006 let PrintMethod = "printAddrMode5Operand<false>"; 1007} 1008 1009def addrmode5_pre : AddrMode5 { 1010 let PrintMethod = "printAddrMode5Operand<true>"; 1011} 1012 1013// addrmode5fp16 := reg +/- imm8*2 1014// 1015def AddrMode5FP16AsmOperand : AsmOperandClass { let Name = "AddrMode5FP16"; } 1016class AddrMode5FP16 : Operand<i32>, 1017 ComplexPattern<i32, 2, "SelectAddrMode5FP16", []> { 1018 let EncoderMethod = "getAddrMode5FP16OpValue"; 1019 let DecoderMethod = "DecodeAddrMode5FP16Operand"; 1020 let ParserMatchClass = AddrMode5FP16AsmOperand; 1021 let MIOperandInfo = (ops GPR:$base, i32imm); 1022} 1023 1024def addrmode5fp16 : AddrMode5FP16 { 1025 let PrintMethod = "printAddrMode5FP16Operand<false>"; 1026} 1027 1028// addrmode6 := reg with optional alignment 1029// 1030def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; } 1031def addrmode6 : MemOperand, 1032 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1033 let PrintMethod = "printAddrMode6Operand"; 1034 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1035 let EncoderMethod = "getAddrMode6AddressOpValue"; 1036 let DecoderMethod = "DecodeAddrMode6Operand"; 1037 let ParserMatchClass = AddrMode6AsmOperand; 1038} 1039 1040def am6offset : MemOperand, 1041 ComplexPattern<i32, 1, "SelectAddrMode6Offset", 1042 [], [SDNPWantRoot]> { 1043 let PrintMethod = "printAddrMode6OffsetOperand"; 1044 let MIOperandInfo = (ops GPR); 1045 let EncoderMethod = "getAddrMode6OffsetOpValue"; 1046 let DecoderMethod = "DecodeGPRRegisterClass"; 1047} 1048 1049// Special version of addrmode6 to handle alignment encoding for VST1/VLD1 1050// (single element from one lane) for size 32. 1051def addrmode6oneL32 : MemOperand, 1052 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1053 let PrintMethod = "printAddrMode6Operand"; 1054 let MIOperandInfo = (ops GPR:$addr, i32imm); 1055 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue"; 1056} 1057 1058// Base class for addrmode6 with specific alignment restrictions. 1059class AddrMode6Align : MemOperand, 1060 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1061 let PrintMethod = "printAddrMode6Operand"; 1062 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1063 let EncoderMethod = "getAddrMode6AddressOpValue"; 1064 let DecoderMethod = "DecodeAddrMode6Operand"; 1065} 1066 1067// Special version of addrmode6 to handle no allowed alignment encoding for 1068// VLD/VST instructions and checking the alignment is not specified. 1069def AddrMode6AlignNoneAsmOperand : AsmOperandClass { 1070 let Name = "AlignedMemoryNone"; 1071 let DiagnosticType = "AlignedMemoryRequiresNone"; 1072} 1073def addrmode6alignNone : AddrMode6Align { 1074 // The alignment specifier can only be omitted. 1075 let ParserMatchClass = AddrMode6AlignNoneAsmOperand; 1076} 1077 1078// Special version of addrmode6 to handle 16-bit alignment encoding for 1079// VLD/VST instructions and checking the alignment value. 1080def AddrMode6Align16AsmOperand : AsmOperandClass { 1081 let Name = "AlignedMemory16"; 1082 let DiagnosticType = "AlignedMemoryRequires16"; 1083} 1084def addrmode6align16 : AddrMode6Align { 1085 // The alignment specifier can only be 16 or omitted. 1086 let ParserMatchClass = AddrMode6Align16AsmOperand; 1087} 1088 1089// Special version of addrmode6 to handle 32-bit alignment encoding for 1090// VLD/VST instructions and checking the alignment value. 1091def AddrMode6Align32AsmOperand : AsmOperandClass { 1092 let Name = "AlignedMemory32"; 1093 let DiagnosticType = "AlignedMemoryRequires32"; 1094} 1095def addrmode6align32 : AddrMode6Align { 1096 // The alignment specifier can only be 32 or omitted. 1097 let ParserMatchClass = AddrMode6Align32AsmOperand; 1098} 1099 1100// Special version of addrmode6 to handle 64-bit alignment encoding for 1101// VLD/VST instructions and checking the alignment value. 1102def AddrMode6Align64AsmOperand : AsmOperandClass { 1103 let Name = "AlignedMemory64"; 1104 let DiagnosticType = "AlignedMemoryRequires64"; 1105} 1106def addrmode6align64 : AddrMode6Align { 1107 // The alignment specifier can only be 64 or omitted. 1108 let ParserMatchClass = AddrMode6Align64AsmOperand; 1109} 1110 1111// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1112// for VLD/VST instructions and checking the alignment value. 1113def AddrMode6Align64or128AsmOperand : AsmOperandClass { 1114 let Name = "AlignedMemory64or128"; 1115 let DiagnosticType = "AlignedMemoryRequires64or128"; 1116} 1117def addrmode6align64or128 : AddrMode6Align { 1118 // The alignment specifier can only be 64, 128 or omitted. 1119 let ParserMatchClass = AddrMode6Align64or128AsmOperand; 1120} 1121 1122// Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment 1123// encoding for VLD/VST instructions and checking the alignment value. 1124def AddrMode6Align64or128or256AsmOperand : AsmOperandClass { 1125 let Name = "AlignedMemory64or128or256"; 1126 let DiagnosticType = "AlignedMemoryRequires64or128or256"; 1127} 1128def addrmode6align64or128or256 : AddrMode6Align { 1129 // The alignment specifier can only be 64, 128, 256 or omitted. 1130 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand; 1131} 1132 1133// Special version of addrmode6 to handle alignment encoding for VLD-dup 1134// instructions, specifically VLD4-dup. 1135def addrmode6dup : MemOperand, 1136 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1137 let PrintMethod = "printAddrMode6Operand"; 1138 let MIOperandInfo = (ops GPR:$addr, i32imm); 1139 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1140 // FIXME: This is close, but not quite right. The alignment specifier is 1141 // different. 1142 let ParserMatchClass = AddrMode6AsmOperand; 1143} 1144 1145// Base class for addrmode6dup with specific alignment restrictions. 1146class AddrMode6DupAlign : MemOperand, 1147 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1148 let PrintMethod = "printAddrMode6Operand"; 1149 let MIOperandInfo = (ops GPR:$addr, i32imm); 1150 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1151} 1152 1153// Special version of addrmode6 to handle no allowed alignment encoding for 1154// VLD-dup instruction and checking the alignment is not specified. 1155def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass { 1156 let Name = "DupAlignedMemoryNone"; 1157 let DiagnosticType = "DupAlignedMemoryRequiresNone"; 1158} 1159def addrmode6dupalignNone : AddrMode6DupAlign { 1160 // The alignment specifier can only be omitted. 1161 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand; 1162} 1163 1164// Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup 1165// instruction and checking the alignment value. 1166def AddrMode6dupAlign16AsmOperand : AsmOperandClass { 1167 let Name = "DupAlignedMemory16"; 1168 let DiagnosticType = "DupAlignedMemoryRequires16"; 1169} 1170def addrmode6dupalign16 : AddrMode6DupAlign { 1171 // The alignment specifier can only be 16 or omitted. 1172 let ParserMatchClass = AddrMode6dupAlign16AsmOperand; 1173} 1174 1175// Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup 1176// instruction and checking the alignment value. 1177def AddrMode6dupAlign32AsmOperand : AsmOperandClass { 1178 let Name = "DupAlignedMemory32"; 1179 let DiagnosticType = "DupAlignedMemoryRequires32"; 1180} 1181def addrmode6dupalign32 : AddrMode6DupAlign { 1182 // The alignment specifier can only be 32 or omitted. 1183 let ParserMatchClass = AddrMode6dupAlign32AsmOperand; 1184} 1185 1186// Special version of addrmode6 to handle 64-bit alignment encoding for VLD 1187// instructions and checking the alignment value. 1188def AddrMode6dupAlign64AsmOperand : AsmOperandClass { 1189 let Name = "DupAlignedMemory64"; 1190 let DiagnosticType = "DupAlignedMemoryRequires64"; 1191} 1192def addrmode6dupalign64 : AddrMode6DupAlign { 1193 // The alignment specifier can only be 64 or omitted. 1194 let ParserMatchClass = AddrMode6dupAlign64AsmOperand; 1195} 1196 1197// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1198// for VLD instructions and checking the alignment value. 1199def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass { 1200 let Name = "DupAlignedMemory64or128"; 1201 let DiagnosticType = "DupAlignedMemoryRequires64or128"; 1202} 1203def addrmode6dupalign64or128 : AddrMode6DupAlign { 1204 // The alignment specifier can only be 64, 128 or omitted. 1205 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand; 1206} 1207 1208// addrmodepc := pc + reg 1209// 1210def addrmodepc : MemOperand, 1211 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 1212 let PrintMethod = "printAddrModePCOperand"; 1213 let MIOperandInfo = (ops GPR, i32imm); 1214} 1215 1216// addr_offset_none := reg 1217// 1218def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; } 1219def addr_offset_none : MemOperand, 1220 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> { 1221 let PrintMethod = "printAddrMode7Operand"; 1222 let DecoderMethod = "DecodeAddrMode7Operand"; 1223 let ParserMatchClass = MemNoOffsetAsmOperand; 1224 let MIOperandInfo = (ops GPR:$base); 1225} 1226 1227def nohash_imm : Operand<i32> { 1228 let PrintMethod = "printNoHashImmediate"; 1229} 1230 1231def CoprocNumAsmOperand : AsmOperandClass { 1232 let Name = "CoprocNum"; 1233 let ParserMethod = "parseCoprocNumOperand"; 1234} 1235def p_imm : Operand<i32> { 1236 let PrintMethod = "printPImmediate"; 1237 let ParserMatchClass = CoprocNumAsmOperand; 1238 let DecoderMethod = "DecodeCoprocessor"; 1239} 1240 1241def CoprocRegAsmOperand : AsmOperandClass { 1242 let Name = "CoprocReg"; 1243 let ParserMethod = "parseCoprocRegOperand"; 1244} 1245def c_imm : Operand<i32> { 1246 let PrintMethod = "printCImmediate"; 1247 let ParserMatchClass = CoprocRegAsmOperand; 1248} 1249def CoprocOptionAsmOperand : AsmOperandClass { 1250 let Name = "CoprocOption"; 1251 let ParserMethod = "parseCoprocOptionOperand"; 1252} 1253def coproc_option_imm : Operand<i32> { 1254 let PrintMethod = "printCoprocOptionImm"; 1255 let ParserMatchClass = CoprocOptionAsmOperand; 1256} 1257 1258//===----------------------------------------------------------------------===// 1259 1260include "ARMInstrFormats.td" 1261 1262//===----------------------------------------------------------------------===// 1263// Multiclass helpers... 1264// 1265 1266/// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a 1267/// binop that produces a value. 1268let TwoOperandAliasConstraint = "$Rn = $Rd" in 1269multiclass AsI1_bin_irs<bits<4> opcod, string opc, 1270 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1271 SDPatternOperator opnode, bit Commutable = 0> { 1272 // The register-immediate version is re-materializable. This is useful 1273 // in particular for taking the address of a local. 1274 let isReMaterializable = 1 in { 1275 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1276 iii, opc, "\t$Rd, $Rn, $imm", 1277 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>, 1278 Sched<[WriteALU, ReadALU]> { 1279 bits<4> Rd; 1280 bits<4> Rn; 1281 bits<12> imm; 1282 let Inst{25} = 1; 1283 let Inst{19-16} = Rn; 1284 let Inst{15-12} = Rd; 1285 let Inst{11-0} = imm; 1286 } 1287 } 1288 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1289 iir, opc, "\t$Rd, $Rn, $Rm", 1290 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, 1291 Sched<[WriteALU, ReadALU, ReadALU]> { 1292 bits<4> Rd; 1293 bits<4> Rn; 1294 bits<4> Rm; 1295 let Inst{25} = 0; 1296 let isCommutable = Commutable; 1297 let Inst{19-16} = Rn; 1298 let Inst{15-12} = Rd; 1299 let Inst{11-4} = 0b00000000; 1300 let Inst{3-0} = Rm; 1301 } 1302 1303 def rsi : AsI1<opcod, (outs GPR:$Rd), 1304 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1305 iis, opc, "\t$Rd, $Rn, $shift", 1306 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>, 1307 Sched<[WriteALUsi, ReadALU]> { 1308 bits<4> Rd; 1309 bits<4> Rn; 1310 bits<12> shift; 1311 let Inst{25} = 0; 1312 let Inst{19-16} = Rn; 1313 let Inst{15-12} = Rd; 1314 let Inst{11-5} = shift{11-5}; 1315 let Inst{4} = 0; 1316 let Inst{3-0} = shift{3-0}; 1317 } 1318 1319 def rsr : AsI1<opcod, (outs GPR:$Rd), 1320 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1321 iis, opc, "\t$Rd, $Rn, $shift", 1322 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>, 1323 Sched<[WriteALUsr, ReadALUsr]> { 1324 bits<4> Rd; 1325 bits<4> Rn; 1326 bits<12> shift; 1327 let Inst{25} = 0; 1328 let Inst{19-16} = Rn; 1329 let Inst{15-12} = Rd; 1330 let Inst{11-8} = shift{11-8}; 1331 let Inst{7} = 0; 1332 let Inst{6-5} = shift{6-5}; 1333 let Inst{4} = 1; 1334 let Inst{3-0} = shift{3-0}; 1335 } 1336} 1337 1338/// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are 1339/// reversed. The 'rr' form is only defined for the disassembler; for codegen 1340/// it is equivalent to the AsI1_bin_irs counterpart. 1341let TwoOperandAliasConstraint = "$Rn = $Rd" in 1342multiclass AsI1_rbin_irs<bits<4> opcod, string opc, 1343 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1344 SDNode opnode, bit Commutable = 0> { 1345 // The register-immediate version is re-materializable. This is useful 1346 // in particular for taking the address of a local. 1347 let isReMaterializable = 1 in { 1348 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1349 iii, opc, "\t$Rd, $Rn, $imm", 1350 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>, 1351 Sched<[WriteALU, ReadALU]> { 1352 bits<4> Rd; 1353 bits<4> Rn; 1354 bits<12> imm; 1355 let Inst{25} = 1; 1356 let Inst{19-16} = Rn; 1357 let Inst{15-12} = Rd; 1358 let Inst{11-0} = imm; 1359 } 1360 } 1361 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1362 iir, opc, "\t$Rd, $Rn, $Rm", 1363 [/* pattern left blank */]>, 1364 Sched<[WriteALU, ReadALU, ReadALU]> { 1365 bits<4> Rd; 1366 bits<4> Rn; 1367 bits<4> Rm; 1368 let Inst{11-4} = 0b00000000; 1369 let Inst{25} = 0; 1370 let Inst{3-0} = Rm; 1371 let Inst{15-12} = Rd; 1372 let Inst{19-16} = Rn; 1373 } 1374 1375 def rsi : AsI1<opcod, (outs GPR:$Rd), 1376 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1377 iis, opc, "\t$Rd, $Rn, $shift", 1378 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>, 1379 Sched<[WriteALUsi, ReadALU]> { 1380 bits<4> Rd; 1381 bits<4> Rn; 1382 bits<12> shift; 1383 let Inst{25} = 0; 1384 let Inst{19-16} = Rn; 1385 let Inst{15-12} = Rd; 1386 let Inst{11-5} = shift{11-5}; 1387 let Inst{4} = 0; 1388 let Inst{3-0} = shift{3-0}; 1389 } 1390 1391 def rsr : AsI1<opcod, (outs GPR:$Rd), 1392 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1393 iis, opc, "\t$Rd, $Rn, $shift", 1394 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>, 1395 Sched<[WriteALUsr, ReadALUsr]> { 1396 bits<4> Rd; 1397 bits<4> Rn; 1398 bits<12> shift; 1399 let Inst{25} = 0; 1400 let Inst{19-16} = Rn; 1401 let Inst{15-12} = Rd; 1402 let Inst{11-8} = shift{11-8}; 1403 let Inst{7} = 0; 1404 let Inst{6-5} = shift{6-5}; 1405 let Inst{4} = 1; 1406 let Inst{3-0} = shift{3-0}; 1407 } 1408} 1409 1410/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default. 1411/// 1412/// These opcodes will be converted to the real non-S opcodes by 1413/// AdjustInstrPostInstrSelection after giving them an optional CPSR operand. 1414let hasPostISelHook = 1, Defs = [CPSR] in { 1415multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir, 1416 InstrItinClass iis, SDNode opnode, 1417 bit Commutable = 0> { 1418 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1419 4, iii, 1420 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>, 1421 Sched<[WriteALU, ReadALU]>; 1422 1423 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p), 1424 4, iir, 1425 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>, 1426 Sched<[WriteALU, ReadALU, ReadALU]> { 1427 let isCommutable = Commutable; 1428 } 1429 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1430 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1431 4, iis, 1432 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1433 so_reg_imm:$shift))]>, 1434 Sched<[WriteALUsi, ReadALU]>; 1435 1436 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1437 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1438 4, iis, 1439 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1440 so_reg_reg:$shift))]>, 1441 Sched<[WriteALUSsr, ReadALUsr]>; 1442} 1443} 1444 1445/// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG 1446/// operands are reversed. 1447let hasPostISelHook = 1, Defs = [CPSR] in { 1448multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir, 1449 InstrItinClass iis, SDNode opnode, 1450 bit Commutable = 0> { 1451 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1452 4, iii, 1453 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>, 1454 Sched<[WriteALU, ReadALU]>; 1455 1456 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1457 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1458 4, iis, 1459 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, 1460 GPR:$Rn))]>, 1461 Sched<[WriteALUsi, ReadALU]>; 1462 1463 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1464 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1465 4, iis, 1466 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, 1467 GPR:$Rn))]>, 1468 Sched<[WriteALUSsr, ReadALUsr]>; 1469} 1470} 1471 1472/// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test 1473/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 1474/// a explicit result, only implicitly set CPSR. 1475let isCompare = 1, Defs = [CPSR] in { 1476multiclass AI1_cmp_irs<bits<4> opcod, string opc, 1477 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1478 SDPatternOperator opnode, bit Commutable = 0, 1479 string rrDecoderMethod = ""> { 1480 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii, 1481 opc, "\t$Rn, $imm", 1482 [(opnode GPR:$Rn, mod_imm:$imm)]>, 1483 Sched<[WriteCMP, ReadALU]> { 1484 bits<4> Rn; 1485 bits<12> imm; 1486 let Inst{25} = 1; 1487 let Inst{20} = 1; 1488 let Inst{19-16} = Rn; 1489 let Inst{15-12} = 0b0000; 1490 let Inst{11-0} = imm; 1491 1492 let Unpredictable{15-12} = 0b1111; 1493 } 1494 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir, 1495 opc, "\t$Rn, $Rm", 1496 [(opnode GPR:$Rn, GPR:$Rm)]>, 1497 Sched<[WriteCMP, ReadALU, ReadALU]> { 1498 bits<4> Rn; 1499 bits<4> Rm; 1500 let isCommutable = Commutable; 1501 let Inst{25} = 0; 1502 let Inst{20} = 1; 1503 let Inst{19-16} = Rn; 1504 let Inst{15-12} = 0b0000; 1505 let Inst{11-4} = 0b00000000; 1506 let Inst{3-0} = Rm; 1507 let DecoderMethod = rrDecoderMethod; 1508 1509 let Unpredictable{15-12} = 0b1111; 1510 } 1511 def rsi : AI1<opcod, (outs), 1512 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis, 1513 opc, "\t$Rn, $shift", 1514 [(opnode GPR:$Rn, so_reg_imm:$shift)]>, 1515 Sched<[WriteCMPsi, ReadALU]> { 1516 bits<4> Rn; 1517 bits<12> shift; 1518 let Inst{25} = 0; 1519 let Inst{20} = 1; 1520 let Inst{19-16} = Rn; 1521 let Inst{15-12} = 0b0000; 1522 let Inst{11-5} = shift{11-5}; 1523 let Inst{4} = 0; 1524 let Inst{3-0} = shift{3-0}; 1525 1526 let Unpredictable{15-12} = 0b1111; 1527 } 1528 def rsr : AI1<opcod, (outs), 1529 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis, 1530 opc, "\t$Rn, $shift", 1531 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>, 1532 Sched<[WriteCMPsr, ReadALU]> { 1533 bits<4> Rn; 1534 bits<12> shift; 1535 let Inst{25} = 0; 1536 let Inst{20} = 1; 1537 let Inst{19-16} = Rn; 1538 let Inst{15-12} = 0b0000; 1539 let Inst{11-8} = shift{11-8}; 1540 let Inst{7} = 0; 1541 let Inst{6-5} = shift{6-5}; 1542 let Inst{4} = 1; 1543 let Inst{3-0} = shift{3-0}; 1544 1545 let Unpredictable{15-12} = 0b1111; 1546 } 1547 1548} 1549} 1550 1551/// AI_ext_rrot - A unary operation with two forms: one whose operand is a 1552/// register and one whose operand is a register rotated by 8/16/24. 1553/// FIXME: Remove the 'r' variant. Its rot_imm is zero. 1554class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> 1555 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1556 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", 1557 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1558 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1559 bits<4> Rd; 1560 bits<4> Rm; 1561 bits<2> rot; 1562 let Inst{19-16} = 0b1111; 1563 let Inst{15-12} = Rd; 1564 let Inst{11-10} = rot; 1565 let Inst{3-0} = Rm; 1566} 1567 1568class AI_ext_rrot_np<bits<8> opcod, string opc> 1569 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1570 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>, 1571 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1572 bits<2> rot; 1573 let Inst{19-16} = 0b1111; 1574 let Inst{11-10} = rot; 1575 } 1576 1577/// AI_exta_rrot - A binary operation with two forms: one whose operand is a 1578/// register and one whose operand is a register rotated by 8/16/24. 1579class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> 1580 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1581 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", 1582 [(set GPRnopc:$Rd, (opnode GPR:$Rn, 1583 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1584 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1585 bits<4> Rd; 1586 bits<4> Rm; 1587 bits<4> Rn; 1588 bits<2> rot; 1589 let Inst{19-16} = Rn; 1590 let Inst{15-12} = Rd; 1591 let Inst{11-10} = rot; 1592 let Inst{9-4} = 0b000111; 1593 let Inst{3-0} = Rm; 1594} 1595 1596class AI_exta_rrot_np<bits<8> opcod, string opc> 1597 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1598 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>, 1599 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1600 bits<4> Rn; 1601 bits<2> rot; 1602 let Inst{19-16} = Rn; 1603 let Inst{11-10} = rot; 1604} 1605 1606/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. 1607let TwoOperandAliasConstraint = "$Rn = $Rd" in 1608multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode, 1609 bit Commutable = 0> { 1610 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1611 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1612 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1613 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>, 1614 Requires<[IsARM]>, 1615 Sched<[WriteALU, ReadALU]> { 1616 bits<4> Rd; 1617 bits<4> Rn; 1618 bits<12> imm; 1619 let Inst{25} = 1; 1620 let Inst{15-12} = Rd; 1621 let Inst{19-16} = Rn; 1622 let Inst{11-0} = imm; 1623 } 1624 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1625 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1626 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>, 1627 Requires<[IsARM]>, 1628 Sched<[WriteALU, ReadALU, ReadALU]> { 1629 bits<4> Rd; 1630 bits<4> Rn; 1631 bits<4> Rm; 1632 let Inst{11-4} = 0b00000000; 1633 let Inst{25} = 0; 1634 let isCommutable = Commutable; 1635 let Inst{3-0} = Rm; 1636 let Inst{15-12} = Rd; 1637 let Inst{19-16} = Rn; 1638 } 1639 def rsi : AsI1<opcod, (outs GPR:$Rd), 1640 (ins GPR:$Rn, so_reg_imm:$shift), 1641 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1642 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>, 1643 Requires<[IsARM]>, 1644 Sched<[WriteALUsi, ReadALU]> { 1645 bits<4> Rd; 1646 bits<4> Rn; 1647 bits<12> shift; 1648 let Inst{25} = 0; 1649 let Inst{19-16} = Rn; 1650 let Inst{15-12} = Rd; 1651 let Inst{11-5} = shift{11-5}; 1652 let Inst{4} = 0; 1653 let Inst{3-0} = shift{3-0}; 1654 } 1655 def rsr : AsI1<opcod, (outs GPRnopc:$Rd), 1656 (ins GPRnopc:$Rn, so_reg_reg:$shift), 1657 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1658 [(set GPRnopc:$Rd, CPSR, 1659 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>, 1660 Requires<[IsARM]>, 1661 Sched<[WriteALUsr, ReadALUsr]> { 1662 bits<4> Rd; 1663 bits<4> Rn; 1664 bits<12> shift; 1665 let Inst{25} = 0; 1666 let Inst{19-16} = Rn; 1667 let Inst{15-12} = Rd; 1668 let Inst{11-8} = shift{11-8}; 1669 let Inst{7} = 0; 1670 let Inst{6-5} = shift{6-5}; 1671 let Inst{4} = 1; 1672 let Inst{3-0} = shift{3-0}; 1673 } 1674 } 1675} 1676 1677/// AI1_rsc_irs - Define instructions and patterns for rsc 1678let TwoOperandAliasConstraint = "$Rn = $Rd" in 1679multiclass AI1_rsc_irs<bits<4> opcod, string opc, SDNode opnode> { 1680 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1681 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1682 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1683 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>, 1684 Requires<[IsARM]>, 1685 Sched<[WriteALU, ReadALU]> { 1686 bits<4> Rd; 1687 bits<4> Rn; 1688 bits<12> imm; 1689 let Inst{25} = 1; 1690 let Inst{15-12} = Rd; 1691 let Inst{19-16} = Rn; 1692 let Inst{11-0} = imm; 1693 } 1694 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1695 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1696 [/* pattern left blank */]>, 1697 Sched<[WriteALU, ReadALU, ReadALU]> { 1698 bits<4> Rd; 1699 bits<4> Rn; 1700 bits<4> Rm; 1701 let Inst{11-4} = 0b00000000; 1702 let Inst{25} = 0; 1703 let Inst{3-0} = Rm; 1704 let Inst{15-12} = Rd; 1705 let Inst{19-16} = Rn; 1706 } 1707 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), 1708 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1709 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>, 1710 Requires<[IsARM]>, 1711 Sched<[WriteALUsi, ReadALU]> { 1712 bits<4> Rd; 1713 bits<4> Rn; 1714 bits<12> shift; 1715 let Inst{25} = 0; 1716 let Inst{19-16} = Rn; 1717 let Inst{15-12} = Rd; 1718 let Inst{11-5} = shift{11-5}; 1719 let Inst{4} = 0; 1720 let Inst{3-0} = shift{3-0}; 1721 } 1722 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), 1723 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1724 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>, 1725 Requires<[IsARM]>, 1726 Sched<[WriteALUsr, ReadALUsr]> { 1727 bits<4> Rd; 1728 bits<4> Rn; 1729 bits<12> shift; 1730 let Inst{25} = 0; 1731 let Inst{19-16} = Rn; 1732 let Inst{15-12} = Rd; 1733 let Inst{11-8} = shift{11-8}; 1734 let Inst{7} = 0; 1735 let Inst{6-5} = shift{6-5}; 1736 let Inst{4} = 1; 1737 let Inst{3-0} = shift{3-0}; 1738 } 1739 } 1740} 1741 1742let canFoldAsLoad = 1, isReMaterializable = 1 in { 1743multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii, 1744 InstrItinClass iir, PatFrag opnode> { 1745 // Note: We use the complex addrmode_imm12 rather than just an input 1746 // GPR and a constrained immediate so that we can use this to match 1747 // frame index references and avoid matching constant pool references. 1748 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 1749 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1750 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { 1751 bits<4> Rt; 1752 bits<17> addr; 1753 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1754 let Inst{19-16} = addr{16-13}; // Rn 1755 let Inst{15-12} = Rt; 1756 let Inst{11-0} = addr{11-0}; // imm12 1757 } 1758 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift), 1759 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1760 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { 1761 bits<4> Rt; 1762 bits<17> shift; 1763 let shift{4} = 0; // Inst{4} = 0 1764 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1765 let Inst{19-16} = shift{16-13}; // Rn 1766 let Inst{15-12} = Rt; 1767 let Inst{11-0} = shift{11-0}; 1768 } 1769} 1770} 1771 1772let canFoldAsLoad = 1, isReMaterializable = 1 in { 1773multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii, 1774 InstrItinClass iir, PatFrag opnode> { 1775 // Note: We use the complex addrmode_imm12 rather than just an input 1776 // GPR and a constrained immediate so that we can use this to match 1777 // frame index references and avoid matching constant pool references. 1778 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), 1779 (ins addrmode_imm12:$addr), 1780 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1781 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> { 1782 bits<4> Rt; 1783 bits<17> addr; 1784 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1785 let Inst{19-16} = addr{16-13}; // Rn 1786 let Inst{15-12} = Rt; 1787 let Inst{11-0} = addr{11-0}; // imm12 1788 } 1789 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), 1790 (ins ldst_so_reg:$shift), 1791 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1792 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> { 1793 bits<4> Rt; 1794 bits<17> shift; 1795 let shift{4} = 0; // Inst{4} = 0 1796 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1797 let Inst{19-16} = shift{16-13}; // Rn 1798 let Inst{15-12} = Rt; 1799 let Inst{11-0} = shift{11-0}; 1800 } 1801} 1802} 1803 1804 1805multiclass AI_str1<bit isByte, string opc, InstrItinClass iii, 1806 InstrItinClass iir, PatFrag opnode> { 1807 // Note: We use the complex addrmode_imm12 rather than just an input 1808 // GPR and a constrained immediate so that we can use this to match 1809 // frame index references and avoid matching constant pool references. 1810 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1811 (ins GPR:$Rt, addrmode_imm12:$addr), 1812 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1813 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> { 1814 bits<4> Rt; 1815 bits<17> addr; 1816 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1817 let Inst{19-16} = addr{16-13}; // Rn 1818 let Inst{15-12} = Rt; 1819 let Inst{11-0} = addr{11-0}; // imm12 1820 } 1821 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift), 1822 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1823 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> { 1824 bits<4> Rt; 1825 bits<17> shift; 1826 let shift{4} = 0; // Inst{4} = 0 1827 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1828 let Inst{19-16} = shift{16-13}; // Rn 1829 let Inst{15-12} = Rt; 1830 let Inst{11-0} = shift{11-0}; 1831 } 1832} 1833 1834multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii, 1835 InstrItinClass iir, PatFrag opnode> { 1836 // Note: We use the complex addrmode_imm12 rather than just an input 1837 // GPR and a constrained immediate so that we can use this to match 1838 // frame index references and avoid matching constant pool references. 1839 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1840 (ins GPRnopc:$Rt, addrmode_imm12:$addr), 1841 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1842 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> { 1843 bits<4> Rt; 1844 bits<17> addr; 1845 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1846 let Inst{19-16} = addr{16-13}; // Rn 1847 let Inst{15-12} = Rt; 1848 let Inst{11-0} = addr{11-0}; // imm12 1849 } 1850 def rs : AI2ldst<0b011, 0, isByte, (outs), 1851 (ins GPRnopc:$Rt, ldst_so_reg:$shift), 1852 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1853 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> { 1854 bits<4> Rt; 1855 bits<17> shift; 1856 let shift{4} = 0; // Inst{4} = 0 1857 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1858 let Inst{19-16} = shift{16-13}; // Rn 1859 let Inst{15-12} = Rt; 1860 let Inst{11-0} = shift{11-0}; 1861 } 1862} 1863 1864 1865//===----------------------------------------------------------------------===// 1866// Instructions 1867//===----------------------------------------------------------------------===// 1868 1869//===----------------------------------------------------------------------===// 1870// Miscellaneous Instructions. 1871// 1872 1873/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 1874/// the function. The first operand is the ID# for this instruction, the second 1875/// is the index into the MachineConstantPool that this is, the third is the 1876/// size in bytes of this constant pool entry. 1877let hasSideEffects = 0, isNotDuplicable = 1 in 1878def CONSTPOOL_ENTRY : 1879PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1880 i32imm:$size), NoItinerary, []>; 1881 1882/// A jumptable consisting of direct 32-bit addresses of the destination basic 1883/// blocks (either absolute, or relative to the start of the jump-table in PIC 1884/// mode). Used mostly in ARM and Thumb-1 modes. 1885def JUMPTABLE_ADDRS : 1886PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1887 i32imm:$size), NoItinerary, []>; 1888 1889/// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables 1890/// that cannot be optimised to use TBB or TBH. 1891def JUMPTABLE_INSTS : 1892PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1893 i32imm:$size), NoItinerary, []>; 1894 1895/// A jumptable consisting of 8-bit unsigned integers representing offsets from 1896/// a TBB instruction. 1897def JUMPTABLE_TBB : 1898PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1899 i32imm:$size), NoItinerary, []>; 1900 1901/// A jumptable consisting of 16-bit unsigned integers representing offsets from 1902/// a TBH instruction. 1903def JUMPTABLE_TBH : 1904PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1905 i32imm:$size), NoItinerary, []>; 1906 1907 1908// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 1909// from removing one half of the matched pairs. That breaks PEI, which assumes 1910// these will always be in pairs, and asserts if it finds otherwise. Better way? 1911let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 1912def ADJCALLSTACKUP : 1913PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, 1914 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; 1915 1916def ADJCALLSTACKDOWN : 1917PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary, 1918 [(ARMcallseq_start timm:$amt)]>; 1919} 1920 1921def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary, 1922 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>, 1923 Requires<[IsARM, HasV6]> { 1924 bits<8> imm; 1925 let Inst{27-8} = 0b00110010000011110000; 1926 let Inst{7-0} = imm; 1927 let DecoderMethod = "DecodeHINTInstruction"; 1928} 1929 1930def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>; 1931def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>; 1932def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>; 1933def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>; 1934def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>; 1935def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>; 1936def : InstAlias<"esb$p", (HINT 16, pred:$p)>, Requires<[IsARM, HasRAS]>; 1937 1938def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel", 1939 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> { 1940 bits<4> Rd; 1941 bits<4> Rn; 1942 bits<4> Rm; 1943 let Inst{3-0} = Rm; 1944 let Inst{15-12} = Rd; 1945 let Inst{19-16} = Rn; 1946 let Inst{27-20} = 0b01101000; 1947 let Inst{7-4} = 0b1011; 1948 let Inst{11-8} = 0b1111; 1949 let Unpredictable{11-8} = 0b1111; 1950} 1951 1952// The 16-bit operand $val can be used by a debugger to store more information 1953// about the breakpoint. 1954def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 1955 "bkpt", "\t$val", []>, Requires<[IsARM]> { 1956 bits<16> val; 1957 let Inst{3-0} = val{3-0}; 1958 let Inst{19-8} = val{15-4}; 1959 let Inst{27-20} = 0b00010010; 1960 let Inst{31-28} = 0xe; // AL 1961 let Inst{7-4} = 0b0111; 1962} 1963// default immediate for breakpoint mnemonic 1964def : InstAlias<"bkpt", (BKPT 0), 0>, Requires<[IsARM]>; 1965 1966def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 1967 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> { 1968 bits<16> val; 1969 let Inst{3-0} = val{3-0}; 1970 let Inst{19-8} = val{15-4}; 1971 let Inst{27-20} = 0b00010000; 1972 let Inst{31-28} = 0xe; // AL 1973 let Inst{7-4} = 0b0111; 1974} 1975 1976// Change Processor State 1977// FIXME: We should use InstAlias to handle the optional operands. 1978class CPS<dag iops, string asm_ops> 1979 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops), 1980 []>, Requires<[IsARM]> { 1981 bits<2> imod; 1982 bits<3> iflags; 1983 bits<5> mode; 1984 bit M; 1985 1986 let Inst{31-28} = 0b1111; 1987 let Inst{27-20} = 0b00010000; 1988 let Inst{19-18} = imod; 1989 let Inst{17} = M; // Enabled if mode is set; 1990 let Inst{16-9} = 0b00000000; 1991 let Inst{8-6} = iflags; 1992 let Inst{5} = 0; 1993 let Inst{4-0} = mode; 1994} 1995 1996let DecoderMethod = "DecodeCPSInstruction" in { 1997let M = 1 in 1998 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode), 1999 "$imod\t$iflags, $mode">; 2000let mode = 0, M = 0 in 2001 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">; 2002 2003let imod = 0, iflags = 0, M = 1 in 2004 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">; 2005} 2006 2007// Preload signals the memory system of possible future data/instruction access. 2008multiclass APreLoad<bits<1> read, bits<1> data, string opc> { 2009 2010 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm, 2011 IIC_Preload, !strconcat(opc, "\t$addr"), 2012 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>, 2013 Sched<[WritePreLd]> { 2014 bits<4> Rt; 2015 bits<17> addr; 2016 let Inst{31-26} = 0b111101; 2017 let Inst{25} = 0; // 0 for immediate form 2018 let Inst{24} = data; 2019 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2020 let Inst{22} = read; 2021 let Inst{21-20} = 0b01; 2022 let Inst{19-16} = addr{16-13}; // Rn 2023 let Inst{15-12} = 0b1111; 2024 let Inst{11-0} = addr{11-0}; // imm12 2025 } 2026 2027 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, 2028 !strconcat(opc, "\t$shift"), 2029 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>, 2030 Sched<[WritePreLd]> { 2031 bits<17> shift; 2032 let Inst{31-26} = 0b111101; 2033 let Inst{25} = 1; // 1 for register form 2034 let Inst{24} = data; 2035 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2036 let Inst{22} = read; 2037 let Inst{21-20} = 0b01; 2038 let Inst{19-16} = shift{16-13}; // Rn 2039 let Inst{15-12} = 0b1111; 2040 let Inst{11-0} = shift{11-0}; 2041 let Inst{4} = 0; 2042 } 2043} 2044 2045defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>; 2046defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>; 2047defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>; 2048 2049def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary, 2050 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> { 2051 bits<1> end; 2052 let Inst{31-10} = 0b1111000100000001000000; 2053 let Inst{9} = end; 2054 let Inst{8-0} = 0; 2055} 2056 2057def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", 2058 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> { 2059 bits<4> opt; 2060 let Inst{27-4} = 0b001100100000111100001111; 2061 let Inst{3-0} = opt; 2062} 2063 2064// A8.8.247 UDF - Undefined (Encoding A1) 2065def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary, 2066 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> { 2067 bits<16> imm16; 2068 let Inst{31-28} = 0b1110; // AL 2069 let Inst{27-25} = 0b011; 2070 let Inst{24-20} = 0b11111; 2071 let Inst{19-8} = imm16{15-4}; 2072 let Inst{7-4} = 0b1111; 2073 let Inst{3-0} = imm16{3-0}; 2074} 2075 2076/* 2077 * A5.4 Permanently UNDEFINED instructions. 2078 * 2079 * For most targets use UDF #65006, for which the OS will generate SIGTRAP. 2080 * Other UDF encodings generate SIGILL. 2081 * 2082 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb. 2083 * Encoding A1: 2084 * 1110 0111 1111 iiii iiii iiii 1111 iiii 2085 * Encoding T1: 2086 * 1101 1110 iiii iiii 2087 * It uses the following encoding: 2088 * 1110 0111 1111 1110 1101 1110 1111 0000 2089 * - In ARM: UDF #60896; 2090 * - In Thumb: UDF #254 followed by a branch-to-self. 2091 */ 2092let isBarrier = 1, isTerminator = 1 in 2093def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary, 2094 "trap", [(trap)]>, 2095 Requires<[IsARM,UseNaClTrap]> { 2096 let Inst = 0xe7fedef0; 2097} 2098let isBarrier = 1, isTerminator = 1 in 2099def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, 2100 "trap", [(trap)]>, 2101 Requires<[IsARM,DontUseNaClTrap]> { 2102 let Inst = 0xe7ffdefe; 2103} 2104 2105// Address computation and loads and stores in PIC mode. 2106let isNotDuplicable = 1 in { 2107def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 2108 4, IIC_iALUr, 2109 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>, 2110 Sched<[WriteALU, ReadALU]>; 2111 2112let AddedComplexity = 10 in { 2113def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 2114 4, IIC_iLoad_r, 2115 [(set GPR:$dst, (load addrmodepc:$addr))]>; 2116 2117def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2118 4, IIC_iLoad_bh_r, 2119 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>; 2120 2121def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2122 4, IIC_iLoad_bh_r, 2123 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>; 2124 2125def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2126 4, IIC_iLoad_bh_r, 2127 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>; 2128 2129def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2130 4, IIC_iLoad_bh_r, 2131 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>; 2132} 2133let AddedComplexity = 10 in { 2134def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2135 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>; 2136 2137def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2138 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, 2139 addrmodepc:$addr)]>; 2140 2141def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2142 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 2143} 2144} // isNotDuplicable = 1 2145 2146 2147// LEApcrel - Load a pc-relative address into a register without offending the 2148// assembler. 2149let hasSideEffects = 0, isReMaterializable = 1 in 2150// The 'adr' mnemonic encodes differently if the label is before or after 2151// the instruction. The {24-21} opcode bits are set by the fixup, as we don't 2152// know until then which form of the instruction will be used. 2153def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), 2154 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>, 2155 Sched<[WriteALU, ReadALU]> { 2156 bits<4> Rd; 2157 bits<14> label; 2158 let Inst{27-25} = 0b001; 2159 let Inst{24} = 0; 2160 let Inst{23-22} = label{13-12}; 2161 let Inst{21} = 0; 2162 let Inst{20} = 0; 2163 let Inst{19-16} = 0b1111; 2164 let Inst{15-12} = Rd; 2165 let Inst{11-0} = label{11-0}; 2166} 2167 2168let hasSideEffects = 1 in { 2169def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 2170 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2171 2172def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd), 2173 (ins i32imm:$label, pred:$p), 2174 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2175} 2176 2177//===----------------------------------------------------------------------===// 2178// Control Flow Instructions. 2179// 2180 2181let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 2182 // ARMV4T and above 2183 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2184 "bx", "\tlr", [(ARMretflag)]>, 2185 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2186 let Inst{27-0} = 0b0001001011111111111100011110; 2187 } 2188 2189 // ARMV4 only 2190 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2191 "mov", "\tpc, lr", [(ARMretflag)]>, 2192 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> { 2193 let Inst{27-0} = 0b0001101000001111000000001110; 2194 } 2195 2196 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets 2197 // the user-space one). 2198 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p), 2199 4, IIC_Br, 2200 [(ARMintretflag imm:$offset)]>; 2201} 2202 2203// Indirect branches 2204let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 2205 // ARMV4T and above 2206 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst", 2207 [(brind GPR:$dst)]>, 2208 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2209 bits<4> dst; 2210 let Inst{31-4} = 0b1110000100101111111111110001; 2211 let Inst{3-0} = dst; 2212 } 2213 2214 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, 2215 "bx", "\t$dst", [/* pattern left blank */]>, 2216 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2217 bits<4> dst; 2218 let Inst{27-4} = 0b000100101111111111110001; 2219 let Inst{3-0} = dst; 2220 } 2221} 2222 2223// SP is marked as a use to prevent stack-pointer assignments that appear 2224// immediately before calls from potentially appearing dead. 2225let isCall = 1, 2226 // FIXME: Do we really need a non-predicated version? If so, it should 2227 // at least be a pseudo instruction expanding to the predicated version 2228 // at MC lowering time. 2229 Defs = [LR], Uses = [SP] in { 2230 def BL : ABXI<0b1011, (outs), (ins arm_bl_target:$func), 2231 IIC_Br, "bl\t$func", 2232 [(ARMcall tglobaladdr:$func)]>, 2233 Requires<[IsARM]>, Sched<[WriteBrL]> { 2234 let Inst{31-28} = 0b1110; 2235 bits<24> func; 2236 let Inst{23-0} = func; 2237 let DecoderMethod = "DecodeBranchImmInstruction"; 2238 } 2239 2240 def BL_pred : ABI<0b1011, (outs), (ins arm_bl_target:$func), 2241 IIC_Br, "bl", "\t$func", 2242 [(ARMcall_pred tglobaladdr:$func)]>, 2243 Requires<[IsARM]>, Sched<[WriteBrL]> { 2244 bits<24> func; 2245 let Inst{23-0} = func; 2246 let DecoderMethod = "DecodeBranchImmInstruction"; 2247 } 2248 2249 // ARMv5T and above 2250 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm, 2251 IIC_Br, "blx\t$func", 2252 [(ARMcall GPR:$func)]>, 2253 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2254 bits<4> func; 2255 let Inst{31-4} = 0b1110000100101111111111110011; 2256 let Inst{3-0} = func; 2257 } 2258 2259 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm, 2260 IIC_Br, "blx", "\t$func", 2261 [(ARMcall_pred GPR:$func)]>, 2262 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2263 bits<4> func; 2264 let Inst{27-4} = 0b000100101111111111110011; 2265 let Inst{3-0} = func; 2266 } 2267 2268 // ARMv4T 2269 // Note: Restrict $func to the tGPR regclass to prevent it being in LR. 2270 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2271 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2272 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>; 2273 2274 // ARMv4 2275 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2276 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2277 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 2278 2279 // mov lr, pc; b if callee is marked noreturn to avoid confusing the 2280 // return stack predictor. 2281 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins arm_bl_target:$func), 2282 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>, 2283 Requires<[IsARM]>, Sched<[WriteBr]>; 2284} 2285 2286let isBranch = 1, isTerminator = 1 in { 2287 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 2288 // a two-value operand where a dag node expects two operands. :( 2289 def Bcc : ABI<0b1010, (outs), (ins arm_br_target:$target), 2290 IIC_Br, "b", "\t$target", 2291 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>, 2292 Sched<[WriteBr]> { 2293 bits<24> target; 2294 let Inst{23-0} = target; 2295 let DecoderMethod = "DecodeBranchImmInstruction"; 2296 } 2297 2298 let isBarrier = 1 in { 2299 // B is "predicable" since it's just a Bcc with an 'always' condition. 2300 let isPredicable = 1 in 2301 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly 2302 // should be sufficient. 2303 // FIXME: Is B really a Barrier? That doesn't seem right. 2304 def B : ARMPseudoExpand<(outs), (ins arm_br_target:$target), 4, IIC_Br, 2305 [(br bb:$target)], (Bcc arm_br_target:$target, 2306 (ops 14, zero_reg))>, 2307 Sched<[WriteBr]>; 2308 2309 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in { 2310 def BR_JTr : ARMPseudoInst<(outs), 2311 (ins GPR:$target, i32imm:$jt), 2312 0, IIC_Br, 2313 [(ARMbrjt GPR:$target, tjumptable:$jt)]>, 2314 Sched<[WriteBr]>; 2315 // FIXME: This shouldn't use the generic "addrmode2," but rather be split 2316 // into i12 and rs suffixed versions. 2317 def BR_JTm : ARMPseudoInst<(outs), 2318 (ins addrmode2:$target, i32imm:$jt), 2319 0, IIC_Br, 2320 [(ARMbrjt (i32 (load addrmode2:$target)), 2321 tjumptable:$jt)]>, Sched<[WriteBrTbl]>; 2322 def BR_JTadd : ARMPseudoInst<(outs), 2323 (ins GPR:$target, GPR:$idx, i32imm:$jt), 2324 0, IIC_Br, 2325 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>, 2326 Sched<[WriteBrTbl]>; 2327 } // isNotDuplicable = 1, isIndirectBranch = 1 2328 } // isBarrier = 1 2329 2330} 2331 2332// BLX (immediate) 2333def BLXi : AXI<(outs), (ins arm_blx_target:$target), BrMiscFrm, NoItinerary, 2334 "blx\t$target", []>, 2335 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2336 let Inst{31-25} = 0b1111101; 2337 bits<25> target; 2338 let Inst{23-0} = target{24-1}; 2339 let Inst{24} = target{0}; 2340 let isCall = 1; 2341} 2342 2343// Branch and Exchange Jazelle 2344def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", 2345 [/* pattern left blank */]>, Sched<[WriteBr]> { 2346 bits<4> func; 2347 let Inst{23-20} = 0b0010; 2348 let Inst{19-8} = 0xfff; 2349 let Inst{7-4} = 0b0010; 2350 let Inst{3-0} = func; 2351 let isBranch = 1; 2352} 2353 2354// Tail calls. 2355 2356let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { 2357 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>, 2358 Sched<[WriteBr]>; 2359 2360 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>, 2361 Sched<[WriteBr]>; 2362 2363 def TAILJMPd : ARMPseudoExpand<(outs), (ins arm_br_target:$dst), 2364 4, IIC_Br, [], 2365 (Bcc arm_br_target:$dst, (ops 14, zero_reg))>, 2366 Requires<[IsARM]>, Sched<[WriteBr]>; 2367 2368 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst), 2369 4, IIC_Br, [], 2370 (BX GPR:$dst)>, Sched<[WriteBr]>, 2371 Requires<[IsARM]>; 2372} 2373 2374// Secure Monitor Call is a system instruction. 2375def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", 2376 []>, Requires<[IsARM, HasTrustZone]> { 2377 bits<4> opt; 2378 let Inst{23-4} = 0b01100000000000000111; 2379 let Inst{3-0} = opt; 2380} 2381def : MnemonicAlias<"smi", "smc">; 2382 2383// Supervisor Call (Software Interrupt) 2384let isCall = 1, Uses = [SP] in { 2385def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>, 2386 Sched<[WriteBr]> { 2387 bits<24> svc; 2388 let Inst{23-0} = svc; 2389} 2390} 2391 2392// Store Return State 2393class SRSI<bit wb, string asm> 2394 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm, 2395 NoItinerary, asm, "", []> { 2396 bits<5> mode; 2397 let Inst{31-28} = 0b1111; 2398 let Inst{27-25} = 0b100; 2399 let Inst{22} = 1; 2400 let Inst{21} = wb; 2401 let Inst{20} = 0; 2402 let Inst{19-16} = 0b1101; // SP 2403 let Inst{15-5} = 0b00000101000; 2404 let Inst{4-0} = mode; 2405} 2406 2407def SRSDA : SRSI<0, "srsda\tsp, $mode"> { 2408 let Inst{24-23} = 0; 2409} 2410def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> { 2411 let Inst{24-23} = 0; 2412} 2413def SRSDB : SRSI<0, "srsdb\tsp, $mode"> { 2414 let Inst{24-23} = 0b10; 2415} 2416def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> { 2417 let Inst{24-23} = 0b10; 2418} 2419def SRSIA : SRSI<0, "srsia\tsp, $mode"> { 2420 let Inst{24-23} = 0b01; 2421} 2422def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> { 2423 let Inst{24-23} = 0b01; 2424} 2425def SRSIB : SRSI<0, "srsib\tsp, $mode"> { 2426 let Inst{24-23} = 0b11; 2427} 2428def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> { 2429 let Inst{24-23} = 0b11; 2430} 2431 2432def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>; 2433def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>; 2434 2435def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>; 2436def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>; 2437 2438def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>; 2439def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>; 2440 2441def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>; 2442def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>; 2443 2444// Return From Exception 2445class RFEI<bit wb, string asm> 2446 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm, 2447 NoItinerary, asm, "", []> { 2448 bits<4> Rn; 2449 let Inst{31-28} = 0b1111; 2450 let Inst{27-25} = 0b100; 2451 let Inst{22} = 0; 2452 let Inst{21} = wb; 2453 let Inst{20} = 1; 2454 let Inst{19-16} = Rn; 2455 let Inst{15-0} = 0xa00; 2456} 2457 2458def RFEDA : RFEI<0, "rfeda\t$Rn"> { 2459 let Inst{24-23} = 0; 2460} 2461def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> { 2462 let Inst{24-23} = 0; 2463} 2464def RFEDB : RFEI<0, "rfedb\t$Rn"> { 2465 let Inst{24-23} = 0b10; 2466} 2467def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> { 2468 let Inst{24-23} = 0b10; 2469} 2470def RFEIA : RFEI<0, "rfeia\t$Rn"> { 2471 let Inst{24-23} = 0b01; 2472} 2473def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> { 2474 let Inst{24-23} = 0b01; 2475} 2476def RFEIB : RFEI<0, "rfeib\t$Rn"> { 2477 let Inst{24-23} = 0b11; 2478} 2479def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> { 2480 let Inst{24-23} = 0b11; 2481} 2482 2483// Hypervisor Call is a system instruction 2484let isCall = 1 in { 2485def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary, 2486 "hvc", "\t$imm", []>, 2487 Requires<[IsARM, HasVirtualization]> { 2488 bits<16> imm; 2489 2490 // Even though HVC isn't predicable, it's encoding includes a condition field. 2491 // The instruction is undefined if the condition field is 0xf otherwise it is 2492 // unpredictable if it isn't condition AL (0xe). 2493 let Inst{31-28} = 0b1110; 2494 let Unpredictable{31-28} = 0b1111; 2495 let Inst{27-24} = 0b0001; 2496 let Inst{23-20} = 0b0100; 2497 let Inst{19-8} = imm{15-4}; 2498 let Inst{7-4} = 0b0111; 2499 let Inst{3-0} = imm{3-0}; 2500} 2501} 2502 2503// Return from exception in Hypervisor mode. 2504let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in 2505def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>, 2506 Requires<[IsARM, HasVirtualization]> { 2507 let Inst{23-0} = 0b011000000000000001101110; 2508} 2509 2510//===----------------------------------------------------------------------===// 2511// Load / Store Instructions. 2512// 2513 2514// Load 2515 2516 2517defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si, load>; 2518defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si, 2519 zextloadi8>; 2520defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si, store>; 2521defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si, 2522 truncstorei8>; 2523 2524// Special LDR for loads from non-pc-relative constpools. 2525let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0, 2526 isReMaterializable = 1, isCodeGenOnly = 1 in 2527def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 2528 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", 2529 []> { 2530 bits<4> Rt; 2531 bits<17> addr; 2532 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2533 let Inst{19-16} = 0b1111; 2534 let Inst{15-12} = Rt; 2535 let Inst{11-0} = addr{11-0}; // imm12 2536} 2537 2538// Loads with zero extension 2539def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2540 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr", 2541 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>; 2542 2543// Loads with sign extension 2544def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2545 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr", 2546 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>; 2547 2548def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2549 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr", 2550 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>; 2551 2552let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in { 2553 // Load doubleword 2554 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr), 2555 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>, 2556 Requires<[IsARM, HasV5TE]>; 2557} 2558 2559def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2560 NoItinerary, "lda", "\t$Rt, $addr", []>; 2561def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2562 NoItinerary, "ldab", "\t$Rt, $addr", []>; 2563def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2564 NoItinerary, "ldah", "\t$Rt, $addr", []>; 2565 2566// Indexed loads 2567multiclass AI2_ldridx<bit isByte, string opc, 2568 InstrItinClass iii, InstrItinClass iir> { 2569 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2570 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii, 2571 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2572 bits<17> addr; 2573 let Inst{25} = 0; 2574 let Inst{23} = addr{12}; 2575 let Inst{19-16} = addr{16-13}; 2576 let Inst{11-0} = addr{11-0}; 2577 let DecoderMethod = "DecodeLDRPreImm"; 2578 } 2579 2580 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2581 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir, 2582 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2583 bits<17> addr; 2584 let Inst{25} = 1; 2585 let Inst{23} = addr{12}; 2586 let Inst{19-16} = addr{16-13}; 2587 let Inst{11-0} = addr{11-0}; 2588 let Inst{4} = 0; 2589 let DecoderMethod = "DecodeLDRPreReg"; 2590 } 2591 2592 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2593 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2594 IndexModePost, LdFrm, iir, 2595 opc, "\t$Rt, $addr, $offset", 2596 "$addr.base = $Rn_wb", []> { 2597 // {12} isAdd 2598 // {11-0} imm12/Rm 2599 bits<14> offset; 2600 bits<4> addr; 2601 let Inst{25} = 1; 2602 let Inst{23} = offset{12}; 2603 let Inst{19-16} = addr; 2604 let Inst{11-0} = offset{11-0}; 2605 let Inst{4} = 0; 2606 2607 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2608 } 2609 2610 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2611 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2612 IndexModePost, LdFrm, iii, 2613 opc, "\t$Rt, $addr, $offset", 2614 "$addr.base = $Rn_wb", []> { 2615 // {12} isAdd 2616 // {11-0} imm12/Rm 2617 bits<14> offset; 2618 bits<4> addr; 2619 let Inst{25} = 0; 2620 let Inst{23} = offset{12}; 2621 let Inst{19-16} = addr; 2622 let Inst{11-0} = offset{11-0}; 2623 2624 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2625 } 2626 2627} 2628 2629let mayLoad = 1, hasSideEffects = 0 in { 2630// FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or 2631// IIC_iLoad_siu depending on whether it the offset register is shifted. 2632defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>; 2633defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>; 2634} 2635 2636multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> { 2637 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2638 (ins addrmode3_pre:$addr), IndexModePre, 2639 LdMiscFrm, itin, 2640 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2641 bits<14> addr; 2642 let Inst{23} = addr{8}; // U bit 2643 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2644 let Inst{19-16} = addr{12-9}; // Rn 2645 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2646 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2647 let DecoderMethod = "DecodeAddrMode3Instruction"; 2648 } 2649 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2650 (ins addr_offset_none:$addr, am3offset:$offset), 2651 IndexModePost, LdMiscFrm, itin, 2652 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2653 []> { 2654 bits<10> offset; 2655 bits<4> addr; 2656 let Inst{23} = offset{8}; // U bit 2657 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2658 let Inst{19-16} = addr; 2659 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2660 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2661 let DecoderMethod = "DecodeAddrMode3Instruction"; 2662 } 2663} 2664 2665let mayLoad = 1, hasSideEffects = 0 in { 2666defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>; 2667defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>; 2668defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>; 2669let hasExtraDefRegAllocReq = 1 in { 2670def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2671 (ins addrmode3_pre:$addr), IndexModePre, 2672 LdMiscFrm, IIC_iLoad_d_ru, 2673 "ldrd", "\t$Rt, $Rt2, $addr!", 2674 "$addr.base = $Rn_wb", []> { 2675 bits<14> addr; 2676 let Inst{23} = addr{8}; // U bit 2677 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2678 let Inst{19-16} = addr{12-9}; // Rn 2679 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2680 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2681 let DecoderMethod = "DecodeAddrMode3Instruction"; 2682} 2683def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2684 (ins addr_offset_none:$addr, am3offset:$offset), 2685 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru, 2686 "ldrd", "\t$Rt, $Rt2, $addr, $offset", 2687 "$addr.base = $Rn_wb", []> { 2688 bits<10> offset; 2689 bits<4> addr; 2690 let Inst{23} = offset{8}; // U bit 2691 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2692 let Inst{19-16} = addr; 2693 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2694 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2695 let DecoderMethod = "DecodeAddrMode3Instruction"; 2696} 2697} // hasExtraDefRegAllocReq = 1 2698} // mayLoad = 1, hasSideEffects = 0 2699 2700// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT. 2701let mayLoad = 1, hasSideEffects = 0 in { 2702def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2703 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2704 IndexModePost, LdFrm, IIC_iLoad_ru, 2705 "ldrt", "\t$Rt, $addr, $offset", 2706 "$addr.base = $Rn_wb", []> { 2707 // {12} isAdd 2708 // {11-0} imm12/Rm 2709 bits<14> offset; 2710 bits<4> addr; 2711 let Inst{25} = 1; 2712 let Inst{23} = offset{12}; 2713 let Inst{21} = 1; // overwrite 2714 let Inst{19-16} = addr; 2715 let Inst{11-5} = offset{11-5}; 2716 let Inst{4} = 0; 2717 let Inst{3-0} = offset{3-0}; 2718 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2719} 2720 2721def LDRT_POST_IMM 2722 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2723 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2724 IndexModePost, LdFrm, IIC_iLoad_ru, 2725 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2726 // {12} isAdd 2727 // {11-0} imm12/Rm 2728 bits<14> offset; 2729 bits<4> addr; 2730 let Inst{25} = 0; 2731 let Inst{23} = offset{12}; 2732 let Inst{21} = 1; // overwrite 2733 let Inst{19-16} = addr; 2734 let Inst{11-0} = offset{11-0}; 2735 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2736} 2737 2738def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2739 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2740 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2741 "ldrbt", "\t$Rt, $addr, $offset", 2742 "$addr.base = $Rn_wb", []> { 2743 // {12} isAdd 2744 // {11-0} imm12/Rm 2745 bits<14> offset; 2746 bits<4> addr; 2747 let Inst{25} = 1; 2748 let Inst{23} = offset{12}; 2749 let Inst{21} = 1; // overwrite 2750 let Inst{19-16} = addr; 2751 let Inst{11-5} = offset{11-5}; 2752 let Inst{4} = 0; 2753 let Inst{3-0} = offset{3-0}; 2754 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2755} 2756 2757def LDRBT_POST_IMM 2758 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2759 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2760 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2761 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2762 // {12} isAdd 2763 // {11-0} imm12/Rm 2764 bits<14> offset; 2765 bits<4> addr; 2766 let Inst{25} = 0; 2767 let Inst{23} = offset{12}; 2768 let Inst{21} = 1; // overwrite 2769 let Inst{19-16} = addr; 2770 let Inst{11-0} = offset{11-0}; 2771 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2772} 2773 2774multiclass AI3ldrT<bits<4> op, string opc> { 2775 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb), 2776 (ins addr_offset_none:$addr, postidx_imm8:$offset), 2777 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2778 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 2779 bits<9> offset; 2780 let Inst{23} = offset{8}; 2781 let Inst{22} = 1; 2782 let Inst{11-8} = offset{7-4}; 2783 let Inst{3-0} = offset{3-0}; 2784 } 2785 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb), 2786 (ins addr_offset_none:$addr, postidx_reg:$Rm), 2787 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2788 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 2789 bits<5> Rm; 2790 let Inst{23} = Rm{4}; 2791 let Inst{22} = 0; 2792 let Inst{11-8} = 0; 2793 let Unpredictable{11-8} = 0b1111; 2794 let Inst{3-0} = Rm{3-0}; 2795 let DecoderMethod = "DecodeLDR"; 2796 } 2797} 2798 2799defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">; 2800defm LDRHT : AI3ldrT<0b1011, "ldrht">; 2801defm LDRSHT : AI3ldrT<0b1111, "ldrsht">; 2802} 2803 2804def LDRT_POST 2805 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2806 (outs GPR:$Rt)>; 2807 2808def LDRBT_POST 2809 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2810 (outs GPR:$Rt)>; 2811 2812// Pseudo instruction ldr Rt, =immediate 2813def LDRConstPool 2814 : ARMAsmPseudo<"ldr${q} $Rt, $immediate", 2815 (ins const_pool_asm_imm:$immediate, pred:$q), 2816 (outs GPR:$Rt)>; 2817 2818// Store 2819 2820// Stores with truncate 2821def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, 2822 IIC_iStore_bh_r, "strh", "\t$Rt, $addr", 2823 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>; 2824 2825// Store doubleword 2826let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 2827 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr), 2828 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>, 2829 Requires<[IsARM, HasV5TE]> { 2830 let Inst{21} = 0; 2831 } 2832} 2833 2834// Indexed stores 2835multiclass AI2_stridx<bit isByte, string opc, 2836 InstrItinClass iii, InstrItinClass iir> { 2837 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2838 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre, 2839 StFrm, iii, 2840 opc, "\t$Rt, $addr!", 2841 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2842 bits<17> addr; 2843 let Inst{25} = 0; 2844 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2845 let Inst{19-16} = addr{16-13}; // Rn 2846 let Inst{11-0} = addr{11-0}; // imm12 2847 let DecoderMethod = "DecodeSTRPreImm"; 2848 } 2849 2850 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2851 (ins GPR:$Rt, ldst_so_reg:$addr), 2852 IndexModePre, StFrm, iir, 2853 opc, "\t$Rt, $addr!", 2854 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2855 bits<17> addr; 2856 let Inst{25} = 1; 2857 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2858 let Inst{19-16} = addr{16-13}; // Rn 2859 let Inst{11-0} = addr{11-0}; 2860 let Inst{4} = 0; // Inst{4} = 0 2861 let DecoderMethod = "DecodeSTRPreReg"; 2862 } 2863 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2864 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2865 IndexModePost, StFrm, iir, 2866 opc, "\t$Rt, $addr, $offset", 2867 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2868 // {12} isAdd 2869 // {11-0} imm12/Rm 2870 bits<14> offset; 2871 bits<4> addr; 2872 let Inst{25} = 1; 2873 let Inst{23} = offset{12}; 2874 let Inst{19-16} = addr; 2875 let Inst{11-0} = offset{11-0}; 2876 let Inst{4} = 0; 2877 2878 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2879 } 2880 2881 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2882 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2883 IndexModePost, StFrm, iii, 2884 opc, "\t$Rt, $addr, $offset", 2885 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2886 // {12} isAdd 2887 // {11-0} imm12/Rm 2888 bits<14> offset; 2889 bits<4> addr; 2890 let Inst{25} = 0; 2891 let Inst{23} = offset{12}; 2892 let Inst{19-16} = addr; 2893 let Inst{11-0} = offset{11-0}; 2894 2895 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2896 } 2897} 2898 2899let mayStore = 1, hasSideEffects = 0 in { 2900// FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or 2901// IIC_iStore_siu depending on whether it the offset register is shifted. 2902defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>; 2903defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>; 2904} 2905 2906def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 2907 am2offset_reg:$offset), 2908 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr, 2909 am2offset_reg:$offset)>; 2910def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 2911 am2offset_imm:$offset), 2912 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr, 2913 am2offset_imm:$offset)>; 2914def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 2915 am2offset_reg:$offset), 2916 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr, 2917 am2offset_reg:$offset)>; 2918def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 2919 am2offset_imm:$offset), 2920 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr, 2921 am2offset_imm:$offset)>; 2922 2923// Pseudo-instructions for pattern matching the pre-indexed stores. We can't 2924// put the patterns on the instruction definitions directly as ISel wants 2925// the address base and offset to be separate operands, not a single 2926// complex operand like we represent the instructions themselves. The 2927// pseudos map between the two. 2928let usesCustomInserter = 1, 2929 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 2930def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2931 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 2932 4, IIC_iStore_ru, 2933 [(set GPR:$Rn_wb, 2934 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 2935def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2936 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 2937 4, IIC_iStore_ru, 2938 [(set GPR:$Rn_wb, 2939 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 2940def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2941 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 2942 4, IIC_iStore_ru, 2943 [(set GPR:$Rn_wb, 2944 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 2945def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2946 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 2947 4, IIC_iStore_ru, 2948 [(set GPR:$Rn_wb, 2949 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 2950def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2951 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p), 2952 4, IIC_iStore_ru, 2953 [(set GPR:$Rn_wb, 2954 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>; 2955} 2956 2957 2958 2959def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb), 2960 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre, 2961 StMiscFrm, IIC_iStore_bh_ru, 2962 "strh", "\t$Rt, $addr!", 2963 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2964 bits<14> addr; 2965 let Inst{23} = addr{8}; // U bit 2966 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2967 let Inst{19-16} = addr{12-9}; // Rn 2968 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2969 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2970 let DecoderMethod = "DecodeAddrMode3Instruction"; 2971} 2972 2973def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb), 2974 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset), 2975 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, 2976 "strh", "\t$Rt, $addr, $offset", 2977 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", 2978 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt, 2979 addr_offset_none:$addr, 2980 am3offset:$offset))]> { 2981 bits<10> offset; 2982 bits<4> addr; 2983 let Inst{23} = offset{8}; // U bit 2984 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2985 let Inst{19-16} = addr; 2986 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2987 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2988 let DecoderMethod = "DecodeAddrMode3Instruction"; 2989} 2990 2991let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 2992def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb), 2993 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr), 2994 IndexModePre, StMiscFrm, IIC_iStore_d_ru, 2995 "strd", "\t$Rt, $Rt2, $addr!", 2996 "$addr.base = $Rn_wb", []> { 2997 bits<14> addr; 2998 let Inst{23} = addr{8}; // U bit 2999 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 3000 let Inst{19-16} = addr{12-9}; // Rn 3001 let Inst{11-8} = addr{7-4}; // imm7_4/zero 3002 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 3003 let DecoderMethod = "DecodeAddrMode3Instruction"; 3004} 3005 3006def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb), 3007 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr, 3008 am3offset:$offset), 3009 IndexModePost, StMiscFrm, IIC_iStore_d_ru, 3010 "strd", "\t$Rt, $Rt2, $addr, $offset", 3011 "$addr.base = $Rn_wb", []> { 3012 bits<10> offset; 3013 bits<4> addr; 3014 let Inst{23} = offset{8}; // U bit 3015 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 3016 let Inst{19-16} = addr; 3017 let Inst{11-8} = offset{7-4}; // imm7_4/zero 3018 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 3019 let DecoderMethod = "DecodeAddrMode3Instruction"; 3020} 3021} // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 3022 3023// STRT, STRBT, and STRHT 3024 3025def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3026 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3027 IndexModePost, StFrm, IIC_iStore_bh_ru, 3028 "strbt", "\t$Rt, $addr, $offset", 3029 "$addr.base = $Rn_wb", []> { 3030 // {12} isAdd 3031 // {11-0} imm12/Rm 3032 bits<14> offset; 3033 bits<4> addr; 3034 let Inst{25} = 1; 3035 let Inst{23} = offset{12}; 3036 let Inst{21} = 1; // overwrite 3037 let Inst{19-16} = addr; 3038 let Inst{11-5} = offset{11-5}; 3039 let Inst{4} = 0; 3040 let Inst{3-0} = offset{3-0}; 3041 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3042} 3043 3044def STRBT_POST_IMM 3045 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3046 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3047 IndexModePost, StFrm, IIC_iStore_bh_ru, 3048 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3049 // {12} isAdd 3050 // {11-0} imm12/Rm 3051 bits<14> offset; 3052 bits<4> addr; 3053 let Inst{25} = 0; 3054 let Inst{23} = offset{12}; 3055 let Inst{21} = 1; // overwrite 3056 let Inst{19-16} = addr; 3057 let Inst{11-0} = offset{11-0}; 3058 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3059} 3060 3061def STRBT_POST 3062 : ARMAsmPseudo<"strbt${q} $Rt, $addr", 3063 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3064 3065let mayStore = 1, hasSideEffects = 0 in { 3066def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3067 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3068 IndexModePost, StFrm, IIC_iStore_ru, 3069 "strt", "\t$Rt, $addr, $offset", 3070 "$addr.base = $Rn_wb", []> { 3071 // {12} isAdd 3072 // {11-0} imm12/Rm 3073 bits<14> offset; 3074 bits<4> addr; 3075 let Inst{25} = 1; 3076 let Inst{23} = offset{12}; 3077 let Inst{21} = 1; // overwrite 3078 let Inst{19-16} = addr; 3079 let Inst{11-5} = offset{11-5}; 3080 let Inst{4} = 0; 3081 let Inst{3-0} = offset{3-0}; 3082 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3083} 3084 3085def STRT_POST_IMM 3086 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3087 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3088 IndexModePost, StFrm, IIC_iStore_ru, 3089 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3090 // {12} isAdd 3091 // {11-0} imm12/Rm 3092 bits<14> offset; 3093 bits<4> addr; 3094 let Inst{25} = 0; 3095 let Inst{23} = offset{12}; 3096 let Inst{21} = 1; // overwrite 3097 let Inst{19-16} = addr; 3098 let Inst{11-0} = offset{11-0}; 3099 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3100} 3101} 3102 3103def STRT_POST 3104 : ARMAsmPseudo<"strt${q} $Rt, $addr", 3105 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3106 3107multiclass AI3strT<bits<4> op, string opc> { 3108 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3109 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset), 3110 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3111 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 3112 bits<9> offset; 3113 let Inst{23} = offset{8}; 3114 let Inst{22} = 1; 3115 let Inst{11-8} = offset{7-4}; 3116 let Inst{3-0} = offset{3-0}; 3117 } 3118 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3119 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm), 3120 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3121 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 3122 bits<5> Rm; 3123 let Inst{23} = Rm{4}; 3124 let Inst{22} = 0; 3125 let Inst{11-8} = 0; 3126 let Inst{3-0} = Rm{3-0}; 3127 } 3128} 3129 3130 3131defm STRHT : AI3strT<0b1011, "strht">; 3132 3133def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3134 NoItinerary, "stl", "\t$Rt, $addr", []>; 3135def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3136 NoItinerary, "stlb", "\t$Rt, $addr", []>; 3137def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3138 NoItinerary, "stlh", "\t$Rt, $addr", []>; 3139 3140//===----------------------------------------------------------------------===// 3141// Load / store multiple Instructions. 3142// 3143 3144multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f, 3145 InstrItinClass itin, InstrItinClass itin_upd> { 3146 // IA is the default, so no need for an explicit suffix on the 3147 // mnemonic here. Without it is the canonical spelling. 3148 def IA : 3149 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3150 IndexModeNone, f, itin, 3151 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> { 3152 let Inst{24-23} = 0b01; // Increment After 3153 let Inst{22} = P_bit; 3154 let Inst{21} = 0; // No writeback 3155 let Inst{20} = L_bit; 3156 } 3157 def IA_UPD : 3158 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3159 IndexModeUpd, f, itin_upd, 3160 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3161 let Inst{24-23} = 0b01; // Increment After 3162 let Inst{22} = P_bit; 3163 let Inst{21} = 1; // Writeback 3164 let Inst{20} = L_bit; 3165 3166 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3167 } 3168 def DA : 3169 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3170 IndexModeNone, f, itin, 3171 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> { 3172 let Inst{24-23} = 0b00; // Decrement After 3173 let Inst{22} = P_bit; 3174 let Inst{21} = 0; // No writeback 3175 let Inst{20} = L_bit; 3176 } 3177 def DA_UPD : 3178 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3179 IndexModeUpd, f, itin_upd, 3180 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3181 let Inst{24-23} = 0b00; // Decrement After 3182 let Inst{22} = P_bit; 3183 let Inst{21} = 1; // Writeback 3184 let Inst{20} = L_bit; 3185 3186 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3187 } 3188 def DB : 3189 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3190 IndexModeNone, f, itin, 3191 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> { 3192 let Inst{24-23} = 0b10; // Decrement Before 3193 let Inst{22} = P_bit; 3194 let Inst{21} = 0; // No writeback 3195 let Inst{20} = L_bit; 3196 } 3197 def DB_UPD : 3198 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3199 IndexModeUpd, f, itin_upd, 3200 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3201 let Inst{24-23} = 0b10; // Decrement Before 3202 let Inst{22} = P_bit; 3203 let Inst{21} = 1; // Writeback 3204 let Inst{20} = L_bit; 3205 3206 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3207 } 3208 def IB : 3209 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3210 IndexModeNone, f, itin, 3211 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> { 3212 let Inst{24-23} = 0b11; // Increment Before 3213 let Inst{22} = P_bit; 3214 let Inst{21} = 0; // No writeback 3215 let Inst{20} = L_bit; 3216 } 3217 def IB_UPD : 3218 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3219 IndexModeUpd, f, itin_upd, 3220 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3221 let Inst{24-23} = 0b11; // Increment Before 3222 let Inst{22} = P_bit; 3223 let Inst{21} = 1; // Writeback 3224 let Inst{20} = L_bit; 3225 3226 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3227 } 3228} 3229 3230let hasSideEffects = 0 in { 3231 3232let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 3233defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m, 3234 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">; 3235 3236let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3237defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m, 3238 IIC_iStore_mu>, 3239 ComplexDeprecationPredicate<"ARMStore">; 3240 3241} // hasSideEffects 3242 3243// FIXME: remove when we have a way to marking a MI with these properties. 3244// FIXME: Should pc be an implicit operand like PICADD, etc? 3245let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 3246 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 3247def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 3248 reglist:$regs, variable_ops), 3249 4, IIC_iLoad_mBr, [], 3250 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 3251 RegConstraint<"$Rn = $wb">; 3252 3253let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 3254defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m, 3255 IIC_iLoad_mu>; 3256 3257let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3258defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m, 3259 IIC_iStore_mu>; 3260 3261 3262 3263//===----------------------------------------------------------------------===// 3264// Move Instructions. 3265// 3266 3267let hasSideEffects = 0 in 3268def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr, 3269 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3270 bits<4> Rd; 3271 bits<4> Rm; 3272 3273 let Inst{19-16} = 0b0000; 3274 let Inst{11-4} = 0b00000000; 3275 let Inst{25} = 0; 3276 let Inst{3-0} = Rm; 3277 let Inst{15-12} = Rd; 3278} 3279 3280// A version for the smaller set of tail call registers. 3281let hasSideEffects = 0 in 3282def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, 3283 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3284 bits<4> Rd; 3285 bits<4> Rm; 3286 3287 let Inst{11-4} = 0b00000000; 3288 let Inst{25} = 0; 3289 let Inst{3-0} = Rm; 3290 let Inst{15-12} = Rd; 3291} 3292 3293def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src), 3294 DPSoRegRegFrm, IIC_iMOVsr, 3295 "mov", "\t$Rd, $src", 3296 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP, 3297 Sched<[WriteALU]> { 3298 bits<4> Rd; 3299 bits<12> src; 3300 let Inst{15-12} = Rd; 3301 let Inst{19-16} = 0b0000; 3302 let Inst{11-8} = src{11-8}; 3303 let Inst{7} = 0; 3304 let Inst{6-5} = src{6-5}; 3305 let Inst{4} = 1; 3306 let Inst{3-0} = src{3-0}; 3307 let Inst{25} = 0; 3308} 3309 3310def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src), 3311 DPSoRegImmFrm, IIC_iMOVsr, 3312 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>, 3313 UnaryDP, Sched<[WriteALU]> { 3314 bits<4> Rd; 3315 bits<12> src; 3316 let Inst{15-12} = Rd; 3317 let Inst{19-16} = 0b0000; 3318 let Inst{11-5} = src{11-5}; 3319 let Inst{4} = 0; 3320 let Inst{3-0} = src{3-0}; 3321 let Inst{25} = 0; 3322} 3323 3324let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3325def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi, 3326 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP, 3327 Sched<[WriteALU]> { 3328 bits<4> Rd; 3329 bits<12> imm; 3330 let Inst{25} = 1; 3331 let Inst{15-12} = Rd; 3332 let Inst{19-16} = 0b0000; 3333 let Inst{11-0} = imm; 3334} 3335 3336let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3337def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm), 3338 DPFrm, IIC_iMOVi, 3339 "movw", "\t$Rd, $imm", 3340 [(set GPR:$Rd, imm0_65535:$imm)]>, 3341 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> { 3342 bits<4> Rd; 3343 bits<16> imm; 3344 let Inst{15-12} = Rd; 3345 let Inst{11-0} = imm{11-0}; 3346 let Inst{19-16} = imm{15-12}; 3347 let Inst{20} = 0; 3348 let Inst{25} = 1; 3349 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3350} 3351 3352def : InstAlias<"mov${p} $Rd, $imm", 3353 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p), 0>, 3354 Requires<[IsARM, HasV6T2]>; 3355 3356def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3357 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3358 Sched<[WriteALU]>; 3359 3360let Constraints = "$src = $Rd" in { 3361def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd), 3362 (ins GPR:$src, imm0_65535_expr:$imm), 3363 DPFrm, IIC_iMOVi, 3364 "movt", "\t$Rd, $imm", 3365 [(set GPRnopc:$Rd, 3366 (or (and GPR:$src, 0xffff), 3367 lo16AllZero:$imm))]>, UnaryDP, 3368 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> { 3369 bits<4> Rd; 3370 bits<16> imm; 3371 let Inst{15-12} = Rd; 3372 let Inst{11-0} = imm{11-0}; 3373 let Inst{19-16} = imm{15-12}; 3374 let Inst{20} = 0; 3375 let Inst{25} = 1; 3376 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3377} 3378 3379def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3380 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3381 Sched<[WriteALU]>; 3382 3383} // Constraints 3384 3385def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>, 3386 Requires<[IsARM, HasV6T2]>; 3387 3388let Uses = [CPSR] in 3389def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, 3390 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP, 3391 Requires<[IsARM]>, Sched<[WriteALU]>; 3392 3393// These aren't really mov instructions, but we have to define them this way 3394// due to flag operands. 3395 3396let Defs = [CPSR] in { 3397def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3398 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP, 3399 Sched<[WriteALU]>, Requires<[IsARM]>; 3400def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3401 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP, 3402 Sched<[WriteALU]>, Requires<[IsARM]>; 3403} 3404 3405//===----------------------------------------------------------------------===// 3406// Extend Instructions. 3407// 3408 3409// Sign extenders 3410 3411def SXTB : AI_ext_rrot<0b01101010, 3412 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 3413def SXTH : AI_ext_rrot<0b01101011, 3414 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 3415 3416def SXTAB : AI_exta_rrot<0b01101010, 3417 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 3418def SXTAH : AI_exta_rrot<0b01101011, 3419 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 3420 3421def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8)), 3422 (SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3423def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot), 3424 i16)), 3425 (SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3426 3427def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; 3428 3429def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; 3430 3431// Zero extenders 3432 3433let AddedComplexity = 16 in { 3434def UXTB : AI_ext_rrot<0b01101110, 3435 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 3436def UXTH : AI_ext_rrot<0b01101111, 3437 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 3438def UXTB16 : AI_ext_rrot<0b01101100, 3439 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 3440 3441// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 3442// The transformation should probably be done as a combiner action 3443// instead so we can include a check for masking back in the upper 3444// eight bits of the source into the lower eight bits of the result. 3445//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 3446// (UXTB16r_rot GPR:$Src, 3)>; 3447def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 3448 (UXTB16 GPR:$Src, 1)>; 3449 3450def UXTAB : AI_exta_rrot<0b01101110, "uxtab", 3451 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 3452def UXTAH : AI_exta_rrot<0b01101111, "uxtah", 3453 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 3454 3455def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 0xFF)), 3456 (UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3457def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 0xFFFF)), 3458 (UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3459} 3460 3461// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 3462def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; 3463 3464 3465def SBFX : I<(outs GPRnopc:$Rd), 3466 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3467 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3468 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3469 Requires<[IsARM, HasV6T2]> { 3470 bits<4> Rd; 3471 bits<4> Rn; 3472 bits<5> lsb; 3473 bits<5> width; 3474 let Inst{27-21} = 0b0111101; 3475 let Inst{6-4} = 0b101; 3476 let Inst{20-16} = width; 3477 let Inst{15-12} = Rd; 3478 let Inst{11-7} = lsb; 3479 let Inst{3-0} = Rn; 3480} 3481 3482def UBFX : I<(outs GPRnopc:$Rd), 3483 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3484 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3485 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3486 Requires<[IsARM, HasV6T2]> { 3487 bits<4> Rd; 3488 bits<4> Rn; 3489 bits<5> lsb; 3490 bits<5> width; 3491 let Inst{27-21} = 0b0111111; 3492 let Inst{6-4} = 0b101; 3493 let Inst{20-16} = width; 3494 let Inst{15-12} = Rd; 3495 let Inst{11-7} = lsb; 3496 let Inst{3-0} = Rn; 3497} 3498 3499//===----------------------------------------------------------------------===// 3500// Arithmetic Instructions. 3501// 3502 3503let isAdd = 1 in 3504defm ADD : AsI1_bin_irs<0b0100, "add", 3505 IIC_iALUi, IIC_iALUr, IIC_iALUsr, add, 1>; 3506defm SUB : AsI1_bin_irs<0b0010, "sub", 3507 IIC_iALUi, IIC_iALUr, IIC_iALUsr, sub>; 3508 3509// ADD and SUB with 's' bit set. 3510// 3511// Currently, ADDS/SUBS are pseudo opcodes that exist only in the 3512// selection DAG. They are "lowered" to real ADD/SUB opcodes by 3513// AdjustInstrPostInstrSelection where we determine whether or not to 3514// set the "s" bit based on CPSR liveness. 3515// 3516// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen 3517// support for an optional CPSR definition that corresponds to the DAG 3518// node's second value. We can then eliminate the implicit def of CPSR. 3519let isAdd = 1 in 3520defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMaddc, 1>; 3521defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>; 3522 3523let isAdd = 1 in 3524defm ADC : AI1_adde_sube_irs<0b0101, "adc", ARMadde, 1>; 3525defm SBC : AI1_adde_sube_irs<0b0110, "sbc", ARMsube>; 3526 3527defm RSB : AsI1_rbin_irs<0b0011, "rsb", 3528 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3529 sub>; 3530 3531// FIXME: Eliminate them if we can write def : Pat patterns which defines 3532// CPSR and the implicit def of CPSR is not needed. 3533defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>; 3534 3535defm RSC : AI1_rsc_irs<0b0111, "rsc", ARMsube>; 3536 3537// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 3538// The assume-no-carry-in form uses the negation of the input since add/sub 3539// assume opposite meanings of the carry flag (i.e., carry == !borrow). 3540// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 3541// details. 3542def : ARMPat<(add GPR:$src, mod_imm_neg:$imm), 3543 (SUBri GPR:$src, mod_imm_neg:$imm)>; 3544def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm), 3545 (SUBSri GPR:$src, mod_imm_neg:$imm)>; 3546 3547def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm), 3548 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3549 Requires<[IsARM, HasV6T2]>; 3550def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm), 3551 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3552 Requires<[IsARM, HasV6T2]>; 3553 3554// The with-carry-in form matches bitwise not instead of the negation. 3555// Effectively, the inverse interpretation of the carry flag already accounts 3556// for part of the negation. 3557def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR), 3558 (SBCri GPR:$src, mod_imm_not:$imm)>; 3559def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR), 3560 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>, 3561 Requires<[IsARM, HasV6T2]>; 3562 3563// Note: These are implemented in C++ code, because they have to generate 3564// ADD/SUBrs instructions, which use a complex pattern that a xform function 3565// cannot produce. 3566// (mul X, 2^n+1) -> (add (X << n), X) 3567// (mul X, 2^n-1) -> (rsb X, (X << n)) 3568 3569// ARM Arithmetic Instruction 3570// GPR:$dst = GPR:$a op GPR:$b 3571class AAI<bits<8> op27_20, bits<8> op11_4, string opc, 3572 list<dag> pattern = [], 3573 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm), 3574 string asm = "\t$Rd, $Rn, $Rm"> 3575 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>, 3576 Sched<[WriteALU, ReadALU, ReadALU]> { 3577 bits<4> Rn; 3578 bits<4> Rd; 3579 bits<4> Rm; 3580 let Inst{27-20} = op27_20; 3581 let Inst{11-4} = op11_4; 3582 let Inst{19-16} = Rn; 3583 let Inst{15-12} = Rd; 3584 let Inst{3-0} = Rm; 3585 3586 let Unpredictable{11-8} = 0b1111; 3587} 3588 3589// Saturating add/subtract 3590 3591let DecoderMethod = "DecodeQADDInstruction" in 3592def QADD : AAI<0b00010000, 0b00000101, "qadd", 3593 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))], 3594 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">; 3595 3596def QSUB : AAI<0b00010010, 0b00000101, "qsub", 3597 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))], 3598 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">; 3599def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], 3600 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3601 "\t$Rd, $Rm, $Rn">; 3602def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], 3603 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3604 "\t$Rd, $Rm, $Rn">; 3605 3606def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">; 3607def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">; 3608def QASX : AAI<0b01100010, 0b11110011, "qasx">; 3609def QSAX : AAI<0b01100010, 0b11110101, "qsax">; 3610def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">; 3611def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">; 3612def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">; 3613def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">; 3614def UQASX : AAI<0b01100110, 0b11110011, "uqasx">; 3615def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">; 3616def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">; 3617def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">; 3618 3619// Signed/Unsigned add/subtract 3620 3621def SASX : AAI<0b01100001, 0b11110011, "sasx">; 3622def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">; 3623def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">; 3624def SSAX : AAI<0b01100001, 0b11110101, "ssax">; 3625def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">; 3626def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">; 3627def UASX : AAI<0b01100101, 0b11110011, "uasx">; 3628def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">; 3629def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">; 3630def USAX : AAI<0b01100101, 0b11110101, "usax">; 3631def USUB16 : AAI<0b01100101, 0b11110111, "usub16">; 3632def USUB8 : AAI<0b01100101, 0b11111111, "usub8">; 3633 3634// Signed/Unsigned halving add/subtract 3635 3636def SHASX : AAI<0b01100011, 0b11110011, "shasx">; 3637def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">; 3638def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">; 3639def SHSAX : AAI<0b01100011, 0b11110101, "shsax">; 3640def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">; 3641def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">; 3642def UHASX : AAI<0b01100111, 0b11110011, "uhasx">; 3643def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">; 3644def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">; 3645def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">; 3646def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">; 3647def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">; 3648 3649// Unsigned Sum of Absolute Differences [and Accumulate]. 3650 3651def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3652 MulFrm /* for convenience */, NoItinerary, "usad8", 3653 "\t$Rd, $Rn, $Rm", []>, 3654 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> { 3655 bits<4> Rd; 3656 bits<4> Rn; 3657 bits<4> Rm; 3658 let Inst{27-20} = 0b01111000; 3659 let Inst{15-12} = 0b1111; 3660 let Inst{7-4} = 0b0001; 3661 let Inst{19-16} = Rd; 3662 let Inst{11-8} = Rm; 3663 let Inst{3-0} = Rn; 3664} 3665def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3666 MulFrm /* for convenience */, NoItinerary, "usada8", 3667 "\t$Rd, $Rn, $Rm, $Ra", []>, 3668 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{ 3669 bits<4> Rd; 3670 bits<4> Rn; 3671 bits<4> Rm; 3672 bits<4> Ra; 3673 let Inst{27-20} = 0b01111000; 3674 let Inst{7-4} = 0b0001; 3675 let Inst{19-16} = Rd; 3676 let Inst{15-12} = Ra; 3677 let Inst{11-8} = Rm; 3678 let Inst{3-0} = Rn; 3679} 3680 3681// Signed/Unsigned saturate 3682 3683def SSAT : AI<(outs GPRnopc:$Rd), 3684 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3685 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>, 3686 Requires<[IsARM,HasV6]>{ 3687 bits<4> Rd; 3688 bits<5> sat_imm; 3689 bits<4> Rn; 3690 bits<8> sh; 3691 let Inst{27-21} = 0b0110101; 3692 let Inst{5-4} = 0b01; 3693 let Inst{20-16} = sat_imm; 3694 let Inst{15-12} = Rd; 3695 let Inst{11-7} = sh{4-0}; 3696 let Inst{6} = sh{5}; 3697 let Inst{3-0} = Rn; 3698} 3699 3700def SSAT16 : AI<(outs GPRnopc:$Rd), 3701 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm, 3702 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []>, 3703 Requires<[IsARM,HasV6]>{ 3704 bits<4> Rd; 3705 bits<4> sat_imm; 3706 bits<4> Rn; 3707 let Inst{27-20} = 0b01101010; 3708 let Inst{11-4} = 0b11110011; 3709 let Inst{15-12} = Rd; 3710 let Inst{19-16} = sat_imm; 3711 let Inst{3-0} = Rn; 3712} 3713 3714def USAT : AI<(outs GPRnopc:$Rd), 3715 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3716 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>, 3717 Requires<[IsARM,HasV6]> { 3718 bits<4> Rd; 3719 bits<5> sat_imm; 3720 bits<4> Rn; 3721 bits<8> sh; 3722 let Inst{27-21} = 0b0110111; 3723 let Inst{5-4} = 0b01; 3724 let Inst{15-12} = Rd; 3725 let Inst{11-7} = sh{4-0}; 3726 let Inst{6} = sh{5}; 3727 let Inst{20-16} = sat_imm; 3728 let Inst{3-0} = Rn; 3729} 3730 3731def USAT16 : AI<(outs GPRnopc:$Rd), 3732 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm, 3733 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []>, 3734 Requires<[IsARM,HasV6]>{ 3735 bits<4> Rd; 3736 bits<4> sat_imm; 3737 bits<4> Rn; 3738 let Inst{27-20} = 0b01101110; 3739 let Inst{11-4} = 0b11110011; 3740 let Inst{15-12} = Rd; 3741 let Inst{19-16} = sat_imm; 3742 let Inst{3-0} = Rn; 3743} 3744 3745def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos), 3746 (SSAT imm1_32:$pos, GPRnopc:$a, 0)>; 3747def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos), 3748 (USAT imm0_31:$pos, GPRnopc:$a, 0)>; 3749def : ARMPat<(ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm), 3750 (SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 3751 3752//===----------------------------------------------------------------------===// 3753// Bitwise Instructions. 3754// 3755 3756defm AND : AsI1_bin_irs<0b0000, "and", 3757 IIC_iBITi, IIC_iBITr, IIC_iBITsr, and, 1>; 3758defm ORR : AsI1_bin_irs<0b1100, "orr", 3759 IIC_iBITi, IIC_iBITr, IIC_iBITsr, or, 1>; 3760defm EOR : AsI1_bin_irs<0b0001, "eor", 3761 IIC_iBITi, IIC_iBITr, IIC_iBITsr, xor, 1>; 3762defm BIC : AsI1_bin_irs<0b1110, "bic", 3763 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3764 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 3765 3766// FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just 3767// like in the actual instruction encoding. The complexity of mapping the mask 3768// to the lsb/msb pair should be handled by ISel, not encapsulated in the 3769// instruction description. 3770def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), 3771 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3772 "bfc", "\t$Rd, $imm", "$src = $Rd", 3773 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>, 3774 Requires<[IsARM, HasV6T2]> { 3775 bits<4> Rd; 3776 bits<10> imm; 3777 let Inst{27-21} = 0b0111110; 3778 let Inst{6-0} = 0b0011111; 3779 let Inst{15-12} = Rd; 3780 let Inst{11-7} = imm{4-0}; // lsb 3781 let Inst{20-16} = imm{9-5}; // msb 3782} 3783 3784// A8.6.18 BFI - Bitfield insert (Encoding A1) 3785def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm), 3786 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3787 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd", 3788 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn, 3789 bf_inv_mask_imm:$imm))]>, 3790 Requires<[IsARM, HasV6T2]> { 3791 bits<4> Rd; 3792 bits<4> Rn; 3793 bits<10> imm; 3794 let Inst{27-21} = 0b0111110; 3795 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 3796 let Inst{15-12} = Rd; 3797 let Inst{11-7} = imm{4-0}; // lsb 3798 let Inst{20-16} = imm{9-5}; // width 3799 let Inst{3-0} = Rn; 3800} 3801 3802def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr, 3803 "mvn", "\t$Rd, $Rm", 3804 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> { 3805 bits<4> Rd; 3806 bits<4> Rm; 3807 let Inst{25} = 0; 3808 let Inst{19-16} = 0b0000; 3809 let Inst{11-4} = 0b00000000; 3810 let Inst{15-12} = Rd; 3811 let Inst{3-0} = Rm; 3812} 3813def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift), 3814 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3815 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP, 3816 Sched<[WriteALU]> { 3817 bits<4> Rd; 3818 bits<12> shift; 3819 let Inst{25} = 0; 3820 let Inst{19-16} = 0b0000; 3821 let Inst{15-12} = Rd; 3822 let Inst{11-5} = shift{11-5}; 3823 let Inst{4} = 0; 3824 let Inst{3-0} = shift{3-0}; 3825} 3826def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift), 3827 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3828 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP, 3829 Sched<[WriteALU]> { 3830 bits<4> Rd; 3831 bits<12> shift; 3832 let Inst{25} = 0; 3833 let Inst{19-16} = 0b0000; 3834 let Inst{15-12} = Rd; 3835 let Inst{11-8} = shift{11-8}; 3836 let Inst{7} = 0; 3837 let Inst{6-5} = shift{6-5}; 3838 let Inst{4} = 1; 3839 let Inst{3-0} = shift{3-0}; 3840} 3841let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3842def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, 3843 IIC_iMVNi, "mvn", "\t$Rd, $imm", 3844 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> { 3845 bits<4> Rd; 3846 bits<12> imm; 3847 let Inst{25} = 1; 3848 let Inst{19-16} = 0b0000; 3849 let Inst{15-12} = Rd; 3850 let Inst{11-0} = imm; 3851} 3852 3853def : ARMPat<(and GPR:$src, mod_imm_not:$imm), 3854 (BICri GPR:$src, mod_imm_not:$imm)>; 3855 3856//===----------------------------------------------------------------------===// 3857// Multiply Instructions. 3858// 3859class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3860 string opc, string asm, list<dag> pattern> 3861 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3862 bits<4> Rd; 3863 bits<4> Rm; 3864 bits<4> Rn; 3865 let Inst{19-16} = Rd; 3866 let Inst{11-8} = Rm; 3867 let Inst{3-0} = Rn; 3868} 3869class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3870 string opc, string asm, list<dag> pattern> 3871 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3872 bits<4> RdLo; 3873 bits<4> RdHi; 3874 bits<4> Rm; 3875 bits<4> Rn; 3876 let Inst{19-16} = RdHi; 3877 let Inst{15-12} = RdLo; 3878 let Inst{11-8} = Rm; 3879 let Inst{3-0} = Rn; 3880} 3881class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3882 string opc, string asm, list<dag> pattern> 3883 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3884 bits<4> RdLo; 3885 bits<4> RdHi; 3886 bits<4> Rm; 3887 bits<4> Rn; 3888 let Inst{19-16} = RdHi; 3889 let Inst{15-12} = RdLo; 3890 let Inst{11-8} = Rm; 3891 let Inst{3-0} = Rn; 3892} 3893 3894// FIXME: The v5 pseudos are only necessary for the additional Constraint 3895// property. Remove them when it's possible to add those properties 3896// on an individual MachineInstr, not just an instruction description. 3897let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in { 3898def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), 3899 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3900 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", 3901 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>, 3902 Requires<[IsARM, HasV6]> { 3903 let Inst{15-12} = 0b0000; 3904 let Unpredictable{15-12} = 0b1111; 3905} 3906 3907let Constraints = "@earlyclobber $Rd" in 3908def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, 3909 pred:$p, cc_out:$s), 3910 4, IIC_iMUL32, 3911 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))], 3912 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 3913 Requires<[IsARM, NoV6, UseMulOps]>; 3914} 3915 3916def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd), 3917 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra), 3918 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra", 3919 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>, 3920 Requires<[IsARM, HasV6, UseMulOps]> { 3921 bits<4> Ra; 3922 let Inst{15-12} = Ra; 3923} 3924 3925let Constraints = "@earlyclobber $Rd" in 3926def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd), 3927 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 3928 pred:$p, cc_out:$s), 4, IIC_iMAC32, 3929 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))], 3930 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>, 3931 Requires<[IsARM, NoV6]>; 3932 3933def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3934 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra", 3935 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>, 3936 Requires<[IsARM, HasV6T2, UseMulOps]> { 3937 bits<4> Rd; 3938 bits<4> Rm; 3939 bits<4> Rn; 3940 bits<4> Ra; 3941 let Inst{19-16} = Rd; 3942 let Inst{15-12} = Ra; 3943 let Inst{11-8} = Rm; 3944 let Inst{3-0} = Rn; 3945} 3946 3947// Extra precision multiplies with low / high results 3948let hasSideEffects = 0 in { 3949let isCommutable = 1 in { 3950def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi), 3951 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 3952 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3953 Requires<[IsARM, HasV6]>; 3954 3955def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), 3956 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 3957 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3958 Requires<[IsARM, HasV6]>; 3959 3960let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { 3961def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3962 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 3963 4, IIC_iMUL64, [], 3964 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 3965 Requires<[IsARM, NoV6]>; 3966 3967def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3968 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 3969 4, IIC_iMUL64, [], 3970 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 3971 Requires<[IsARM, NoV6]>; 3972} 3973} 3974 3975// Multiply + accumulate 3976def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi), 3977 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 3978 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3979 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>; 3980def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi), 3981 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 3982 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3983 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>; 3984 3985def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi), 3986 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 3987 IIC_iMAC64, 3988 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3989 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]> { 3990 bits<4> RdLo; 3991 bits<4> RdHi; 3992 bits<4> Rm; 3993 bits<4> Rn; 3994 let Inst{19-16} = RdHi; 3995 let Inst{15-12} = RdLo; 3996 let Inst{11-8} = Rm; 3997 let Inst{3-0} = Rn; 3998} 3999 4000let Constraints = 4001 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in { 4002def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4003 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4004 4, IIC_iMAC64, [], 4005 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4006 pred:$p, cc_out:$s)>, 4007 Requires<[IsARM, NoV6]>; 4008def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4009 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4010 4, IIC_iMAC64, [], 4011 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4012 pred:$p, cc_out:$s)>, 4013 Requires<[IsARM, NoV6]>; 4014} 4015 4016} // hasSideEffects 4017 4018// Most significant word multiply 4019def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4020 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm", 4021 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>, 4022 Requires<[IsARM, HasV6]> { 4023 let Inst{15-12} = 0b1111; 4024} 4025 4026def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4027 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>, 4028 Requires<[IsARM, HasV6]> { 4029 let Inst{15-12} = 0b1111; 4030} 4031 4032def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd), 4033 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4034 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra", 4035 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, 4036 Requires<[IsARM, HasV6, UseMulOps]>; 4037 4038def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd), 4039 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4040 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>, 4041 Requires<[IsARM, HasV6]>; 4042 4043def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd), 4044 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4045 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>, 4046 Requires<[IsARM, HasV6, UseMulOps]>; 4047 4048def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd), 4049 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4050 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>, 4051 Requires<[IsARM, HasV6]>; 4052 4053multiclass AI_smul<string opc> { 4054 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4055 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 4056 [(set GPR:$Rd, (mul (sext_inreg GPR:$Rn, i16), 4057 (sext_inreg GPR:$Rm, i16)))]>, 4058 Requires<[IsARM, HasV5TE]>; 4059 4060 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4061 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 4062 [(set GPR:$Rd, (mul (sext_inreg GPR:$Rn, i16), 4063 (sra GPR:$Rm, (i32 16))))]>, 4064 Requires<[IsARM, HasV5TE]>; 4065 4066 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4067 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 4068 [(set GPR:$Rd, (mul (sra GPR:$Rn, (i32 16)), 4069 (sext_inreg GPR:$Rm, i16)))]>, 4070 Requires<[IsARM, HasV5TE]>; 4071 4072 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4073 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 4074 [(set GPR:$Rd, (mul (sra GPR:$Rn, (i32 16)), 4075 (sra GPR:$Rm, (i32 16))))]>, 4076 Requires<[IsARM, HasV5TE]>; 4077 4078 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4079 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 4080 []>, 4081 Requires<[IsARM, HasV5TE]>; 4082 4083 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4084 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 4085 []>, 4086 Requires<[IsARM, HasV5TE]>; 4087} 4088 4089 4090multiclass AI_smla<string opc> { 4091 let DecoderMethod = "DecodeSMLAInstruction" in { 4092 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd), 4093 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4094 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 4095 [(set GPRnopc:$Rd, (add GPR:$Ra, 4096 (mul (sext_inreg GPRnopc:$Rn, i16), 4097 (sext_inreg GPRnopc:$Rm, i16))))]>, 4098 Requires<[IsARM, HasV5TE, UseMulOps]>; 4099 4100 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd), 4101 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4102 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 4103 [(set GPRnopc:$Rd, 4104 (add GPR:$Ra, (mul (sext_inreg GPRnopc:$Rn, i16), 4105 (sra GPRnopc:$Rm, (i32 16)))))]>, 4106 Requires<[IsARM, HasV5TE, UseMulOps]>; 4107 4108 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd), 4109 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4110 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 4111 [(set GPRnopc:$Rd, 4112 (add GPR:$Ra, (mul (sra GPRnopc:$Rn, (i32 16)), 4113 (sext_inreg GPRnopc:$Rm, i16))))]>, 4114 Requires<[IsARM, HasV5TE, UseMulOps]>; 4115 4116 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd), 4117 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4118 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 4119 [(set GPRnopc:$Rd, 4120 (add GPR:$Ra, (mul (sra GPRnopc:$Rn, (i32 16)), 4121 (sra GPRnopc:$Rm, (i32 16)))))]>, 4122 Requires<[IsARM, HasV5TE, UseMulOps]>; 4123 4124 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd), 4125 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4126 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 4127 []>, 4128 Requires<[IsARM, HasV5TE, UseMulOps]>; 4129 4130 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd), 4131 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4132 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 4133 []>, 4134 Requires<[IsARM, HasV5TE, UseMulOps]>; 4135 } 4136} 4137 4138defm SMUL : AI_smul<"smul">; 4139defm SMLA : AI_smla<"smla">; 4140 4141// Halfword multiply accumulate long: SMLAL<x><y>. 4142def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4143 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4144 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4145 Requires<[IsARM, HasV5TE]>; 4146 4147def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4148 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4149 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4150 Requires<[IsARM, HasV5TE]>; 4151 4152def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4153 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4154 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4155 Requires<[IsARM, HasV5TE]>; 4156 4157def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4158 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4159 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4160 Requires<[IsARM, HasV5TE]>; 4161 4162// Helper class for AI_smld. 4163class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops, 4164 InstrItinClass itin, string opc, string asm> 4165 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> { 4166 bits<4> Rn; 4167 bits<4> Rm; 4168 let Inst{27-23} = 0b01110; 4169 let Inst{22} = long; 4170 let Inst{21-20} = 0b00; 4171 let Inst{11-8} = Rm; 4172 let Inst{7} = 0; 4173 let Inst{6} = sub; 4174 let Inst{5} = swap; 4175 let Inst{4} = 1; 4176 let Inst{3-0} = Rn; 4177} 4178class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops, 4179 InstrItinClass itin, string opc, string asm> 4180 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4181 bits<4> Rd; 4182 let Inst{15-12} = 0b1111; 4183 let Inst{19-16} = Rd; 4184} 4185class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops, 4186 InstrItinClass itin, string opc, string asm> 4187 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4188 bits<4> Ra; 4189 bits<4> Rd; 4190 let Inst{19-16} = Rd; 4191 let Inst{15-12} = Ra; 4192} 4193class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops, 4194 InstrItinClass itin, string opc, string asm> 4195 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4196 bits<4> RdLo; 4197 bits<4> RdHi; 4198 let Inst{19-16} = RdHi; 4199 let Inst{15-12} = RdLo; 4200} 4201 4202multiclass AI_smld<bit sub, string opc> { 4203 4204 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd), 4205 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4206 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">; 4207 4208 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd), 4209 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4210 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">; 4211 4212 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4213 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary, 4214 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">; 4215 4216 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4217 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary, 4218 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">; 4219 4220} 4221 4222defm SMLA : AI_smld<0, "smla">; 4223defm SMLS : AI_smld<1, "smls">; 4224 4225multiclass AI_sdml<bit sub, string opc> { 4226 4227 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), 4228 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">; 4229 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm), 4230 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">; 4231} 4232 4233defm SMUA : AI_sdml<0, "smua">; 4234defm SMUS : AI_sdml<1, "smus">; 4235 4236//===----------------------------------------------------------------------===// 4237// Division Instructions (ARMv7-A with virtualization extension) 4238// 4239def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4240 "sdiv", "\t$Rd, $Rn, $Rm", 4241 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>, 4242 Requires<[IsARM, HasDivideInARM]>; 4243 4244def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4245 "udiv", "\t$Rd, $Rn, $Rm", 4246 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>, 4247 Requires<[IsARM, HasDivideInARM]>; 4248 4249//===----------------------------------------------------------------------===// 4250// Misc. Arithmetic Instructions. 4251// 4252 4253def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm), 4254 IIC_iUNAr, "clz", "\t$Rd, $Rm", 4255 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>, 4256 Sched<[WriteALU]>; 4257 4258def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4259 IIC_iUNAr, "rbit", "\t$Rd, $Rm", 4260 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>, 4261 Requires<[IsARM, HasV6T2]>, 4262 Sched<[WriteALU]>; 4263 4264def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4265 IIC_iUNAr, "rev", "\t$Rd, $Rm", 4266 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>, 4267 Sched<[WriteALU]>; 4268 4269let AddedComplexity = 5 in 4270def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4271 IIC_iUNAr, "rev16", "\t$Rd, $Rm", 4272 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>, 4273 Requires<[IsARM, HasV6]>, 4274 Sched<[WriteALU]>; 4275 4276def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)), 4277 (REV16 (LDRH addrmode3:$addr))>; 4278def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr), 4279 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>; 4280 4281let AddedComplexity = 5 in 4282def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4283 IIC_iUNAr, "revsh", "\t$Rd, $Rm", 4284 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>, 4285 Requires<[IsARM, HasV6]>, 4286 Sched<[WriteALU]>; 4287 4288def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)), 4289 (and (srl GPR:$Rm, (i32 8)), 0xFF)), 4290 (REVSH GPR:$Rm)>; 4291 4292def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd), 4293 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh), 4294 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 4295 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF), 4296 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh), 4297 0xFFFF0000)))]>, 4298 Requires<[IsARM, HasV6]>, 4299 Sched<[WriteALUsi, ReadALU]>; 4300 4301// Alternate cases for PKHBT where identities eliminate some nodes. 4302def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)), 4303 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>; 4304def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)), 4305 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>; 4306 4307// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 4308// will match the pattern below. 4309def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd), 4310 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh), 4311 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 4312 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000), 4313 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh), 4314 0xFFFF)))]>, 4315 Requires<[IsARM, HasV6]>, 4316 Sched<[WriteALUsi, ReadALU]>; 4317 4318// Alternate cases for PKHTB where identities eliminate some nodes. Note that 4319// a shift amount of 0 is *not legal* here, it is PKHBT instead. 4320// We also can not replace a srl (17..31) by an arithmetic shift we would use in 4321// pkhtb src1, src2, asr (17..31). 4322def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4323 (srl GPRnopc:$src2, imm16:$sh)), 4324 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>; 4325def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4326 (sra GPRnopc:$src2, imm16_31:$sh)), 4327 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>; 4328def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4329 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)), 4330 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>; 4331 4332//===----------------------------------------------------------------------===// 4333// CRC Instructions 4334// 4335// Polynomials: 4336// + CRC32{B,H,W} 0x04C11DB7 4337// + CRC32C{B,H,W} 0x1EDC6F41 4338// 4339 4340class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin> 4341 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary, 4342 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm", 4343 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>, 4344 Requires<[IsARM, HasV8, HasCRC]> { 4345 bits<4> Rd; 4346 bits<4> Rn; 4347 bits<4> Rm; 4348 4349 let Inst{31-28} = 0b1110; 4350 let Inst{27-23} = 0b00010; 4351 let Inst{22-21} = sz; 4352 let Inst{20} = 0; 4353 let Inst{19-16} = Rn; 4354 let Inst{15-12} = Rd; 4355 let Inst{11-10} = 0b00; 4356 let Inst{9} = C; 4357 let Inst{8} = 0; 4358 let Inst{7-4} = 0b0100; 4359 let Inst{3-0} = Rm; 4360 4361 let Unpredictable{11-8} = 0b1101; 4362} 4363 4364def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>; 4365def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>; 4366def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>; 4367def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>; 4368def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>; 4369def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>; 4370 4371//===----------------------------------------------------------------------===// 4372// ARMv8.1a Privilege Access Never extension 4373// 4374// SETPAN #imm1 4375 4376def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan", 4377 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> { 4378 bits<1> imm; 4379 4380 let Inst{31-28} = 0b1111; 4381 let Inst{27-20} = 0b00010001; 4382 let Inst{19-16} = 0b0000; 4383 let Inst{15-10} = 0b000000; 4384 let Inst{9} = imm; 4385 let Inst{8} = 0b0; 4386 let Inst{7-4} = 0b0000; 4387 let Inst{3-0} = 0b0000; 4388 4389 let Unpredictable{19-16} = 0b1111; 4390 let Unpredictable{15-10} = 0b111111; 4391 let Unpredictable{8} = 0b1; 4392 let Unpredictable{3-0} = 0b1111; 4393} 4394 4395//===----------------------------------------------------------------------===// 4396// Comparison Instructions... 4397// 4398 4399defm CMP : AI1_cmp_irs<0b1010, "cmp", 4400 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, ARMcmp>; 4401 4402// ARMcmpZ can re-use the above instruction definitions. 4403def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm), 4404 (CMPri GPR:$src, mod_imm:$imm)>; 4405def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs), 4406 (CMPrr GPR:$src, GPR:$rhs)>; 4407def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs), 4408 (CMPrsi GPR:$src, so_reg_imm:$rhs)>; 4409def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs), 4410 (CMPrsr GPR:$src, so_reg_reg:$rhs)>; 4411 4412// CMN register-integer 4413let isCompare = 1, Defs = [CPSR] in { 4414def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi, 4415 "cmn", "\t$Rn, $imm", 4416 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>, 4417 Sched<[WriteCMP, ReadALU]> { 4418 bits<4> Rn; 4419 bits<12> imm; 4420 let Inst{25} = 1; 4421 let Inst{20} = 1; 4422 let Inst{19-16} = Rn; 4423 let Inst{15-12} = 0b0000; 4424 let Inst{11-0} = imm; 4425 4426 let Unpredictable{15-12} = 0b1111; 4427} 4428 4429// CMN register-register/shift 4430def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr, 4431 "cmn", "\t$Rn, $Rm", 4432 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4433 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> { 4434 bits<4> Rn; 4435 bits<4> Rm; 4436 let isCommutable = 1; 4437 let Inst{25} = 0; 4438 let Inst{20} = 1; 4439 let Inst{19-16} = Rn; 4440 let Inst{15-12} = 0b0000; 4441 let Inst{11-4} = 0b00000000; 4442 let Inst{3-0} = Rm; 4443 4444 let Unpredictable{15-12} = 0b1111; 4445} 4446 4447def CMNzrsi : AI1<0b1011, (outs), 4448 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr, 4449 "cmn", "\t$Rn, $shift", 4450 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4451 GPR:$Rn, so_reg_imm:$shift)]>, 4452 Sched<[WriteCMPsi, ReadALU]> { 4453 bits<4> Rn; 4454 bits<12> shift; 4455 let Inst{25} = 0; 4456 let Inst{20} = 1; 4457 let Inst{19-16} = Rn; 4458 let Inst{15-12} = 0b0000; 4459 let Inst{11-5} = shift{11-5}; 4460 let Inst{4} = 0; 4461 let Inst{3-0} = shift{3-0}; 4462 4463 let Unpredictable{15-12} = 0b1111; 4464} 4465 4466def CMNzrsr : AI1<0b1011, (outs), 4467 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr, 4468 "cmn", "\t$Rn, $shift", 4469 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4470 GPRnopc:$Rn, so_reg_reg:$shift)]>, 4471 Sched<[WriteCMPsr, ReadALU]> { 4472 bits<4> Rn; 4473 bits<12> shift; 4474 let Inst{25} = 0; 4475 let Inst{20} = 1; 4476 let Inst{19-16} = Rn; 4477 let Inst{15-12} = 0b0000; 4478 let Inst{11-8} = shift{11-8}; 4479 let Inst{7} = 0; 4480 let Inst{6-5} = shift{6-5}; 4481 let Inst{4} = 1; 4482 let Inst{3-0} = shift{3-0}; 4483 4484 let Unpredictable{15-12} = 0b1111; 4485} 4486 4487} 4488 4489def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm), 4490 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4491 4492def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm), 4493 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4494 4495// Note that TST/TEQ don't set all the same flags that CMP does! 4496defm TST : AI1_cmp_irs<0b1000, "tst", 4497 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4498 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1, 4499 "DecodeTSTInstruction">; 4500defm TEQ : AI1_cmp_irs<0b1001, "teq", 4501 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4502 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>; 4503 4504// Pseudo i64 compares for some floating point compares. 4505let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, 4506 Defs = [CPSR] in { 4507def BCCi64 : PseudoInst<(outs), 4508 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst), 4509 IIC_Br, 4510 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>, 4511 Sched<[WriteBr]>; 4512 4513def BCCZi64 : PseudoInst<(outs), 4514 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, 4515 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>, 4516 Sched<[WriteBr]>; 4517} // usesCustomInserter 4518 4519 4520// Conditional moves 4521let hasSideEffects = 0 in { 4522 4523let isCommutable = 1, isSelect = 1 in 4524def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), 4525 (ins GPR:$false, GPR:$Rm, cmovpred:$p), 4526 4, IIC_iCMOVr, 4527 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, 4528 cmovpred:$p))]>, 4529 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4530 4531def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd), 4532 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p), 4533 4, IIC_iCMOVsr, 4534 [(set GPR:$Rd, 4535 (ARMcmov GPR:$false, so_reg_imm:$shift, 4536 cmovpred:$p))]>, 4537 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4538def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd), 4539 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p), 4540 4, IIC_iCMOVsr, 4541 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift, 4542 cmovpred:$p))]>, 4543 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4544 4545 4546let isMoveImm = 1 in 4547def MOVCCi16 4548 : ARMPseudoInst<(outs GPR:$Rd), 4549 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p), 4550 4, IIC_iMOVi, 4551 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm, 4552 cmovpred:$p))]>, 4553 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>, 4554 Sched<[WriteALU]>; 4555 4556let isMoveImm = 1 in 4557def MOVCCi : ARMPseudoInst<(outs GPR:$Rd), 4558 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 4559 4, IIC_iCMOVi, 4560 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm, 4561 cmovpred:$p))]>, 4562 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4563 4564// Two instruction predicate mov immediate. 4565let isMoveImm = 1 in 4566def MOVCCi32imm 4567 : ARMPseudoInst<(outs GPR:$Rd), 4568 (ins GPR:$false, i32imm:$src, cmovpred:$p), 4569 8, IIC_iCMOVix2, 4570 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src, 4571 cmovpred:$p))]>, 4572 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>; 4573 4574let isMoveImm = 1 in 4575def MVNCCi : ARMPseudoInst<(outs GPR:$Rd), 4576 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 4577 4, IIC_iCMOVi, 4578 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm, 4579 cmovpred:$p))]>, 4580 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4581 4582} // hasSideEffects 4583 4584 4585//===----------------------------------------------------------------------===// 4586// Atomic operations intrinsics 4587// 4588 4589def MemBarrierOptOperand : AsmOperandClass { 4590 let Name = "MemBarrierOpt"; 4591 let ParserMethod = "parseMemBarrierOptOperand"; 4592} 4593def memb_opt : Operand<i32> { 4594 let PrintMethod = "printMemBOption"; 4595 let ParserMatchClass = MemBarrierOptOperand; 4596 let DecoderMethod = "DecodeMemBarrierOption"; 4597} 4598 4599def InstSyncBarrierOptOperand : AsmOperandClass { 4600 let Name = "InstSyncBarrierOpt"; 4601 let ParserMethod = "parseInstSyncBarrierOptOperand"; 4602} 4603def instsyncb_opt : Operand<i32> { 4604 let PrintMethod = "printInstSyncBOption"; 4605 let ParserMatchClass = InstSyncBarrierOptOperand; 4606 let DecoderMethod = "DecodeInstSyncBarrierOption"; 4607} 4608 4609// Memory barriers protect the atomic sequences 4610let hasSideEffects = 1 in { 4611def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4612 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>, 4613 Requires<[IsARM, HasDB]> { 4614 bits<4> opt; 4615 let Inst{31-4} = 0xf57ff05; 4616 let Inst{3-0} = opt; 4617} 4618 4619def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4620 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>, 4621 Requires<[IsARM, HasDB]> { 4622 bits<4> opt; 4623 let Inst{31-4} = 0xf57ff04; 4624 let Inst{3-0} = opt; 4625} 4626 4627// ISB has only full system option 4628def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary, 4629 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>, 4630 Requires<[IsARM, HasDB]> { 4631 bits<4> opt; 4632 let Inst{31-4} = 0xf57ff06; 4633 let Inst{3-0} = opt; 4634} 4635} 4636 4637let usesCustomInserter = 1, Defs = [CPSR] in { 4638 4639// Pseudo instruction that combines movs + predicated rsbmi 4640// to implement integer ABS 4641 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>; 4642} 4643 4644let usesCustomInserter = 1 in { 4645 def COPY_STRUCT_BYVAL_I32 : PseudoInst< 4646 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment), 4647 NoItinerary, 4648 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>; 4649} 4650 4651let hasPostISelHook = 1, Constraints = "$newdst = $dst, $newsrc = $src" in { 4652 // %newsrc, %newdst = MEMCPY %dst, %src, N, ...N scratch regs... 4653 // Copies N registers worth of memory from address %src to address %dst 4654 // and returns the incremented addresses. N scratch register will 4655 // be attached for the copy to use. 4656 def MEMCPY : PseudoInst< 4657 (outs GPR:$newdst, GPR:$newsrc), 4658 (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops), 4659 NoItinerary, 4660 [(set GPR:$newdst, GPR:$newsrc, 4661 (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>; 4662} 4663 4664def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4665 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4666}]>; 4667 4668def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4669 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4670}]>; 4671 4672def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4673 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4674}]>; 4675 4676def strex_1 : PatFrag<(ops node:$val, node:$ptr), 4677 (int_arm_strex node:$val, node:$ptr), [{ 4678 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4679}]>; 4680 4681def strex_2 : PatFrag<(ops node:$val, node:$ptr), 4682 (int_arm_strex node:$val, node:$ptr), [{ 4683 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4684}]>; 4685 4686def strex_4 : PatFrag<(ops node:$val, node:$ptr), 4687 (int_arm_strex node:$val, node:$ptr), [{ 4688 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4689}]>; 4690 4691def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4692 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4693}]>; 4694 4695def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4696 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4697}]>; 4698 4699def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4700 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4701}]>; 4702 4703def stlex_1 : PatFrag<(ops node:$val, node:$ptr), 4704 (int_arm_stlex node:$val, node:$ptr), [{ 4705 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4706}]>; 4707 4708def stlex_2 : PatFrag<(ops node:$val, node:$ptr), 4709 (int_arm_stlex node:$val, node:$ptr), [{ 4710 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4711}]>; 4712 4713def stlex_4 : PatFrag<(ops node:$val, node:$ptr), 4714 (int_arm_stlex node:$val, node:$ptr), [{ 4715 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4716}]>; 4717 4718let mayLoad = 1 in { 4719def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4720 NoItinerary, "ldrexb", "\t$Rt, $addr", 4721 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>; 4722def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4723 NoItinerary, "ldrexh", "\t$Rt, $addr", 4724 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>; 4725def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4726 NoItinerary, "ldrex", "\t$Rt, $addr", 4727 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>; 4728let hasExtraDefRegAllocReq = 1 in 4729def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 4730 NoItinerary, "ldrexd", "\t$Rt, $addr", []> { 4731 let DecoderMethod = "DecodeDoubleRegLoad"; 4732} 4733 4734def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4735 NoItinerary, "ldaexb", "\t$Rt, $addr", 4736 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>; 4737def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4738 NoItinerary, "ldaexh", "\t$Rt, $addr", 4739 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>; 4740def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4741 NoItinerary, "ldaex", "\t$Rt, $addr", 4742 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>; 4743let hasExtraDefRegAllocReq = 1 in 4744def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 4745 NoItinerary, "ldaexd", "\t$Rt, $addr", []> { 4746 let DecoderMethod = "DecodeDoubleRegLoad"; 4747} 4748} 4749 4750let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 4751def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4752 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", 4753 [(set GPR:$Rd, (strex_1 GPR:$Rt, 4754 addr_offset_none:$addr))]>; 4755def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4756 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", 4757 [(set GPR:$Rd, (strex_2 GPR:$Rt, 4758 addr_offset_none:$addr))]>; 4759def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4760 NoItinerary, "strex", "\t$Rd, $Rt, $addr", 4761 [(set GPR:$Rd, (strex_4 GPR:$Rt, 4762 addr_offset_none:$addr))]>; 4763let hasExtraSrcRegAllocReq = 1 in 4764def STREXD : AIstrex<0b01, (outs GPR:$Rd), 4765 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 4766 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> { 4767 let DecoderMethod = "DecodeDoubleRegStore"; 4768} 4769def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4770 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr", 4771 [(set GPR:$Rd, 4772 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>; 4773def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4774 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr", 4775 [(set GPR:$Rd, 4776 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>; 4777def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4778 NoItinerary, "stlex", "\t$Rd, $Rt, $addr", 4779 [(set GPR:$Rd, 4780 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>; 4781let hasExtraSrcRegAllocReq = 1 in 4782def STLEXD : AIstlex<0b01, (outs GPR:$Rd), 4783 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 4784 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> { 4785 let DecoderMethod = "DecodeDoubleRegStore"; 4786} 4787} 4788 4789def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", 4790 [(int_arm_clrex)]>, 4791 Requires<[IsARM, HasV6K]> { 4792 let Inst{31-0} = 0b11110101011111111111000000011111; 4793} 4794 4795def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 4796 (STREXB GPR:$Rt, addr_offset_none:$addr)>; 4797def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 4798 (STREXH GPR:$Rt, addr_offset_none:$addr)>; 4799 4800def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 4801 (STLEXB GPR:$Rt, addr_offset_none:$addr)>; 4802def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 4803 (STLEXH GPR:$Rt, addr_offset_none:$addr)>; 4804 4805class acquiring_load<PatFrag base> 4806 : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 4807 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 4808 return isAcquireOrStronger(Ordering); 4809}]>; 4810 4811def atomic_load_acquire_8 : acquiring_load<atomic_load_8>; 4812def atomic_load_acquire_16 : acquiring_load<atomic_load_16>; 4813def atomic_load_acquire_32 : acquiring_load<atomic_load_32>; 4814 4815class releasing_store<PatFrag base> 4816 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 4817 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 4818 return isReleaseOrStronger(Ordering); 4819}]>; 4820 4821def atomic_store_release_8 : releasing_store<atomic_store_8>; 4822def atomic_store_release_16 : releasing_store<atomic_store_16>; 4823def atomic_store_release_32 : releasing_store<atomic_store_32>; 4824 4825let AddedComplexity = 8 in { 4826 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>; 4827 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>; 4828 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>; 4829 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>; 4830 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>; 4831 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>; 4832} 4833 4834// SWP/SWPB are deprecated in V6/V7. 4835let mayLoad = 1, mayStore = 1 in { 4836def SWP : AIswp<0, (outs GPRnopc:$Rt), 4837 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>, 4838 Requires<[PreV8]>; 4839def SWPB: AIswp<1, (outs GPRnopc:$Rt), 4840 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>, 4841 Requires<[PreV8]>; 4842} 4843 4844//===----------------------------------------------------------------------===// 4845// Coprocessor Instructions. 4846// 4847 4848def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4849 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4850 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4851 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4852 imm:$CRm, imm:$opc2)]>, 4853 Requires<[PreV8]> { 4854 bits<4> opc1; 4855 bits<4> CRn; 4856 bits<4> CRd; 4857 bits<4> cop; 4858 bits<3> opc2; 4859 bits<4> CRm; 4860 4861 let Inst{3-0} = CRm; 4862 let Inst{4} = 0; 4863 let Inst{7-5} = opc2; 4864 let Inst{11-8} = cop; 4865 let Inst{15-12} = CRd; 4866 let Inst{19-16} = CRn; 4867 let Inst{23-20} = opc1; 4868} 4869 4870def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4871 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4872 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4873 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4874 imm:$CRm, imm:$opc2)]>, 4875 Requires<[PreV8]> { 4876 let Inst{31-28} = 0b1111; 4877 bits<4> opc1; 4878 bits<4> CRn; 4879 bits<4> CRd; 4880 bits<4> cop; 4881 bits<3> opc2; 4882 bits<4> CRm; 4883 4884 let Inst{3-0} = CRm; 4885 let Inst{4} = 0; 4886 let Inst{7-5} = opc2; 4887 let Inst{11-8} = cop; 4888 let Inst{15-12} = CRd; 4889 let Inst{19-16} = CRn; 4890 let Inst{23-20} = opc1; 4891} 4892 4893class ACI<dag oops, dag iops, string opc, string asm, 4894 list<dag> pattern, IndexMode im = IndexModeNone> 4895 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 4896 opc, asm, "", pattern> { 4897 let Inst{27-25} = 0b110; 4898} 4899class ACInoP<dag oops, dag iops, string opc, string asm, 4900 list<dag> pattern, IndexMode im = IndexModeNone> 4901 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 4902 opc, asm, "", pattern> { 4903 let Inst{31-28} = 0b1111; 4904 let Inst{27-25} = 0b110; 4905} 4906multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> { 4907 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 4908 asm, "\t$cop, $CRd, $addr", pattern> { 4909 bits<13> addr; 4910 bits<4> cop; 4911 bits<4> CRd; 4912 let Inst{24} = 1; // P = 1 4913 let Inst{23} = addr{8}; 4914 let Inst{22} = Dbit; 4915 let Inst{21} = 0; // W = 0 4916 let Inst{20} = load; 4917 let Inst{19-16} = addr{12-9}; 4918 let Inst{15-12} = CRd; 4919 let Inst{11-8} = cop; 4920 let Inst{7-0} = addr{7-0}; 4921 let DecoderMethod = "DecodeCopMemInstruction"; 4922 } 4923 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 4924 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { 4925 bits<13> addr; 4926 bits<4> cop; 4927 bits<4> CRd; 4928 let Inst{24} = 1; // P = 1 4929 let Inst{23} = addr{8}; 4930 let Inst{22} = Dbit; 4931 let Inst{21} = 1; // W = 1 4932 let Inst{20} = load; 4933 let Inst{19-16} = addr{12-9}; 4934 let Inst{15-12} = CRd; 4935 let Inst{11-8} = cop; 4936 let Inst{7-0} = addr{7-0}; 4937 let DecoderMethod = "DecodeCopMemInstruction"; 4938 } 4939 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4940 postidx_imm8s4:$offset), 4941 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { 4942 bits<9> offset; 4943 bits<4> addr; 4944 bits<4> cop; 4945 bits<4> CRd; 4946 let Inst{24} = 0; // P = 0 4947 let Inst{23} = offset{8}; 4948 let Inst{22} = Dbit; 4949 let Inst{21} = 1; // W = 1 4950 let Inst{20} = load; 4951 let Inst{19-16} = addr; 4952 let Inst{15-12} = CRd; 4953 let Inst{11-8} = cop; 4954 let Inst{7-0} = offset{7-0}; 4955 let DecoderMethod = "DecodeCopMemInstruction"; 4956 } 4957 def _OPTION : ACI<(outs), 4958 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4959 coproc_option_imm:$option), 4960 asm, "\t$cop, $CRd, $addr, $option", []> { 4961 bits<8> option; 4962 bits<4> addr; 4963 bits<4> cop; 4964 bits<4> CRd; 4965 let Inst{24} = 0; // P = 0 4966 let Inst{23} = 1; // U = 1 4967 let Inst{22} = Dbit; 4968 let Inst{21} = 0; // W = 0 4969 let Inst{20} = load; 4970 let Inst{19-16} = addr; 4971 let Inst{15-12} = CRd; 4972 let Inst{11-8} = cop; 4973 let Inst{7-0} = option; 4974 let DecoderMethod = "DecodeCopMemInstruction"; 4975 } 4976} 4977multiclass LdSt2Cop<bit load, bit Dbit, string asm, list<dag> pattern> { 4978 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 4979 asm, "\t$cop, $CRd, $addr", pattern> { 4980 bits<13> addr; 4981 bits<4> cop; 4982 bits<4> CRd; 4983 let Inst{24} = 1; // P = 1 4984 let Inst{23} = addr{8}; 4985 let Inst{22} = Dbit; 4986 let Inst{21} = 0; // W = 0 4987 let Inst{20} = load; 4988 let Inst{19-16} = addr{12-9}; 4989 let Inst{15-12} = CRd; 4990 let Inst{11-8} = cop; 4991 let Inst{7-0} = addr{7-0}; 4992 let DecoderMethod = "DecodeCopMemInstruction"; 4993 } 4994 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 4995 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { 4996 bits<13> addr; 4997 bits<4> cop; 4998 bits<4> CRd; 4999 let Inst{24} = 1; // P = 1 5000 let Inst{23} = addr{8}; 5001 let Inst{22} = Dbit; 5002 let Inst{21} = 1; // W = 1 5003 let Inst{20} = load; 5004 let Inst{19-16} = addr{12-9}; 5005 let Inst{15-12} = CRd; 5006 let Inst{11-8} = cop; 5007 let Inst{7-0} = addr{7-0}; 5008 let DecoderMethod = "DecodeCopMemInstruction"; 5009 } 5010 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5011 postidx_imm8s4:$offset), 5012 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { 5013 bits<9> offset; 5014 bits<4> addr; 5015 bits<4> cop; 5016 bits<4> CRd; 5017 let Inst{24} = 0; // P = 0 5018 let Inst{23} = offset{8}; 5019 let Inst{22} = Dbit; 5020 let Inst{21} = 1; // W = 1 5021 let Inst{20} = load; 5022 let Inst{19-16} = addr; 5023 let Inst{15-12} = CRd; 5024 let Inst{11-8} = cop; 5025 let Inst{7-0} = offset{7-0}; 5026 let DecoderMethod = "DecodeCopMemInstruction"; 5027 } 5028 def _OPTION : ACInoP<(outs), 5029 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5030 coproc_option_imm:$option), 5031 asm, "\t$cop, $CRd, $addr, $option", []> { 5032 bits<8> option; 5033 bits<4> addr; 5034 bits<4> cop; 5035 bits<4> CRd; 5036 let Inst{24} = 0; // P = 0 5037 let Inst{23} = 1; // U = 1 5038 let Inst{22} = Dbit; 5039 let Inst{21} = 0; // W = 0 5040 let Inst{20} = load; 5041 let Inst{19-16} = addr; 5042 let Inst{15-12} = CRd; 5043 let Inst{11-8} = cop; 5044 let Inst{7-0} = option; 5045 let DecoderMethod = "DecodeCopMemInstruction"; 5046 } 5047} 5048 5049defm LDC : LdStCop <1, 0, "ldc", [(int_arm_ldc imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5050defm LDCL : LdStCop <1, 1, "ldcl", [(int_arm_ldcl imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5051defm LDC2 : LdSt2Cop<1, 0, "ldc2", [(int_arm_ldc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8]>; 5052defm LDC2L : LdSt2Cop<1, 1, "ldc2l", [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8]>; 5053 5054defm STC : LdStCop <0, 0, "stc", [(int_arm_stc imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5055defm STCL : LdStCop <0, 1, "stcl", [(int_arm_stcl imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5056defm STC2 : LdSt2Cop<0, 0, "stc2", [(int_arm_stc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8]>; 5057defm STC2L : LdSt2Cop<0, 1, "stc2l", [(int_arm_stc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8]>; 5058 5059//===----------------------------------------------------------------------===// 5060// Move between coprocessor and ARM core register. 5061// 5062 5063class MovRCopro<string opc, bit direction, dag oops, dag iops, 5064 list<dag> pattern> 5065 : ABI<0b1110, oops, iops, NoItinerary, opc, 5066 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> { 5067 let Inst{20} = direction; 5068 let Inst{4} = 1; 5069 5070 bits<4> Rt; 5071 bits<4> cop; 5072 bits<3> opc1; 5073 bits<3> opc2; 5074 bits<4> CRm; 5075 bits<4> CRn; 5076 5077 let Inst{15-12} = Rt; 5078 let Inst{11-8} = cop; 5079 let Inst{23-21} = opc1; 5080 let Inst{7-5} = opc2; 5081 let Inst{3-0} = CRm; 5082 let Inst{19-16} = CRn; 5083} 5084 5085def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */, 5086 (outs), 5087 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5088 c_imm:$CRm, imm0_7:$opc2), 5089 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 5090 imm:$CRm, imm:$opc2)]>, 5091 ComplexDeprecationPredicate<"MCR">; 5092def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 5093 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5094 c_imm:$CRm, 0, pred:$p)>; 5095def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, 5096 (outs GPRwithAPSR:$Rt), 5097 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5098 imm0_7:$opc2), []>; 5099def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", 5100 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5101 c_imm:$CRm, 0, pred:$p)>; 5102 5103def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 5104 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 5105 5106class MovRCopro2<string opc, bit direction, dag oops, dag iops, 5107 list<dag> pattern> 5108 : ABXI<0b1110, oops, iops, NoItinerary, 5109 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> { 5110 let Inst{31-24} = 0b11111110; 5111 let Inst{20} = direction; 5112 let Inst{4} = 1; 5113 5114 bits<4> Rt; 5115 bits<4> cop; 5116 bits<3> opc1; 5117 bits<3> opc2; 5118 bits<4> CRm; 5119 bits<4> CRn; 5120 5121 let Inst{15-12} = Rt; 5122 let Inst{11-8} = cop; 5123 let Inst{23-21} = opc1; 5124 let Inst{7-5} = opc2; 5125 let Inst{3-0} = CRm; 5126 let Inst{19-16} = CRn; 5127} 5128 5129def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */, 5130 (outs), 5131 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5132 c_imm:$CRm, imm0_7:$opc2), 5133 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 5134 imm:$CRm, imm:$opc2)]>, 5135 Requires<[PreV8]>; 5136def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm", 5137 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5138 c_imm:$CRm, 0)>; 5139def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, 5140 (outs GPRwithAPSR:$Rt), 5141 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5142 imm0_7:$opc2), []>, 5143 Requires<[PreV8]>; 5144def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm", 5145 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5146 c_imm:$CRm, 0)>; 5147 5148def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, 5149 imm:$CRm, imm:$opc2), 5150 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 5151 5152class MovRRCopro<string opc, bit direction, dag oops, dag iops, list<dag> 5153 pattern = []> 5154 : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", 5155 pattern> { 5156 5157 let Inst{23-21} = 0b010; 5158 let Inst{20} = direction; 5159 5160 bits<4> Rt; 5161 bits<4> Rt2; 5162 bits<4> cop; 5163 bits<4> opc1; 5164 bits<4> CRm; 5165 5166 let Inst{15-12} = Rt; 5167 let Inst{19-16} = Rt2; 5168 let Inst{11-8} = cop; 5169 let Inst{7-4} = opc1; 5170 let Inst{3-0} = CRm; 5171} 5172 5173def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */, 5174 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5175 GPRnopc:$Rt2, c_imm:$CRm), 5176 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt, 5177 GPRnopc:$Rt2, imm:$CRm)]>; 5178def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */, 5179 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5180 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5181 5182class MovRRCopro2<string opc, bit direction, dag oops, dag iops, 5183 list<dag> pattern = []> 5184 : ABXI<0b1100, oops, iops, NoItinerary, 5185 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>, 5186 Requires<[PreV8]> { 5187 let Inst{31-28} = 0b1111; 5188 let Inst{23-21} = 0b010; 5189 let Inst{20} = direction; 5190 5191 bits<4> Rt; 5192 bits<4> Rt2; 5193 bits<4> cop; 5194 bits<4> opc1; 5195 bits<4> CRm; 5196 5197 let Inst{15-12} = Rt; 5198 let Inst{19-16} = Rt2; 5199 let Inst{11-8} = cop; 5200 let Inst{7-4} = opc1; 5201 let Inst{3-0} = CRm; 5202 5203 let DecoderMethod = "DecoderForMRRC2AndMCRR2"; 5204} 5205 5206def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */, 5207 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5208 GPRnopc:$Rt2, c_imm:$CRm), 5209 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt, 5210 GPRnopc:$Rt2, imm:$CRm)]>; 5211 5212def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */, 5213 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5214 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5215 5216//===----------------------------------------------------------------------===// 5217// Move between special register and ARM core register 5218// 5219 5220// Move to ARM core register from Special Register 5221def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5222 "mrs", "\t$Rd, apsr", []> { 5223 bits<4> Rd; 5224 let Inst{23-16} = 0b00001111; 5225 let Unpredictable{19-17} = 0b111; 5226 5227 let Inst{15-12} = Rd; 5228 5229 let Inst{11-0} = 0b000000000000; 5230 let Unpredictable{11-0} = 0b110100001111; 5231} 5232 5233def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p), 0>, 5234 Requires<[IsARM]>; 5235 5236// The MRSsys instruction is the MRS instruction from the ARM ARM, 5237// section B9.3.9, with the R bit set to 1. 5238def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5239 "mrs", "\t$Rd, spsr", []> { 5240 bits<4> Rd; 5241 let Inst{23-16} = 0b01001111; 5242 let Unpredictable{19-16} = 0b1111; 5243 5244 let Inst{15-12} = Rd; 5245 5246 let Inst{11-0} = 0b000000000000; 5247 let Unpredictable{11-0} = 0b110100001111; 5248} 5249 5250// However, the MRS (banked register) system instruction (ARMv7VE) *does* have a 5251// separate encoding (distinguished by bit 5. 5252def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked), 5253 NoItinerary, "mrs", "\t$Rd, $banked", []>, 5254 Requires<[IsARM, HasVirtualization]> { 5255 bits<6> banked; 5256 bits<4> Rd; 5257 5258 let Inst{23} = 0; 5259 let Inst{22} = banked{5}; // R bit 5260 let Inst{21-20} = 0b00; 5261 let Inst{19-16} = banked{3-0}; 5262 let Inst{15-12} = Rd; 5263 let Inst{11-9} = 0b001; 5264 let Inst{8} = banked{4}; 5265 let Inst{7-0} = 0b00000000; 5266} 5267 5268// Move from ARM core register to Special Register 5269// 5270// No need to have both system and application versions of MSR (immediate) or 5271// MSR (register), the encodings are the same and the assembly parser has no way 5272// to distinguish between them. The mask operand contains the special register 5273// (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be 5274// accessed in the special register. 5275let Defs = [CPSR] in 5276def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, 5277 "msr", "\t$mask, $Rn", []> { 5278 bits<5> mask; 5279 bits<4> Rn; 5280 5281 let Inst{23} = 0; 5282 let Inst{22} = mask{4}; // R bit 5283 let Inst{21-20} = 0b10; 5284 let Inst{19-16} = mask{3-0}; 5285 let Inst{15-12} = 0b1111; 5286 let Inst{11-4} = 0b00000000; 5287 let Inst{3-0} = Rn; 5288} 5289 5290let Defs = [CPSR] in 5291def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary, 5292 "msr", "\t$mask, $imm", []> { 5293 bits<5> mask; 5294 bits<12> imm; 5295 5296 let Inst{23} = 0; 5297 let Inst{22} = mask{4}; // R bit 5298 let Inst{21-20} = 0b10; 5299 let Inst{19-16} = mask{3-0}; 5300 let Inst{15-12} = 0b1111; 5301 let Inst{11-0} = imm; 5302} 5303 5304// However, the MSR (banked register) system instruction (ARMv7VE) *does* have a 5305// separate encoding (distinguished by bit 5. 5306def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn), 5307 NoItinerary, "msr", "\t$banked, $Rn", []>, 5308 Requires<[IsARM, HasVirtualization]> { 5309 bits<6> banked; 5310 bits<4> Rn; 5311 5312 let Inst{23} = 0; 5313 let Inst{22} = banked{5}; // R bit 5314 let Inst{21-20} = 0b10; 5315 let Inst{19-16} = banked{3-0}; 5316 let Inst{15-12} = 0b1111; 5317 let Inst{11-9} = 0b001; 5318 let Inst{8} = banked{4}; 5319 let Inst{7-4} = 0b0000; 5320 let Inst{3-0} = Rn; 5321} 5322 5323// Dynamic stack allocation yields a _chkstk for Windows targets. These calls 5324// are needed to probe the stack when allocating more than 5325// 4k bytes in one go. Touching the stack at 4K increments is necessary to 5326// ensure that the guard pages used by the OS virtual memory manager are 5327// allocated in correct sequence. 5328// The main point of having separate instruction are extra unmodelled effects 5329// (compared to ordinary calls) like stack pointer change. 5330 5331def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone, 5332 [SDNPHasChain, SDNPSideEffect]>; 5333let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in 5334 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>; 5335 5336def win__dbzchk : SDNode<"ARMISD::WIN__DBZCHK", SDT_WIN__DBZCHK, 5337 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 5338let usesCustomInserter = 1, Defs = [CPSR] in 5339 def WIN__DBZCHK : PseudoInst<(outs), (ins tGPR:$divisor), NoItinerary, 5340 [(win__dbzchk tGPR:$divisor)]>; 5341 5342//===----------------------------------------------------------------------===// 5343// TLS Instructions 5344// 5345 5346// __aeabi_read_tp preserves the registers r1-r3. 5347// This is a pseudo inst so that we can get the encoding right, 5348// complete with fixup for the aeabi_read_tp function. 5349// TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern 5350// is defined in "ARMInstrThumb.td". 5351let isCall = 1, 5352 Defs = [R0, R12, LR, CPSR], Uses = [SP] in { 5353 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br, 5354 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>; 5355} 5356 5357//===----------------------------------------------------------------------===// 5358// SJLJ Exception handling intrinsics 5359// eh_sjlj_setjmp() is an instruction sequence to store the return 5360// address and save #0 in R0 for the non-longjmp case. 5361// Since by its nature we may be coming from some other function to get 5362// here, and we're using the stack frame for the containing function to 5363// save/restore registers, we can't keep anything live in regs across 5364// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 5365// when we get here from a longjmp(). We force everything out of registers 5366// except for our own input by listing the relevant registers in Defs. By 5367// doing so, we also cause the prologue/epilogue code to actively preserve 5368// all of the callee-saved resgisters, which is exactly what we want. 5369// A constant value is passed in $val, and we use the location as a scratch. 5370// 5371// These are pseudo-instructions and are lowered to individual MC-insts, so 5372// no encoding information is necessary. 5373let Defs = 5374 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 5375 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ], 5376 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5377 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5378 NoItinerary, 5379 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5380 Requires<[IsARM, HasVFP2]>; 5381} 5382 5383let Defs = 5384 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 5385 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5386 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5387 NoItinerary, 5388 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5389 Requires<[IsARM, NoVFP]>; 5390} 5391 5392// FIXME: Non-IOS version(s) 5393let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, 5394 Defs = [ R7, LR, SP ] in { 5395def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch), 5396 NoItinerary, 5397 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 5398 Requires<[IsARM]>; 5399} 5400 5401let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in 5402def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary, 5403 [(ARMeh_sjlj_setup_dispatch)]>; 5404 5405// eh.sjlj.dispatchsetup pseudo-instruction. 5406// This pseudo is used for both ARM and Thumb. Any differences are handled when 5407// the pseudo is expanded (which happens before any passes that need the 5408// instruction size). 5409let isBarrier = 1 in 5410def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>; 5411 5412 5413//===----------------------------------------------------------------------===// 5414// Non-Instruction Patterns 5415// 5416 5417// ARMv4 indirect branch using (MOVr PC, dst) 5418let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in 5419 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst), 5420 4, IIC_Br, [(brind GPR:$dst)], 5421 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5422 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5423 5424// Large immediate handling. 5425 5426// 32-bit immediate using two piece mod_imms or movw + movt. 5427// This is a single pseudo instruction, the benefit is that it can be remat'd 5428// as a single unit instead of having to handle reg inputs. 5429// FIXME: Remove this when we can do generalized remat. 5430let isReMaterializable = 1, isMoveImm = 1 in 5431def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 5432 [(set GPR:$dst, (arm_i32imm:$src))]>, 5433 Requires<[IsARM]>; 5434 5435def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i, 5436 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>, 5437 Requires<[IsARM, DontUseMovt]>; 5438 5439// Pseudo instruction that combines movw + movt + add pc (if PIC). 5440// It also makes it possible to rematerialize the instructions. 5441// FIXME: Remove this when we can do generalized remat and when machine licm 5442// can properly the instructions. 5443let isReMaterializable = 1 in { 5444def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5445 IIC_iMOVix2addpc, 5446 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 5447 Requires<[IsARM, UseMovt]>; 5448 5449def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5450 IIC_iLoadiALU, 5451 [(set GPR:$dst, 5452 (ARMWrapperPIC tglobaladdr:$addr))]>, 5453 Requires<[IsARM, DontUseMovt]>; 5454 5455let AddedComplexity = 10 in 5456def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5457 NoItinerary, 5458 [(set GPR:$dst, 5459 (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5460 Requires<[IsARM, DontUseMovt]>; 5461 5462let AddedComplexity = 10 in 5463def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5464 IIC_iMOVix2ld, 5465 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5466 Requires<[IsARM, UseMovt]>; 5467} // isReMaterializable 5468 5469// The many different faces of TLS access. 5470def : ARMPat<(ARMWrapper tglobaltlsaddr :$dst), 5471 (MOVi32imm tglobaltlsaddr :$dst)>, 5472 Requires<[IsARM, UseMovt]>; 5473 5474def : Pat<(ARMWrapper tglobaltlsaddr:$src), 5475 (LDRLIT_ga_abs tglobaltlsaddr:$src)>, 5476 Requires<[IsARM, DontUseMovt]>; 5477 5478def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5479 (MOV_ga_pcrel tglobaltlsaddr:$addr)>, Requires<[IsARM, UseMovt]>; 5480 5481def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5482 (LDRLIT_ga_pcrel tglobaltlsaddr:$addr)>, 5483 Requires<[IsARM, DontUseMovt]>; 5484let AddedComplexity = 10 in 5485def : Pat<(load (ARMWrapperPIC tglobaltlsaddr:$addr)), 5486 (MOV_ga_pcrel_ldr tglobaltlsaddr:$addr)>, 5487 Requires<[IsARM, UseMovt]>; 5488 5489 5490// ConstantPool, GlobalAddress, and JumpTable 5491def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 5492def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>, 5493 Requires<[IsARM, UseMovt]>; 5494def : ARMPat<(ARMWrapper texternalsym :$dst), (MOVi32imm texternalsym :$dst)>, 5495 Requires<[IsARM, UseMovt]>; 5496def : ARMPat<(ARMWrapperJT tjumptable:$dst), 5497 (LEApcrelJT tjumptable:$dst)>; 5498 5499// TODO: add,sub,and, 3-instr forms? 5500 5501// Tail calls. These patterns also apply to Thumb mode. 5502def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>; 5503def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>; 5504def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>; 5505 5506// Direct calls 5507def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; 5508def : ARMPat<(ARMcall_nolink texternalsym:$func), 5509 (BMOVPCB_CALL texternalsym:$func)>; 5510 5511// zextload i1 -> zextload i8 5512def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5513def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5514 5515// extload -> zextload 5516def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5517def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5518def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5519def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5520 5521def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 5522 5523def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; 5524def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; 5525 5526// smul* and smla* 5527def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 5528 (SMULBB GPR:$a, GPR:$b)>; 5529def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))), 5530 (SMULBT GPR:$a, GPR:$b)>; 5531def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b), 5532 (SMULTB GPR:$a, GPR:$b)>; 5533def : ARMV5MOPat<(add GPR:$acc, 5534 (mul sext_16_node:$a, sext_16_node:$b)), 5535 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5536def : ARMV5MOPat<(add GPR:$acc, 5537 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))), 5538 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5539def : ARMV5MOPat<(add GPR:$acc, 5540 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)), 5541 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5542 5543// Pre-v7 uses MCR for synchronization barriers. 5544def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>, 5545 Requires<[IsARM, HasV6]>; 5546 5547// SXT/UXT with no rotate 5548let AddedComplexity = 16 in { 5549def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>; 5550def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>; 5551def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>; 5552def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)), 5553 (UXTAB GPR:$Rn, GPR:$Rm, 0)>; 5554def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)), 5555 (UXTAH GPR:$Rn, GPR:$Rm, 0)>; 5556} 5557 5558def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>; 5559def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; 5560 5561def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)), 5562 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>; 5563def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)), 5564 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>; 5565 5566// Atomic load/store patterns 5567def : ARMPat<(atomic_load_8 ldst_so_reg:$src), 5568 (LDRBrs ldst_so_reg:$src)>; 5569def : ARMPat<(atomic_load_8 addrmode_imm12:$src), 5570 (LDRBi12 addrmode_imm12:$src)>; 5571def : ARMPat<(atomic_load_16 addrmode3:$src), 5572 (LDRH addrmode3:$src)>; 5573def : ARMPat<(atomic_load_32 ldst_so_reg:$src), 5574 (LDRrs ldst_so_reg:$src)>; 5575def : ARMPat<(atomic_load_32 addrmode_imm12:$src), 5576 (LDRi12 addrmode_imm12:$src)>; 5577def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val), 5578 (STRBrs GPR:$val, ldst_so_reg:$ptr)>; 5579def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val), 5580 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>; 5581def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val), 5582 (STRH GPR:$val, addrmode3:$ptr)>; 5583def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val), 5584 (STRrs GPR:$val, ldst_so_reg:$ptr)>; 5585def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val), 5586 (STRi12 GPR:$val, addrmode_imm12:$ptr)>; 5587 5588 5589//===----------------------------------------------------------------------===// 5590// Thumb Support 5591// 5592 5593include "ARMInstrThumb.td" 5594 5595//===----------------------------------------------------------------------===// 5596// Thumb2 Support 5597// 5598 5599include "ARMInstrThumb2.td" 5600 5601//===----------------------------------------------------------------------===// 5602// Floating Point Support 5603// 5604 5605include "ARMInstrVFP.td" 5606 5607//===----------------------------------------------------------------------===// 5608// Advanced SIMD (NEON) Support 5609// 5610 5611include "ARMInstrNEON.td" 5612 5613//===----------------------------------------------------------------------===// 5614// Assembler aliases 5615// 5616 5617// Memory barriers 5618def : InstAlias<"dmb", (DMB 0xf), 0>, Requires<[IsARM, HasDB]>; 5619def : InstAlias<"dsb", (DSB 0xf), 0>, Requires<[IsARM, HasDB]>; 5620def : InstAlias<"isb", (ISB 0xf), 0>, Requires<[IsARM, HasDB]>; 5621 5622// System instructions 5623def : MnemonicAlias<"swi", "svc">; 5624 5625// Load / Store Multiple 5626def : MnemonicAlias<"ldmfd", "ldm">; 5627def : MnemonicAlias<"ldmia", "ldm">; 5628def : MnemonicAlias<"ldmea", "ldmdb">; 5629def : MnemonicAlias<"stmfd", "stmdb">; 5630def : MnemonicAlias<"stmia", "stm">; 5631def : MnemonicAlias<"stmea", "stm">; 5632 5633// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the 5634// input operands swapped when the shift amount is zero (i.e., unspecified). 5635def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 5636 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p), 0>, 5637 Requires<[IsARM, HasV6]>; 5638def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 5639 (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p), 0>, 5640 Requires<[IsARM, HasV6]>; 5641 5642// PUSH/POP aliases for STM/LDM 5643def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>; 5644def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>; 5645 5646// SSAT/USAT optional shift operand. 5647def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 5648 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5649def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn", 5650 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5651 5652 5653// Extend instruction optional rotate operand. 5654def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm", 5655 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5656def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm", 5657 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5658def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 5659 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5660def : ARMInstAlias<"sxtb${p} $Rd, $Rm", 5661 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5662def : ARMInstAlias<"sxtb16${p} $Rd, $Rm", 5663 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5664def : ARMInstAlias<"sxth${p} $Rd, $Rm", 5665 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5666 5667def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm", 5668 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5669def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm", 5670 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5671def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 5672 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5673def : ARMInstAlias<"uxtb${p} $Rd, $Rm", 5674 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5675def : ARMInstAlias<"uxtb16${p} $Rd, $Rm", 5676 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5677def : ARMInstAlias<"uxth${p} $Rd, $Rm", 5678 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5679 5680 5681// RFE aliases 5682def : MnemonicAlias<"rfefa", "rfeda">; 5683def : MnemonicAlias<"rfeea", "rfedb">; 5684def : MnemonicAlias<"rfefd", "rfeia">; 5685def : MnemonicAlias<"rfeed", "rfeib">; 5686def : MnemonicAlias<"rfe", "rfeia">; 5687 5688// SRS aliases 5689def : MnemonicAlias<"srsfa", "srsib">; 5690def : MnemonicAlias<"srsea", "srsia">; 5691def : MnemonicAlias<"srsfd", "srsdb">; 5692def : MnemonicAlias<"srsed", "srsda">; 5693def : MnemonicAlias<"srs", "srsia">; 5694 5695// QSAX == QSUBADDX 5696def : MnemonicAlias<"qsubaddx", "qsax">; 5697// SASX == SADDSUBX 5698def : MnemonicAlias<"saddsubx", "sasx">; 5699// SHASX == SHADDSUBX 5700def : MnemonicAlias<"shaddsubx", "shasx">; 5701// SHSAX == SHSUBADDX 5702def : MnemonicAlias<"shsubaddx", "shsax">; 5703// SSAX == SSUBADDX 5704def : MnemonicAlias<"ssubaddx", "ssax">; 5705// UASX == UADDSUBX 5706def : MnemonicAlias<"uaddsubx", "uasx">; 5707// UHASX == UHADDSUBX 5708def : MnemonicAlias<"uhaddsubx", "uhasx">; 5709// UHSAX == UHSUBADDX 5710def : MnemonicAlias<"uhsubaddx", "uhsax">; 5711// UQASX == UQADDSUBX 5712def : MnemonicAlias<"uqaddsubx", "uqasx">; 5713// UQSAX == UQSUBADDX 5714def : MnemonicAlias<"uqsubaddx", "uqsax">; 5715// USAX == USUBADDX 5716def : MnemonicAlias<"usubaddx", "usax">; 5717 5718// "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like 5719// for isel. 5720def : ARMInstAlias<"mov${s}${p} $Rd, $imm", 5721 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 5722def : ARMInstAlias<"mvn${s}${p} $Rd, $imm", 5723 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 5724// Same for AND <--> BIC 5725def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm", 5726 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 5727 pred:$p, cc_out:$s)>; 5728def : ARMInstAlias<"bic${s}${p} $Rdn, $imm", 5729 (ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 5730 pred:$p, cc_out:$s)>; 5731def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm", 5732 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 5733 pred:$p, cc_out:$s)>; 5734def : ARMInstAlias<"and${s}${p} $Rdn, $imm", 5735 (BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 5736 pred:$p, cc_out:$s)>; 5737 5738// Likewise, "add Rd, mod_imm_neg" -> sub 5739def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm", 5740 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 5741def : ARMInstAlias<"add${s}${p} $Rd, $imm", 5742 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 5743// Same for CMP <--> CMN via mod_imm_neg 5744def : ARMInstAlias<"cmp${p} $Rd, $imm", 5745 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 5746def : ARMInstAlias<"cmn${p} $Rd, $imm", 5747 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 5748 5749// The shifter forms of the MOV instruction are aliased to the ASR, LSL, 5750// LSR, ROR, and RRX instructions. 5751// FIXME: We need C++ parser hooks to map the alias to the MOV 5752// encoding. It seems we should be able to do that sort of thing 5753// in tblgen, but it could get ugly. 5754let TwoOperandAliasConstraint = "$Rm = $Rd" in { 5755def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm", 5756 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 5757 cc_out:$s)>; 5758def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm", 5759 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 5760 cc_out:$s)>; 5761def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm", 5762 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 5763 cc_out:$s)>; 5764def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm", 5765 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 5766 cc_out:$s)>; 5767} 5768def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm", 5769 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>; 5770let TwoOperandAliasConstraint = "$Rn = $Rd" in { 5771def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm", 5772 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5773 cc_out:$s)>; 5774def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm", 5775 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5776 cc_out:$s)>; 5777def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm", 5778 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5779 cc_out:$s)>; 5780def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm", 5781 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5782 cc_out:$s)>; 5783} 5784 5785// "neg" is and alias for "rsb rd, rn, #0" 5786def : ARMInstAlias<"neg${s}${p} $Rd, $Rm", 5787 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>; 5788 5789// Pre-v6, 'mov r0, r0' was used as a NOP encoding. 5790def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>, 5791 Requires<[IsARM, NoV6]>; 5792 5793// MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but 5794// the instruction definitions need difference constraints pre-v6. 5795// Use these aliases for the assembly parsing on pre-v6. 5796def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm", 5797 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s), 0>, 5798 Requires<[IsARM, NoV6]>; 5799def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra", 5800 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 5801 pred:$p, cc_out:$s), 0>, 5802 Requires<[IsARM, NoV6]>; 5803def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5804 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 5805 Requires<[IsARM, NoV6]>; 5806def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5807 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 5808 Requires<[IsARM, NoV6]>; 5809def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5810 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 5811 Requires<[IsARM, NoV6]>; 5812def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5813 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 5814 Requires<[IsARM, NoV6]>; 5815 5816// 'it' blocks in ARM mode just validate the predicates. The IT itself 5817// is discarded. 5818def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>, 5819 ComplexDeprecationPredicate<"IT">; 5820 5821let mayLoad = 1, mayStore =1, hasSideEffects = 1 in 5822def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn), 5823 NoItinerary, 5824 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>; 5825 5826//===---------------------------------- 5827// Atomic cmpxchg for -O0 5828//===---------------------------------- 5829 5830// The fast register allocator used during -O0 inserts spills to cover any VRegs 5831// live across basic block boundaries. When this happens between an LDXR and an 5832// STXR it can clear the exclusive monitor, causing all cmpxchg attempts to 5833// fail. 5834 5835// Unfortunately, this means we have to have an alternative (expanded 5836// post-regalloc) path for -O0 compilations. Fortunately this path can be 5837// significantly more naive than the standard expansion: we conservatively 5838// assume seq_cst, strong cmpxchg and omit clrex on failure. 5839 5840let Constraints = "@earlyclobber $Rd,@earlyclobber $status", 5841 mayLoad = 1, mayStore = 1 in { 5842def CMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, GPR:$status), 5843 (ins GPR:$addr, GPR:$desired, GPR:$new), 5844 NoItinerary, []>, Sched<[]>; 5845 5846def CMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, GPR:$status), 5847 (ins GPR:$addr, GPR:$desired, GPR:$new), 5848 NoItinerary, []>, Sched<[]>; 5849 5850def CMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, GPR:$status), 5851 (ins GPR:$addr, GPR:$desired, GPR:$new), 5852 NoItinerary, []>, Sched<[]>; 5853 5854def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$status), 5855 (ins GPR:$addr, GPRPair:$desired, GPRPair:$new), 5856 NoItinerary, []>, Sched<[]>; 5857} 5858