1 //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the ARM implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMInstrInfo.h"
15 #include "ARM.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/Target/TargetAsmInfo.h"
25 #include "llvm/Support/CommandLine.h"
26 using namespace llvm;
27 
28 static cl::opt<bool>
29 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
30                cl::desc("Enable ARM 2-addr to 3-addr conv"));
31 
32 static inline
33 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
34   return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
35 }
36 
37 static inline
38 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
39   return MIB.addReg(0);
40 }
41 
42 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget &STI)
43   : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)) {
44 }
45 
46 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
47   : ARMBaseInstrInfo(STI), RI(*this, STI) {
48 }
49 
50 /// Return true if the instruction is a register to register move and
51 /// leave the source and dest operands in the passed parameters.
52 ///
53 bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
54                                unsigned &SrcReg, unsigned &DstReg,
55                                unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
56   SrcSubIdx = DstSubIdx = 0; // No sub-registers.
57 
58   unsigned oc = MI.getOpcode();
59   switch (oc) {
60   default:
61     return false;
62   case ARM::FCPYS:
63   case ARM::FCPYD:
64   case ARM::VMOVD:
65   case ARM::VMOVQ:
66     SrcReg = MI.getOperand(1).getReg();
67     DstReg = MI.getOperand(0).getReg();
68     return true;
69   case ARM::MOVr:
70     assert(MI.getDesc().getNumOperands() >= 2 &&
71            MI.getOperand(0).isReg() &&
72            MI.getOperand(1).isReg() &&
73            "Invalid ARM MOV instruction");
74     SrcReg = MI.getOperand(1).getReg();
75     DstReg = MI.getOperand(0).getReg();
76     return true;
77   }
78 }
79 
80 unsigned ARMInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
81                                            int &FrameIndex) const {
82   switch (MI->getOpcode()) {
83   default: break;
84   case ARM::LDR:
85     if (MI->getOperand(1).isFI() &&
86         MI->getOperand(2).isReg() &&
87         MI->getOperand(3).isImm() &&
88         MI->getOperand(2).getReg() == 0 &&
89         MI->getOperand(3).getImm() == 0) {
90       FrameIndex = MI->getOperand(1).getIndex();
91       return MI->getOperand(0).getReg();
92     }
93     break;
94   case ARM::FLDD:
95   case ARM::FLDS:
96     if (MI->getOperand(1).isFI() &&
97         MI->getOperand(2).isImm() &&
98         MI->getOperand(2).getImm() == 0) {
99       FrameIndex = MI->getOperand(1).getIndex();
100       return MI->getOperand(0).getReg();
101     }
102     break;
103   }
104   return 0;
105 }
106 
107 unsigned ARMInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
108                                           int &FrameIndex) const {
109   switch (MI->getOpcode()) {
110   default: break;
111   case ARM::STR:
112     if (MI->getOperand(1).isFI() &&
113         MI->getOperand(2).isReg() &&
114         MI->getOperand(3).isImm() &&
115         MI->getOperand(2).getReg() == 0 &&
116         MI->getOperand(3).getImm() == 0) {
117       FrameIndex = MI->getOperand(1).getIndex();
118       return MI->getOperand(0).getReg();
119     }
120     break;
121   case ARM::FSTD:
122   case ARM::FSTS:
123     if (MI->getOperand(1).isFI() &&
124         MI->getOperand(2).isImm() &&
125         MI->getOperand(2).getImm() == 0) {
126       FrameIndex = MI->getOperand(1).getIndex();
127       return MI->getOperand(0).getReg();
128     }
129     break;
130   }
131 
132   return 0;
133 }
134 
135 void ARMInstrInfo::reMaterialize(MachineBasicBlock &MBB,
136                                  MachineBasicBlock::iterator I,
137                                  unsigned DestReg,
138                                  const MachineInstr *Orig) const {
139   DebugLoc dl = Orig->getDebugLoc();
140   if (Orig->getOpcode() == ARM::MOVi2pieces) {
141     RI.emitLoadConstPool(MBB, I, this, dl,
142                          DestReg,
143                          Orig->getOperand(1).getImm(),
144                          (ARMCC::CondCodes)Orig->getOperand(2).getImm(),
145                          Orig->getOperand(3).getReg());
146     return;
147   }
148 
149   MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
150   MI->getOperand(0).setReg(DestReg);
151   MBB.insert(I, MI);
152 }
153 
154 static unsigned getUnindexedOpcode(unsigned Opc) {
155   switch (Opc) {
156   default: break;
157   case ARM::LDR_PRE:
158   case ARM::LDR_POST:
159     return ARM::LDR;
160   case ARM::LDRH_PRE:
161   case ARM::LDRH_POST:
162     return ARM::LDRH;
163   case ARM::LDRB_PRE:
164   case ARM::LDRB_POST:
165     return ARM::LDRB;
166   case ARM::LDRSH_PRE:
167   case ARM::LDRSH_POST:
168     return ARM::LDRSH;
169   case ARM::LDRSB_PRE:
170   case ARM::LDRSB_POST:
171     return ARM::LDRSB;
172   case ARM::STR_PRE:
173   case ARM::STR_POST:
174     return ARM::STR;
175   case ARM::STRH_PRE:
176   case ARM::STRH_POST:
177     return ARM::STRH;
178   case ARM::STRB_PRE:
179   case ARM::STRB_POST:
180     return ARM::STRB;
181   }
182   return 0;
183 }
184 
185 MachineInstr *
186 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
187                                         MachineBasicBlock::iterator &MBBI,
188                                         LiveVariables *LV) const {
189   if (!EnableARM3Addr)
190     return NULL;
191 
192   MachineInstr *MI = MBBI;
193   MachineFunction &MF = *MI->getParent()->getParent();
194   unsigned TSFlags = MI->getDesc().TSFlags;
195   bool isPre = false;
196   switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
197   default: return NULL;
198   case ARMII::IndexModePre:
199     isPre = true;
200     break;
201   case ARMII::IndexModePost:
202     break;
203   }
204 
205   // Try splitting an indexed load/store to an un-indexed one plus an add/sub
206   // operation.
207   unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
208   if (MemOpc == 0)
209     return NULL;
210 
211   MachineInstr *UpdateMI = NULL;
212   MachineInstr *MemMI = NULL;
213   unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
214   const TargetInstrDesc &TID = MI->getDesc();
215   unsigned NumOps = TID.getNumOperands();
216   bool isLoad = !TID.mayStore();
217   const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
218   const MachineOperand &Base = MI->getOperand(2);
219   const MachineOperand &Offset = MI->getOperand(NumOps-3);
220   unsigned WBReg = WB.getReg();
221   unsigned BaseReg = Base.getReg();
222   unsigned OffReg = Offset.getReg();
223   unsigned OffImm = MI->getOperand(NumOps-2).getImm();
224   ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
225   switch (AddrMode) {
226   default:
227     assert(false && "Unknown indexed op!");
228     return NULL;
229   case ARMII::AddrMode2: {
230     bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
231     unsigned Amt = ARM_AM::getAM2Offset(OffImm);
232     if (OffReg == 0) {
233       int SOImmVal = ARM_AM::getSOImmVal(Amt);
234       if (SOImmVal == -1)
235         // Can't encode it in a so_imm operand. This transformation will
236         // add more than 1 instruction. Abandon!
237         return NULL;
238       UpdateMI = BuildMI(MF, MI->getDebugLoc(),
239                          get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
240         .addReg(BaseReg).addImm(SOImmVal)
241         .addImm(Pred).addReg(0).addReg(0);
242     } else if (Amt != 0) {
243       ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
244       unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
245       UpdateMI = BuildMI(MF, MI->getDebugLoc(),
246                          get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
247         .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
248         .addImm(Pred).addReg(0).addReg(0);
249     } else
250       UpdateMI = BuildMI(MF, MI->getDebugLoc(),
251                          get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
252         .addReg(BaseReg).addReg(OffReg)
253         .addImm(Pred).addReg(0).addReg(0);
254     break;
255   }
256   case ARMII::AddrMode3 : {
257     bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
258     unsigned Amt = ARM_AM::getAM3Offset(OffImm);
259     if (OffReg == 0)
260       // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
261       UpdateMI = BuildMI(MF, MI->getDebugLoc(),
262                          get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
263         .addReg(BaseReg).addImm(Amt)
264         .addImm(Pred).addReg(0).addReg(0);
265     else
266       UpdateMI = BuildMI(MF, MI->getDebugLoc(),
267                          get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
268         .addReg(BaseReg).addReg(OffReg)
269         .addImm(Pred).addReg(0).addReg(0);
270     break;
271   }
272   }
273 
274   std::vector<MachineInstr*> NewMIs;
275   if (isPre) {
276     if (isLoad)
277       MemMI = BuildMI(MF, MI->getDebugLoc(),
278                       get(MemOpc), MI->getOperand(0).getReg())
279         .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
280     else
281       MemMI = BuildMI(MF, MI->getDebugLoc(),
282                       get(MemOpc)).addReg(MI->getOperand(1).getReg())
283         .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
284     NewMIs.push_back(MemMI);
285     NewMIs.push_back(UpdateMI);
286   } else {
287     if (isLoad)
288       MemMI = BuildMI(MF, MI->getDebugLoc(),
289                       get(MemOpc), MI->getOperand(0).getReg())
290         .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
291     else
292       MemMI = BuildMI(MF, MI->getDebugLoc(),
293                       get(MemOpc)).addReg(MI->getOperand(1).getReg())
294         .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
295     if (WB.isDead())
296       UpdateMI->getOperand(0).setIsDead();
297     NewMIs.push_back(UpdateMI);
298     NewMIs.push_back(MemMI);
299   }
300 
301   // Transfer LiveVariables states, kill / dead info.
302   if (LV) {
303     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
304       MachineOperand &MO = MI->getOperand(i);
305       if (MO.isReg() && MO.getReg() &&
306           TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
307         unsigned Reg = MO.getReg();
308 
309         LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
310         if (MO.isDef()) {
311           MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
312           if (MO.isDead())
313             LV->addVirtualRegisterDead(Reg, NewMI);
314         }
315         if (MO.isUse() && MO.isKill()) {
316           for (unsigned j = 0; j < 2; ++j) {
317             // Look at the two new MI's in reverse order.
318             MachineInstr *NewMI = NewMIs[j];
319             if (!NewMI->readsRegister(Reg))
320               continue;
321             LV->addVirtualRegisterKilled(Reg, NewMI);
322             if (VI.removeKill(MI))
323               VI.Kills.push_back(NewMI);
324             break;
325           }
326         }
327       }
328     }
329   }
330 
331   MFI->insert(MBBI, NewMIs[1]);
332   MFI->insert(MBBI, NewMIs[0]);
333   return NewMIs[0];
334 }
335 
336 // Branch analysis.
337 bool
338   ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
339                                   MachineBasicBlock *&FBB,
340                                   SmallVectorImpl<MachineOperand> &Cond,
341                                   bool AllowModify) const {
342   // If the block has no terminators, it just falls into the block after it.
343   MachineBasicBlock::iterator I = MBB.end();
344   if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
345     return false;
346 
347   // Get the last instruction in the block.
348   MachineInstr *LastInst = I;
349 
350   // If there is only one terminator instruction, process it.
351   unsigned LastOpc = LastInst->getOpcode();
352   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
353     if (LastOpc == ARM::B || LastOpc == ARM::tB || LastOpc == ARM::t2B) {
354       TBB = LastInst->getOperand(0).getMBB();
355       return false;
356     }
357     if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc || LastOpc == ARM::t2Bcc) {
358       // Block ends with fall-through condbranch.
359       TBB = LastInst->getOperand(0).getMBB();
360       Cond.push_back(LastInst->getOperand(1));
361       Cond.push_back(LastInst->getOperand(2));
362       return false;
363     }
364     return true;  // Can't handle indirect branch.
365   }
366 
367   // Get the instruction before it if it is a terminator.
368   MachineInstr *SecondLastInst = I;
369 
370   // If there are three terminators, we don't know what sort of block this is.
371   if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
372     return true;
373 
374   // If the block ends with ARM::B/ARM::tB/ARM::t2B and a
375   // ARM::Bcc/ARM::tBcc/ARM::t2Bcc, handle it.
376   unsigned SecondLastOpc = SecondLastInst->getOpcode();
377   if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
378       (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB) ||
379       (SecondLastOpc == ARM::t2Bcc && LastOpc == ARM::t2B)) {
380     TBB =  SecondLastInst->getOperand(0).getMBB();
381     Cond.push_back(SecondLastInst->getOperand(1));
382     Cond.push_back(SecondLastInst->getOperand(2));
383     FBB = LastInst->getOperand(0).getMBB();
384     return false;
385   }
386 
387   // If the block ends with two unconditional branches, handle it.  The second
388   // one is not executed, so remove it.
389   if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB ||
390        SecondLastOpc==ARM::t2B) &&
391       (LastOpc == ARM::B || LastOpc == ARM::tB || LastOpc == ARM::t2B)) {
392     TBB = SecondLastInst->getOperand(0).getMBB();
393     I = LastInst;
394     if (AllowModify)
395       I->eraseFromParent();
396     return false;
397   }
398 
399   // ...likewise if it ends with a branch table followed by an unconditional
400   // branch. The branch folder can create these, and we must get rid of them for
401   // correctness of Thumb constant islands.
402   if ((SecondLastOpc == ARM::BR_JTr || SecondLastOpc==ARM::BR_JTm ||
403        SecondLastOpc == ARM::BR_JTadd || SecondLastOpc==ARM::tBR_JTr ||
404        SecondLastOpc == ARM::t2BR_JTr || SecondLastOpc==ARM::t2BR_JTm ||
405        SecondLastOpc == ARM::t2BR_JTadd) &&
406       (LastOpc == ARM::B || LastOpc == ARM::tB || LastOpc == ARM::t2B)) {
407     I = LastInst;
408     if (AllowModify)
409       I->eraseFromParent();
410     return true;
411   }
412 
413   // Otherwise, can't handle this.
414   return true;
415 }
416 
417 
418 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
419   MachineFunction &MF = *MBB.getParent();
420   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
421   int BOpc   = AFI->isThumbFunction() ?
422     (AFI->isThumb2Function() ? ARM::t2B : ARM::tB) : ARM::B;
423   int BccOpc = AFI->isThumbFunction() ?
424     (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
425 
426   MachineBasicBlock::iterator I = MBB.end();
427   if (I == MBB.begin()) return 0;
428   --I;
429   if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc)
430     return 0;
431 
432   // Remove the branch.
433   I->eraseFromParent();
434 
435   I = MBB.end();
436 
437   if (I == MBB.begin()) return 1;
438   --I;
439   if (I->getOpcode() != BccOpc)
440     return 1;
441 
442   // Remove the branch.
443   I->eraseFromParent();
444   return 2;
445 }
446 
447 unsigned
448 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
449                                MachineBasicBlock *FBB,
450                              const SmallVectorImpl<MachineOperand> &Cond) const {
451   // FIXME this should probably have a DebugLoc argument
452   DebugLoc dl = DebugLoc::getUnknownLoc();
453   MachineFunction &MF = *MBB.getParent();
454   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
455   int BOpc   = AFI->isThumbFunction() ?
456     (AFI->isThumb2Function() ? ARM::t2B : ARM::tB) : ARM::B;
457   int BccOpc = AFI->isThumbFunction() ?
458     (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
459 
460   // Shouldn't be a fall through.
461   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
462   assert((Cond.size() == 2 || Cond.size() == 0) &&
463          "ARM branch conditions have two components!");
464 
465   if (FBB == 0) {
466     if (Cond.empty()) // Unconditional branch?
467       BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
468     else
469       BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
470         .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
471     return 1;
472   }
473 
474   // Two-way conditional branch.
475   BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
476     .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
477   BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
478   return 2;
479 }
480 
481 bool ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
482                                 MachineBasicBlock::iterator I,
483                                 unsigned DestReg, unsigned SrcReg,
484                                 const TargetRegisterClass *DestRC,
485                                 const TargetRegisterClass *SrcRC) const {
486   DebugLoc DL = DebugLoc::getUnknownLoc();
487   if (I != MBB.end()) DL = I->getDebugLoc();
488 
489   if (DestRC != SrcRC) {
490     // Not yet supported!
491     return false;
492   }
493 
494   if (DestRC == ARM::GPRRegisterClass)
495     AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
496                                 .addReg(SrcReg)));
497   else if (DestRC == ARM::SPRRegisterClass)
498     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
499                    .addReg(SrcReg));
500   else if (DestRC == ARM::DPRRegisterClass)
501     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
502                    .addReg(SrcReg));
503   else if (DestRC == ARM::QPRRegisterClass)
504     BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
505   else
506     return false;
507 
508   return true;
509 }
510 
511 void ARMInstrInfo::
512 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
513                     unsigned SrcReg, bool isKill, int FI,
514                     const TargetRegisterClass *RC) const {
515   DebugLoc DL = DebugLoc::getUnknownLoc();
516   if (I != MBB.end()) DL = I->getDebugLoc();
517 
518   if (RC == ARM::GPRRegisterClass) {
519     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
520                    .addReg(SrcReg, getKillRegState(isKill))
521                    .addFrameIndex(FI).addReg(0).addImm(0));
522   } else if (RC == ARM::DPRRegisterClass) {
523     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
524                    .addReg(SrcReg, getKillRegState(isKill))
525                    .addFrameIndex(FI).addImm(0));
526   } else {
527     assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
528     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
529                    .addReg(SrcReg, getKillRegState(isKill))
530                    .addFrameIndex(FI).addImm(0));
531   }
532 }
533 
534 void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
535                                   bool isKill,
536                                   SmallVectorImpl<MachineOperand> &Addr,
537                                   const TargetRegisterClass *RC,
538                                   SmallVectorImpl<MachineInstr*> &NewMIs) const{
539   DebugLoc DL = DebugLoc::getUnknownLoc();
540   unsigned Opc = 0;
541   if (RC == ARM::GPRRegisterClass) {
542     Opc = ARM::STR;
543   } else if (RC == ARM::DPRRegisterClass) {
544     Opc = ARM::FSTD;
545   } else {
546     assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
547     Opc = ARM::FSTS;
548   }
549 
550   MachineInstrBuilder MIB =
551     BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
552   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
553     MIB.addOperand(Addr[i]);
554   AddDefaultPred(MIB);
555   NewMIs.push_back(MIB);
556   return;
557 }
558 
559 void ARMInstrInfo::
560 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
561                      unsigned DestReg, int FI,
562                      const TargetRegisterClass *RC) const {
563   DebugLoc DL = DebugLoc::getUnknownLoc();
564   if (I != MBB.end()) DL = I->getDebugLoc();
565 
566   if (RC == ARM::GPRRegisterClass) {
567     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
568                    .addFrameIndex(FI).addReg(0).addImm(0));
569   } else if (RC == ARM::DPRRegisterClass) {
570     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
571                    .addFrameIndex(FI).addImm(0));
572   } else {
573     assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
574     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
575                    .addFrameIndex(FI).addImm(0));
576   }
577 }
578 
579 void ARMInstrInfo::
580 loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
581                 SmallVectorImpl<MachineOperand> &Addr,
582                 const TargetRegisterClass *RC,
583                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
584   DebugLoc DL = DebugLoc::getUnknownLoc();
585   unsigned Opc = 0;
586   if (RC == ARM::GPRRegisterClass) {
587     Opc = ARM::LDR;
588   } else if (RC == ARM::DPRRegisterClass) {
589     Opc = ARM::FLDD;
590   } else {
591     assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
592     Opc = ARM::FLDS;
593   }
594 
595   MachineInstrBuilder MIB =  BuildMI(MF, DL, get(Opc), DestReg);
596   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
597     MIB.addOperand(Addr[i]);
598   AddDefaultPred(MIB);
599   NewMIs.push_back(MIB);
600   return;
601 }
602 
603 MachineInstr *ARMInstrInfo::
604 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
605                       const SmallVectorImpl<unsigned> &Ops, int FI) const {
606   if (Ops.size() != 1) return NULL;
607 
608   unsigned OpNum = Ops[0];
609   unsigned Opc = MI->getOpcode();
610   MachineInstr *NewMI = NULL;
611   switch (Opc) {
612   default: break;
613   case ARM::MOVr: {
614     if (MI->getOperand(4).getReg() == ARM::CPSR)
615       // If it is updating CPSR, then it cannot be folded.
616       break;
617     unsigned Pred = MI->getOperand(2).getImm();
618     unsigned PredReg = MI->getOperand(3).getReg();
619     if (OpNum == 0) { // move -> store
620       unsigned SrcReg = MI->getOperand(1).getReg();
621       bool isKill = MI->getOperand(1).isKill();
622       bool isUndef = MI->getOperand(1).isUndef();
623       NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
624         .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
625         .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
626     } else {          // move -> load
627       unsigned DstReg = MI->getOperand(0).getReg();
628       bool isDead = MI->getOperand(0).isDead();
629       bool isUndef = MI->getOperand(0).isUndef();
630       NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
631         .addReg(DstReg,
632                 RegState::Define |
633                 getDeadRegState(isDead) |
634                 getUndefRegState(isUndef))
635         .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
636     }
637     break;
638   }
639   case ARM::FCPYS: {
640     unsigned Pred = MI->getOperand(2).getImm();
641     unsigned PredReg = MI->getOperand(3).getReg();
642     if (OpNum == 0) { // move -> store
643       unsigned SrcReg = MI->getOperand(1).getReg();
644       bool isKill = MI->getOperand(1).isKill();
645       bool isUndef = MI->getOperand(1).isUndef();
646       NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
647         .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
648         .addFrameIndex(FI)
649         .addImm(0).addImm(Pred).addReg(PredReg);
650     } else {          // move -> load
651       unsigned DstReg = MI->getOperand(0).getReg();
652       bool isDead = MI->getOperand(0).isDead();
653       bool isUndef = MI->getOperand(0).isUndef();
654       NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS))
655         .addReg(DstReg,
656                 RegState::Define |
657                 getDeadRegState(isDead) |
658                 getUndefRegState(isUndef))
659         .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
660     }
661     break;
662   }
663   case ARM::FCPYD: {
664     unsigned Pred = MI->getOperand(2).getImm();
665     unsigned PredReg = MI->getOperand(3).getReg();
666     if (OpNum == 0) { // move -> store
667       unsigned SrcReg = MI->getOperand(1).getReg();
668       bool isKill = MI->getOperand(1).isKill();
669       bool isUndef = MI->getOperand(1).isUndef();
670       NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
671         .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
672         .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
673     } else {          // move -> load
674       unsigned DstReg = MI->getOperand(0).getReg();
675       bool isDead = MI->getOperand(0).isDead();
676       bool isUndef = MI->getOperand(0).isUndef();
677       NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
678         .addReg(DstReg,
679                 RegState::Define |
680                 getDeadRegState(isDead) |
681                 getUndefRegState(isUndef))
682         .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
683     }
684     break;
685   }
686   }
687 
688   return NewMI;
689 }
690 
691 bool
692 ARMInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
693                                    const SmallVectorImpl<unsigned> &Ops) const {
694   if (Ops.size() != 1) return false;
695 
696   unsigned Opc = MI->getOpcode();
697   switch (Opc) {
698   default: break;
699   case ARM::MOVr:
700     // If it is updating CPSR, then it cannot be folded.
701     return MI->getOperand(4).getReg() != ARM::CPSR;
702   case ARM::FCPYS:
703   case ARM::FCPYD:
704     return true;
705 
706   case ARM::VMOVD:
707   case ARM::VMOVQ:
708     return false; // FIXME
709   }
710 
711   return false;
712 }
713 
714 bool
715 ARMBaseInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
716   if (MBB.empty()) return false;
717 
718   switch (MBB.back().getOpcode()) {
719   case ARM::BX_RET:   // Return.
720   case ARM::LDM_RET:
721   case ARM::tBX_RET:
722   case ARM::tBX_RET_vararg:
723   case ARM::tPOP_RET:
724   case ARM::B:
725   case ARM::tB:
726   case ARM::t2B:      // Uncond branch.
727   case ARM::tBR_JTr:
728   case ARM::t2BR_JTr:
729   case ARM::BR_JTr:   // Jumptable branch.
730   case ARM::t2BR_JTm:
731   case ARM::BR_JTm:   // Jumptable branch through mem.
732   case ARM::t2BR_JTadd:
733   case ARM::BR_JTadd: // Jumptable branch add to pc.
734     return true;
735   default: return false;
736   }
737 }
738 
739 bool ARMBaseInstrInfo::
740 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
741   ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
742   Cond[0].setImm(ARMCC::getOppositeCondition(CC));
743   return false;
744 }
745 
746 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
747   int PIdx = MI->findFirstPredOperandIdx();
748   return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
749 }
750 
751 bool ARMBaseInstrInfo::
752 PredicateInstruction(MachineInstr *MI,
753                      const SmallVectorImpl<MachineOperand> &Pred) const {
754   unsigned Opc = MI->getOpcode();
755   if (Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B) {
756     MI->setDesc(get((Opc == ARM::B) ? ARM::Bcc :
757                     ((Opc == ARM::tB) ? ARM::tBcc : ARM::t2Bcc)));
758     MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
759     MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
760     return true;
761   }
762 
763   int PIdx = MI->findFirstPredOperandIdx();
764   if (PIdx != -1) {
765     MachineOperand &PMO = MI->getOperand(PIdx);
766     PMO.setImm(Pred[0].getImm());
767     MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
768     return true;
769   }
770   return false;
771 }
772 
773 bool ARMBaseInstrInfo::
774 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
775                   const SmallVectorImpl<MachineOperand> &Pred2) const {
776   if (Pred1.size() > 2 || Pred2.size() > 2)
777     return false;
778 
779   ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
780   ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
781   if (CC1 == CC2)
782     return true;
783 
784   switch (CC1) {
785   default:
786     return false;
787   case ARMCC::AL:
788     return true;
789   case ARMCC::HS:
790     return CC2 == ARMCC::HI;
791   case ARMCC::LS:
792     return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
793   case ARMCC::GE:
794     return CC2 == ARMCC::GT;
795   case ARMCC::LE:
796     return CC2 == ARMCC::LT;
797   }
798 }
799 
800 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
801                                     std::vector<MachineOperand> &Pred) const {
802   const TargetInstrDesc &TID = MI->getDesc();
803   if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
804     return false;
805 
806   bool Found = false;
807   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
808     const MachineOperand &MO = MI->getOperand(i);
809     if (MO.isReg() && MO.getReg() == ARM::CPSR) {
810       Pred.push_back(MO);
811       Found = true;
812     }
813   }
814 
815   return Found;
816 }
817 
818 
819 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
820 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
821                                 unsigned JTI) DISABLE_INLINE;
822 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
823                                 unsigned JTI) {
824   return JT[JTI].MBBs.size();
825 }
826 
827 /// GetInstSize - Return the size of the specified MachineInstr.
828 ///
829 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
830   const MachineBasicBlock &MBB = *MI->getParent();
831   const MachineFunction *MF = MBB.getParent();
832   const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
833 
834   // Basic size info comes from the TSFlags field.
835   const TargetInstrDesc &TID = MI->getDesc();
836   unsigned TSFlags = TID.TSFlags;
837 
838   switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
839   default: {
840     // If this machine instr is an inline asm, measure it.
841     if (MI->getOpcode() == ARM::INLINEASM)
842       return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
843     if (MI->isLabel())
844       return 0;
845     switch (MI->getOpcode()) {
846     default:
847       assert(0 && "Unknown or unset size field for instr!");
848       break;
849     case TargetInstrInfo::IMPLICIT_DEF:
850     case TargetInstrInfo::DECLARE:
851     case TargetInstrInfo::DBG_LABEL:
852     case TargetInstrInfo::EH_LABEL:
853       return 0;
854     }
855     break;
856   }
857   case ARMII::Size8Bytes: return 8;          // Arm instruction x 2.
858   case ARMII::Size4Bytes: return 4;          // Arm instruction.
859   case ARMII::Size2Bytes: return 2;          // Thumb instruction.
860   case ARMII::SizeSpecial: {
861     switch (MI->getOpcode()) {
862     case ARM::CONSTPOOL_ENTRY:
863       // If this machine instr is a constant pool entry, its size is recorded as
864       // operand #2.
865       return MI->getOperand(2).getImm();
866     case ARM::Int_eh_sjlj_setjmp: return 12;
867     case ARM::BR_JTr:
868     case ARM::BR_JTm:
869     case ARM::BR_JTadd:
870     case ARM::t2BR_JTr:
871     case ARM::t2BR_JTm:
872     case ARM::t2BR_JTadd:
873     case ARM::tBR_JTr: {
874       // These are jumptable branches, i.e. a branch followed by an inlined
875       // jumptable. The size is 4 + 4 * number of entries.
876       unsigned NumOps = TID.getNumOperands();
877       MachineOperand JTOP =
878         MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
879       unsigned JTI = JTOP.getIndex();
880       const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
881       const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
882       assert(JTI < JT.size());
883       // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
884       // 4 aligned. The assembler / linker may add 2 byte padding just before
885       // the JT entries.  The size does not include this padding; the
886       // constant islands pass does separate bookkeeping for it.
887       // FIXME: If we know the size of the function is less than (1 << 16) *2
888       // bytes, we can use 16-bit entries instead. Then there won't be an
889       // alignment issue.
890       return getNumJTEntries(JT, JTI) * 4 +
891         ((MI->getOpcode()==ARM::tBR_JTr) ? 2 : 4);
892     }
893     default:
894       // Otherwise, pseudo-instruction sizes are zero.
895       return 0;
896     }
897   }
898   }
899   return 0; // Not reached
900 }
901