1 //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the ARM implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMInstrInfo.h"
15 #include "ARM.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/Target/TargetAsmInfo.h"
25 #include "llvm/Support/CommandLine.h"
26 using namespace llvm;
27 
28 static cl::opt<bool>
29 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
30                cl::desc("Enable ARM 2-addr to 3-addr conv"));
31 
32 static inline
33 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
34   return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
35 }
36 
37 static inline
38 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
39   return MIB.addReg(0);
40 }
41 
42 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
43   : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
44     RI(*this, STI) {
45 }
46 
47 
48 /// Return true if the instruction is a register to register move and
49 /// leave the source and dest operands in the passed parameters.
50 ///
51 bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
52                                unsigned &SrcReg, unsigned &DstReg,
53                                unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
54   SrcSubIdx = DstSubIdx = 0; // No sub-registers.
55 
56   unsigned oc = MI.getOpcode();
57   switch (oc) {
58   default:
59     return false;
60   case ARM::FCPYS:
61   case ARM::FCPYD:
62     SrcReg = MI.getOperand(1).getReg();
63     DstReg = MI.getOperand(0).getReg();
64     return true;
65   case ARM::MOVr:
66   case ARM::tMOVr:
67   case ARM::tMOVhir2lor:
68   case ARM::tMOVlor2hir:
69   case ARM::tMOVhir2hir:
70     assert(MI.getDesc().getNumOperands() >= 2 &&
71            MI.getOperand(0).isReg() &&
72            MI.getOperand(1).isReg() &&
73            "Invalid ARM MOV instruction");
74     SrcReg = MI.getOperand(1).getReg();
75     DstReg = MI.getOperand(0).getReg();
76     return true;
77   }
78 }
79 
80 unsigned ARMInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
81                                            int &FrameIndex) const {
82   switch (MI->getOpcode()) {
83   default: break;
84   case ARM::LDR:
85     if (MI->getOperand(1).isFI() &&
86         MI->getOperand(2).isReg() &&
87         MI->getOperand(3).isImm() &&
88         MI->getOperand(2).getReg() == 0 &&
89         MI->getOperand(3).getImm() == 0) {
90       FrameIndex = MI->getOperand(1).getIndex();
91       return MI->getOperand(0).getReg();
92     }
93     break;
94   case ARM::FLDD:
95   case ARM::FLDS:
96     if (MI->getOperand(1).isFI() &&
97         MI->getOperand(2).isImm() &&
98         MI->getOperand(2).getImm() == 0) {
99       FrameIndex = MI->getOperand(1).getIndex();
100       return MI->getOperand(0).getReg();
101     }
102     break;
103   case ARM::tRestore:
104     if (MI->getOperand(1).isFI() &&
105         MI->getOperand(2).isImm() &&
106         MI->getOperand(2).getImm() == 0) {
107       FrameIndex = MI->getOperand(1).getIndex();
108       return MI->getOperand(0).getReg();
109     }
110     break;
111   }
112   return 0;
113 }
114 
115 unsigned ARMInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
116                                           int &FrameIndex) const {
117   switch (MI->getOpcode()) {
118   default: break;
119   case ARM::STR:
120     if (MI->getOperand(1).isFI() &&
121         MI->getOperand(2).isReg() &&
122         MI->getOperand(3).isImm() &&
123         MI->getOperand(2).getReg() == 0 &&
124         MI->getOperand(3).getImm() == 0) {
125       FrameIndex = MI->getOperand(1).getIndex();
126       return MI->getOperand(0).getReg();
127     }
128     break;
129   case ARM::FSTD:
130   case ARM::FSTS:
131     if (MI->getOperand(1).isFI() &&
132         MI->getOperand(2).isImm() &&
133         MI->getOperand(2).getImm() == 0) {
134       FrameIndex = MI->getOperand(1).getIndex();
135       return MI->getOperand(0).getReg();
136     }
137     break;
138   case ARM::tSpill:
139     if (MI->getOperand(1).isFI() &&
140         MI->getOperand(2).isImm() &&
141         MI->getOperand(2).getImm() == 0) {
142       FrameIndex = MI->getOperand(1).getIndex();
143       return MI->getOperand(0).getReg();
144     }
145     break;
146   }
147   return 0;
148 }
149 
150 void ARMInstrInfo::reMaterialize(MachineBasicBlock &MBB,
151                                  MachineBasicBlock::iterator I,
152                                  unsigned DestReg,
153                                  const MachineInstr *Orig) const {
154   DebugLoc dl = Orig->getDebugLoc();
155   if (Orig->getOpcode() == ARM::MOVi2pieces) {
156     RI.emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImm(),
157                          Orig->getOperand(2).getImm(),
158                          Orig->getOperand(3).getReg(), this, false, dl);
159     return;
160   }
161 
162   MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
163   MI->getOperand(0).setReg(DestReg);
164   MBB.insert(I, MI);
165 }
166 
167 static unsigned getUnindexedOpcode(unsigned Opc) {
168   switch (Opc) {
169   default: break;
170   case ARM::LDR_PRE:
171   case ARM::LDR_POST:
172     return ARM::LDR;
173   case ARM::LDRH_PRE:
174   case ARM::LDRH_POST:
175     return ARM::LDRH;
176   case ARM::LDRB_PRE:
177   case ARM::LDRB_POST:
178     return ARM::LDRB;
179   case ARM::LDRSH_PRE:
180   case ARM::LDRSH_POST:
181     return ARM::LDRSH;
182   case ARM::LDRSB_PRE:
183   case ARM::LDRSB_POST:
184     return ARM::LDRSB;
185   case ARM::STR_PRE:
186   case ARM::STR_POST:
187     return ARM::STR;
188   case ARM::STRH_PRE:
189   case ARM::STRH_POST:
190     return ARM::STRH;
191   case ARM::STRB_PRE:
192   case ARM::STRB_POST:
193     return ARM::STRB;
194   }
195   return 0;
196 }
197 
198 MachineInstr *
199 ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
200                                     MachineBasicBlock::iterator &MBBI,
201                                     LiveVariables *LV) const {
202   if (!EnableARM3Addr)
203     return NULL;
204 
205   MachineInstr *MI = MBBI;
206   MachineFunction &MF = *MI->getParent()->getParent();
207   unsigned TSFlags = MI->getDesc().TSFlags;
208   bool isPre = false;
209   switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
210   default: return NULL;
211   case ARMII::IndexModePre:
212     isPre = true;
213     break;
214   case ARMII::IndexModePost:
215     break;
216   }
217 
218   // Try splitting an indexed load/store to an un-indexed one plus an add/sub
219   // operation.
220   unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
221   if (MemOpc == 0)
222     return NULL;
223 
224   MachineInstr *UpdateMI = NULL;
225   MachineInstr *MemMI = NULL;
226   unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
227   const TargetInstrDesc &TID = MI->getDesc();
228   unsigned NumOps = TID.getNumOperands();
229   bool isLoad = !TID.mayStore();
230   const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
231   const MachineOperand &Base = MI->getOperand(2);
232   const MachineOperand &Offset = MI->getOperand(NumOps-3);
233   unsigned WBReg = WB.getReg();
234   unsigned BaseReg = Base.getReg();
235   unsigned OffReg = Offset.getReg();
236   unsigned OffImm = MI->getOperand(NumOps-2).getImm();
237   ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
238   switch (AddrMode) {
239   default:
240     assert(false && "Unknown indexed op!");
241     return NULL;
242   case ARMII::AddrMode2: {
243     bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
244     unsigned Amt = ARM_AM::getAM2Offset(OffImm);
245     if (OffReg == 0) {
246       int SOImmVal = ARM_AM::getSOImmVal(Amt);
247       if (SOImmVal == -1)
248         // Can't encode it in a so_imm operand. This transformation will
249         // add more than 1 instruction. Abandon!
250         return NULL;
251       UpdateMI = BuildMI(MF, MI->getDebugLoc(),
252                          get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
253         .addReg(BaseReg).addImm(SOImmVal)
254         .addImm(Pred).addReg(0).addReg(0);
255     } else if (Amt != 0) {
256       ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
257       unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
258       UpdateMI = BuildMI(MF, MI->getDebugLoc(),
259                          get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
260         .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
261         .addImm(Pred).addReg(0).addReg(0);
262     } else
263       UpdateMI = BuildMI(MF, MI->getDebugLoc(),
264                          get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
265         .addReg(BaseReg).addReg(OffReg)
266         .addImm(Pred).addReg(0).addReg(0);
267     break;
268   }
269   case ARMII::AddrMode3 : {
270     bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
271     unsigned Amt = ARM_AM::getAM3Offset(OffImm);
272     if (OffReg == 0)
273       // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
274       UpdateMI = BuildMI(MF, MI->getDebugLoc(),
275                          get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
276         .addReg(BaseReg).addImm(Amt)
277         .addImm(Pred).addReg(0).addReg(0);
278     else
279       UpdateMI = BuildMI(MF, MI->getDebugLoc(),
280                          get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
281         .addReg(BaseReg).addReg(OffReg)
282         .addImm(Pred).addReg(0).addReg(0);
283     break;
284   }
285   }
286 
287   std::vector<MachineInstr*> NewMIs;
288   if (isPre) {
289     if (isLoad)
290       MemMI = BuildMI(MF, MI->getDebugLoc(),
291                       get(MemOpc), MI->getOperand(0).getReg())
292         .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
293     else
294       MemMI = BuildMI(MF, MI->getDebugLoc(),
295                       get(MemOpc)).addReg(MI->getOperand(1).getReg())
296         .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
297     NewMIs.push_back(MemMI);
298     NewMIs.push_back(UpdateMI);
299   } else {
300     if (isLoad)
301       MemMI = BuildMI(MF, MI->getDebugLoc(),
302                       get(MemOpc), MI->getOperand(0).getReg())
303         .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
304     else
305       MemMI = BuildMI(MF, MI->getDebugLoc(),
306                       get(MemOpc)).addReg(MI->getOperand(1).getReg())
307         .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
308     if (WB.isDead())
309       UpdateMI->getOperand(0).setIsDead();
310     NewMIs.push_back(UpdateMI);
311     NewMIs.push_back(MemMI);
312   }
313 
314   // Transfer LiveVariables states, kill / dead info.
315   if (LV) {
316     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
317       MachineOperand &MO = MI->getOperand(i);
318       if (MO.isReg() && MO.getReg() &&
319           TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
320         unsigned Reg = MO.getReg();
321 
322         LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
323         if (MO.isDef()) {
324           MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
325           if (MO.isDead())
326             LV->addVirtualRegisterDead(Reg, NewMI);
327         }
328         if (MO.isUse() && MO.isKill()) {
329           for (unsigned j = 0; j < 2; ++j) {
330             // Look at the two new MI's in reverse order.
331             MachineInstr *NewMI = NewMIs[j];
332             if (!NewMI->readsRegister(Reg))
333               continue;
334             LV->addVirtualRegisterKilled(Reg, NewMI);
335             if (VI.removeKill(MI))
336               VI.Kills.push_back(NewMI);
337             break;
338           }
339         }
340       }
341     }
342   }
343 
344   MFI->insert(MBBI, NewMIs[1]);
345   MFI->insert(MBBI, NewMIs[0]);
346   return NewMIs[0];
347 }
348 
349 // Branch analysis.
350 bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
351                                  MachineBasicBlock *&FBB,
352                                  SmallVectorImpl<MachineOperand> &Cond,
353                                  bool AllowModify) const {
354   // If the block has no terminators, it just falls into the block after it.
355   MachineBasicBlock::iterator I = MBB.end();
356   if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
357     return false;
358 
359   // Get the last instruction in the block.
360   MachineInstr *LastInst = I;
361 
362   // If there is only one terminator instruction, process it.
363   unsigned LastOpc = LastInst->getOpcode();
364   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
365     if (LastOpc == ARM::B || LastOpc == ARM::tB) {
366       TBB = LastInst->getOperand(0).getMBB();
367       return false;
368     }
369     if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
370       // Block ends with fall-through condbranch.
371       TBB = LastInst->getOperand(0).getMBB();
372       Cond.push_back(LastInst->getOperand(1));
373       Cond.push_back(LastInst->getOperand(2));
374       return false;
375     }
376     return true;  // Can't handle indirect branch.
377   }
378 
379   // Get the instruction before it if it is a terminator.
380   MachineInstr *SecondLastInst = I;
381 
382   // If there are three terminators, we don't know what sort of block this is.
383   if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
384     return true;
385 
386   // If the block ends with ARM::B/ARM::tB and a ARM::Bcc/ARM::tBcc, handle it.
387   unsigned SecondLastOpc = SecondLastInst->getOpcode();
388   if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
389       (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
390     TBB =  SecondLastInst->getOperand(0).getMBB();
391     Cond.push_back(SecondLastInst->getOperand(1));
392     Cond.push_back(SecondLastInst->getOperand(2));
393     FBB = LastInst->getOperand(0).getMBB();
394     return false;
395   }
396 
397   // If the block ends with two unconditional branches, handle it.  The second
398   // one is not executed, so remove it.
399   if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB) &&
400       (LastOpc == ARM::B || LastOpc == ARM::tB)) {
401     TBB = SecondLastInst->getOperand(0).getMBB();
402     I = LastInst;
403     if (AllowModify)
404       I->eraseFromParent();
405     return false;
406   }
407 
408   // ...likewise if it ends with a branch table followed by an unconditional
409   // branch. The branch folder can create these, and we must get rid of them for
410   // correctness of Thumb constant islands.
411   if ((SecondLastOpc == ARM::BR_JTr || SecondLastOpc==ARM::BR_JTm ||
412        SecondLastOpc == ARM::BR_JTadd || SecondLastOpc==ARM::tBR_JTr) &&
413       (LastOpc == ARM::B || LastOpc == ARM::tB)) {
414     I = LastInst;
415     if (AllowModify)
416       I->eraseFromParent();
417     return true;
418   }
419 
420   // Otherwise, can't handle this.
421   return true;
422 }
423 
424 
425 unsigned ARMInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
426   MachineFunction &MF = *MBB.getParent();
427   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
428   int BOpc   = AFI->isThumbFunction() ? ARM::tB : ARM::B;
429   int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
430 
431   MachineBasicBlock::iterator I = MBB.end();
432   if (I == MBB.begin()) return 0;
433   --I;
434   if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc)
435     return 0;
436 
437   // Remove the branch.
438   I->eraseFromParent();
439 
440   I = MBB.end();
441 
442   if (I == MBB.begin()) return 1;
443   --I;
444   if (I->getOpcode() != BccOpc)
445     return 1;
446 
447   // Remove the branch.
448   I->eraseFromParent();
449   return 2;
450 }
451 
452 unsigned
453 ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
454                            MachineBasicBlock *FBB,
455                            const SmallVectorImpl<MachineOperand> &Cond) const {
456   // FIXME this should probably have a DebugLoc argument
457   DebugLoc dl = DebugLoc::getUnknownLoc();
458   MachineFunction &MF = *MBB.getParent();
459   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
460   int BOpc   = AFI->isThumbFunction() ? ARM::tB : ARM::B;
461   int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
462 
463   // Shouldn't be a fall through.
464   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
465   assert((Cond.size() == 2 || Cond.size() == 0) &&
466          "ARM branch conditions have two components!");
467 
468   if (FBB == 0) {
469     if (Cond.empty()) // Unconditional branch?
470       BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
471     else
472       BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
473         .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
474     return 1;
475   }
476 
477   // Two-way conditional branch.
478   BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
479     .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
480   BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
481   return 2;
482 }
483 
484 bool ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
485                                 MachineBasicBlock::iterator I,
486                                 unsigned DestReg, unsigned SrcReg,
487                                 const TargetRegisterClass *DestRC,
488                                 const TargetRegisterClass *SrcRC) const {
489   MachineFunction &MF = *MBB.getParent();
490   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
491   DebugLoc DL = DebugLoc::getUnknownLoc();
492   if (I != MBB.end()) DL = I->getDebugLoc();
493 
494   if (!AFI->isThumbFunction()) {
495     if (DestRC == ARM::GPRRegisterClass) {
496       AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
497                                   .addReg(SrcReg)));
498       return true;
499     }
500   } else {
501     if (DestRC == ARM::GPRRegisterClass) {
502       if (SrcRC == ARM::GPRRegisterClass) {
503         BuildMI(MBB, I, DL, get(ARM::tMOVhir2hir), DestReg).addReg(SrcReg);
504         return true;
505       } else if (SrcRC == ARM::tGPRRegisterClass) {
506         BuildMI(MBB, I, DL, get(ARM::tMOVlor2hir), DestReg).addReg(SrcReg);
507         return true;
508       }
509     } else if (DestRC == ARM::tGPRRegisterClass) {
510       if (SrcRC == ARM::GPRRegisterClass) {
511         BuildMI(MBB, I, DL, get(ARM::tMOVhir2lor), DestReg).addReg(SrcReg);
512         return true;
513       } else if (SrcRC == ARM::tGPRRegisterClass) {
514         BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
515         return true;
516       }
517     }
518   }
519   if (DestRC != SrcRC) {
520     // Not yet supported!
521     return false;
522   }
523 
524 
525   if (DestRC == ARM::SPRRegisterClass)
526     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
527                    .addReg(SrcReg));
528   else if (DestRC == ARM::DPRRegisterClass)
529     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
530                    .addReg(SrcReg));
531   else
532     return false;
533 
534   return true;
535 }
536 
537 void ARMInstrInfo::
538 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
539                     unsigned SrcReg, bool isKill, int FI,
540                     const TargetRegisterClass *RC) const {
541   DebugLoc DL = DebugLoc::getUnknownLoc();
542   if (I != MBB.end()) DL = I->getDebugLoc();
543 
544   if (RC == ARM::GPRRegisterClass) {
545     MachineFunction &MF = *MBB.getParent();
546     ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
547     assert (!AFI->isThumbFunction());
548     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
549                    .addReg(SrcReg, getKillRegState(isKill))
550                    .addFrameIndex(FI).addReg(0).addImm(0));
551   } else if (RC == ARM::tGPRRegisterClass) {
552     MachineFunction &MF = *MBB.getParent();
553     ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
554     assert (AFI->isThumbFunction());
555     BuildMI(MBB, I, DL, get(ARM::tSpill))
556       .addReg(SrcReg, getKillRegState(isKill))
557       .addFrameIndex(FI).addImm(0);
558   } else if (RC == ARM::DPRRegisterClass) {
559     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
560                    .addReg(SrcReg, getKillRegState(isKill))
561                    .addFrameIndex(FI).addImm(0));
562   } else {
563     assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
564     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
565                    .addReg(SrcReg, getKillRegState(isKill))
566                    .addFrameIndex(FI).addImm(0));
567   }
568 }
569 
570 void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
571                                   bool isKill,
572                                   SmallVectorImpl<MachineOperand> &Addr,
573                                   const TargetRegisterClass *RC,
574                                   SmallVectorImpl<MachineInstr*> &NewMIs) const{
575   DebugLoc DL = DebugLoc::getUnknownLoc();
576   unsigned Opc = 0;
577   if (RC == ARM::GPRRegisterClass) {
578     ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
579     if (AFI->isThumbFunction()) {
580       Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR;
581       MachineInstrBuilder MIB =
582         BuildMI(MF, DL,  get(Opc)).addReg(SrcReg, getKillRegState(isKill));
583       for (unsigned i = 0, e = Addr.size(); i != e; ++i)
584         MIB.addOperand(Addr[i]);
585       NewMIs.push_back(MIB);
586       return;
587     }
588     Opc = ARM::STR;
589   } else if (RC == ARM::DPRRegisterClass) {
590     Opc = ARM::FSTD;
591   } else {
592     assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
593     Opc = ARM::FSTS;
594   }
595 
596   MachineInstrBuilder MIB =
597     BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
598   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
599     MIB.addOperand(Addr[i]);
600   AddDefaultPred(MIB);
601   NewMIs.push_back(MIB);
602   return;
603 }
604 
605 void ARMInstrInfo::
606 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
607                      unsigned DestReg, int FI,
608                      const TargetRegisterClass *RC) const {
609   DebugLoc DL = DebugLoc::getUnknownLoc();
610   if (I != MBB.end()) DL = I->getDebugLoc();
611 
612   if (RC == ARM::GPRRegisterClass) {
613     MachineFunction &MF = *MBB.getParent();
614     ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
615     assert (!AFI->isThumbFunction());
616     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
617                    .addFrameIndex(FI).addReg(0).addImm(0));
618   } else if (RC == ARM::tGPRRegisterClass) {
619     MachineFunction &MF = *MBB.getParent();
620     ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
621     assert (AFI->isThumbFunction());
622     BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
623       .addFrameIndex(FI).addImm(0);
624   } else if (RC == ARM::DPRRegisterClass) {
625     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
626                    .addFrameIndex(FI).addImm(0));
627   } else {
628     assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
629     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
630                    .addFrameIndex(FI).addImm(0));
631   }
632 }
633 
634 void ARMInstrInfo::
635 loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
636                 SmallVectorImpl<MachineOperand> &Addr,
637                 const TargetRegisterClass *RC,
638                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
639   DebugLoc DL = DebugLoc::getUnknownLoc();
640   unsigned Opc = 0;
641   if (RC == ARM::GPRRegisterClass) {
642     ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
643     if (AFI->isThumbFunction()) {
644       Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR;
645       MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
646       for (unsigned i = 0, e = Addr.size(); i != e; ++i)
647         MIB.addOperand(Addr[i]);
648       NewMIs.push_back(MIB);
649       return;
650     }
651     Opc = ARM::LDR;
652   } else if (RC == ARM::DPRRegisterClass) {
653     Opc = ARM::FLDD;
654   } else {
655     assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
656     Opc = ARM::FLDS;
657   }
658 
659   MachineInstrBuilder MIB =  BuildMI(MF, DL, get(Opc), DestReg);
660   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
661     MIB.addOperand(Addr[i]);
662   AddDefaultPred(MIB);
663   NewMIs.push_back(MIB);
664   return;
665 }
666 
667 bool ARMInstrInfo::
668 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
669                           MachineBasicBlock::iterator MI,
670                           const std::vector<CalleeSavedInfo> &CSI) const {
671   MachineFunction &MF = *MBB.getParent();
672   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
673   if (!AFI->isThumbFunction() || CSI.empty())
674     return false;
675 
676   DebugLoc DL = DebugLoc::getUnknownLoc();
677   if (MI != MBB.end()) DL = MI->getDebugLoc();
678 
679   MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
680   for (unsigned i = CSI.size(); i != 0; --i) {
681     unsigned Reg = CSI[i-1].getReg();
682     // Add the callee-saved register as live-in. It's killed at the spill.
683     MBB.addLiveIn(Reg);
684     MIB.addReg(Reg, RegState::Kill);
685   }
686   return true;
687 }
688 
689 bool ARMInstrInfo::
690 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
691                             MachineBasicBlock::iterator MI,
692                             const std::vector<CalleeSavedInfo> &CSI) const {
693   MachineFunction &MF = *MBB.getParent();
694   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
695   if (!AFI->isThumbFunction() || CSI.empty())
696     return false;
697 
698   bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
699   MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc());
700   MBB.insert(MI, PopMI);
701   for (unsigned i = CSI.size(); i != 0; --i) {
702     unsigned Reg = CSI[i-1].getReg();
703     if (Reg == ARM::LR) {
704       // Special epilogue for vararg functions. See emitEpilogue
705       if (isVarArg)
706         continue;
707       Reg = ARM::PC;
708       PopMI->setDesc(get(ARM::tPOP_RET));
709       MBB.erase(MI);
710     }
711     PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
712   }
713   return true;
714 }
715 
716 MachineInstr *ARMInstrInfo::
717 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
718                       const SmallVectorImpl<unsigned> &Ops, int FI) const {
719   if (Ops.size() != 1) return NULL;
720 
721   unsigned OpNum = Ops[0];
722   unsigned Opc = MI->getOpcode();
723   MachineInstr *NewMI = NULL;
724   switch (Opc) {
725   default: break;
726   case ARM::MOVr: {
727     if (MI->getOperand(4).getReg() == ARM::CPSR)
728       // If it is updating CPSR, then it cannot be folded.
729       break;
730     unsigned Pred = MI->getOperand(2).getImm();
731     unsigned PredReg = MI->getOperand(3).getReg();
732     if (OpNum == 0) { // move -> store
733       unsigned SrcReg = MI->getOperand(1).getReg();
734       bool isKill = MI->getOperand(1).isKill();
735       NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
736         .addReg(SrcReg, getKillRegState(isKill))
737         .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
738     } else {          // move -> load
739       unsigned DstReg = MI->getOperand(0).getReg();
740       bool isDead = MI->getOperand(0).isDead();
741       NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
742         .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
743         .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
744     }
745     break;
746   }
747   case ARM::tMOVr:
748   case ARM::tMOVlor2hir:
749   case ARM::tMOVhir2lor:
750   case ARM::tMOVhir2hir: {
751     if (OpNum == 0) { // move -> store
752       unsigned SrcReg = MI->getOperand(1).getReg();
753       bool isKill = MI->getOperand(1).isKill();
754       if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
755         // tSpill cannot take a high register operand.
756         break;
757       NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
758         .addReg(SrcReg, getKillRegState(isKill))
759         .addFrameIndex(FI).addImm(0);
760     } else {          // move -> load
761       unsigned DstReg = MI->getOperand(0).getReg();
762       if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
763         // tRestore cannot target a high register operand.
764         break;
765       bool isDead = MI->getOperand(0).isDead();
766       NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
767         .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
768         .addFrameIndex(FI).addImm(0);
769     }
770     break;
771   }
772   case ARM::FCPYS: {
773     unsigned Pred = MI->getOperand(2).getImm();
774     unsigned PredReg = MI->getOperand(3).getReg();
775     if (OpNum == 0) { // move -> store
776       unsigned SrcReg = MI->getOperand(1).getReg();
777       NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
778         .addReg(SrcReg).addFrameIndex(FI)
779         .addImm(0).addImm(Pred).addReg(PredReg);
780     } else {          // move -> load
781       unsigned DstReg = MI->getOperand(0).getReg();
782       NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS), DstReg)
783         .addFrameIndex(FI)
784         .addImm(0).addImm(Pred).addReg(PredReg);
785     }
786     break;
787   }
788   case ARM::FCPYD: {
789     unsigned Pred = MI->getOperand(2).getImm();
790     unsigned PredReg = MI->getOperand(3).getReg();
791     if (OpNum == 0) { // move -> store
792       unsigned SrcReg = MI->getOperand(1).getReg();
793       bool isKill = MI->getOperand(1).isKill();
794       NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
795         .addReg(SrcReg, getKillRegState(isKill))
796         .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
797     } else {          // move -> load
798       unsigned DstReg = MI->getOperand(0).getReg();
799       bool isDead = MI->getOperand(0).isDead();
800       NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
801         .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
802         .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
803     }
804     break;
805   }
806   }
807 
808   return NewMI;
809 }
810 
811 bool ARMInstrInfo::
812 canFoldMemoryOperand(const MachineInstr *MI,
813                      const SmallVectorImpl<unsigned> &Ops) const {
814   if (Ops.size() != 1) return false;
815 
816   unsigned OpNum = Ops[0];
817   unsigned Opc = MI->getOpcode();
818   switch (Opc) {
819   default: break;
820   case ARM::MOVr:
821     // If it is updating CPSR, then it cannot be folded.
822     return MI->getOperand(4).getReg() != ARM::CPSR;
823   case ARM::tMOVr:
824   case ARM::tMOVlor2hir:
825   case ARM::tMOVhir2lor:
826   case ARM::tMOVhir2hir: {
827     if (OpNum == 0) { // move -> store
828       unsigned SrcReg = MI->getOperand(1).getReg();
829       if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
830         // tSpill cannot take a high register operand.
831         return false;
832     } else {          // move -> load
833       unsigned DstReg = MI->getOperand(0).getReg();
834       if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
835         // tRestore cannot target a high register operand.
836         return false;
837     }
838     return true;
839   }
840   case ARM::FCPYS:
841   case ARM::FCPYD:
842     return true;
843   }
844 
845   return false;
846 }
847 
848 bool ARMInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
849   if (MBB.empty()) return false;
850 
851   switch (MBB.back().getOpcode()) {
852   case ARM::BX_RET:   // Return.
853   case ARM::LDM_RET:
854   case ARM::tBX_RET:
855   case ARM::tBX_RET_vararg:
856   case ARM::tPOP_RET:
857   case ARM::B:
858   case ARM::tB:       // Uncond branch.
859   case ARM::tBR_JTr:
860   case ARM::BR_JTr:   // Jumptable branch.
861   case ARM::BR_JTm:   // Jumptable branch through mem.
862   case ARM::BR_JTadd: // Jumptable branch add to pc.
863     return true;
864   default: return false;
865   }
866 }
867 
868 bool ARMInstrInfo::
869 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
870   ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
871   Cond[0].setImm(ARMCC::getOppositeCondition(CC));
872   return false;
873 }
874 
875 bool ARMInstrInfo::isPredicated(const MachineInstr *MI) const {
876   int PIdx = MI->findFirstPredOperandIdx();
877   return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
878 }
879 
880 bool ARMInstrInfo::
881 PredicateInstruction(MachineInstr *MI,
882                      const SmallVectorImpl<MachineOperand> &Pred) const {
883   unsigned Opc = MI->getOpcode();
884   if (Opc == ARM::B || Opc == ARM::tB) {
885     MI->setDesc(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
886     MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
887     MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
888     return true;
889   }
890 
891   int PIdx = MI->findFirstPredOperandIdx();
892   if (PIdx != -1) {
893     MachineOperand &PMO = MI->getOperand(PIdx);
894     PMO.setImm(Pred[0].getImm());
895     MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
896     return true;
897   }
898   return false;
899 }
900 
901 bool ARMInstrInfo::
902 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
903                   const SmallVectorImpl<MachineOperand> &Pred2) const {
904   if (Pred1.size() > 2 || Pred2.size() > 2)
905     return false;
906 
907   ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
908   ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
909   if (CC1 == CC2)
910     return true;
911 
912   switch (CC1) {
913   default:
914     return false;
915   case ARMCC::AL:
916     return true;
917   case ARMCC::HS:
918     return CC2 == ARMCC::HI;
919   case ARMCC::LS:
920     return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
921   case ARMCC::GE:
922     return CC2 == ARMCC::GT;
923   case ARMCC::LE:
924     return CC2 == ARMCC::LT;
925   }
926 }
927 
928 bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
929                                     std::vector<MachineOperand> &Pred) const {
930   const TargetInstrDesc &TID = MI->getDesc();
931   if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
932     return false;
933 
934   bool Found = false;
935   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
936     const MachineOperand &MO = MI->getOperand(i);
937     if (MO.isReg() && MO.getReg() == ARM::CPSR) {
938       Pred.push_back(MO);
939       Found = true;
940     }
941   }
942 
943   return Found;
944 }
945 
946 
947 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
948 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
949                                 unsigned JTI) DISABLE_INLINE;
950 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
951                                 unsigned JTI) {
952   return JT[JTI].MBBs.size();
953 }
954 
955 /// GetInstSize - Return the size of the specified MachineInstr.
956 ///
957 unsigned ARMInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
958   const MachineBasicBlock &MBB = *MI->getParent();
959   const MachineFunction *MF = MBB.getParent();
960   const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
961 
962   // Basic size info comes from the TSFlags field.
963   const TargetInstrDesc &TID = MI->getDesc();
964   unsigned TSFlags = TID.TSFlags;
965 
966   switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
967   default: {
968     // If this machine instr is an inline asm, measure it.
969     if (MI->getOpcode() == ARM::INLINEASM)
970       return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
971     if (MI->isLabel())
972       return 0;
973     switch (MI->getOpcode()) {
974     default:
975       assert(0 && "Unknown or unset size field for instr!");
976       break;
977     case TargetInstrInfo::IMPLICIT_DEF:
978     case TargetInstrInfo::DECLARE:
979     case TargetInstrInfo::DBG_LABEL:
980     case TargetInstrInfo::EH_LABEL:
981       return 0;
982     }
983     break;
984   }
985   case ARMII::Size8Bytes: return 8;          // Arm instruction x 2.
986   case ARMII::Size4Bytes: return 4;          // Arm instruction.
987   case ARMII::Size2Bytes: return 2;          // Thumb instruction.
988   case ARMII::SizeSpecial: {
989     switch (MI->getOpcode()) {
990     case ARM::CONSTPOOL_ENTRY:
991       // If this machine instr is a constant pool entry, its size is recorded as
992       // operand #2.
993       return MI->getOperand(2).getImm();
994     case ARM::Int_eh_sjlj_setjmp: return 12;
995     case ARM::BR_JTr:
996     case ARM::BR_JTm:
997     case ARM::BR_JTadd:
998     case ARM::tBR_JTr: {
999       // These are jumptable branches, i.e. a branch followed by an inlined
1000       // jumptable. The size is 4 + 4 * number of entries.
1001       unsigned NumOps = TID.getNumOperands();
1002       MachineOperand JTOP =
1003         MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
1004       unsigned JTI = JTOP.getIndex();
1005       const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1006       const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1007       assert(JTI < JT.size());
1008       // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
1009       // 4 aligned. The assembler / linker may add 2 byte padding just before
1010       // the JT entries.  The size does not include this padding; the
1011       // constant islands pass does separate bookkeeping for it.
1012       // FIXME: If we know the size of the function is less than (1 << 16) *2
1013       // bytes, we can use 16-bit entries instead. Then there won't be an
1014       // alignment issue.
1015       return getNumJTEntries(JT, JTI) * 4 +
1016              (MI->getOpcode()==ARM::tBR_JTr ? 2 : 4);
1017     }
1018     default:
1019       // Otherwise, pseudo-instruction sizes are zero.
1020       return 0;
1021     }
1022   }
1023   }
1024   return 0; // Not reached
1025 }
1026