1 //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the ARM implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMInstrInfo.h"
15 #include "ARM.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/MC/MCAsmInfo.h"
25 #include "llvm/Support/CommandLine.h"
26 using namespace llvm;
27 
28 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
29   : RI(*this, STI), Subtarget(STI) {
30 }
31 
32 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
33   switch (Opc) {
34   default: break;
35   case ARM::LDR_PRE:
36   case ARM::LDR_POST:
37     return ARM::LDR;
38   case ARM::LDRH_PRE:
39   case ARM::LDRH_POST:
40     return ARM::LDRH;
41   case ARM::LDRB_PRE:
42   case ARM::LDRB_POST:
43     return ARM::LDRB;
44   case ARM::LDRSH_PRE:
45   case ARM::LDRSH_POST:
46     return ARM::LDRSH;
47   case ARM::LDRSB_PRE:
48   case ARM::LDRSB_POST:
49     return ARM::LDRSB;
50   case ARM::STR_PRE:
51   case ARM::STR_POST:
52     return ARM::STR;
53   case ARM::STRH_PRE:
54   case ARM::STRH_POST:
55     return ARM::STRH;
56   case ARM::STRB_PRE:
57   case ARM::STRB_POST:
58     return ARM::STRB;
59   }
60 
61   return 0;
62 }
63 
64 bool ARMInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
65   if (MBB.empty()) return false;
66 
67   switch (MBB.back().getOpcode()) {
68   case ARM::BX_RET:   // Return.
69   case ARM::LDM_RET:
70   case ARM::B:
71   case ARM::BR_JTr:   // Jumptable branch.
72   case ARM::BR_JTm:   // Jumptable branch through mem.
73   case ARM::BR_JTadd: // Jumptable branch add to pc.
74     return true;
75   default:
76     break;
77   }
78 
79   return false;
80 }
81 
82 void ARMInstrInfo::
83 reMaterialize(MachineBasicBlock &MBB,
84               MachineBasicBlock::iterator I,
85               unsigned DestReg, unsigned SubIdx,
86               const MachineInstr *Orig) const {
87   DebugLoc dl = Orig->getDebugLoc();
88   if (Orig->getOpcode() == ARM::MOVi2pieces) {
89     RI.emitLoadConstPool(MBB, I, dl,
90                          DestReg, SubIdx,
91                          Orig->getOperand(1).getImm(),
92                          (ARMCC::CondCodes)Orig->getOperand(2).getImm(),
93                          Orig->getOperand(3).getReg());
94     return;
95   }
96 
97   MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
98   MI->getOperand(0).setReg(DestReg);
99   MBB.insert(I, MI);
100 }
101 
102