1 //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the ARM implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMInstrInfo.h"
15 #include "ARM.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/MC/MCAsmInfo.h"
25 using namespace llvm;
26 
27 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
28   : ARMBaseInstrInfo(STI), RI(*this, STI) {
29 }
30 
31 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
32   switch (Opc) {
33   default: break;
34   case ARM::LDR_PRE:
35   case ARM::LDR_POST:
36     return ARM::LDR;
37   case ARM::LDRH_PRE:
38   case ARM::LDRH_POST:
39     return ARM::LDRH;
40   case ARM::LDRB_PRE:
41   case ARM::LDRB_POST:
42     return ARM::LDRB;
43   case ARM::LDRSH_PRE:
44   case ARM::LDRSH_POST:
45     return ARM::LDRSH;
46   case ARM::LDRSB_PRE:
47   case ARM::LDRSB_POST:
48     return ARM::LDRSB;
49   case ARM::STR_PRE:
50   case ARM::STR_POST:
51     return ARM::STR;
52   case ARM::STRH_PRE:
53   case ARM::STRH_POST:
54     return ARM::STRH;
55   case ARM::STRB_PRE:
56   case ARM::STRB_POST:
57     return ARM::STRB;
58   }
59 
60   return 0;
61 }
62 
63 void ARMInstrInfo::
64 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
65               unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig,
66               const TargetRegisterInfo &TRI) const {
67   DebugLoc dl = Orig->getDebugLoc();
68   unsigned Opcode = Orig->getOpcode();
69   switch (Opcode) {
70   default:
71     break;
72   case ARM::MOVi2pieces: {
73     RI.emitLoadConstPool(MBB, I, dl,
74                          DestReg, SubIdx,
75                          Orig->getOperand(1).getImm(),
76                          (ARMCC::CondCodes)Orig->getOperand(2).getImm(),
77                          Orig->getOperand(3).getReg());
78     MachineInstr *NewMI = prior(I);
79     NewMI->getOperand(0).setSubReg(SubIdx);
80     return;
81   }
82   }
83 
84   return ARMBaseInstrInfo::reMaterialize(MBB, I, DestReg, SubIdx, Orig, TRI);
85 }
86 
87