1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that ARM uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 16 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 17 18 #include "MCTargetDesc/ARMBaseInfo.h" 19 #include "llvm/ADT/SmallVector.h" 20 #include "llvm/ADT/StringRef.h" 21 #include "llvm/CodeGen/CallingConvLower.h" 22 #include "llvm/CodeGen/MachineFunction.h" 23 #include "llvm/CodeGen/MachineValueType.h" 24 #include "llvm/CodeGen/SelectionDAG.h" 25 #include "llvm/CodeGen/SelectionDAGNodes.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/IR/CallingConv.h" 28 #include "llvm/IR/IRBuilder.h" 29 #include "llvm/IR/InlineAsm.h" 30 #include "llvm/Support/CodeGen.h" 31 #include "llvm/Target/TargetLowering.h" 32 #include <utility> 33 34 namespace llvm { 35 36 class ARMSubtarget; 37 class InstrItineraryData; 38 39 namespace ARMISD { 40 41 // ARM Specific DAG Nodes 42 enum NodeType : unsigned { 43 // Start the numbering where the builtin ops and target ops leave off. 44 FIRST_NUMBER = ISD::BUILTIN_OP_END, 45 46 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 47 // TargetExternalSymbol, and TargetGlobalAddress. 48 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in 49 // PIC mode. 50 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 51 52 // Add pseudo op to model memcpy for struct byval. 53 COPY_STRUCT_BYVAL, 54 55 CALL, // Function call. 56 CALL_PRED, // Function call that's predicable. 57 CALL_NOLINK, // Function call with branch not branch-and-link. 58 BRCOND, // Conditional branch. 59 BR_JT, // Jumptable branch. 60 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 61 RET_FLAG, // Return with a flag operand. 62 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand. 63 64 PIC_ADD, // Add with a PC operand and a PIC label. 65 66 CMP, // ARM compare instructions. 67 CMN, // ARM CMN instructions. 68 CMPZ, // ARM compare that sets only Z flag. 69 CMPFP, // ARM VFP compare instruction, sets FPSCR. 70 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 71 FMSTAT, // ARM fmstat instruction. 72 73 CMOV, // ARM conditional move instructions. 74 75 SSAT, // Signed saturation 76 77 BCC_i64, 78 79 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 80 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 81 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 82 83 ADDC, // Add with carry 84 ADDE, // Add using carry 85 SUBC, // Sub with carry 86 SUBE, // Sub using carry 87 88 VMOVRRD, // double to two gprs. 89 VMOVDRR, // Two gprs to double. 90 91 EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 92 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 93 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch. 94 95 TC_RETURN, // Tail call return pseudo. 96 97 THREAD_POINTER, 98 99 DYN_ALLOC, // Dynamic allocation on the stack. 100 101 MEMBARRIER_MCR, // Memory barrier (MCR) 102 103 PRELOAD, // Preload 104 105 WIN__CHKSTK, // Windows' __chkstk call to do stack probing. 106 WIN__DBZCHK, // Windows' divide by zero check 107 108 VCEQ, // Vector compare equal. 109 VCEQZ, // Vector compare equal to zero. 110 VCGE, // Vector compare greater than or equal. 111 VCGEZ, // Vector compare greater than or equal to zero. 112 VCLEZ, // Vector compare less than or equal to zero. 113 VCGEU, // Vector compare unsigned greater than or equal. 114 VCGT, // Vector compare greater than. 115 VCGTZ, // Vector compare greater than zero. 116 VCLTZ, // Vector compare less than zero. 117 VCGTU, // Vector compare unsigned greater than. 118 VTST, // Vector test bits. 119 120 // Vector shift by immediate: 121 VSHL, // ...left 122 VSHRs, // ...right (signed) 123 VSHRu, // ...right (unsigned) 124 125 // Vector rounding shift by immediate: 126 VRSHRs, // ...right (signed) 127 VRSHRu, // ...right (unsigned) 128 VRSHRN, // ...right narrow 129 130 // Vector saturating shift by immediate: 131 VQSHLs, // ...left (signed) 132 VQSHLu, // ...left (unsigned) 133 VQSHLsu, // ...left (signed to unsigned) 134 VQSHRNs, // ...right narrow (signed) 135 VQSHRNu, // ...right narrow (unsigned) 136 VQSHRNsu, // ...right narrow (signed to unsigned) 137 138 // Vector saturating rounding shift by immediate: 139 VQRSHRNs, // ...right narrow (signed) 140 VQRSHRNu, // ...right narrow (unsigned) 141 VQRSHRNsu, // ...right narrow (signed to unsigned) 142 143 // Vector shift and insert: 144 VSLI, // ...left 145 VSRI, // ...right 146 147 // Vector get lane (VMOV scalar to ARM core register) 148 // (These are used for 8- and 16-bit element types only.) 149 VGETLANEu, // zero-extend vector extract element 150 VGETLANEs, // sign-extend vector extract element 151 152 // Vector move immediate and move negated immediate: 153 VMOVIMM, 154 VMVNIMM, 155 156 // Vector move f32 immediate: 157 VMOVFPIMM, 158 159 // Vector duplicate: 160 VDUP, 161 VDUPLANE, 162 163 // Vector shuffles: 164 VEXT, // extract 165 VREV64, // reverse elements within 64-bit doublewords 166 VREV32, // reverse elements within 32-bit words 167 VREV16, // reverse elements within 16-bit halfwords 168 VZIP, // zip (interleave) 169 VUZP, // unzip (deinterleave) 170 VTRN, // transpose 171 VTBL1, // 1-register shuffle with mask 172 VTBL2, // 2-register shuffle with mask 173 174 // Vector multiply long: 175 VMULLs, // ...signed 176 VMULLu, // ...unsigned 177 178 UMLAL, // 64bit Unsigned Accumulate Multiply 179 SMLAL, // 64bit Signed Accumulate Multiply 180 UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply 181 182 // Operands of the standard BUILD_VECTOR node are not legalized, which 183 // is fine if BUILD_VECTORs are always lowered to shuffles or other 184 // operations, but for ARM some BUILD_VECTORs are legal as-is and their 185 // operands need to be legalized. Define an ARM-specific version of 186 // BUILD_VECTOR for this purpose. 187 BUILD_VECTOR, 188 189 // Bit-field insert 190 BFI, 191 192 // Vector OR with immediate 193 VORRIMM, 194 // Vector AND with NOT of immediate 195 VBICIMM, 196 197 // Vector bitwise select 198 VBSL, 199 200 // Pseudo-instruction representing a memory copy using ldm/stm 201 // instructions. 202 MEMCPY, 203 204 // Vector load N-element structure to all lanes: 205 VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE, 206 VLD2DUP, 207 VLD3DUP, 208 VLD4DUP, 209 210 // NEON loads with post-increment base updates: 211 VLD1_UPD, 212 VLD2_UPD, 213 VLD3_UPD, 214 VLD4_UPD, 215 VLD2LN_UPD, 216 VLD3LN_UPD, 217 VLD4LN_UPD, 218 VLD1DUP_UPD, 219 VLD2DUP_UPD, 220 VLD3DUP_UPD, 221 VLD4DUP_UPD, 222 223 // NEON stores with post-increment base updates: 224 VST1_UPD, 225 VST2_UPD, 226 VST3_UPD, 227 VST4_UPD, 228 VST2LN_UPD, 229 VST3LN_UPD, 230 VST4LN_UPD 231 }; 232 233 } // end namespace ARMISD 234 235 /// Define some predicates that are used for node matching. 236 namespace ARM { 237 238 bool isBitFieldInvertedMask(unsigned v); 239 240 } // end namespace ARM 241 242 //===--------------------------------------------------------------------===// 243 // ARMTargetLowering - ARM Implementation of the TargetLowering interface 244 245 class ARMTargetLowering : public TargetLowering { 246 public: 247 explicit ARMTargetLowering(const TargetMachine &TM, 248 const ARMSubtarget &STI); 249 250 unsigned getJumpTableEncoding() const override; 251 bool useSoftFloat() const override; 252 253 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 254 255 /// ReplaceNodeResults - Replace the results of node with an illegal result 256 /// type with new values built out of custom code. 257 /// 258 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 259 SelectionDAG &DAG) const override; 260 261 const char *getTargetNodeName(unsigned Opcode) const override; 262 263 bool isSelectSupported(SelectSupportKind Kind) const override { 264 // ARM does not support scalar condition selects on vectors. 265 return (Kind != ScalarCondVectorVal); 266 } 267 268 /// getSetCCResultType - Return the value type to use for ISD::SETCC. 269 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 270 EVT VT) const override; 271 272 MachineBasicBlock * 273 EmitInstrWithCustomInserter(MachineInstr &MI, 274 MachineBasicBlock *MBB) const override; 275 276 void AdjustInstrPostInstrSelection(MachineInstr &MI, 277 SDNode *Node) const override; 278 279 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const; 280 SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const; 281 SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const; 282 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 283 284 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override; 285 286 /// allowsMisalignedMemoryAccesses - Returns true if the target allows 287 /// unaligned memory accesses of the specified type. Returns whether it 288 /// is "fast" by reference in the second argument. 289 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, 290 unsigned Align, 291 bool *Fast) const override; 292 293 EVT getOptimalMemOpType(uint64_t Size, 294 unsigned DstAlign, unsigned SrcAlign, 295 bool IsMemset, bool ZeroMemset, 296 bool MemcpyStrSrc, 297 MachineFunction &MF) const override; 298 299 using TargetLowering::isZExtFree; 300 bool isZExtFree(SDValue Val, EVT VT2) const override; 301 302 bool isVectorLoadExtDesirable(SDValue ExtVal) const override; 303 304 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override; 305 306 307 /// isLegalAddressingMode - Return true if the addressing mode represented 308 /// by AM is legal for this target, for a load/store of the specified type. 309 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 310 Type *Ty, unsigned AS) const override; 311 312 /// getScalingFactorCost - Return the cost of the scaling used in 313 /// addressing mode represented by AM. 314 /// If the AM is supported, the return value must be >= 0. 315 /// If the AM is not supported, the return value must be negative. 316 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, 317 unsigned AS) const override; 318 319 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 320 321 /// isLegalICmpImmediate - Return true if the specified immediate is legal 322 /// icmp immediate, that is the target has icmp instructions which can 323 /// compare a register against the immediate without having to materialize 324 /// the immediate into a register. 325 bool isLegalICmpImmediate(int64_t Imm) const override; 326 327 /// isLegalAddImmediate - Return true if the specified immediate is legal 328 /// add immediate, that is the target has add instructions which can 329 /// add a register and the immediate without having to materialize 330 /// the immediate into a register. 331 bool isLegalAddImmediate(int64_t Imm) const override; 332 333 /// getPreIndexedAddressParts - returns true by value, base pointer and 334 /// offset pointer and addressing mode by reference if the node's address 335 /// can be legally represented as pre-indexed load / store address. 336 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, 337 ISD::MemIndexedMode &AM, 338 SelectionDAG &DAG) const override; 339 340 /// getPostIndexedAddressParts - returns true by value, base pointer and 341 /// offset pointer and addressing mode by reference if this node can be 342 /// combined with a load / store to form a post-indexed load / store. 343 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, 344 SDValue &Offset, ISD::MemIndexedMode &AM, 345 SelectionDAG &DAG) const override; 346 347 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, 348 APInt &KnownOne, 349 const SelectionDAG &DAG, 350 unsigned Depth) const override; 351 352 353 bool ExpandInlineAsm(CallInst *CI) const override; 354 355 ConstraintType getConstraintType(StringRef Constraint) const override; 356 357 /// Examine constraint string and operand type and determine a weight value. 358 /// The operand object must already have been set up with the operand type. 359 ConstraintWeight getSingleConstraintMatchWeight( 360 AsmOperandInfo &info, const char *constraint) const override; 361 362 std::pair<unsigned, const TargetRegisterClass *> 363 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 364 StringRef Constraint, MVT VT) const override; 365 366 const char *LowerXConstraint(EVT ConstraintVT) const override; 367 368 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 369 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 370 /// true it means one of the asm constraint of the inline asm instruction 371 /// being processed is 'm'. 372 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 373 std::vector<SDValue> &Ops, 374 SelectionDAG &DAG) const override; 375 376 unsigned 377 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 378 if (ConstraintCode == "Q") 379 return InlineAsm::Constraint_Q; 380 else if (ConstraintCode == "o") 381 return InlineAsm::Constraint_o; 382 else if (ConstraintCode.size() == 2) { 383 if (ConstraintCode[0] == 'U') { 384 switch(ConstraintCode[1]) { 385 default: 386 break; 387 case 'm': 388 return InlineAsm::Constraint_Um; 389 case 'n': 390 return InlineAsm::Constraint_Un; 391 case 'q': 392 return InlineAsm::Constraint_Uq; 393 case 's': 394 return InlineAsm::Constraint_Us; 395 case 't': 396 return InlineAsm::Constraint_Ut; 397 case 'v': 398 return InlineAsm::Constraint_Uv; 399 case 'y': 400 return InlineAsm::Constraint_Uy; 401 } 402 } 403 } 404 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 405 } 406 407 const ARMSubtarget* getSubtarget() const { 408 return Subtarget; 409 } 410 411 /// getRegClassFor - Return the register class that should be used for the 412 /// specified value type. 413 const TargetRegisterClass *getRegClassFor(MVT VT) const override; 414 415 /// Returns true if a cast between SrcAS and DestAS is a noop. 416 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override { 417 // Addrspacecasts are always noops. 418 return true; 419 } 420 421 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize, 422 unsigned &PrefAlign) const override; 423 424 /// createFastISel - This method returns a target specific FastISel object, 425 /// or null if the target does not support "fast" ISel. 426 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 427 const TargetLibraryInfo *libInfo) const override; 428 429 Sched::Preference getSchedulingPreference(SDNode *N) const override; 430 431 bool 432 isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override; 433 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 434 435 /// isFPImmLegal - Returns true if the target can instruction select the 436 /// specified FP immediate natively. If false, the legalizer will 437 /// materialize the FP immediate as a load from a constant pool. 438 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; 439 440 bool getTgtMemIntrinsic(IntrinsicInfo &Info, 441 const CallInst &I, 442 unsigned Intrinsic) const override; 443 444 /// \brief Returns true if it is beneficial to convert a load of a constant 445 /// to just the constant itself. 446 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 447 Type *Ty) const override; 448 449 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type 450 /// with this index. 451 bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override; 452 453 /// \brief Returns true if an argument of type Ty needs to be passed in a 454 /// contiguous block of registers in calling convention CallConv. 455 bool functionArgumentNeedsConsecutiveRegisters( 456 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override; 457 458 /// If a physical register, this returns the register that receives the 459 /// exception address on entry to an EH pad. 460 unsigned 461 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 462 463 /// If a physical register, this returns the register that receives the 464 /// exception typeid on entry to a landing pad. 465 unsigned 466 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 467 468 Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const; 469 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr, 470 AtomicOrdering Ord) const override; 471 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val, 472 Value *Addr, AtomicOrdering Ord) const override; 473 474 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override; 475 476 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord, 477 bool IsStore, bool IsLoad) const override; 478 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord, 479 bool IsStore, bool IsLoad) const override; 480 481 unsigned getMaxSupportedInterleaveFactor() const override { return 4; } 482 483 bool lowerInterleavedLoad(LoadInst *LI, 484 ArrayRef<ShuffleVectorInst *> Shuffles, 485 ArrayRef<unsigned> Indices, 486 unsigned Factor) const override; 487 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, 488 unsigned Factor) const override; 489 490 bool shouldInsertFencesForAtomic(const Instruction *I) const override; 491 TargetLoweringBase::AtomicExpansionKind 492 shouldExpandAtomicLoadInIR(LoadInst *LI) const override; 493 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override; 494 TargetLoweringBase::AtomicExpansionKind 495 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 496 bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; 497 498 bool useLoadStackGuardNode() const override; 499 500 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, 501 unsigned &Cost) const override; 502 503 bool isCheapToSpeculateCttz() const override; 504 bool isCheapToSpeculateCtlz() const override; 505 506 bool supportSwiftError() const override { 507 return true; 508 } 509 510 bool hasStandaloneRem(EVT VT) const override { 511 return HasStandaloneRem; 512 } 513 514 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const; 515 CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const; 516 517 protected: 518 std::pair<const TargetRegisterClass *, uint8_t> 519 findRepresentativeClass(const TargetRegisterInfo *TRI, 520 MVT VT) const override; 521 522 private: 523 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 524 /// make the right decision when generating code for different targets. 525 const ARMSubtarget *Subtarget; 526 527 const TargetRegisterInfo *RegInfo; 528 529 const InstrItineraryData *Itins; 530 531 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. 532 /// 533 unsigned ARMPCLabelIndex; 534 535 // TODO: remove this, and have shouldInsertFencesForAtomic do the proper 536 // check. 537 bool InsertFencesForAtomic; 538 539 bool HasStandaloneRem = true; 540 541 void InitLibcallCallingConvs(); 542 543 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT); 544 void addDRTypeForNEON(MVT VT); 545 void addQRTypeForNEON(MVT VT); 546 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const; 547 548 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector; 549 550 void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain, 551 SDValue &Arg, RegsToPassVector &RegsToPass, 552 CCValAssign &VA, CCValAssign &NextVA, 553 SDValue &StackPtr, 554 SmallVectorImpl<SDValue> &MemOpChains, 555 ISD::ArgFlagsTy Flags) const; 556 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 557 SDValue &Root, SelectionDAG &DAG, 558 const SDLoc &dl) const; 559 560 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC, 561 bool isVarArg) const; 562 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, 563 bool isVarArg) const; 564 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 565 const SDLoc &dl, SelectionDAG &DAG, 566 const CCValAssign &VA, 567 ISD::ArgFlagsTy Flags) const; 568 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 569 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 570 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const; 571 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 572 const ARMSubtarget *Subtarget) const; 573 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 574 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 575 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 576 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const; 577 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 578 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 579 SelectionDAG &DAG) const; 580 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 581 SelectionDAG &DAG, 582 TLSModel::Model model) const; 583 SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 584 SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const; 585 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const; 586 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 587 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const; 588 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 589 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 590 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 591 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 592 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 593 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 594 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 595 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 596 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 597 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG, 598 const ARMSubtarget *ST) const; 599 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 600 const ARMSubtarget *ST) const; 601 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const; 602 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const; 603 SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const; 604 void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed, 605 SmallVectorImpl<SDValue> &Results) const; 606 SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed, 607 SDValue &Chain) const; 608 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const; 609 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 610 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 611 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 612 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const; 613 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 614 615 unsigned getRegisterByName(const char* RegName, EVT VT, 616 SelectionDAG &DAG) const override; 617 618 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 619 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 620 /// expanded to FMAs when this method returns true, otherwise fmuladd is 621 /// expanded to fmul + fadd. 622 /// 623 /// ARM supports both fused and unfused multiply-add operations; we already 624 /// lower a pair of fmul and fadd to the latter so it's not clear that there 625 /// would be a gain or that the gain would be worthwhile enough to risk 626 /// correctness bugs. 627 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; } 628 629 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 630 631 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 632 CallingConv::ID CallConv, bool isVarArg, 633 const SmallVectorImpl<ISD::InputArg> &Ins, 634 const SDLoc &dl, SelectionDAG &DAG, 635 SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 636 SDValue ThisVal) const; 637 638 bool supportSplitCSR(MachineFunction *MF) const override { 639 return MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS && 640 MF->getFunction()->hasFnAttribute(Attribute::NoUnwind); 641 } 642 643 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 644 void insertCopiesSplitCSR( 645 MachineBasicBlock *Entry, 646 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 647 648 SDValue 649 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 650 const SmallVectorImpl<ISD::InputArg> &Ins, 651 const SDLoc &dl, SelectionDAG &DAG, 652 SmallVectorImpl<SDValue> &InVals) const override; 653 654 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl, 655 SDValue &Chain, const Value *OrigArg, 656 unsigned InRegsParamRecordIdx, int ArgOffset, 657 unsigned ArgSize) const; 658 659 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 660 const SDLoc &dl, SDValue &Chain, 661 unsigned ArgOffset, unsigned TotalArgRegsSaveSize, 662 bool ForceMutable = false) const; 663 664 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 665 SmallVectorImpl<SDValue> &InVals) const override; 666 667 /// HandleByVal - Target-specific cleanup for ByVal support. 668 void HandleByVal(CCState *, unsigned &, unsigned) const override; 669 670 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 671 /// for tail call optimization. Targets which want to do tail call 672 /// optimization should implement this function. 673 bool IsEligibleForTailCallOptimization(SDValue Callee, 674 CallingConv::ID CalleeCC, 675 bool isVarArg, 676 bool isCalleeStructRet, 677 bool isCallerStructRet, 678 const SmallVectorImpl<ISD::OutputArg> &Outs, 679 const SmallVectorImpl<SDValue> &OutVals, 680 const SmallVectorImpl<ISD::InputArg> &Ins, 681 SelectionDAG& DAG) const; 682 683 bool CanLowerReturn(CallingConv::ID CallConv, 684 MachineFunction &MF, bool isVarArg, 685 const SmallVectorImpl<ISD::OutputArg> &Outs, 686 LLVMContext &Context) const override; 687 688 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 689 const SmallVectorImpl<ISD::OutputArg> &Outs, 690 const SmallVectorImpl<SDValue> &OutVals, 691 const SDLoc &dl, SelectionDAG &DAG) const override; 692 693 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override; 694 695 bool mayBeEmittedAsTailCall(CallInst *CI) const override; 696 697 SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal, 698 SDValue ARMcc, SDValue CCR, SDValue Cmp, 699 SelectionDAG &DAG) const; 700 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 701 SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const; 702 SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, 703 const SDLoc &dl) const; 704 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const; 705 706 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const; 707 708 void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, 709 MachineBasicBlock *DispatchBB, int FI) const; 710 711 void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const; 712 713 bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const; 714 715 MachineBasicBlock *EmitStructByval(MachineInstr &MI, 716 MachineBasicBlock *MBB) const; 717 718 MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI, 719 MachineBasicBlock *MBB) const; 720 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI, 721 MachineBasicBlock *MBB) const; 722 }; 723 724 enum NEONModImmType { 725 VMOVModImm, 726 VMVNModImm, 727 OtherModImm 728 }; 729 730 namespace ARM { 731 732 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 733 const TargetLibraryInfo *libInfo); 734 735 } // end namespace ARM 736 737 } // end namespace llvm 738 739 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 740