1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that ARM uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "arm-isel" 16 #include "ARM.h" 17 #include "ARMCallingConv.h" 18 #include "ARMConstantPoolValue.h" 19 #include "ARMISelLowering.h" 20 #include "ARMMachineFunctionInfo.h" 21 #include "ARMPerfectShuffle.h" 22 #include "ARMRegisterInfo.h" 23 #include "ARMSubtarget.h" 24 #include "ARMTargetMachine.h" 25 #include "ARMTargetObjectFile.h" 26 #include "MCTargetDesc/ARMAddressingModes.h" 27 #include "llvm/CallingConv.h" 28 #include "llvm/Constants.h" 29 #include "llvm/Function.h" 30 #include "llvm/GlobalValue.h" 31 #include "llvm/Instruction.h" 32 #include "llvm/Instructions.h" 33 #include "llvm/Intrinsics.h" 34 #include "llvm/Type.h" 35 #include "llvm/CodeGen/CallingConvLower.h" 36 #include "llvm/CodeGen/IntrinsicLowering.h" 37 #include "llvm/CodeGen/MachineBasicBlock.h" 38 #include "llvm/CodeGen/MachineFrameInfo.h" 39 #include "llvm/CodeGen/MachineFunction.h" 40 #include "llvm/CodeGen/MachineInstrBuilder.h" 41 #include "llvm/CodeGen/MachineRegisterInfo.h" 42 #include "llvm/CodeGen/PseudoSourceValue.h" 43 #include "llvm/CodeGen/SelectionDAG.h" 44 #include "llvm/MC/MCSectionMachO.h" 45 #include "llvm/Target/TargetOptions.h" 46 #include "llvm/ADT/VectorExtras.h" 47 #include "llvm/ADT/StringExtras.h" 48 #include "llvm/ADT/Statistic.h" 49 #include "llvm/Support/CommandLine.h" 50 #include "llvm/Support/ErrorHandling.h" 51 #include "llvm/Support/MathExtras.h" 52 #include "llvm/Support/raw_ostream.h" 53 #include <sstream> 54 using namespace llvm; 55 56 STATISTIC(NumTailCalls, "Number of tail calls"); 57 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt"); 58 59 // This option should go away when tail calls fully work. 60 static cl::opt<bool> 61 EnableARMTailCalls("arm-tail-calls", cl::Hidden, 62 cl::desc("Generate tail calls (TEMPORARY OPTION)."), 63 cl::init(false)); 64 65 cl::opt<bool> 66 EnableARMLongCalls("arm-long-calls", cl::Hidden, 67 cl::desc("Generate calls via indirect call instructions"), 68 cl::init(false)); 69 70 static cl::opt<bool> 71 ARMInterworking("arm-interworking", cl::Hidden, 72 cl::desc("Enable / disable ARM interworking (for debugging only)"), 73 cl::init(true)); 74 75 namespace llvm { 76 class ARMCCState : public CCState { 77 public: 78 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF, 79 const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs, 80 LLVMContext &C, ParmContext PC) 81 : CCState(CC, isVarArg, MF, TM, locs, C) { 82 assert(((PC == Call) || (PC == Prologue)) && 83 "ARMCCState users must specify whether their context is call" 84 "or prologue generation."); 85 CallOrPrologue = PC; 86 } 87 }; 88 } 89 90 // The APCS parameter registers. 91 static const unsigned GPRArgRegs[] = { 92 ARM::R0, ARM::R1, ARM::R2, ARM::R3 93 }; 94 95 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT, 96 EVT PromotedBitwiseVT) { 97 if (VT != PromotedLdStVT) { 98 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote); 99 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(), 100 PromotedLdStVT.getSimpleVT()); 101 102 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote); 103 AddPromotedToType (ISD::STORE, VT.getSimpleVT(), 104 PromotedLdStVT.getSimpleVT()); 105 } 106 107 EVT ElemTy = VT.getVectorElementType(); 108 if (ElemTy != MVT::i64 && ElemTy != MVT::f64) 109 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom); 110 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom); 111 if (ElemTy != MVT::i32) { 112 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand); 113 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand); 114 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand); 115 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand); 116 } 117 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom); 118 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom); 119 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal); 120 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal); 121 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand); 122 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand); 123 if (VT.isInteger()) { 124 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom); 125 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom); 126 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom); 127 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand); 128 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand); 129 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 130 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 131 setTruncStoreAction(VT.getSimpleVT(), 132 (MVT::SimpleValueType)InnerVT, Expand); 133 } 134 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand); 135 136 // Promote all bit-wise operations. 137 if (VT.isInteger() && VT != PromotedBitwiseVT) { 138 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote); 139 AddPromotedToType (ISD::AND, VT.getSimpleVT(), 140 PromotedBitwiseVT.getSimpleVT()); 141 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote); 142 AddPromotedToType (ISD::OR, VT.getSimpleVT(), 143 PromotedBitwiseVT.getSimpleVT()); 144 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote); 145 AddPromotedToType (ISD::XOR, VT.getSimpleVT(), 146 PromotedBitwiseVT.getSimpleVT()); 147 } 148 149 // Neon does not support vector divide/remainder operations. 150 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand); 151 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand); 152 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand); 153 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand); 154 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand); 155 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand); 156 } 157 158 void ARMTargetLowering::addDRTypeForNEON(EVT VT) { 159 addRegisterClass(VT, ARM::DPRRegisterClass); 160 addTypeForNEON(VT, MVT::f64, MVT::v2i32); 161 } 162 163 void ARMTargetLowering::addQRTypeForNEON(EVT VT) { 164 addRegisterClass(VT, ARM::QPRRegisterClass); 165 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); 166 } 167 168 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) { 169 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin()) 170 return new TargetLoweringObjectFileMachO(); 171 172 return new ARMElfTargetObjectFile(); 173 } 174 175 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) 176 : TargetLowering(TM, createTLOF(TM)) { 177 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 178 RegInfo = TM.getRegisterInfo(); 179 Itins = TM.getInstrItineraryData(); 180 181 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 182 183 if (Subtarget->isTargetDarwin()) { 184 // Uses VFP for Thumb libfuncs if available. 185 if (Subtarget->isThumb() && Subtarget->hasVFP2()) { 186 // Single-precision floating-point arithmetic. 187 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); 188 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); 189 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp"); 190 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp"); 191 192 // Double-precision floating-point arithmetic. 193 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp"); 194 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp"); 195 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp"); 196 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp"); 197 198 // Single-precision comparisons. 199 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp"); 200 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp"); 201 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp"); 202 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp"); 203 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp"); 204 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp"); 205 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp"); 206 setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); 207 208 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 209 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); 210 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 211 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 212 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 213 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 214 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 215 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 216 217 // Double-precision comparisons. 218 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp"); 219 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp"); 220 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp"); 221 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp"); 222 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp"); 223 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp"); 224 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp"); 225 setLibcallName(RTLIB::O_F64, "__unorddf2vfp"); 226 227 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 228 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); 229 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 230 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 231 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 232 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 233 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 234 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 235 236 // Floating-point to integer conversions. 237 // i64 conversions are done via library routines even when generating VFP 238 // instructions, so use the same ones. 239 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp"); 240 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp"); 241 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp"); 242 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp"); 243 244 // Conversions between floating types. 245 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp"); 246 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp"); 247 248 // Integer to floating-point conversions. 249 // i64 conversions are done via library routines even when generating VFP 250 // instructions, so use the same ones. 251 // FIXME: There appears to be some naming inconsistency in ARM libgcc: 252 // e.g., __floatunsidf vs. __floatunssidfvfp. 253 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp"); 254 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp"); 255 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp"); 256 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp"); 257 } 258 } 259 260 // These libcalls are not available in 32-bit. 261 setLibcallName(RTLIB::SHL_I128, 0); 262 setLibcallName(RTLIB::SRL_I128, 0); 263 setLibcallName(RTLIB::SRA_I128, 0); 264 265 if (Subtarget->isAAPCS_ABI()) { 266 // Double-precision floating-point arithmetic helper functions 267 // RTABI chapter 4.1.2, Table 2 268 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd"); 269 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv"); 270 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul"); 271 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub"); 272 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS); 273 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS); 274 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS); 275 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS); 276 277 // Double-precision floating-point comparison helper functions 278 // RTABI chapter 4.1.2, Table 3 279 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq"); 280 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 281 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq"); 282 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ); 283 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt"); 284 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 285 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple"); 286 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 287 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge"); 288 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 289 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt"); 290 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 291 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun"); 292 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 293 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun"); 294 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 295 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS); 296 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS); 297 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS); 298 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS); 299 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS); 300 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS); 301 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS); 302 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS); 303 304 // Single-precision floating-point arithmetic helper functions 305 // RTABI chapter 4.1.2, Table 4 306 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd"); 307 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv"); 308 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul"); 309 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub"); 310 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS); 311 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS); 312 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS); 313 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS); 314 315 // Single-precision floating-point comparison helper functions 316 // RTABI chapter 4.1.2, Table 5 317 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq"); 318 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 319 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq"); 320 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ); 321 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt"); 322 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 323 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple"); 324 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 325 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge"); 326 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 327 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt"); 328 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 329 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun"); 330 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 331 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun"); 332 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 333 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS); 334 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS); 335 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS); 336 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS); 337 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS); 338 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS); 339 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS); 340 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS); 341 342 // Floating-point to integer conversions. 343 // RTABI chapter 4.1.2, Table 6 344 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz"); 345 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz"); 346 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz"); 347 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz"); 348 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz"); 349 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz"); 350 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz"); 351 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz"); 352 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS); 353 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS); 354 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS); 355 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS); 356 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS); 357 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS); 358 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS); 359 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS); 360 361 // Conversions between floating types. 362 // RTABI chapter 4.1.2, Table 7 363 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f"); 364 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d"); 365 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS); 366 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS); 367 368 // Integer to floating-point conversions. 369 // RTABI chapter 4.1.2, Table 8 370 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d"); 371 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d"); 372 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d"); 373 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d"); 374 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f"); 375 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f"); 376 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f"); 377 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f"); 378 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS); 379 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS); 380 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS); 381 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS); 382 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS); 383 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS); 384 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS); 385 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS); 386 387 // Long long helper functions 388 // RTABI chapter 4.2, Table 9 389 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul"); 390 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod"); 391 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod"); 392 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl"); 393 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr"); 394 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr"); 395 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS); 396 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS); 397 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS); 398 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS); 399 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS); 400 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS); 401 402 // Integer division functions 403 // RTABI chapter 4.3.1 404 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv"); 405 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv"); 406 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv"); 407 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv"); 408 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv"); 409 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv"); 410 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS); 411 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS); 412 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS); 413 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS); 414 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS); 415 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS); 416 417 // Memory operations 418 // RTABI chapter 4.3.4 419 setLibcallName(RTLIB::MEMCPY, "__aeabi_memcpy"); 420 setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove"); 421 setLibcallName(RTLIB::MEMSET, "__aeabi_memset"); 422 } 423 424 if (Subtarget->isThumb1Only()) 425 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass); 426 else 427 addRegisterClass(MVT::i32, ARM::GPRRegisterClass); 428 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 429 addRegisterClass(MVT::f32, ARM::SPRRegisterClass); 430 if (!Subtarget->isFPOnlySP()) 431 addRegisterClass(MVT::f64, ARM::DPRRegisterClass); 432 433 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 434 } 435 436 if (Subtarget->hasNEON()) { 437 addDRTypeForNEON(MVT::v2f32); 438 addDRTypeForNEON(MVT::v8i8); 439 addDRTypeForNEON(MVT::v4i16); 440 addDRTypeForNEON(MVT::v2i32); 441 addDRTypeForNEON(MVT::v1i64); 442 443 addQRTypeForNEON(MVT::v4f32); 444 addQRTypeForNEON(MVT::v2f64); 445 addQRTypeForNEON(MVT::v16i8); 446 addQRTypeForNEON(MVT::v8i16); 447 addQRTypeForNEON(MVT::v4i32); 448 addQRTypeForNEON(MVT::v2i64); 449 450 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but 451 // neither Neon nor VFP support any arithmetic operations on it. 452 setOperationAction(ISD::FADD, MVT::v2f64, Expand); 453 setOperationAction(ISD::FSUB, MVT::v2f64, Expand); 454 setOperationAction(ISD::FMUL, MVT::v2f64, Expand); 455 setOperationAction(ISD::FDIV, MVT::v2f64, Expand); 456 setOperationAction(ISD::FREM, MVT::v2f64, Expand); 457 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand); 458 setOperationAction(ISD::SETCC, MVT::v2f64, Expand); 459 setOperationAction(ISD::FNEG, MVT::v2f64, Expand); 460 setOperationAction(ISD::FABS, MVT::v2f64, Expand); 461 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand); 462 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); 463 setOperationAction(ISD::FCOS, MVT::v2f64, Expand); 464 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand); 465 setOperationAction(ISD::FPOW, MVT::v2f64, Expand); 466 setOperationAction(ISD::FLOG, MVT::v2f64, Expand); 467 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand); 468 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand); 469 setOperationAction(ISD::FEXP, MVT::v2f64, Expand); 470 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); 471 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand); 472 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand); 473 setOperationAction(ISD::FRINT, MVT::v2f64, Expand); 474 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); 475 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand); 476 477 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand); 478 479 // Neon does not support some operations on v1i64 and v2i64 types. 480 setOperationAction(ISD::MUL, MVT::v1i64, Expand); 481 // Custom handling for some quad-vector types to detect VMULL. 482 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 483 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 484 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 485 // Custom handling for some vector types to avoid expensive expansions 486 setOperationAction(ISD::SDIV, MVT::v4i16, Custom); 487 setOperationAction(ISD::SDIV, MVT::v8i8, Custom); 488 setOperationAction(ISD::UDIV, MVT::v4i16, Custom); 489 setOperationAction(ISD::UDIV, MVT::v8i8, Custom); 490 setOperationAction(ISD::SETCC, MVT::v1i64, Expand); 491 setOperationAction(ISD::SETCC, MVT::v2i64, Expand); 492 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with 493 // a destination type that is wider than the source. 494 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); 495 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); 496 497 setTargetDAGCombine(ISD::INTRINSIC_VOID); 498 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN); 499 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); 500 setTargetDAGCombine(ISD::SHL); 501 setTargetDAGCombine(ISD::SRL); 502 setTargetDAGCombine(ISD::SRA); 503 setTargetDAGCombine(ISD::SIGN_EXTEND); 504 setTargetDAGCombine(ISD::ZERO_EXTEND); 505 setTargetDAGCombine(ISD::ANY_EXTEND); 506 setTargetDAGCombine(ISD::SELECT_CC); 507 setTargetDAGCombine(ISD::BUILD_VECTOR); 508 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 509 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); 510 setTargetDAGCombine(ISD::STORE); 511 setTargetDAGCombine(ISD::FP_TO_SINT); 512 setTargetDAGCombine(ISD::FP_TO_UINT); 513 setTargetDAGCombine(ISD::FDIV); 514 } 515 516 computeRegisterProperties(); 517 518 // ARM does not have f32 extending load. 519 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 520 521 // ARM does not have i1 sign extending load. 522 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 523 524 // ARM supports all 4 flavors of integer indexed load / store. 525 if (!Subtarget->isThumb1Only()) { 526 for (unsigned im = (unsigned)ISD::PRE_INC; 527 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 528 setIndexedLoadAction(im, MVT::i1, Legal); 529 setIndexedLoadAction(im, MVT::i8, Legal); 530 setIndexedLoadAction(im, MVT::i16, Legal); 531 setIndexedLoadAction(im, MVT::i32, Legal); 532 setIndexedStoreAction(im, MVT::i1, Legal); 533 setIndexedStoreAction(im, MVT::i8, Legal); 534 setIndexedStoreAction(im, MVT::i16, Legal); 535 setIndexedStoreAction(im, MVT::i32, Legal); 536 } 537 } 538 539 // i64 operation support. 540 setOperationAction(ISD::MUL, MVT::i64, Expand); 541 setOperationAction(ISD::MULHU, MVT::i32, Expand); 542 if (Subtarget->isThumb1Only()) { 543 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 544 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 545 } 546 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops() 547 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP())) 548 setOperationAction(ISD::MULHS, MVT::i32, Expand); 549 550 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 551 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 552 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 553 setOperationAction(ISD::SRL, MVT::i64, Custom); 554 setOperationAction(ISD::SRA, MVT::i64, Custom); 555 556 if (!Subtarget->isThumb1Only()) { 557 // FIXME: We should do this for Thumb1 as well. 558 setOperationAction(ISD::ADDC, MVT::i32, Custom); 559 setOperationAction(ISD::ADDE, MVT::i32, Custom); 560 setOperationAction(ISD::SUBC, MVT::i32, Custom); 561 setOperationAction(ISD::SUBE, MVT::i32, Custom); 562 } 563 564 // ARM does not have ROTL. 565 setOperationAction(ISD::ROTL, MVT::i32, Expand); 566 setOperationAction(ISD::CTTZ, MVT::i32, Custom); 567 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 568 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) 569 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 570 571 // Only ARMv6 has BSWAP. 572 if (!Subtarget->hasV6Ops()) 573 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 574 575 // These are expanded into libcalls. 576 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) { 577 // v7M has a hardware divider 578 setOperationAction(ISD::SDIV, MVT::i32, Expand); 579 setOperationAction(ISD::UDIV, MVT::i32, Expand); 580 } 581 setOperationAction(ISD::SREM, MVT::i32, Expand); 582 setOperationAction(ISD::UREM, MVT::i32, Expand); 583 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 584 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 585 586 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 587 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 588 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); 589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 590 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 591 592 setOperationAction(ISD::TRAP, MVT::Other, Legal); 593 594 // Use the default implementation. 595 setOperationAction(ISD::VASTART, MVT::Other, Custom); 596 setOperationAction(ISD::VAARG, MVT::Other, Expand); 597 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 598 setOperationAction(ISD::VAEND, MVT::Other, Expand); 599 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 600 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 601 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 602 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 603 setExceptionPointerRegister(ARM::R0); 604 setExceptionSelectorRegister(ARM::R1); 605 606 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 607 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use 608 // the default expansion. 609 // FIXME: This should be checking for v6k, not just v6. 610 if (Subtarget->hasDataBarrier() || 611 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) { 612 // membarrier needs custom lowering; the rest are legal and handled 613 // normally. 614 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 615 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 616 // Custom lowering for 64-bit ops 617 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 618 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 619 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 620 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 621 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 622 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 623 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); 624 // Automatically insert fences (dmb ist) around ATOMIC_SWAP etc. 625 setInsertFencesForAtomic(true); 626 } else { 627 // Set them all for expansion, which will force libcalls. 628 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 629 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); 630 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); 631 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand); 632 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand); 633 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand); 634 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand); 635 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand); 636 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand); 637 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); 638 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand); 639 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand); 640 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand); 641 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand); 642 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 643 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 644 // Since the libcalls include locking, fold in the fences 645 setShouldFoldAtomicFences(true); 646 } 647 648 setOperationAction(ISD::PREFETCH, MVT::Other, Custom); 649 650 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes. 651 if (!Subtarget->hasV6Ops()) { 652 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 653 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 654 } 655 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 656 657 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 658 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR 659 // iff target supports vfp2. 660 setOperationAction(ISD::BITCAST, MVT::i64, Custom); 661 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 662 } 663 664 // We want to custom lower some of our intrinsics. 665 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 666 if (Subtarget->isTargetDarwin()) { 667 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom); 668 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); 669 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom); 670 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume"); 671 } 672 673 setOperationAction(ISD::SETCC, MVT::i32, Expand); 674 setOperationAction(ISD::SETCC, MVT::f32, Expand); 675 setOperationAction(ISD::SETCC, MVT::f64, Expand); 676 setOperationAction(ISD::SELECT, MVT::i32, Custom); 677 setOperationAction(ISD::SELECT, MVT::f32, Custom); 678 setOperationAction(ISD::SELECT, MVT::f64, Custom); 679 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 680 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 681 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 682 683 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 684 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 685 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 686 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 687 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 688 689 // We don't support sin/cos/fmod/copysign/pow 690 setOperationAction(ISD::FSIN, MVT::f64, Expand); 691 setOperationAction(ISD::FSIN, MVT::f32, Expand); 692 setOperationAction(ISD::FCOS, MVT::f32, Expand); 693 setOperationAction(ISD::FCOS, MVT::f64, Expand); 694 setOperationAction(ISD::FREM, MVT::f64, Expand); 695 setOperationAction(ISD::FREM, MVT::f32, Expand); 696 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 697 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 698 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 699 } 700 setOperationAction(ISD::FPOW, MVT::f64, Expand); 701 setOperationAction(ISD::FPOW, MVT::f32, Expand); 702 703 setOperationAction(ISD::FMA, MVT::f64, Expand); 704 setOperationAction(ISD::FMA, MVT::f32, Expand); 705 706 // Various VFP goodness 707 if (!UseSoftFloat && !Subtarget->isThumb1Only()) { 708 // int <-> fp are custom expanded into bit_convert + ARMISD ops. 709 if (Subtarget->hasVFP2()) { 710 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 711 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 712 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 713 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 714 } 715 // Special handling for half-precision FP. 716 if (!Subtarget->hasFP16()) { 717 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand); 718 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand); 719 } 720 } 721 722 // We have target-specific dag combine patterns for the following nodes: 723 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine 724 setTargetDAGCombine(ISD::ADD); 725 setTargetDAGCombine(ISD::SUB); 726 setTargetDAGCombine(ISD::MUL); 727 728 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON()) 729 setTargetDAGCombine(ISD::OR); 730 if (Subtarget->hasNEON()) 731 setTargetDAGCombine(ISD::AND); 732 733 setStackPointerRegisterToSaveRestore(ARM::SP); 734 735 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2()) 736 setSchedulingPreference(Sched::RegPressure); 737 else 738 setSchedulingPreference(Sched::Hybrid); 739 740 //// temporary - rewrite interface to use type 741 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1; 742 743 // On ARM arguments smaller than 4 bytes are extended, so all arguments 744 // are at least 4 bytes aligned. 745 setMinStackArgumentAlignment(4); 746 747 benefitFromCodePlacementOpt = true; 748 749 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2); 750 } 751 752 // FIXME: It might make sense to define the representative register class as the 753 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is 754 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently, 755 // SPR's representative would be DPR_VFP2. This should work well if register 756 // pressure tracking were modified such that a register use would increment the 757 // pressure of the register class's representative and all of it's super 758 // classes' representatives transitively. We have not implemented this because 759 // of the difficulty prior to coalescing of modeling operand register classes 760 // due to the common occurrence of cross class copies and subregister insertions 761 // and extractions. 762 std::pair<const TargetRegisterClass*, uint8_t> 763 ARMTargetLowering::findRepresentativeClass(EVT VT) const{ 764 const TargetRegisterClass *RRC = 0; 765 uint8_t Cost = 1; 766 switch (VT.getSimpleVT().SimpleTy) { 767 default: 768 return TargetLowering::findRepresentativeClass(VT); 769 // Use DPR as representative register class for all floating point 770 // and vector types. Since there are 32 SPR registers and 32 DPR registers so 771 // the cost is 1 for both f32 and f64. 772 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16: 773 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32: 774 RRC = ARM::DPRRegisterClass; 775 // When NEON is used for SP, only half of the register file is available 776 // because operations that define both SP and DP results will be constrained 777 // to the VFP2 class (D0-D15). We currently model this constraint prior to 778 // coalescing by double-counting the SP regs. See the FIXME above. 779 if (Subtarget->useNEONForSinglePrecisionFP()) 780 Cost = 2; 781 break; 782 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 783 case MVT::v4f32: case MVT::v2f64: 784 RRC = ARM::DPRRegisterClass; 785 Cost = 2; 786 break; 787 case MVT::v4i64: 788 RRC = ARM::DPRRegisterClass; 789 Cost = 4; 790 break; 791 case MVT::v8i64: 792 RRC = ARM::DPRRegisterClass; 793 Cost = 8; 794 break; 795 } 796 return std::make_pair(RRC, Cost); 797 } 798 799 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 800 switch (Opcode) { 801 default: return 0; 802 case ARMISD::Wrapper: return "ARMISD::Wrapper"; 803 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN"; 804 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC"; 805 case ARMISD::WrapperJT: return "ARMISD::WrapperJT"; 806 case ARMISD::CALL: return "ARMISD::CALL"; 807 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED"; 808 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK"; 809 case ARMISD::tCALL: return "ARMISD::tCALL"; 810 case ARMISD::BRCOND: return "ARMISD::BRCOND"; 811 case ARMISD::BR_JT: return "ARMISD::BR_JT"; 812 case ARMISD::BR2_JT: return "ARMISD::BR2_JT"; 813 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; 814 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; 815 case ARMISD::CMP: return "ARMISD::CMP"; 816 case ARMISD::CMPZ: return "ARMISD::CMPZ"; 817 case ARMISD::CMPFP: return "ARMISD::CMPFP"; 818 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; 819 case ARMISD::BCC_i64: return "ARMISD::BCC_i64"; 820 case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; 821 case ARMISD::CMOV: return "ARMISD::CMOV"; 822 823 case ARMISD::RBIT: return "ARMISD::RBIT"; 824 825 case ARMISD::FTOSI: return "ARMISD::FTOSI"; 826 case ARMISD::FTOUI: return "ARMISD::FTOUI"; 827 case ARMISD::SITOF: return "ARMISD::SITOF"; 828 case ARMISD::UITOF: return "ARMISD::UITOF"; 829 830 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG"; 831 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; 832 case ARMISD::RRX: return "ARMISD::RRX"; 833 834 case ARMISD::ADDC: return "ARMISD::ADDC"; 835 case ARMISD::ADDE: return "ARMISD::ADDE"; 836 case ARMISD::SUBC: return "ARMISD::SUBC"; 837 case ARMISD::SUBE: return "ARMISD::SUBE"; 838 839 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; 840 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR"; 841 842 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP"; 843 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP"; 844 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP"; 845 846 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN"; 847 848 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; 849 850 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC"; 851 852 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER"; 853 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR"; 854 855 case ARMISD::PRELOAD: return "ARMISD::PRELOAD"; 856 857 case ARMISD::VCEQ: return "ARMISD::VCEQ"; 858 case ARMISD::VCEQZ: return "ARMISD::VCEQZ"; 859 case ARMISD::VCGE: return "ARMISD::VCGE"; 860 case ARMISD::VCGEZ: return "ARMISD::VCGEZ"; 861 case ARMISD::VCLEZ: return "ARMISD::VCLEZ"; 862 case ARMISD::VCGEU: return "ARMISD::VCGEU"; 863 case ARMISD::VCGT: return "ARMISD::VCGT"; 864 case ARMISD::VCGTZ: return "ARMISD::VCGTZ"; 865 case ARMISD::VCLTZ: return "ARMISD::VCLTZ"; 866 case ARMISD::VCGTU: return "ARMISD::VCGTU"; 867 case ARMISD::VTST: return "ARMISD::VTST"; 868 869 case ARMISD::VSHL: return "ARMISD::VSHL"; 870 case ARMISD::VSHRs: return "ARMISD::VSHRs"; 871 case ARMISD::VSHRu: return "ARMISD::VSHRu"; 872 case ARMISD::VSHLLs: return "ARMISD::VSHLLs"; 873 case ARMISD::VSHLLu: return "ARMISD::VSHLLu"; 874 case ARMISD::VSHLLi: return "ARMISD::VSHLLi"; 875 case ARMISD::VSHRN: return "ARMISD::VSHRN"; 876 case ARMISD::VRSHRs: return "ARMISD::VRSHRs"; 877 case ARMISD::VRSHRu: return "ARMISD::VRSHRu"; 878 case ARMISD::VRSHRN: return "ARMISD::VRSHRN"; 879 case ARMISD::VQSHLs: return "ARMISD::VQSHLs"; 880 case ARMISD::VQSHLu: return "ARMISD::VQSHLu"; 881 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu"; 882 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs"; 883 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu"; 884 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu"; 885 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs"; 886 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu"; 887 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu"; 888 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu"; 889 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs"; 890 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM"; 891 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM"; 892 case ARMISD::VDUP: return "ARMISD::VDUP"; 893 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; 894 case ARMISD::VEXT: return "ARMISD::VEXT"; 895 case ARMISD::VREV64: return "ARMISD::VREV64"; 896 case ARMISD::VREV32: return "ARMISD::VREV32"; 897 case ARMISD::VREV16: return "ARMISD::VREV16"; 898 case ARMISD::VZIP: return "ARMISD::VZIP"; 899 case ARMISD::VUZP: return "ARMISD::VUZP"; 900 case ARMISD::VTRN: return "ARMISD::VTRN"; 901 case ARMISD::VTBL1: return "ARMISD::VTBL1"; 902 case ARMISD::VTBL2: return "ARMISD::VTBL2"; 903 case ARMISD::VMULLs: return "ARMISD::VMULLs"; 904 case ARMISD::VMULLu: return "ARMISD::VMULLu"; 905 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR"; 906 case ARMISD::FMAX: return "ARMISD::FMAX"; 907 case ARMISD::FMIN: return "ARMISD::FMIN"; 908 case ARMISD::BFI: return "ARMISD::BFI"; 909 case ARMISD::VORRIMM: return "ARMISD::VORRIMM"; 910 case ARMISD::VBICIMM: return "ARMISD::VBICIMM"; 911 case ARMISD::VBSL: return "ARMISD::VBSL"; 912 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP"; 913 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP"; 914 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP"; 915 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD"; 916 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD"; 917 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD"; 918 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD"; 919 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD"; 920 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD"; 921 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD"; 922 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD"; 923 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD"; 924 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD"; 925 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD"; 926 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD"; 927 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD"; 928 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD"; 929 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD"; 930 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD"; 931 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD"; 932 } 933 } 934 935 EVT ARMTargetLowering::getSetCCResultType(EVT VT) const { 936 if (!VT.isVector()) return getPointerTy(); 937 return VT.changeVectorElementTypeToInteger(); 938 } 939 940 /// getRegClassFor - Return the register class that should be used for the 941 /// specified value type. 942 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const { 943 // Map v4i64 to QQ registers but do not make the type legal. Similarly map 944 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to 945 // load / store 4 to 8 consecutive D registers. 946 if (Subtarget->hasNEON()) { 947 if (VT == MVT::v4i64) 948 return ARM::QQPRRegisterClass; 949 else if (VT == MVT::v8i64) 950 return ARM::QQQQPRRegisterClass; 951 } 952 return TargetLowering::getRegClassFor(VT); 953 } 954 955 // Create a fast isel object. 956 FastISel * 957 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 958 return ARM::createFastISel(funcInfo); 959 } 960 961 /// getMaximalGlobalOffset - Returns the maximal possible offset which can 962 /// be used for loads / stores from the global. 963 unsigned ARMTargetLowering::getMaximalGlobalOffset() const { 964 return (Subtarget->isThumb1Only() ? 127 : 4095); 965 } 966 967 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const { 968 unsigned NumVals = N->getNumValues(); 969 if (!NumVals) 970 return Sched::RegPressure; 971 972 for (unsigned i = 0; i != NumVals; ++i) { 973 EVT VT = N->getValueType(i); 974 if (VT == MVT::Glue || VT == MVT::Other) 975 continue; 976 if (VT.isFloatingPoint() || VT.isVector()) 977 return Sched::Latency; 978 } 979 980 if (!N->isMachineOpcode()) 981 return Sched::RegPressure; 982 983 // Load are scheduled for latency even if there instruction itinerary 984 // is not available. 985 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 986 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); 987 988 if (MCID.getNumDefs() == 0) 989 return Sched::RegPressure; 990 if (!Itins->isEmpty() && 991 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2) 992 return Sched::Latency; 993 994 return Sched::RegPressure; 995 } 996 997 //===----------------------------------------------------------------------===// 998 // Lowering Code 999 //===----------------------------------------------------------------------===// 1000 1001 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC 1002 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 1003 switch (CC) { 1004 default: llvm_unreachable("Unknown condition code!"); 1005 case ISD::SETNE: return ARMCC::NE; 1006 case ISD::SETEQ: return ARMCC::EQ; 1007 case ISD::SETGT: return ARMCC::GT; 1008 case ISD::SETGE: return ARMCC::GE; 1009 case ISD::SETLT: return ARMCC::LT; 1010 case ISD::SETLE: return ARMCC::LE; 1011 case ISD::SETUGT: return ARMCC::HI; 1012 case ISD::SETUGE: return ARMCC::HS; 1013 case ISD::SETULT: return ARMCC::LO; 1014 case ISD::SETULE: return ARMCC::LS; 1015 } 1016 } 1017 1018 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. 1019 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, 1020 ARMCC::CondCodes &CondCode2) { 1021 CondCode2 = ARMCC::AL; 1022 switch (CC) { 1023 default: llvm_unreachable("Unknown FP condition!"); 1024 case ISD::SETEQ: 1025 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 1026 case ISD::SETGT: 1027 case ISD::SETOGT: CondCode = ARMCC::GT; break; 1028 case ISD::SETGE: 1029 case ISD::SETOGE: CondCode = ARMCC::GE; break; 1030 case ISD::SETOLT: CondCode = ARMCC::MI; break; 1031 case ISD::SETOLE: CondCode = ARMCC::LS; break; 1032 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; 1033 case ISD::SETO: CondCode = ARMCC::VC; break; 1034 case ISD::SETUO: CondCode = ARMCC::VS; break; 1035 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; 1036 case ISD::SETUGT: CondCode = ARMCC::HI; break; 1037 case ISD::SETUGE: CondCode = ARMCC::PL; break; 1038 case ISD::SETLT: 1039 case ISD::SETULT: CondCode = ARMCC::LT; break; 1040 case ISD::SETLE: 1041 case ISD::SETULE: CondCode = ARMCC::LE; break; 1042 case ISD::SETNE: 1043 case ISD::SETUNE: CondCode = ARMCC::NE; break; 1044 } 1045 } 1046 1047 //===----------------------------------------------------------------------===// 1048 // Calling Convention Implementation 1049 //===----------------------------------------------------------------------===// 1050 1051 #include "ARMGenCallingConv.inc" 1052 1053 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the 1054 /// given CallingConvention value. 1055 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC, 1056 bool Return, 1057 bool isVarArg) const { 1058 switch (CC) { 1059 default: 1060 llvm_unreachable("Unsupported calling convention"); 1061 case CallingConv::Fast: 1062 if (Subtarget->hasVFP2() && !isVarArg) { 1063 if (!Subtarget->isAAPCS_ABI()) 1064 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS); 1065 // For AAPCS ABI targets, just use VFP variant of the calling convention. 1066 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1067 } 1068 // Fallthrough 1069 case CallingConv::C: { 1070 // Use target triple & subtarget features to do actual dispatch. 1071 if (!Subtarget->isAAPCS_ABI()) 1072 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS); 1073 else if (Subtarget->hasVFP2() && 1074 FloatABIType == FloatABI::Hard && !isVarArg) 1075 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1076 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS); 1077 } 1078 case CallingConv::ARM_AAPCS_VFP: 1079 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1080 case CallingConv::ARM_AAPCS: 1081 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS); 1082 case CallingConv::ARM_APCS: 1083 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS); 1084 } 1085 } 1086 1087 /// LowerCallResult - Lower the result values of a call into the 1088 /// appropriate copies out of appropriate physical registers. 1089 SDValue 1090 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1091 CallingConv::ID CallConv, bool isVarArg, 1092 const SmallVectorImpl<ISD::InputArg> &Ins, 1093 DebugLoc dl, SelectionDAG &DAG, 1094 SmallVectorImpl<SDValue> &InVals) const { 1095 1096 // Assign locations to each value returned by this call. 1097 SmallVector<CCValAssign, 16> RVLocs; 1098 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1099 getTargetMachine(), RVLocs, *DAG.getContext(), Call); 1100 CCInfo.AnalyzeCallResult(Ins, 1101 CCAssignFnForNode(CallConv, /* Return*/ true, 1102 isVarArg)); 1103 1104 // Copy all of the result registers out of their specified physreg. 1105 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1106 CCValAssign VA = RVLocs[i]; 1107 1108 SDValue Val; 1109 if (VA.needsCustom()) { 1110 // Handle f64 or half of a v2f64. 1111 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1112 InFlag); 1113 Chain = Lo.getValue(1); 1114 InFlag = Lo.getValue(2); 1115 VA = RVLocs[++i]; // skip ahead to next loc 1116 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1117 InFlag); 1118 Chain = Hi.getValue(1); 1119 InFlag = Hi.getValue(2); 1120 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 1121 1122 if (VA.getLocVT() == MVT::v2f64) { 1123 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 1124 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 1125 DAG.getConstant(0, MVT::i32)); 1126 1127 VA = RVLocs[++i]; // skip ahead to next loc 1128 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 1129 Chain = Lo.getValue(1); 1130 InFlag = Lo.getValue(2); 1131 VA = RVLocs[++i]; // skip ahead to next loc 1132 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 1133 Chain = Hi.getValue(1); 1134 InFlag = Hi.getValue(2); 1135 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 1136 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 1137 DAG.getConstant(1, MVT::i32)); 1138 } 1139 } else { 1140 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), 1141 InFlag); 1142 Chain = Val.getValue(1); 1143 InFlag = Val.getValue(2); 1144 } 1145 1146 switch (VA.getLocInfo()) { 1147 default: llvm_unreachable("Unknown loc info!"); 1148 case CCValAssign::Full: break; 1149 case CCValAssign::BCvt: 1150 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); 1151 break; 1152 } 1153 1154 InVals.push_back(Val); 1155 } 1156 1157 return Chain; 1158 } 1159 1160 /// LowerMemOpCallTo - Store the argument to the stack. 1161 SDValue 1162 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, 1163 SDValue StackPtr, SDValue Arg, 1164 DebugLoc dl, SelectionDAG &DAG, 1165 const CCValAssign &VA, 1166 ISD::ArgFlagsTy Flags) const { 1167 unsigned LocMemOffset = VA.getLocMemOffset(); 1168 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1169 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1170 return DAG.getStore(Chain, dl, Arg, PtrOff, 1171 MachinePointerInfo::getStack(LocMemOffset), 1172 false, false, 0); 1173 } 1174 1175 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 1176 SDValue Chain, SDValue &Arg, 1177 RegsToPassVector &RegsToPass, 1178 CCValAssign &VA, CCValAssign &NextVA, 1179 SDValue &StackPtr, 1180 SmallVector<SDValue, 8> &MemOpChains, 1181 ISD::ArgFlagsTy Flags) const { 1182 1183 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, 1184 DAG.getVTList(MVT::i32, MVT::i32), Arg); 1185 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd)); 1186 1187 if (NextVA.isRegLoc()) 1188 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1))); 1189 else { 1190 assert(NextVA.isMemLoc()); 1191 if (StackPtr.getNode() == 0) 1192 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 1193 1194 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1), 1195 dl, DAG, NextVA, 1196 Flags)); 1197 } 1198 } 1199 1200 /// LowerCall - Lowering a call into a callseq_start <- 1201 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter 1202 /// nodes. 1203 SDValue 1204 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1205 CallingConv::ID CallConv, bool isVarArg, 1206 bool &isTailCall, 1207 const SmallVectorImpl<ISD::OutputArg> &Outs, 1208 const SmallVectorImpl<SDValue> &OutVals, 1209 const SmallVectorImpl<ISD::InputArg> &Ins, 1210 DebugLoc dl, SelectionDAG &DAG, 1211 SmallVectorImpl<SDValue> &InVals) const { 1212 MachineFunction &MF = DAG.getMachineFunction(); 1213 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); 1214 bool IsSibCall = false; 1215 // Temporarily disable tail calls so things don't break. 1216 if (!EnableARMTailCalls) 1217 isTailCall = false; 1218 if (isTailCall) { 1219 // Check if it's really possible to do a tail call. 1220 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 1221 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 1222 Outs, OutVals, Ins, DAG); 1223 // We don't support GuaranteedTailCallOpt for ARM, only automatically 1224 // detected sibcalls. 1225 if (isTailCall) { 1226 ++NumTailCalls; 1227 IsSibCall = true; 1228 } 1229 } 1230 1231 // Analyze operands of the call, assigning locations to each operand. 1232 SmallVector<CCValAssign, 16> ArgLocs; 1233 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1234 getTargetMachine(), ArgLocs, *DAG.getContext(), Call); 1235 CCInfo.AnalyzeCallOperands(Outs, 1236 CCAssignFnForNode(CallConv, /* Return*/ false, 1237 isVarArg)); 1238 1239 // Get a count of how many bytes are to be pushed on the stack. 1240 unsigned NumBytes = CCInfo.getNextStackOffset(); 1241 1242 // For tail calls, memory operands are available in our caller's stack. 1243 if (IsSibCall) 1244 NumBytes = 0; 1245 1246 // Adjust the stack pointer for the new arguments... 1247 // These operations are automatically eliminated by the prolog/epilog pass 1248 if (!IsSibCall) 1249 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1250 1251 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 1252 1253 RegsToPassVector RegsToPass; 1254 SmallVector<SDValue, 8> MemOpChains; 1255 1256 // Walk the register/memloc assignments, inserting copies/loads. In the case 1257 // of tail call optimization, arguments are handled later. 1258 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 1259 i != e; 1260 ++i, ++realArgIdx) { 1261 CCValAssign &VA = ArgLocs[i]; 1262 SDValue Arg = OutVals[realArgIdx]; 1263 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 1264 bool isByVal = Flags.isByVal(); 1265 1266 // Promote the value if needed. 1267 switch (VA.getLocInfo()) { 1268 default: llvm_unreachable("Unknown loc info!"); 1269 case CCValAssign::Full: break; 1270 case CCValAssign::SExt: 1271 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 1272 break; 1273 case CCValAssign::ZExt: 1274 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 1275 break; 1276 case CCValAssign::AExt: 1277 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 1278 break; 1279 case CCValAssign::BCvt: 1280 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 1281 break; 1282 } 1283 1284 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces 1285 if (VA.needsCustom()) { 1286 if (VA.getLocVT() == MVT::v2f64) { 1287 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1288 DAG.getConstant(0, MVT::i32)); 1289 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1290 DAG.getConstant(1, MVT::i32)); 1291 1292 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, 1293 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1294 1295 VA = ArgLocs[++i]; // skip ahead to next loc 1296 if (VA.isRegLoc()) { 1297 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, 1298 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1299 } else { 1300 assert(VA.isMemLoc()); 1301 1302 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1, 1303 dl, DAG, VA, Flags)); 1304 } 1305 } else { 1306 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i], 1307 StackPtr, MemOpChains, Flags); 1308 } 1309 } else if (VA.isRegLoc()) { 1310 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1311 } else if (isByVal) { 1312 assert(VA.isMemLoc()); 1313 unsigned offset = 0; 1314 1315 // True if this byval aggregate will be split between registers 1316 // and memory. 1317 if (CCInfo.isFirstByValRegValid()) { 1318 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1319 unsigned int i, j; 1320 for (i = 0, j = CCInfo.getFirstByValReg(); j < ARM::R4; i++, j++) { 1321 SDValue Const = DAG.getConstant(4*i, MVT::i32); 1322 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 1323 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 1324 MachinePointerInfo(), 1325 false, false, 0); 1326 MemOpChains.push_back(Load.getValue(1)); 1327 RegsToPass.push_back(std::make_pair(j, Load)); 1328 } 1329 offset = ARM::R4 - CCInfo.getFirstByValReg(); 1330 CCInfo.clearFirstByValReg(); 1331 } 1332 1333 unsigned LocMemOffset = VA.getLocMemOffset(); 1334 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset); 1335 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, 1336 StkPtrOff); 1337 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset); 1338 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset); 1339 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, 1340 MVT::i32); 1341 MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, 1342 Flags.getByValAlign(), 1343 /*isVolatile=*/false, 1344 /*AlwaysInline=*/false, 1345 MachinePointerInfo(0), 1346 MachinePointerInfo(0))); 1347 1348 } else if (!IsSibCall) { 1349 assert(VA.isMemLoc()); 1350 1351 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 1352 dl, DAG, VA, Flags)); 1353 } 1354 } 1355 1356 if (!MemOpChains.empty()) 1357 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1358 &MemOpChains[0], MemOpChains.size()); 1359 1360 // Build a sequence of copy-to-reg nodes chained together with token chain 1361 // and flag operands which copy the outgoing args into the appropriate regs. 1362 SDValue InFlag; 1363 // Tail call byval lowering might overwrite argument registers so in case of 1364 // tail call optimization the copies to registers are lowered later. 1365 if (!isTailCall) 1366 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1367 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1368 RegsToPass[i].second, InFlag); 1369 InFlag = Chain.getValue(1); 1370 } 1371 1372 // For tail calls lower the arguments to the 'real' stack slot. 1373 if (isTailCall) { 1374 // Force all the incoming stack arguments to be loaded from the stack 1375 // before any new outgoing arguments are stored to the stack, because the 1376 // outgoing stack slots may alias the incoming argument stack slots, and 1377 // the alias isn't otherwise explicit. This is slightly more conservative 1378 // than necessary, because it means that each store effectively depends 1379 // on every argument instead of just those arguments it would clobber. 1380 1381 // Do not flag preceding copytoreg stuff together with the following stuff. 1382 InFlag = SDValue(); 1383 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1384 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1385 RegsToPass[i].second, InFlag); 1386 InFlag = Chain.getValue(1); 1387 } 1388 InFlag =SDValue(); 1389 } 1390 1391 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1392 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1393 // node so that legalize doesn't hack it. 1394 bool isDirect = false; 1395 bool isARMFunc = false; 1396 bool isLocalARMFunc = false; 1397 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1398 1399 if (EnableARMLongCalls) { 1400 assert (getTargetMachine().getRelocationModel() == Reloc::Static 1401 && "long-calls with non-static relocation model!"); 1402 // Handle a global address or an external symbol. If it's not one of 1403 // those, the target's already in a register, so we don't need to do 1404 // anything extra. 1405 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1406 const GlobalValue *GV = G->getGlobal(); 1407 // Create a constant pool entry for the callee address 1408 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1409 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, 1410 ARMPCLabelIndex, 1411 ARMCP::CPValue, 0); 1412 // Get the address of the callee into a register 1413 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1414 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1415 Callee = DAG.getLoad(getPointerTy(), dl, 1416 DAG.getEntryNode(), CPAddr, 1417 MachinePointerInfo::getConstantPool(), 1418 false, false, 0); 1419 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) { 1420 const char *Sym = S->getSymbol(); 1421 1422 // Create a constant pool entry for the callee address 1423 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1424 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(), 1425 Sym, ARMPCLabelIndex, 0); 1426 // Get the address of the callee into a register 1427 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1428 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1429 Callee = DAG.getLoad(getPointerTy(), dl, 1430 DAG.getEntryNode(), CPAddr, 1431 MachinePointerInfo::getConstantPool(), 1432 false, false, 0); 1433 } 1434 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1435 const GlobalValue *GV = G->getGlobal(); 1436 isDirect = true; 1437 bool isExt = GV->isDeclaration() || GV->isWeakForLinker(); 1438 bool isStub = (isExt && Subtarget->isTargetDarwin()) && 1439 getTargetMachine().getRelocationModel() != Reloc::Static; 1440 isARMFunc = !Subtarget->isThumb() || isStub; 1441 // ARM call to a local ARM function is predicable. 1442 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking); 1443 // tBX takes a register source operand. 1444 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1445 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1446 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, 1447 ARMPCLabelIndex, 1448 ARMCP::CPValue, 4); 1449 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1450 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1451 Callee = DAG.getLoad(getPointerTy(), dl, 1452 DAG.getEntryNode(), CPAddr, 1453 MachinePointerInfo::getConstantPool(), 1454 false, false, 0); 1455 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1456 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1457 getPointerTy(), Callee, PICLabel); 1458 } else { 1459 // On ELF targets for PIC code, direct calls should go through the PLT 1460 unsigned OpFlags = 0; 1461 if (Subtarget->isTargetELF() && 1462 getTargetMachine().getRelocationModel() == Reloc::PIC_) 1463 OpFlags = ARMII::MO_PLT; 1464 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 1465 } 1466 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1467 isDirect = true; 1468 bool isStub = Subtarget->isTargetDarwin() && 1469 getTargetMachine().getRelocationModel() != Reloc::Static; 1470 isARMFunc = !Subtarget->isThumb() || isStub; 1471 // tBX takes a register source operand. 1472 const char *Sym = S->getSymbol(); 1473 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1474 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1475 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(), 1476 Sym, ARMPCLabelIndex, 4); 1477 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1478 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1479 Callee = DAG.getLoad(getPointerTy(), dl, 1480 DAG.getEntryNode(), CPAddr, 1481 MachinePointerInfo::getConstantPool(), 1482 false, false, 0); 1483 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1484 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1485 getPointerTy(), Callee, PICLabel); 1486 } else { 1487 unsigned OpFlags = 0; 1488 // On ELF targets for PIC code, direct calls should go through the PLT 1489 if (Subtarget->isTargetELF() && 1490 getTargetMachine().getRelocationModel() == Reloc::PIC_) 1491 OpFlags = ARMII::MO_PLT; 1492 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags); 1493 } 1494 } 1495 1496 // FIXME: handle tail calls differently. 1497 unsigned CallOpc; 1498 if (Subtarget->isThumb()) { 1499 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps()) 1500 CallOpc = ARMISD::CALL_NOLINK; 1501 else 1502 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; 1503 } else { 1504 CallOpc = (isDirect || Subtarget->hasV5TOps()) 1505 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL) 1506 : ARMISD::CALL_NOLINK; 1507 } 1508 1509 std::vector<SDValue> Ops; 1510 Ops.push_back(Chain); 1511 Ops.push_back(Callee); 1512 1513 // Add argument registers to the end of the list so that they are known live 1514 // into the call. 1515 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1516 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1517 RegsToPass[i].second.getValueType())); 1518 1519 if (InFlag.getNode()) 1520 Ops.push_back(InFlag); 1521 1522 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1523 if (isTailCall) 1524 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size()); 1525 1526 // Returns a chain and a flag for retval copy to use. 1527 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 1528 InFlag = Chain.getValue(1); 1529 1530 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 1531 DAG.getIntPtrConstant(0, true), InFlag); 1532 if (!Ins.empty()) 1533 InFlag = Chain.getValue(1); 1534 1535 // Handle result values, copying them out of physregs into vregs that we 1536 // return. 1537 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, 1538 dl, DAG, InVals); 1539 } 1540 1541 /// HandleByVal - Every parameter *after* a byval parameter is passed 1542 /// on the stack. Remember the next parameter register to allocate, 1543 /// and then confiscate the rest of the parameter registers to insure 1544 /// this. 1545 void 1546 llvm::ARMTargetLowering::HandleByVal(CCState *State, unsigned &size) const { 1547 unsigned reg = State->AllocateReg(GPRArgRegs, 4); 1548 assert((State->getCallOrPrologue() == Prologue || 1549 State->getCallOrPrologue() == Call) && 1550 "unhandled ParmContext"); 1551 if ((!State->isFirstByValRegValid()) && 1552 (ARM::R0 <= reg) && (reg <= ARM::R3)) { 1553 State->setFirstByValReg(reg); 1554 // At a call site, a byval parameter that is split between 1555 // registers and memory needs its size truncated here. In a 1556 // function prologue, such byval parameters are reassembled in 1557 // memory, and are not truncated. 1558 if (State->getCallOrPrologue() == Call) { 1559 unsigned excess = 4 * (ARM::R4 - reg); 1560 assert(size >= excess && "expected larger existing stack allocation"); 1561 size -= excess; 1562 } 1563 } 1564 // Confiscate any remaining parameter registers to preclude their 1565 // assignment to subsequent parameters. 1566 while (State->AllocateReg(GPRArgRegs, 4)) 1567 ; 1568 } 1569 1570 /// MatchingStackOffset - Return true if the given stack call argument is 1571 /// already available in the same position (relatively) of the caller's 1572 /// incoming argument stack. 1573 static 1574 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 1575 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 1576 const ARMInstrInfo *TII) { 1577 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 1578 int FI = INT_MAX; 1579 if (Arg.getOpcode() == ISD::CopyFromReg) { 1580 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 1581 if (!TargetRegisterInfo::isVirtualRegister(VR)) 1582 return false; 1583 MachineInstr *Def = MRI->getVRegDef(VR); 1584 if (!Def) 1585 return false; 1586 if (!Flags.isByVal()) { 1587 if (!TII->isLoadFromStackSlot(Def, FI)) 1588 return false; 1589 } else { 1590 return false; 1591 } 1592 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 1593 if (Flags.isByVal()) 1594 // ByVal argument is passed in as a pointer but it's now being 1595 // dereferenced. e.g. 1596 // define @foo(%struct.X* %A) { 1597 // tail call @bar(%struct.X* byval %A) 1598 // } 1599 return false; 1600 SDValue Ptr = Ld->getBasePtr(); 1601 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 1602 if (!FINode) 1603 return false; 1604 FI = FINode->getIndex(); 1605 } else 1606 return false; 1607 1608 assert(FI != INT_MAX); 1609 if (!MFI->isFixedObjectIndex(FI)) 1610 return false; 1611 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 1612 } 1613 1614 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 1615 /// for tail call optimization. Targets which want to do tail call 1616 /// optimization should implement this function. 1617 bool 1618 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 1619 CallingConv::ID CalleeCC, 1620 bool isVarArg, 1621 bool isCalleeStructRet, 1622 bool isCallerStructRet, 1623 const SmallVectorImpl<ISD::OutputArg> &Outs, 1624 const SmallVectorImpl<SDValue> &OutVals, 1625 const SmallVectorImpl<ISD::InputArg> &Ins, 1626 SelectionDAG& DAG) const { 1627 const Function *CallerF = DAG.getMachineFunction().getFunction(); 1628 CallingConv::ID CallerCC = CallerF->getCallingConv(); 1629 bool CCMatch = CallerCC == CalleeCC; 1630 1631 // Look for obvious safe cases to perform tail call optimization that do not 1632 // require ABI changes. This is what gcc calls sibcall. 1633 1634 // Do not sibcall optimize vararg calls unless the call site is not passing 1635 // any arguments. 1636 if (isVarArg && !Outs.empty()) 1637 return false; 1638 1639 // Also avoid sibcall optimization if either caller or callee uses struct 1640 // return semantics. 1641 if (isCalleeStructRet || isCallerStructRet) 1642 return false; 1643 1644 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo:: 1645 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as 1646 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation 1647 // support in the assembler and linker to be used. This would need to be 1648 // fixed to fully support tail calls in Thumb1. 1649 // 1650 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take 1651 // LR. This means if we need to reload LR, it takes an extra instructions, 1652 // which outweighs the value of the tail call; but here we don't know yet 1653 // whether LR is going to be used. Probably the right approach is to 1654 // generate the tail call here and turn it back into CALL/RET in 1655 // emitEpilogue if LR is used. 1656 1657 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls, 1658 // but we need to make sure there are enough registers; the only valid 1659 // registers are the 4 used for parameters. We don't currently do this 1660 // case. 1661 if (Subtarget->isThumb1Only()) 1662 return false; 1663 1664 // If the calling conventions do not match, then we'd better make sure the 1665 // results are returned in the same way as what the caller expects. 1666 if (!CCMatch) { 1667 SmallVector<CCValAssign, 16> RVLocs1; 1668 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 1669 getTargetMachine(), RVLocs1, *DAG.getContext(), Call); 1670 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg)); 1671 1672 SmallVector<CCValAssign, 16> RVLocs2; 1673 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 1674 getTargetMachine(), RVLocs2, *DAG.getContext(), Call); 1675 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg)); 1676 1677 if (RVLocs1.size() != RVLocs2.size()) 1678 return false; 1679 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 1680 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 1681 return false; 1682 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 1683 return false; 1684 if (RVLocs1[i].isRegLoc()) { 1685 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 1686 return false; 1687 } else { 1688 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 1689 return false; 1690 } 1691 } 1692 } 1693 1694 // If the callee takes no arguments then go on to check the results of the 1695 // call. 1696 if (!Outs.empty()) { 1697 // Check if stack adjustment is needed. For now, do not do this if any 1698 // argument is passed on the stack. 1699 SmallVector<CCValAssign, 16> ArgLocs; 1700 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 1701 getTargetMachine(), ArgLocs, *DAG.getContext(), Call); 1702 CCInfo.AnalyzeCallOperands(Outs, 1703 CCAssignFnForNode(CalleeCC, false, isVarArg)); 1704 if (CCInfo.getNextStackOffset()) { 1705 MachineFunction &MF = DAG.getMachineFunction(); 1706 1707 // Check if the arguments are already laid out in the right way as 1708 // the caller's fixed stack objects. 1709 MachineFrameInfo *MFI = MF.getFrameInfo(); 1710 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 1711 const ARMInstrInfo *TII = 1712 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo(); 1713 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 1714 i != e; 1715 ++i, ++realArgIdx) { 1716 CCValAssign &VA = ArgLocs[i]; 1717 EVT RegVT = VA.getLocVT(); 1718 SDValue Arg = OutVals[realArgIdx]; 1719 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 1720 if (VA.getLocInfo() == CCValAssign::Indirect) 1721 return false; 1722 if (VA.needsCustom()) { 1723 // f64 and vector types are split into multiple registers or 1724 // register/stack-slot combinations. The types will not match 1725 // the registers; give up on memory f64 refs until we figure 1726 // out what to do about this. 1727 if (!VA.isRegLoc()) 1728 return false; 1729 if (!ArgLocs[++i].isRegLoc()) 1730 return false; 1731 if (RegVT == MVT::v2f64) { 1732 if (!ArgLocs[++i].isRegLoc()) 1733 return false; 1734 if (!ArgLocs[++i].isRegLoc()) 1735 return false; 1736 } 1737 } else if (!VA.isRegLoc()) { 1738 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 1739 MFI, MRI, TII)) 1740 return false; 1741 } 1742 } 1743 } 1744 } 1745 1746 return true; 1747 } 1748 1749 SDValue 1750 ARMTargetLowering::LowerReturn(SDValue Chain, 1751 CallingConv::ID CallConv, bool isVarArg, 1752 const SmallVectorImpl<ISD::OutputArg> &Outs, 1753 const SmallVectorImpl<SDValue> &OutVals, 1754 DebugLoc dl, SelectionDAG &DAG) const { 1755 1756 // CCValAssign - represent the assignment of the return value to a location. 1757 SmallVector<CCValAssign, 16> RVLocs; 1758 1759 // CCState - Info about the registers and stack slots. 1760 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1761 getTargetMachine(), RVLocs, *DAG.getContext(), Call); 1762 1763 // Analyze outgoing return values. 1764 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true, 1765 isVarArg)); 1766 1767 // If this is the first return lowered for this function, add 1768 // the regs to the liveout set for the function. 1769 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 1770 for (unsigned i = 0; i != RVLocs.size(); ++i) 1771 if (RVLocs[i].isRegLoc()) 1772 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 1773 } 1774 1775 SDValue Flag; 1776 1777 // Copy the result values into the output registers. 1778 for (unsigned i = 0, realRVLocIdx = 0; 1779 i != RVLocs.size(); 1780 ++i, ++realRVLocIdx) { 1781 CCValAssign &VA = RVLocs[i]; 1782 assert(VA.isRegLoc() && "Can only return in registers!"); 1783 1784 SDValue Arg = OutVals[realRVLocIdx]; 1785 1786 switch (VA.getLocInfo()) { 1787 default: llvm_unreachable("Unknown loc info!"); 1788 case CCValAssign::Full: break; 1789 case CCValAssign::BCvt: 1790 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 1791 break; 1792 } 1793 1794 if (VA.needsCustom()) { 1795 if (VA.getLocVT() == MVT::v2f64) { 1796 // Extract the first half and return it in two registers. 1797 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1798 DAG.getConstant(0, MVT::i32)); 1799 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, 1800 DAG.getVTList(MVT::i32, MVT::i32), Half); 1801 1802 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag); 1803 Flag = Chain.getValue(1); 1804 VA = RVLocs[++i]; // skip ahead to next loc 1805 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 1806 HalfGPRs.getValue(1), Flag); 1807 Flag = Chain.getValue(1); 1808 VA = RVLocs[++i]; // skip ahead to next loc 1809 1810 // Extract the 2nd half and fall through to handle it as an f64 value. 1811 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1812 DAG.getConstant(1, MVT::i32)); 1813 } 1814 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is 1815 // available. 1816 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, 1817 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1); 1818 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag); 1819 Flag = Chain.getValue(1); 1820 VA = RVLocs[++i]; // skip ahead to next loc 1821 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1), 1822 Flag); 1823 } else 1824 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); 1825 1826 // Guarantee that all emitted copies are 1827 // stuck together, avoiding something bad. 1828 Flag = Chain.getValue(1); 1829 } 1830 1831 SDValue result; 1832 if (Flag.getNode()) 1833 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 1834 else // Return Void 1835 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain); 1836 1837 return result; 1838 } 1839 1840 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const { 1841 if (N->getNumValues() != 1) 1842 return false; 1843 if (!N->hasNUsesOfValue(1, 0)) 1844 return false; 1845 1846 unsigned NumCopies = 0; 1847 SDNode* Copies[2]; 1848 SDNode *Use = *N->use_begin(); 1849 if (Use->getOpcode() == ISD::CopyToReg) { 1850 Copies[NumCopies++] = Use; 1851 } else if (Use->getOpcode() == ARMISD::VMOVRRD) { 1852 // f64 returned in a pair of GPRs. 1853 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end(); 1854 UI != UE; ++UI) { 1855 if (UI->getOpcode() != ISD::CopyToReg) 1856 return false; 1857 Copies[UI.getUse().getResNo()] = *UI; 1858 ++NumCopies; 1859 } 1860 } else if (Use->getOpcode() == ISD::BITCAST) { 1861 // f32 returned in a single GPR. 1862 if (!Use->hasNUsesOfValue(1, 0)) 1863 return false; 1864 Use = *Use->use_begin(); 1865 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0)) 1866 return false; 1867 Copies[NumCopies++] = Use; 1868 } else { 1869 return false; 1870 } 1871 1872 if (NumCopies != 1 && NumCopies != 2) 1873 return false; 1874 1875 bool HasRet = false; 1876 for (unsigned i = 0; i < NumCopies; ++i) { 1877 SDNode *Copy = Copies[i]; 1878 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1879 UI != UE; ++UI) { 1880 if (UI->getOpcode() == ISD::CopyToReg) { 1881 SDNode *Use = *UI; 1882 if (Use == Copies[0] || Use == Copies[1]) 1883 continue; 1884 return false; 1885 } 1886 if (UI->getOpcode() != ARMISD::RET_FLAG) 1887 return false; 1888 HasRet = true; 1889 } 1890 } 1891 1892 return HasRet; 1893 } 1894 1895 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1896 if (!EnableARMTailCalls) 1897 return false; 1898 1899 if (!CI->isTailCall()) 1900 return false; 1901 1902 return !Subtarget->isThumb1Only(); 1903 } 1904 1905 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 1906 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is 1907 // one of the above mentioned nodes. It has to be wrapped because otherwise 1908 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 1909 // be used to form addressing mode. These wrapped nodes will be selected 1910 // into MOVi. 1911 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 1912 EVT PtrVT = Op.getValueType(); 1913 // FIXME there is no actual debug info here 1914 DebugLoc dl = Op.getDebugLoc(); 1915 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1916 SDValue Res; 1917 if (CP->isMachineConstantPoolEntry()) 1918 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 1919 CP->getAlignment()); 1920 else 1921 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 1922 CP->getAlignment()); 1923 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res); 1924 } 1925 1926 unsigned ARMTargetLowering::getJumpTableEncoding() const { 1927 return MachineJumpTableInfo::EK_Inline; 1928 } 1929 1930 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op, 1931 SelectionDAG &DAG) const { 1932 MachineFunction &MF = DAG.getMachineFunction(); 1933 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1934 unsigned ARMPCLabelIndex = 0; 1935 DebugLoc DL = Op.getDebugLoc(); 1936 EVT PtrVT = getPointerTy(); 1937 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1938 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 1939 SDValue CPAddr; 1940 if (RelocM == Reloc::Static) { 1941 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4); 1942 } else { 1943 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 1944 ARMPCLabelIndex = AFI->createPICLabelUId(); 1945 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex, 1946 ARMCP::CPBlockAddress, 1947 PCAdj); 1948 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1949 } 1950 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr); 1951 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr, 1952 MachinePointerInfo::getConstantPool(), 1953 false, false, 0); 1954 if (RelocM == Reloc::Static) 1955 return Result; 1956 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1957 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel); 1958 } 1959 1960 // Lower ISD::GlobalTLSAddress using the "general dynamic" model 1961 SDValue 1962 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 1963 SelectionDAG &DAG) const { 1964 DebugLoc dl = GA->getDebugLoc(); 1965 EVT PtrVT = getPointerTy(); 1966 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 1967 MachineFunction &MF = DAG.getMachineFunction(); 1968 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1969 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1970 ARMConstantPoolValue *CPV = 1971 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, 1972 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true); 1973 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1974 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument); 1975 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, 1976 MachinePointerInfo::getConstantPool(), 1977 false, false, 0); 1978 SDValue Chain = Argument.getValue(1); 1979 1980 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1981 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel); 1982 1983 // call __tls_get_addr. 1984 ArgListTy Args; 1985 ArgListEntry Entry; 1986 Entry.Node = Argument; 1987 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext()); 1988 Args.push_back(Entry); 1989 // FIXME: is there useful debug info available here? 1990 std::pair<SDValue, SDValue> CallResult = 1991 LowerCallTo(Chain, (Type *) Type::getInt32Ty(*DAG.getContext()), 1992 false, false, false, false, 1993 0, CallingConv::C, false, /*isReturnValueUsed=*/true, 1994 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl); 1995 return CallResult.first; 1996 } 1997 1998 // Lower ISD::GlobalTLSAddress using the "initial exec" or 1999 // "local exec" model. 2000 SDValue 2001 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, 2002 SelectionDAG &DAG) const { 2003 const GlobalValue *GV = GA->getGlobal(); 2004 DebugLoc dl = GA->getDebugLoc(); 2005 SDValue Offset; 2006 SDValue Chain = DAG.getEntryNode(); 2007 EVT PtrVT = getPointerTy(); 2008 // Get the Thread Pointer 2009 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 2010 2011 if (GV->isDeclaration()) { 2012 MachineFunction &MF = DAG.getMachineFunction(); 2013 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2014 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2015 // Initial exec model. 2016 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 2017 ARMConstantPoolValue *CPV = 2018 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, 2019 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, true); 2020 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2021 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 2022 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2023 MachinePointerInfo::getConstantPool(), 2024 false, false, 0); 2025 Chain = Offset.getValue(1); 2026 2027 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2028 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel); 2029 2030 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2031 MachinePointerInfo::getConstantPool(), 2032 false, false, 0); 2033 } else { 2034 // local exec model 2035 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMCP::TPOFF); 2036 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2037 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 2038 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2039 MachinePointerInfo::getConstantPool(), 2040 false, false, 0); 2041 } 2042 2043 // The address of the thread local variable is the add of the thread 2044 // pointer with the offset of the variable. 2045 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 2046 } 2047 2048 SDValue 2049 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 2050 // TODO: implement the "local dynamic" model 2051 assert(Subtarget->isTargetELF() && 2052 "TLS not implemented for non-ELF targets"); 2053 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 2054 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 2055 // otherwise use the "Local Exec" TLS Model 2056 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 2057 return LowerToTLSGeneralDynamicModel(GA, DAG); 2058 else 2059 return LowerToTLSExecModels(GA, DAG); 2060 } 2061 2062 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, 2063 SelectionDAG &DAG) const { 2064 EVT PtrVT = getPointerTy(); 2065 DebugLoc dl = Op.getDebugLoc(); 2066 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 2067 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2068 if (RelocM == Reloc::PIC_) { 2069 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility(); 2070 ARMConstantPoolValue *CPV = 2071 new ARMConstantPoolValue(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT); 2072 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2073 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2074 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 2075 CPAddr, 2076 MachinePointerInfo::getConstantPool(), 2077 false, false, 0); 2078 SDValue Chain = Result.getValue(1); 2079 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT); 2080 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT); 2081 if (!UseGOTOFF) 2082 Result = DAG.getLoad(PtrVT, dl, Chain, Result, 2083 MachinePointerInfo::getGOT(), false, false, 0); 2084 return Result; 2085 } 2086 2087 // If we have T2 ops, we can materialize the address directly via movt/movw 2088 // pair. This is always cheaper. 2089 if (Subtarget->useMovt()) { 2090 ++NumMovwMovt; 2091 // FIXME: Once remat is capable of dealing with instructions with register 2092 // operands, expand this into two nodes. 2093 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT, 2094 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2095 } else { 2096 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 2097 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2098 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2099 MachinePointerInfo::getConstantPool(), 2100 false, false, 0); 2101 } 2102 } 2103 2104 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, 2105 SelectionDAG &DAG) const { 2106 EVT PtrVT = getPointerTy(); 2107 DebugLoc dl = Op.getDebugLoc(); 2108 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 2109 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2110 MachineFunction &MF = DAG.getMachineFunction(); 2111 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2112 2113 // FIXME: Enable this for static codegen when tool issues are fixed. 2114 if (Subtarget->useMovt() && RelocM != Reloc::Static) { 2115 ++NumMovwMovt; 2116 // FIXME: Once remat is capable of dealing with instructions with register 2117 // operands, expand this into two nodes. 2118 if (RelocM == Reloc::Static) 2119 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT, 2120 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2121 2122 unsigned Wrapper = (RelocM == Reloc::PIC_) 2123 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN; 2124 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, 2125 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2126 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) 2127 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result, 2128 MachinePointerInfo::getGOT(), false, false, 0); 2129 return Result; 2130 } 2131 2132 unsigned ARMPCLabelIndex = 0; 2133 SDValue CPAddr; 2134 if (RelocM == Reloc::Static) { 2135 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 2136 } else { 2137 ARMPCLabelIndex = AFI->createPICLabelUId(); 2138 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8); 2139 ARMConstantPoolValue *CPV = 2140 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj); 2141 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2142 } 2143 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2144 2145 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2146 MachinePointerInfo::getConstantPool(), 2147 false, false, 0); 2148 SDValue Chain = Result.getValue(1); 2149 2150 if (RelocM == Reloc::PIC_) { 2151 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2152 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2153 } 2154 2155 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) 2156 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(), 2157 false, false, 0); 2158 2159 return Result; 2160 } 2161 2162 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, 2163 SelectionDAG &DAG) const { 2164 assert(Subtarget->isTargetELF() && 2165 "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); 2166 MachineFunction &MF = DAG.getMachineFunction(); 2167 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2168 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2169 EVT PtrVT = getPointerTy(); 2170 DebugLoc dl = Op.getDebugLoc(); 2171 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 2172 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(), 2173 "_GLOBAL_OFFSET_TABLE_", 2174 ARMPCLabelIndex, PCAdj); 2175 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2176 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2177 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2178 MachinePointerInfo::getConstantPool(), 2179 false, false, 0); 2180 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2181 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2182 } 2183 2184 SDValue 2185 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG) 2186 const { 2187 DebugLoc dl = Op.getDebugLoc(); 2188 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other, 2189 Op.getOperand(0), Op.getOperand(1)); 2190 } 2191 2192 SDValue 2193 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const { 2194 DebugLoc dl = Op.getDebugLoc(); 2195 SDValue Val = DAG.getConstant(0, MVT::i32); 2196 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0), 2197 Op.getOperand(1), Val); 2198 } 2199 2200 SDValue 2201 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const { 2202 DebugLoc dl = Op.getDebugLoc(); 2203 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0), 2204 Op.getOperand(1), DAG.getConstant(0, MVT::i32)); 2205 } 2206 2207 SDValue 2208 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 2209 const ARMSubtarget *Subtarget) const { 2210 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 2211 DebugLoc dl = Op.getDebugLoc(); 2212 switch (IntNo) { 2213 default: return SDValue(); // Don't custom lower most intrinsics. 2214 case Intrinsic::arm_thread_pointer: { 2215 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2216 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 2217 } 2218 case Intrinsic::eh_sjlj_lsda: { 2219 MachineFunction &MF = DAG.getMachineFunction(); 2220 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2221 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2222 EVT PtrVT = getPointerTy(); 2223 DebugLoc dl = Op.getDebugLoc(); 2224 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2225 SDValue CPAddr; 2226 unsigned PCAdj = (RelocM != Reloc::PIC_) 2227 ? 0 : (Subtarget->isThumb() ? 4 : 8); 2228 ARMConstantPoolValue *CPV = 2229 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex, 2230 ARMCP::CPLSDA, PCAdj); 2231 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2232 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2233 SDValue Result = 2234 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2235 MachinePointerInfo::getConstantPool(), 2236 false, false, 0); 2237 2238 if (RelocM == Reloc::PIC_) { 2239 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2240 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2241 } 2242 return Result; 2243 } 2244 case Intrinsic::arm_neon_vmulls: 2245 case Intrinsic::arm_neon_vmullu: { 2246 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls) 2247 ? ARMISD::VMULLs : ARMISD::VMULLu; 2248 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(), 2249 Op.getOperand(1), Op.getOperand(2)); 2250 } 2251 } 2252 } 2253 2254 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG, 2255 const ARMSubtarget *Subtarget) { 2256 DebugLoc dl = Op.getDebugLoc(); 2257 if (!Subtarget->hasDataBarrier()) { 2258 // Some ARMv6 cpus can support data barriers with an mcr instruction. 2259 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get 2260 // here. 2261 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() && 2262 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!"); 2263 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0), 2264 DAG.getConstant(0, MVT::i32)); 2265 } 2266 2267 SDValue Op5 = Op.getOperand(5); 2268 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0; 2269 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 2270 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 2271 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0); 2272 2273 ARM_MB::MemBOpt DMBOpt; 2274 if (isDeviceBarrier) 2275 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY; 2276 else 2277 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH; 2278 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), 2279 DAG.getConstant(DMBOpt, MVT::i32)); 2280 } 2281 2282 2283 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, 2284 const ARMSubtarget *Subtarget) { 2285 // FIXME: handle "fence singlethread" more efficiently. 2286 DebugLoc dl = Op.getDebugLoc(); 2287 if (!Subtarget->hasDataBarrier()) { 2288 // Some ARMv6 cpus can support data barriers with an mcr instruction. 2289 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get 2290 // here. 2291 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() && 2292 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!"); 2293 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0), 2294 DAG.getConstant(0, MVT::i32)); 2295 } 2296 2297 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), 2298 DAG.getConstant(ARM_MB::ISH, MVT::i32)); 2299 } 2300 2301 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG, 2302 const ARMSubtarget *Subtarget) { 2303 // ARM pre v5TE and Thumb1 does not have preload instructions. 2304 if (!(Subtarget->isThumb2() || 2305 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps()))) 2306 // Just preserve the chain. 2307 return Op.getOperand(0); 2308 2309 DebugLoc dl = Op.getDebugLoc(); 2310 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1; 2311 if (!isRead && 2312 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension())) 2313 // ARMv7 with MP extension has PLDW. 2314 return Op.getOperand(0); 2315 2316 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 2317 if (Subtarget->isThumb()) { 2318 // Invert the bits. 2319 isRead = ~isRead & 1; 2320 isData = ~isData & 1; 2321 } 2322 2323 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0), 2324 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32), 2325 DAG.getConstant(isData, MVT::i32)); 2326 } 2327 2328 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) { 2329 MachineFunction &MF = DAG.getMachineFunction(); 2330 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>(); 2331 2332 // vastart just stores the address of the VarArgsFrameIndex slot into the 2333 // memory location argument. 2334 DebugLoc dl = Op.getDebugLoc(); 2335 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2336 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2337 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2338 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), 2339 MachinePointerInfo(SV), false, false, 0); 2340 } 2341 2342 SDValue 2343 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 2344 SDValue &Root, SelectionDAG &DAG, 2345 DebugLoc dl) const { 2346 MachineFunction &MF = DAG.getMachineFunction(); 2347 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2348 2349 TargetRegisterClass *RC; 2350 if (AFI->isThumb1OnlyFunction()) 2351 RC = ARM::tGPRRegisterClass; 2352 else 2353 RC = ARM::GPRRegisterClass; 2354 2355 // Transform the arguments stored in physical registers into virtual ones. 2356 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2357 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 2358 2359 SDValue ArgValue2; 2360 if (NextVA.isMemLoc()) { 2361 MachineFrameInfo *MFI = MF.getFrameInfo(); 2362 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true); 2363 2364 // Create load node to retrieve arguments from the stack. 2365 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2366 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, 2367 MachinePointerInfo::getFixedStack(FI), 2368 false, false, 0); 2369 } else { 2370 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); 2371 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 2372 } 2373 2374 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2); 2375 } 2376 2377 void 2378 ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF, 2379 unsigned &VARegSize, unsigned &VARegSaveSize) 2380 const { 2381 unsigned NumGPRs; 2382 if (CCInfo.isFirstByValRegValid()) 2383 NumGPRs = ARM::R4 - CCInfo.getFirstByValReg(); 2384 else { 2385 unsigned int firstUnalloced; 2386 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs, 2387 sizeof(GPRArgRegs) / 2388 sizeof(GPRArgRegs[0])); 2389 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0; 2390 } 2391 2392 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment(); 2393 VARegSize = NumGPRs * 4; 2394 VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); 2395 } 2396 2397 // The remaining GPRs hold either the beginning of variable-argument 2398 // data, or the beginning of an aggregate passed by value (usuall 2399 // byval). Either way, we allocate stack slots adjacent to the data 2400 // provided by our caller, and store the unallocated registers there. 2401 // If this is a variadic function, the va_list pointer will begin with 2402 // these values; otherwise, this reassembles a (byval) structure that 2403 // was split between registers and memory. 2404 void 2405 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 2406 DebugLoc dl, SDValue &Chain, 2407 unsigned ArgOffset) const { 2408 MachineFunction &MF = DAG.getMachineFunction(); 2409 MachineFrameInfo *MFI = MF.getFrameInfo(); 2410 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2411 unsigned firstRegToSaveIndex; 2412 if (CCInfo.isFirstByValRegValid()) 2413 firstRegToSaveIndex = CCInfo.getFirstByValReg() - ARM::R0; 2414 else { 2415 firstRegToSaveIndex = CCInfo.getFirstUnallocated 2416 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0])); 2417 } 2418 2419 unsigned VARegSize, VARegSaveSize; 2420 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize); 2421 if (VARegSaveSize) { 2422 // If this function is vararg, store any remaining integer argument regs 2423 // to their spots on the stack so that they may be loaded by deferencing 2424 // the result of va_next. 2425 AFI->setVarArgsRegSaveSize(VARegSaveSize); 2426 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(VARegSaveSize, 2427 ArgOffset + VARegSaveSize 2428 - VARegSize, 2429 false)); 2430 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), 2431 getPointerTy()); 2432 2433 SmallVector<SDValue, 4> MemOps; 2434 for (; firstRegToSaveIndex < 4; ++firstRegToSaveIndex) { 2435 TargetRegisterClass *RC; 2436 if (AFI->isThumb1OnlyFunction()) 2437 RC = ARM::tGPRRegisterClass; 2438 else 2439 RC = ARM::GPRRegisterClass; 2440 2441 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC); 2442 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 2443 SDValue Store = 2444 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2445 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()), 2446 false, false, 0); 2447 MemOps.push_back(Store); 2448 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, 2449 DAG.getConstant(4, getPointerTy())); 2450 } 2451 if (!MemOps.empty()) 2452 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2453 &MemOps[0], MemOps.size()); 2454 } else 2455 // This will point to the next argument passed via stack. 2456 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true)); 2457 } 2458 2459 SDValue 2460 ARMTargetLowering::LowerFormalArguments(SDValue Chain, 2461 CallingConv::ID CallConv, bool isVarArg, 2462 const SmallVectorImpl<ISD::InputArg> 2463 &Ins, 2464 DebugLoc dl, SelectionDAG &DAG, 2465 SmallVectorImpl<SDValue> &InVals) 2466 const { 2467 MachineFunction &MF = DAG.getMachineFunction(); 2468 MachineFrameInfo *MFI = MF.getFrameInfo(); 2469 2470 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2471 2472 // Assign locations to all of the incoming arguments. 2473 SmallVector<CCValAssign, 16> ArgLocs; 2474 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2475 getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue); 2476 CCInfo.AnalyzeFormalArguments(Ins, 2477 CCAssignFnForNode(CallConv, /* Return*/ false, 2478 isVarArg)); 2479 2480 SmallVector<SDValue, 16> ArgValues; 2481 int lastInsIndex = -1; 2482 2483 SDValue ArgValue; 2484 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2485 CCValAssign &VA = ArgLocs[i]; 2486 2487 // Arguments stored in registers. 2488 if (VA.isRegLoc()) { 2489 EVT RegVT = VA.getLocVT(); 2490 2491 if (VA.needsCustom()) { 2492 // f64 and vector types are split up into multiple registers or 2493 // combinations of registers and stack slots. 2494 if (VA.getLocVT() == MVT::v2f64) { 2495 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i], 2496 Chain, DAG, dl); 2497 VA = ArgLocs[++i]; // skip ahead to next loc 2498 SDValue ArgValue2; 2499 if (VA.isMemLoc()) { 2500 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true); 2501 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2502 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN, 2503 MachinePointerInfo::getFixedStack(FI), 2504 false, false, 0); 2505 } else { 2506 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], 2507 Chain, DAG, dl); 2508 } 2509 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 2510 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 2511 ArgValue, ArgValue1, DAG.getIntPtrConstant(0)); 2512 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 2513 ArgValue, ArgValue2, DAG.getIntPtrConstant(1)); 2514 } else 2515 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); 2516 2517 } else { 2518 TargetRegisterClass *RC; 2519 2520 if (RegVT == MVT::f32) 2521 RC = ARM::SPRRegisterClass; 2522 else if (RegVT == MVT::f64) 2523 RC = ARM::DPRRegisterClass; 2524 else if (RegVT == MVT::v2f64) 2525 RC = ARM::QPRRegisterClass; 2526 else if (RegVT == MVT::i32) 2527 RC = (AFI->isThumb1OnlyFunction() ? 2528 ARM::tGPRRegisterClass : ARM::GPRRegisterClass); 2529 else 2530 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering"); 2531 2532 // Transform the arguments in physical registers into virtual ones. 2533 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2534 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2535 } 2536 2537 // If this is an 8 or 16-bit value, it is really passed promoted 2538 // to 32 bits. Insert an assert[sz]ext to capture this, then 2539 // truncate to the right size. 2540 switch (VA.getLocInfo()) { 2541 default: llvm_unreachable("Unknown loc info!"); 2542 case CCValAssign::Full: break; 2543 case CCValAssign::BCvt: 2544 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 2545 break; 2546 case CCValAssign::SExt: 2547 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 2548 DAG.getValueType(VA.getValVT())); 2549 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2550 break; 2551 case CCValAssign::ZExt: 2552 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 2553 DAG.getValueType(VA.getValVT())); 2554 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2555 break; 2556 } 2557 2558 InVals.push_back(ArgValue); 2559 2560 } else { // VA.isRegLoc() 2561 2562 // sanity check 2563 assert(VA.isMemLoc()); 2564 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered"); 2565 2566 int index = ArgLocs[i].getValNo(); 2567 2568 // Some Ins[] entries become multiple ArgLoc[] entries. 2569 // Process them only once. 2570 if (index != lastInsIndex) 2571 { 2572 ISD::ArgFlagsTy Flags = Ins[index].Flags; 2573 // FIXME: For now, all byval parameter objects are marked mutable. 2574 // This can be changed with more analysis. 2575 // In case of tail call optimization mark all arguments mutable. 2576 // Since they could be overwritten by lowering of arguments in case of 2577 // a tail call. 2578 if (Flags.isByVal()) { 2579 unsigned VARegSize, VARegSaveSize; 2580 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize); 2581 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, 0); 2582 unsigned Bytes = Flags.getByValSize() - VARegSize; 2583 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 2584 int FI = MFI->CreateFixedObject(Bytes, 2585 VA.getLocMemOffset(), false); 2586 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy())); 2587 } else { 2588 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8, 2589 VA.getLocMemOffset(), true); 2590 2591 // Create load nodes to retrieve arguments from the stack. 2592 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2593 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 2594 MachinePointerInfo::getFixedStack(FI), 2595 false, false, 0)); 2596 } 2597 lastInsIndex = index; 2598 } 2599 } 2600 } 2601 2602 // varargs 2603 if (isVarArg) 2604 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset()); 2605 2606 return Chain; 2607 } 2608 2609 /// isFloatingPointZero - Return true if this is +0.0. 2610 static bool isFloatingPointZero(SDValue Op) { 2611 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 2612 return CFP->getValueAPF().isPosZero(); 2613 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 2614 // Maybe this has already been legalized into the constant pool? 2615 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { 2616 SDValue WrapperOp = Op.getOperand(1).getOperand(0); 2617 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) 2618 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 2619 return CFP->getValueAPF().isPosZero(); 2620 } 2621 } 2622 return false; 2623 } 2624 2625 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for 2626 /// the given operands. 2627 SDValue 2628 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 2629 SDValue &ARMcc, SelectionDAG &DAG, 2630 DebugLoc dl) const { 2631 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { 2632 unsigned C = RHSC->getZExtValue(); 2633 if (!isLegalICmpImmediate(C)) { 2634 // Constant does not fit, try adjusting it by one? 2635 switch (CC) { 2636 default: break; 2637 case ISD::SETLT: 2638 case ISD::SETGE: 2639 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) { 2640 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 2641 RHS = DAG.getConstant(C-1, MVT::i32); 2642 } 2643 break; 2644 case ISD::SETULT: 2645 case ISD::SETUGE: 2646 if (C != 0 && isLegalICmpImmediate(C-1)) { 2647 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 2648 RHS = DAG.getConstant(C-1, MVT::i32); 2649 } 2650 break; 2651 case ISD::SETLE: 2652 case ISD::SETGT: 2653 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) { 2654 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 2655 RHS = DAG.getConstant(C+1, MVT::i32); 2656 } 2657 break; 2658 case ISD::SETULE: 2659 case ISD::SETUGT: 2660 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) { 2661 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 2662 RHS = DAG.getConstant(C+1, MVT::i32); 2663 } 2664 break; 2665 } 2666 } 2667 } 2668 2669 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 2670 ARMISD::NodeType CompareType; 2671 switch (CondCode) { 2672 default: 2673 CompareType = ARMISD::CMP; 2674 break; 2675 case ARMCC::EQ: 2676 case ARMCC::NE: 2677 // Uses only Z Flag 2678 CompareType = ARMISD::CMPZ; 2679 break; 2680 } 2681 ARMcc = DAG.getConstant(CondCode, MVT::i32); 2682 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS); 2683 } 2684 2685 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. 2686 SDValue 2687 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, 2688 DebugLoc dl) const { 2689 SDValue Cmp; 2690 if (!isFloatingPointZero(RHS)) 2691 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS); 2692 else 2693 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS); 2694 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp); 2695 } 2696 2697 /// duplicateCmp - Glue values can have only one use, so this function 2698 /// duplicates a comparison node. 2699 SDValue 2700 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const { 2701 unsigned Opc = Cmp.getOpcode(); 2702 DebugLoc DL = Cmp.getDebugLoc(); 2703 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ) 2704 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1)); 2705 2706 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation"); 2707 Cmp = Cmp.getOperand(0); 2708 Opc = Cmp.getOpcode(); 2709 if (Opc == ARMISD::CMPFP) 2710 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1)); 2711 else { 2712 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"); 2713 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0)); 2714 } 2715 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp); 2716 } 2717 2718 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 2719 SDValue Cond = Op.getOperand(0); 2720 SDValue SelectTrue = Op.getOperand(1); 2721 SDValue SelectFalse = Op.getOperand(2); 2722 DebugLoc dl = Op.getDebugLoc(); 2723 2724 // Convert: 2725 // 2726 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond) 2727 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond) 2728 // 2729 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) { 2730 const ConstantSDNode *CMOVTrue = 2731 dyn_cast<ConstantSDNode>(Cond.getOperand(0)); 2732 const ConstantSDNode *CMOVFalse = 2733 dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 2734 2735 if (CMOVTrue && CMOVFalse) { 2736 unsigned CMOVTrueVal = CMOVTrue->getZExtValue(); 2737 unsigned CMOVFalseVal = CMOVFalse->getZExtValue(); 2738 2739 SDValue True; 2740 SDValue False; 2741 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) { 2742 True = SelectTrue; 2743 False = SelectFalse; 2744 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) { 2745 True = SelectFalse; 2746 False = SelectTrue; 2747 } 2748 2749 if (True.getNode() && False.getNode()) { 2750 EVT VT = Op.getValueType(); 2751 SDValue ARMcc = Cond.getOperand(2); 2752 SDValue CCR = Cond.getOperand(3); 2753 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG); 2754 assert(True.getValueType() == VT); 2755 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp); 2756 } 2757 } 2758 } 2759 2760 return DAG.getSelectCC(dl, Cond, 2761 DAG.getConstant(0, Cond.getValueType()), 2762 SelectTrue, SelectFalse, ISD::SETNE); 2763 } 2764 2765 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 2766 EVT VT = Op.getValueType(); 2767 SDValue LHS = Op.getOperand(0); 2768 SDValue RHS = Op.getOperand(1); 2769 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 2770 SDValue TrueVal = Op.getOperand(2); 2771 SDValue FalseVal = Op.getOperand(3); 2772 DebugLoc dl = Op.getDebugLoc(); 2773 2774 if (LHS.getValueType() == MVT::i32) { 2775 SDValue ARMcc; 2776 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2777 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2778 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp); 2779 } 2780 2781 ARMCC::CondCodes CondCode, CondCode2; 2782 FPCCToARMCC(CC, CondCode, CondCode2); 2783 2784 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32); 2785 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 2786 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2787 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, 2788 ARMcc, CCR, Cmp); 2789 if (CondCode2 != ARMCC::AL) { 2790 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32); 2791 // FIXME: Needs another CMP because flag can have but one use. 2792 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl); 2793 Result = DAG.getNode(ARMISD::CMOV, dl, VT, 2794 Result, TrueVal, ARMcc2, CCR, Cmp2); 2795 } 2796 return Result; 2797 } 2798 2799 /// canChangeToInt - Given the fp compare operand, return true if it is suitable 2800 /// to morph to an integer compare sequence. 2801 static bool canChangeToInt(SDValue Op, bool &SeenZero, 2802 const ARMSubtarget *Subtarget) { 2803 SDNode *N = Op.getNode(); 2804 if (!N->hasOneUse()) 2805 // Otherwise it requires moving the value from fp to integer registers. 2806 return false; 2807 if (!N->getNumValues()) 2808 return false; 2809 EVT VT = Op.getValueType(); 2810 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow()) 2811 // f32 case is generally profitable. f64 case only makes sense when vcmpe + 2812 // vmrs are very slow, e.g. cortex-a8. 2813 return false; 2814 2815 if (isFloatingPointZero(Op)) { 2816 SeenZero = true; 2817 return true; 2818 } 2819 return ISD::isNormalLoad(N); 2820 } 2821 2822 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) { 2823 if (isFloatingPointZero(Op)) 2824 return DAG.getConstant(0, MVT::i32); 2825 2826 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) 2827 return DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2828 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(), 2829 Ld->isVolatile(), Ld->isNonTemporal(), 2830 Ld->getAlignment()); 2831 2832 llvm_unreachable("Unknown VFP cmp argument!"); 2833 } 2834 2835 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG, 2836 SDValue &RetVal1, SDValue &RetVal2) { 2837 if (isFloatingPointZero(Op)) { 2838 RetVal1 = DAG.getConstant(0, MVT::i32); 2839 RetVal2 = DAG.getConstant(0, MVT::i32); 2840 return; 2841 } 2842 2843 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) { 2844 SDValue Ptr = Ld->getBasePtr(); 2845 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2846 Ld->getChain(), Ptr, 2847 Ld->getPointerInfo(), 2848 Ld->isVolatile(), Ld->isNonTemporal(), 2849 Ld->getAlignment()); 2850 2851 EVT PtrType = Ptr.getValueType(); 2852 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4); 2853 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(), 2854 PtrType, Ptr, DAG.getConstant(4, PtrType)); 2855 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2856 Ld->getChain(), NewPtr, 2857 Ld->getPointerInfo().getWithOffset(4), 2858 Ld->isVolatile(), Ld->isNonTemporal(), 2859 NewAlign); 2860 return; 2861 } 2862 2863 llvm_unreachable("Unknown VFP cmp argument!"); 2864 } 2865 2866 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some 2867 /// f32 and even f64 comparisons to integer ones. 2868 SDValue 2869 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const { 2870 SDValue Chain = Op.getOperand(0); 2871 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 2872 SDValue LHS = Op.getOperand(2); 2873 SDValue RHS = Op.getOperand(3); 2874 SDValue Dest = Op.getOperand(4); 2875 DebugLoc dl = Op.getDebugLoc(); 2876 2877 bool SeenZero = false; 2878 if (canChangeToInt(LHS, SeenZero, Subtarget) && 2879 canChangeToInt(RHS, SeenZero, Subtarget) && 2880 // If one of the operand is zero, it's safe to ignore the NaN case since 2881 // we only care about equality comparisons. 2882 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) { 2883 // If unsafe fp math optimization is enabled and there are no other uses of 2884 // the CMP operands, and the condition code is EQ or NE, we can optimize it 2885 // to an integer comparison. 2886 if (CC == ISD::SETOEQ) 2887 CC = ISD::SETEQ; 2888 else if (CC == ISD::SETUNE) 2889 CC = ISD::SETNE; 2890 2891 SDValue ARMcc; 2892 if (LHS.getValueType() == MVT::f32) { 2893 LHS = bitcastf32Toi32(LHS, DAG); 2894 RHS = bitcastf32Toi32(RHS, DAG); 2895 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2896 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2897 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 2898 Chain, Dest, ARMcc, CCR, Cmp); 2899 } 2900 2901 SDValue LHS1, LHS2; 2902 SDValue RHS1, RHS2; 2903 expandf64Toi32(LHS, DAG, LHS1, LHS2); 2904 expandf64Toi32(RHS, DAG, RHS1, RHS2); 2905 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 2906 ARMcc = DAG.getConstant(CondCode, MVT::i32); 2907 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); 2908 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; 2909 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7); 2910 } 2911 2912 return SDValue(); 2913 } 2914 2915 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 2916 SDValue Chain = Op.getOperand(0); 2917 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 2918 SDValue LHS = Op.getOperand(2); 2919 SDValue RHS = Op.getOperand(3); 2920 SDValue Dest = Op.getOperand(4); 2921 DebugLoc dl = Op.getDebugLoc(); 2922 2923 if (LHS.getValueType() == MVT::i32) { 2924 SDValue ARMcc; 2925 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2926 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2927 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 2928 Chain, Dest, ARMcc, CCR, Cmp); 2929 } 2930 2931 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 2932 2933 if (UnsafeFPMath && 2934 (CC == ISD::SETEQ || CC == ISD::SETOEQ || 2935 CC == ISD::SETNE || CC == ISD::SETUNE)) { 2936 SDValue Result = OptimizeVFPBrcond(Op, DAG); 2937 if (Result.getNode()) 2938 return Result; 2939 } 2940 2941 ARMCC::CondCodes CondCode, CondCode2; 2942 FPCCToARMCC(CC, CondCode, CondCode2); 2943 2944 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32); 2945 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 2946 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2947 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); 2948 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp }; 2949 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 2950 if (CondCode2 != ARMCC::AL) { 2951 ARMcc = DAG.getConstant(CondCode2, MVT::i32); 2952 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) }; 2953 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 2954 } 2955 return Res; 2956 } 2957 2958 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 2959 SDValue Chain = Op.getOperand(0); 2960 SDValue Table = Op.getOperand(1); 2961 SDValue Index = Op.getOperand(2); 2962 DebugLoc dl = Op.getDebugLoc(); 2963 2964 EVT PTy = getPointerTy(); 2965 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 2966 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); 2967 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); 2968 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); 2969 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId); 2970 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy)); 2971 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 2972 if (Subtarget->isThumb2()) { 2973 // Thumb2 uses a two-level jump. That is, it jumps into the jump table 2974 // which does another jump to the destination. This also makes it easier 2975 // to translate it to TBB / TBH later. 2976 // FIXME: This might not work if the function is extremely large. 2977 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain, 2978 Addr, Op.getOperand(2), JTI, UId); 2979 } 2980 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2981 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, 2982 MachinePointerInfo::getJumpTable(), 2983 false, false, 0); 2984 Chain = Addr.getValue(1); 2985 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table); 2986 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); 2987 } else { 2988 Addr = DAG.getLoad(PTy, dl, Chain, Addr, 2989 MachinePointerInfo::getJumpTable(), false, false, 0); 2990 Chain = Addr.getValue(1); 2991 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); 2992 } 2993 } 2994 2995 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) { 2996 DebugLoc dl = Op.getDebugLoc(); 2997 unsigned Opc; 2998 2999 switch (Op.getOpcode()) { 3000 default: 3001 assert(0 && "Invalid opcode!"); 3002 case ISD::FP_TO_SINT: 3003 Opc = ARMISD::FTOSI; 3004 break; 3005 case ISD::FP_TO_UINT: 3006 Opc = ARMISD::FTOUI; 3007 break; 3008 } 3009 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0)); 3010 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3011 } 3012 3013 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 3014 EVT VT = Op.getValueType(); 3015 DebugLoc dl = Op.getDebugLoc(); 3016 3017 assert(Op.getOperand(0).getValueType() == MVT::v4i16 && 3018 "Invalid type for custom lowering!"); 3019 if (VT != MVT::v4f32) 3020 return DAG.UnrollVectorOp(Op.getNode()); 3021 3022 unsigned CastOpc; 3023 unsigned Opc; 3024 switch (Op.getOpcode()) { 3025 default: 3026 assert(0 && "Invalid opcode!"); 3027 case ISD::SINT_TO_FP: 3028 CastOpc = ISD::SIGN_EXTEND; 3029 Opc = ISD::SINT_TO_FP; 3030 break; 3031 case ISD::UINT_TO_FP: 3032 CastOpc = ISD::ZERO_EXTEND; 3033 Opc = ISD::UINT_TO_FP; 3034 break; 3035 } 3036 3037 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0)); 3038 return DAG.getNode(Opc, dl, VT, Op); 3039 } 3040 3041 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 3042 EVT VT = Op.getValueType(); 3043 if (VT.isVector()) 3044 return LowerVectorINT_TO_FP(Op, DAG); 3045 3046 DebugLoc dl = Op.getDebugLoc(); 3047 unsigned Opc; 3048 3049 switch (Op.getOpcode()) { 3050 default: 3051 assert(0 && "Invalid opcode!"); 3052 case ISD::SINT_TO_FP: 3053 Opc = ARMISD::SITOF; 3054 break; 3055 case ISD::UINT_TO_FP: 3056 Opc = ARMISD::UITOF; 3057 break; 3058 } 3059 3060 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0)); 3061 return DAG.getNode(Opc, dl, VT, Op); 3062 } 3063 3064 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 3065 // Implement fcopysign with a fabs and a conditional fneg. 3066 SDValue Tmp0 = Op.getOperand(0); 3067 SDValue Tmp1 = Op.getOperand(1); 3068 DebugLoc dl = Op.getDebugLoc(); 3069 EVT VT = Op.getValueType(); 3070 EVT SrcVT = Tmp1.getValueType(); 3071 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST || 3072 Tmp0.getOpcode() == ARMISD::VMOVDRR; 3073 bool UseNEON = !InGPR && Subtarget->hasNEON(); 3074 3075 if (UseNEON) { 3076 // Use VBSL to copy the sign bit. 3077 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80); 3078 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32, 3079 DAG.getTargetConstant(EncodedVal, MVT::i32)); 3080 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64; 3081 if (VT == MVT::f64) 3082 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT, 3083 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask), 3084 DAG.getConstant(32, MVT::i32)); 3085 else /*if (VT == MVT::f32)*/ 3086 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); 3087 if (SrcVT == MVT::f32) { 3088 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1); 3089 if (VT == MVT::f64) 3090 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT, 3091 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), 3092 DAG.getConstant(32, MVT::i32)); 3093 } else if (VT == MVT::f32) 3094 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64, 3095 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1), 3096 DAG.getConstant(32, MVT::i32)); 3097 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); 3098 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); 3099 3100 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff), 3101 MVT::i32); 3102 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes); 3103 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask, 3104 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes)); 3105 3106 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT, 3107 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask), 3108 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot)); 3109 if (VT == MVT::f32) { 3110 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res); 3111 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res, 3112 DAG.getConstant(0, MVT::i32)); 3113 } else { 3114 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res); 3115 } 3116 3117 return Res; 3118 } 3119 3120 // Bitcast operand 1 to i32. 3121 if (SrcVT == MVT::f64) 3122 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), 3123 &Tmp1, 1).getValue(1); 3124 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1); 3125 3126 // Or in the signbit with integer operations. 3127 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32); 3128 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32); 3129 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1); 3130 if (VT == MVT::f32) { 3131 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32, 3132 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2); 3133 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 3134 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1)); 3135 } 3136 3137 // f64: Or the high part with signbit and then combine two parts. 3138 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), 3139 &Tmp0, 1); 3140 SDValue Lo = Tmp0.getValue(0); 3141 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2); 3142 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1); 3143 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 3144 } 3145 3146 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{ 3147 MachineFunction &MF = DAG.getMachineFunction(); 3148 MachineFrameInfo *MFI = MF.getFrameInfo(); 3149 MFI->setReturnAddressIsTaken(true); 3150 3151 EVT VT = Op.getValueType(); 3152 DebugLoc dl = Op.getDebugLoc(); 3153 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 3154 if (Depth) { 3155 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 3156 SDValue Offset = DAG.getConstant(4, MVT::i32); 3157 return DAG.getLoad(VT, dl, DAG.getEntryNode(), 3158 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), 3159 MachinePointerInfo(), false, false, 0); 3160 } 3161 3162 // Return LR, which contains the return address. Mark it an implicit live-in. 3163 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32)); 3164 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT); 3165 } 3166 3167 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 3168 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3169 MFI->setFrameAddressIsTaken(true); 3170 3171 EVT VT = Op.getValueType(); 3172 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 3173 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 3174 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin()) 3175 ? ARM::R7 : ARM::R11; 3176 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 3177 while (Depth--) 3178 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 3179 MachinePointerInfo(), 3180 false, false, 0); 3181 return FrameAddr; 3182 } 3183 3184 /// ExpandBITCAST - If the target supports VFP, this function is called to 3185 /// expand a bit convert where either the source or destination type is i64 to 3186 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64 3187 /// operand type is illegal (e.g., v2f32 for a target that doesn't support 3188 /// vectors), since the legalizer won't know what to do with that. 3189 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) { 3190 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3191 DebugLoc dl = N->getDebugLoc(); 3192 SDValue Op = N->getOperand(0); 3193 3194 // This function is only supposed to be called for i64 types, either as the 3195 // source or destination of the bit convert. 3196 EVT SrcVT = Op.getValueType(); 3197 EVT DstVT = N->getValueType(0); 3198 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) && 3199 "ExpandBITCAST called for non-i64 type"); 3200 3201 // Turn i64->f64 into VMOVDRR. 3202 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) { 3203 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 3204 DAG.getConstant(0, MVT::i32)); 3205 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 3206 DAG.getConstant(1, MVT::i32)); 3207 return DAG.getNode(ISD::BITCAST, dl, DstVT, 3208 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi)); 3209 } 3210 3211 // Turn f64->i64 into VMOVRRD. 3212 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) { 3213 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, 3214 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1); 3215 // Merge the pieces into a single i64 value. 3216 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); 3217 } 3218 3219 return SDValue(); 3220 } 3221 3222 /// getZeroVector - Returns a vector of specified type with all zero elements. 3223 /// Zero vectors are used to represent vector negation and in those cases 3224 /// will be implemented with the NEON VNEG instruction. However, VNEG does 3225 /// not support i64 elements, so sometimes the zero vectors will need to be 3226 /// explicitly constructed. Regardless, use a canonical VMOV to create the 3227 /// zero vector. 3228 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3229 assert(VT.isVector() && "Expected a vector type"); 3230 // The canonical modified immediate encoding of a zero vector is....0! 3231 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32); 3232 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; 3233 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal); 3234 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); 3235 } 3236 3237 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two 3238 /// i32 values and take a 2 x i32 value to shift plus a shift amount. 3239 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op, 3240 SelectionDAG &DAG) const { 3241 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 3242 EVT VT = Op.getValueType(); 3243 unsigned VTBits = VT.getSizeInBits(); 3244 DebugLoc dl = Op.getDebugLoc(); 3245 SDValue ShOpLo = Op.getOperand(0); 3246 SDValue ShOpHi = Op.getOperand(1); 3247 SDValue ShAmt = Op.getOperand(2); 3248 SDValue ARMcc; 3249 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL; 3250 3251 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS); 3252 3253 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, 3254 DAG.getConstant(VTBits, MVT::i32), ShAmt); 3255 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); 3256 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, 3257 DAG.getConstant(VTBits, MVT::i32)); 3258 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); 3259 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 3260 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt); 3261 3262 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 3263 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, 3264 ARMcc, DAG, dl); 3265 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt); 3266 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, 3267 CCR, Cmp); 3268 3269 SDValue Ops[2] = { Lo, Hi }; 3270 return DAG.getMergeValues(Ops, 2, dl); 3271 } 3272 3273 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two 3274 /// i32 values and take a 2 x i32 value to shift plus a shift amount. 3275 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op, 3276 SelectionDAG &DAG) const { 3277 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 3278 EVT VT = Op.getValueType(); 3279 unsigned VTBits = VT.getSizeInBits(); 3280 DebugLoc dl = Op.getDebugLoc(); 3281 SDValue ShOpLo = Op.getOperand(0); 3282 SDValue ShOpHi = Op.getOperand(1); 3283 SDValue ShAmt = Op.getOperand(2); 3284 SDValue ARMcc; 3285 3286 assert(Op.getOpcode() == ISD::SHL_PARTS); 3287 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, 3288 DAG.getConstant(VTBits, MVT::i32), ShAmt); 3289 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); 3290 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, 3291 DAG.getConstant(VTBits, MVT::i32)); 3292 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); 3293 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); 3294 3295 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 3296 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 3297 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, 3298 ARMcc, DAG, dl); 3299 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 3300 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc, 3301 CCR, Cmp); 3302 3303 SDValue Ops[2] = { Lo, Hi }; 3304 return DAG.getMergeValues(Ops, 2, dl); 3305 } 3306 3307 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op, 3308 SelectionDAG &DAG) const { 3309 // The rounding mode is in bits 23:22 of the FPSCR. 3310 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0 3311 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3) 3312 // so that the shift + and get folded into a bitfield extract. 3313 DebugLoc dl = Op.getDebugLoc(); 3314 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, 3315 DAG.getConstant(Intrinsic::arm_get_fpscr, 3316 MVT::i32)); 3317 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR, 3318 DAG.getConstant(1U << 22, MVT::i32)); 3319 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds, 3320 DAG.getConstant(22, MVT::i32)); 3321 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE, 3322 DAG.getConstant(3, MVT::i32)); 3323 } 3324 3325 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG, 3326 const ARMSubtarget *ST) { 3327 EVT VT = N->getValueType(0); 3328 DebugLoc dl = N->getDebugLoc(); 3329 3330 if (!ST->hasV6T2Ops()) 3331 return SDValue(); 3332 3333 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0)); 3334 return DAG.getNode(ISD::CTLZ, dl, VT, rbit); 3335 } 3336 3337 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, 3338 const ARMSubtarget *ST) { 3339 EVT VT = N->getValueType(0); 3340 DebugLoc dl = N->getDebugLoc(); 3341 3342 if (!VT.isVector()) 3343 return SDValue(); 3344 3345 // Lower vector shifts on NEON to use VSHL. 3346 assert(ST->hasNEON() && "unexpected vector shift"); 3347 3348 // Left shifts translate directly to the vshiftu intrinsic. 3349 if (N->getOpcode() == ISD::SHL) 3350 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 3351 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32), 3352 N->getOperand(0), N->getOperand(1)); 3353 3354 assert((N->getOpcode() == ISD::SRA || 3355 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode"); 3356 3357 // NEON uses the same intrinsics for both left and right shifts. For 3358 // right shifts, the shift amounts are negative, so negate the vector of 3359 // shift amounts. 3360 EVT ShiftVT = N->getOperand(1).getValueType(); 3361 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT, 3362 getZeroVector(ShiftVT, DAG, dl), 3363 N->getOperand(1)); 3364 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ? 3365 Intrinsic::arm_neon_vshifts : 3366 Intrinsic::arm_neon_vshiftu); 3367 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 3368 DAG.getConstant(vshiftInt, MVT::i32), 3369 N->getOperand(0), NegatedCount); 3370 } 3371 3372 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG, 3373 const ARMSubtarget *ST) { 3374 EVT VT = N->getValueType(0); 3375 DebugLoc dl = N->getDebugLoc(); 3376 3377 // We can get here for a node like i32 = ISD::SHL i32, i64 3378 if (VT != MVT::i64) 3379 return SDValue(); 3380 3381 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && 3382 "Unknown shift to lower!"); 3383 3384 // We only lower SRA, SRL of 1 here, all others use generic lowering. 3385 if (!isa<ConstantSDNode>(N->getOperand(1)) || 3386 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1) 3387 return SDValue(); 3388 3389 // If we are in thumb mode, we don't have RRX. 3390 if (ST->isThumb1Only()) return SDValue(); 3391 3392 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. 3393 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 3394 DAG.getConstant(0, MVT::i32)); 3395 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 3396 DAG.getConstant(1, MVT::i32)); 3397 3398 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and 3399 // captures the result into a carry flag. 3400 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; 3401 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1); 3402 3403 // The low part is an ARMISD::RRX operand, which shifts the carry in. 3404 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1)); 3405 3406 // Merge the pieces into a single i64 value. 3407 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 3408 } 3409 3410 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 3411 SDValue TmpOp0, TmpOp1; 3412 bool Invert = false; 3413 bool Swap = false; 3414 unsigned Opc = 0; 3415 3416 SDValue Op0 = Op.getOperand(0); 3417 SDValue Op1 = Op.getOperand(1); 3418 SDValue CC = Op.getOperand(2); 3419 EVT VT = Op.getValueType(); 3420 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 3421 DebugLoc dl = Op.getDebugLoc(); 3422 3423 if (Op.getOperand(1).getValueType().isFloatingPoint()) { 3424 switch (SetCCOpcode) { 3425 default: llvm_unreachable("Illegal FP comparison"); break; 3426 case ISD::SETUNE: 3427 case ISD::SETNE: Invert = true; // Fallthrough 3428 case ISD::SETOEQ: 3429 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; 3430 case ISD::SETOLT: 3431 case ISD::SETLT: Swap = true; // Fallthrough 3432 case ISD::SETOGT: 3433 case ISD::SETGT: Opc = ARMISD::VCGT; break; 3434 case ISD::SETOLE: 3435 case ISD::SETLE: Swap = true; // Fallthrough 3436 case ISD::SETOGE: 3437 case ISD::SETGE: Opc = ARMISD::VCGE; break; 3438 case ISD::SETUGE: Swap = true; // Fallthrough 3439 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break; 3440 case ISD::SETUGT: Swap = true; // Fallthrough 3441 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break; 3442 case ISD::SETUEQ: Invert = true; // Fallthrough 3443 case ISD::SETONE: 3444 // Expand this to (OLT | OGT). 3445 TmpOp0 = Op0; 3446 TmpOp1 = Op1; 3447 Opc = ISD::OR; 3448 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); 3449 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1); 3450 break; 3451 case ISD::SETUO: Invert = true; // Fallthrough 3452 case ISD::SETO: 3453 // Expand this to (OLT | OGE). 3454 TmpOp0 = Op0; 3455 TmpOp1 = Op1; 3456 Opc = ISD::OR; 3457 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); 3458 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1); 3459 break; 3460 } 3461 } else { 3462 // Integer comparisons. 3463 switch (SetCCOpcode) { 3464 default: llvm_unreachable("Illegal integer comparison"); break; 3465 case ISD::SETNE: Invert = true; 3466 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; 3467 case ISD::SETLT: Swap = true; 3468 case ISD::SETGT: Opc = ARMISD::VCGT; break; 3469 case ISD::SETLE: Swap = true; 3470 case ISD::SETGE: Opc = ARMISD::VCGE; break; 3471 case ISD::SETULT: Swap = true; 3472 case ISD::SETUGT: Opc = ARMISD::VCGTU; break; 3473 case ISD::SETULE: Swap = true; 3474 case ISD::SETUGE: Opc = ARMISD::VCGEU; break; 3475 } 3476 3477 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero). 3478 if (Opc == ARMISD::VCEQ) { 3479 3480 SDValue AndOp; 3481 if (ISD::isBuildVectorAllZeros(Op1.getNode())) 3482 AndOp = Op0; 3483 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) 3484 AndOp = Op1; 3485 3486 // Ignore bitconvert. 3487 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST) 3488 AndOp = AndOp.getOperand(0); 3489 3490 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) { 3491 Opc = ARMISD::VTST; 3492 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0)); 3493 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1)); 3494 Invert = !Invert; 3495 } 3496 } 3497 } 3498 3499 if (Swap) 3500 std::swap(Op0, Op1); 3501 3502 // If one of the operands is a constant vector zero, attempt to fold the 3503 // comparison to a specialized compare-against-zero form. 3504 SDValue SingleOp; 3505 if (ISD::isBuildVectorAllZeros(Op1.getNode())) 3506 SingleOp = Op0; 3507 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) { 3508 if (Opc == ARMISD::VCGE) 3509 Opc = ARMISD::VCLEZ; 3510 else if (Opc == ARMISD::VCGT) 3511 Opc = ARMISD::VCLTZ; 3512 SingleOp = Op1; 3513 } 3514 3515 SDValue Result; 3516 if (SingleOp.getNode()) { 3517 switch (Opc) { 3518 case ARMISD::VCEQ: 3519 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break; 3520 case ARMISD::VCGE: 3521 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break; 3522 case ARMISD::VCLEZ: 3523 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break; 3524 case ARMISD::VCGT: 3525 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break; 3526 case ARMISD::VCLTZ: 3527 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break; 3528 default: 3529 Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 3530 } 3531 } else { 3532 Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 3533 } 3534 3535 if (Invert) 3536 Result = DAG.getNOT(dl, Result, VT); 3537 3538 return Result; 3539 } 3540 3541 /// isNEONModifiedImm - Check if the specified splat value corresponds to a 3542 /// valid vector constant for a NEON instruction with a "modified immediate" 3543 /// operand (e.g., VMOV). If so, return the encoded value. 3544 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, 3545 unsigned SplatBitSize, SelectionDAG &DAG, 3546 EVT &VT, bool is128Bits, NEONModImmType type) { 3547 unsigned OpCmode, Imm; 3548 3549 // SplatBitSize is set to the smallest size that splats the vector, so a 3550 // zero vector will always have SplatBitSize == 8. However, NEON modified 3551 // immediate instructions others than VMOV do not support the 8-bit encoding 3552 // of a zero vector, and the default encoding of zero is supposed to be the 3553 // 32-bit version. 3554 if (SplatBits == 0) 3555 SplatBitSize = 32; 3556 3557 switch (SplatBitSize) { 3558 case 8: 3559 if (type != VMOVModImm) 3560 return SDValue(); 3561 // Any 1-byte value is OK. Op=0, Cmode=1110. 3562 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big"); 3563 OpCmode = 0xe; 3564 Imm = SplatBits; 3565 VT = is128Bits ? MVT::v16i8 : MVT::v8i8; 3566 break; 3567 3568 case 16: 3569 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero. 3570 VT = is128Bits ? MVT::v8i16 : MVT::v4i16; 3571 if ((SplatBits & ~0xff) == 0) { 3572 // Value = 0x00nn: Op=x, Cmode=100x. 3573 OpCmode = 0x8; 3574 Imm = SplatBits; 3575 break; 3576 } 3577 if ((SplatBits & ~0xff00) == 0) { 3578 // Value = 0xnn00: Op=x, Cmode=101x. 3579 OpCmode = 0xa; 3580 Imm = SplatBits >> 8; 3581 break; 3582 } 3583 return SDValue(); 3584 3585 case 32: 3586 // NEON's 32-bit VMOV supports splat values where: 3587 // * only one byte is nonzero, or 3588 // * the least significant byte is 0xff and the second byte is nonzero, or 3589 // * the least significant 2 bytes are 0xff and the third is nonzero. 3590 VT = is128Bits ? MVT::v4i32 : MVT::v2i32; 3591 if ((SplatBits & ~0xff) == 0) { 3592 // Value = 0x000000nn: Op=x, Cmode=000x. 3593 OpCmode = 0; 3594 Imm = SplatBits; 3595 break; 3596 } 3597 if ((SplatBits & ~0xff00) == 0) { 3598 // Value = 0x0000nn00: Op=x, Cmode=001x. 3599 OpCmode = 0x2; 3600 Imm = SplatBits >> 8; 3601 break; 3602 } 3603 if ((SplatBits & ~0xff0000) == 0) { 3604 // Value = 0x00nn0000: Op=x, Cmode=010x. 3605 OpCmode = 0x4; 3606 Imm = SplatBits >> 16; 3607 break; 3608 } 3609 if ((SplatBits & ~0xff000000) == 0) { 3610 // Value = 0xnn000000: Op=x, Cmode=011x. 3611 OpCmode = 0x6; 3612 Imm = SplatBits >> 24; 3613 break; 3614 } 3615 3616 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC 3617 if (type == OtherModImm) return SDValue(); 3618 3619 if ((SplatBits & ~0xffff) == 0 && 3620 ((SplatBits | SplatUndef) & 0xff) == 0xff) { 3621 // Value = 0x0000nnff: Op=x, Cmode=1100. 3622 OpCmode = 0xc; 3623 Imm = SplatBits >> 8; 3624 SplatBits |= 0xff; 3625 break; 3626 } 3627 3628 if ((SplatBits & ~0xffffff) == 0 && 3629 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) { 3630 // Value = 0x00nnffff: Op=x, Cmode=1101. 3631 OpCmode = 0xd; 3632 Imm = SplatBits >> 16; 3633 SplatBits |= 0xffff; 3634 break; 3635 } 3636 3637 // Note: there are a few 32-bit splat values (specifically: 00ffff00, 3638 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not 3639 // VMOV.I32. A (very) minor optimization would be to replicate the value 3640 // and fall through here to test for a valid 64-bit splat. But, then the 3641 // caller would also need to check and handle the change in size. 3642 return SDValue(); 3643 3644 case 64: { 3645 if (type != VMOVModImm) 3646 return SDValue(); 3647 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff. 3648 uint64_t BitMask = 0xff; 3649 uint64_t Val = 0; 3650 unsigned ImmMask = 1; 3651 Imm = 0; 3652 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) { 3653 if (((SplatBits | SplatUndef) & BitMask) == BitMask) { 3654 Val |= BitMask; 3655 Imm |= ImmMask; 3656 } else if ((SplatBits & BitMask) != 0) { 3657 return SDValue(); 3658 } 3659 BitMask <<= 8; 3660 ImmMask <<= 1; 3661 } 3662 // Op=1, Cmode=1110. 3663 OpCmode = 0x1e; 3664 SplatBits = Val; 3665 VT = is128Bits ? MVT::v2i64 : MVT::v1i64; 3666 break; 3667 } 3668 3669 default: 3670 llvm_unreachable("unexpected size for isNEONModifiedImm"); 3671 return SDValue(); 3672 } 3673 3674 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm); 3675 return DAG.getTargetConstant(EncodedVal, MVT::i32); 3676 } 3677 3678 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT, 3679 bool &ReverseVEXT, unsigned &Imm) { 3680 unsigned NumElts = VT.getVectorNumElements(); 3681 ReverseVEXT = false; 3682 3683 // Assume that the first shuffle index is not UNDEF. Fail if it is. 3684 if (M[0] < 0) 3685 return false; 3686 3687 Imm = M[0]; 3688 3689 // If this is a VEXT shuffle, the immediate value is the index of the first 3690 // element. The other shuffle indices must be the successive elements after 3691 // the first one. 3692 unsigned ExpectedElt = Imm; 3693 for (unsigned i = 1; i < NumElts; ++i) { 3694 // Increment the expected index. If it wraps around, it may still be 3695 // a VEXT but the source vectors must be swapped. 3696 ExpectedElt += 1; 3697 if (ExpectedElt == NumElts * 2) { 3698 ExpectedElt = 0; 3699 ReverseVEXT = true; 3700 } 3701 3702 if (M[i] < 0) continue; // ignore UNDEF indices 3703 if (ExpectedElt != static_cast<unsigned>(M[i])) 3704 return false; 3705 } 3706 3707 // Adjust the index value if the source operands will be swapped. 3708 if (ReverseVEXT) 3709 Imm -= NumElts; 3710 3711 return true; 3712 } 3713 3714 /// isVREVMask - Check if a vector shuffle corresponds to a VREV 3715 /// instruction with the specified blocksize. (The order of the elements 3716 /// within each block of the vector is reversed.) 3717 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT, 3718 unsigned BlockSize) { 3719 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) && 3720 "Only possible block sizes for VREV are: 16, 32, 64"); 3721 3722 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3723 if (EltSz == 64) 3724 return false; 3725 3726 unsigned NumElts = VT.getVectorNumElements(); 3727 unsigned BlockElts = M[0] + 1; 3728 // If the first shuffle index is UNDEF, be optimistic. 3729 if (M[0] < 0) 3730 BlockElts = BlockSize / EltSz; 3731 3732 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz) 3733 return false; 3734 3735 for (unsigned i = 0; i < NumElts; ++i) { 3736 if (M[i] < 0) continue; // ignore UNDEF indices 3737 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts)) 3738 return false; 3739 } 3740 3741 return true; 3742 } 3743 3744 static bool isVTBLMask(const SmallVectorImpl<int> &M, EVT VT) { 3745 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of 3746 // range, then 0 is placed into the resulting vector. So pretty much any mask 3747 // of 8 elements can work here. 3748 return VT == MVT::v8i8 && M.size() == 8; 3749 } 3750 3751 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT, 3752 unsigned &WhichResult) { 3753 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3754 if (EltSz == 64) 3755 return false; 3756 3757 unsigned NumElts = VT.getVectorNumElements(); 3758 WhichResult = (M[0] == 0 ? 0 : 1); 3759 for (unsigned i = 0; i < NumElts; i += 2) { 3760 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) || 3761 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult)) 3762 return false; 3763 } 3764 return true; 3765 } 3766 3767 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of 3768 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3769 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>. 3770 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3771 unsigned &WhichResult) { 3772 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3773 if (EltSz == 64) 3774 return false; 3775 3776 unsigned NumElts = VT.getVectorNumElements(); 3777 WhichResult = (M[0] == 0 ? 0 : 1); 3778 for (unsigned i = 0; i < NumElts; i += 2) { 3779 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) || 3780 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult)) 3781 return false; 3782 } 3783 return true; 3784 } 3785 3786 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT, 3787 unsigned &WhichResult) { 3788 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3789 if (EltSz == 64) 3790 return false; 3791 3792 unsigned NumElts = VT.getVectorNumElements(); 3793 WhichResult = (M[0] == 0 ? 0 : 1); 3794 for (unsigned i = 0; i != NumElts; ++i) { 3795 if (M[i] < 0) continue; // ignore UNDEF indices 3796 if ((unsigned) M[i] != 2 * i + WhichResult) 3797 return false; 3798 } 3799 3800 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3801 if (VT.is64BitVector() && EltSz == 32) 3802 return false; 3803 3804 return true; 3805 } 3806 3807 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of 3808 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3809 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>, 3810 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3811 unsigned &WhichResult) { 3812 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3813 if (EltSz == 64) 3814 return false; 3815 3816 unsigned Half = VT.getVectorNumElements() / 2; 3817 WhichResult = (M[0] == 0 ? 0 : 1); 3818 for (unsigned j = 0; j != 2; ++j) { 3819 unsigned Idx = WhichResult; 3820 for (unsigned i = 0; i != Half; ++i) { 3821 int MIdx = M[i + j * Half]; 3822 if (MIdx >= 0 && (unsigned) MIdx != Idx) 3823 return false; 3824 Idx += 2; 3825 } 3826 } 3827 3828 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3829 if (VT.is64BitVector() && EltSz == 32) 3830 return false; 3831 3832 return true; 3833 } 3834 3835 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT, 3836 unsigned &WhichResult) { 3837 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3838 if (EltSz == 64) 3839 return false; 3840 3841 unsigned NumElts = VT.getVectorNumElements(); 3842 WhichResult = (M[0] == 0 ? 0 : 1); 3843 unsigned Idx = WhichResult * NumElts / 2; 3844 for (unsigned i = 0; i != NumElts; i += 2) { 3845 if ((M[i] >= 0 && (unsigned) M[i] != Idx) || 3846 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts)) 3847 return false; 3848 Idx += 1; 3849 } 3850 3851 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3852 if (VT.is64BitVector() && EltSz == 32) 3853 return false; 3854 3855 return true; 3856 } 3857 3858 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of 3859 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3860 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>. 3861 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3862 unsigned &WhichResult) { 3863 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3864 if (EltSz == 64) 3865 return false; 3866 3867 unsigned NumElts = VT.getVectorNumElements(); 3868 WhichResult = (M[0] == 0 ? 0 : 1); 3869 unsigned Idx = WhichResult * NumElts / 2; 3870 for (unsigned i = 0; i != NumElts; i += 2) { 3871 if ((M[i] >= 0 && (unsigned) M[i] != Idx) || 3872 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx)) 3873 return false; 3874 Idx += 1; 3875 } 3876 3877 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3878 if (VT.is64BitVector() && EltSz == 32) 3879 return false; 3880 3881 return true; 3882 } 3883 3884 // If N is an integer constant that can be moved into a register in one 3885 // instruction, return an SDValue of such a constant (will become a MOV 3886 // instruction). Otherwise return null. 3887 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG, 3888 const ARMSubtarget *ST, DebugLoc dl) { 3889 uint64_t Val; 3890 if (!isa<ConstantSDNode>(N)) 3891 return SDValue(); 3892 Val = cast<ConstantSDNode>(N)->getZExtValue(); 3893 3894 if (ST->isThumb1Only()) { 3895 if (Val <= 255 || ~Val <= 255) 3896 return DAG.getConstant(Val, MVT::i32); 3897 } else { 3898 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1) 3899 return DAG.getConstant(Val, MVT::i32); 3900 } 3901 return SDValue(); 3902 } 3903 3904 // If this is a case we can't handle, return null and let the default 3905 // expansion code take care of it. 3906 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 3907 const ARMSubtarget *ST) const { 3908 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode()); 3909 DebugLoc dl = Op.getDebugLoc(); 3910 EVT VT = Op.getValueType(); 3911 3912 APInt SplatBits, SplatUndef; 3913 unsigned SplatBitSize; 3914 bool HasAnyUndefs; 3915 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 3916 if (SplatBitSize <= 64) { 3917 // Check if an immediate VMOV works. 3918 EVT VmovVT; 3919 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), 3920 SplatUndef.getZExtValue(), SplatBitSize, 3921 DAG, VmovVT, VT.is128BitVector(), 3922 VMOVModImm); 3923 if (Val.getNode()) { 3924 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val); 3925 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); 3926 } 3927 3928 // Try an immediate VMVN. 3929 uint64_t NegatedImm = (SplatBits.getZExtValue() ^ 3930 ((1LL << SplatBitSize) - 1)); 3931 Val = isNEONModifiedImm(NegatedImm, 3932 SplatUndef.getZExtValue(), SplatBitSize, 3933 DAG, VmovVT, VT.is128BitVector(), 3934 VMVNModImm); 3935 if (Val.getNode()) { 3936 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val); 3937 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); 3938 } 3939 } 3940 } 3941 3942 // Scan through the operands to see if only one value is used. 3943 unsigned NumElts = VT.getVectorNumElements(); 3944 bool isOnlyLowElement = true; 3945 bool usesOnlyOneValue = true; 3946 bool isConstant = true; 3947 SDValue Value; 3948 for (unsigned i = 0; i < NumElts; ++i) { 3949 SDValue V = Op.getOperand(i); 3950 if (V.getOpcode() == ISD::UNDEF) 3951 continue; 3952 if (i > 0) 3953 isOnlyLowElement = false; 3954 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 3955 isConstant = false; 3956 3957 if (!Value.getNode()) 3958 Value = V; 3959 else if (V != Value) 3960 usesOnlyOneValue = false; 3961 } 3962 3963 if (!Value.getNode()) 3964 return DAG.getUNDEF(VT); 3965 3966 if (isOnlyLowElement) 3967 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); 3968 3969 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 3970 3971 // Use VDUP for non-constant splats. For f32 constant splats, reduce to 3972 // i32 and try again. 3973 if (usesOnlyOneValue && EltSize <= 32) { 3974 if (!isConstant) 3975 return DAG.getNode(ARMISD::VDUP, dl, VT, Value); 3976 if (VT.getVectorElementType().isFloatingPoint()) { 3977 SmallVector<SDValue, 8> Ops; 3978 for (unsigned i = 0; i < NumElts; ++i) 3979 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32, 3980 Op.getOperand(i))); 3981 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts); 3982 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts); 3983 Val = LowerBUILD_VECTOR(Val, DAG, ST); 3984 if (Val.getNode()) 3985 return DAG.getNode(ISD::BITCAST, dl, VT, Val); 3986 } 3987 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl); 3988 if (Val.getNode()) 3989 return DAG.getNode(ARMISD::VDUP, dl, VT, Val); 3990 } 3991 3992 // If all elements are constants and the case above didn't get hit, fall back 3993 // to the default expansion, which will generate a load from the constant 3994 // pool. 3995 if (isConstant) 3996 return SDValue(); 3997 3998 // Empirical tests suggest this is rarely worth it for vectors of length <= 2. 3999 if (NumElts >= 4) { 4000 SDValue shuffle = ReconstructShuffle(Op, DAG); 4001 if (shuffle != SDValue()) 4002 return shuffle; 4003 } 4004 4005 // Vectors with 32- or 64-bit elements can be built by directly assigning 4006 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands 4007 // will be legalized. 4008 if (EltSize >= 32) { 4009 // Do the expansion with floating-point types, since that is what the VFP 4010 // registers are defined to use, and since i64 is not legal. 4011 EVT EltVT = EVT::getFloatingPointVT(EltSize); 4012 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); 4013 SmallVector<SDValue, 8> Ops; 4014 for (unsigned i = 0; i < NumElts; ++i) 4015 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i))); 4016 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); 4017 return DAG.getNode(ISD::BITCAST, dl, VT, Val); 4018 } 4019 4020 return SDValue(); 4021 } 4022 4023 // Gather data to see if the operation can be modelled as a 4024 // shuffle in combination with VEXTs. 4025 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op, 4026 SelectionDAG &DAG) const { 4027 DebugLoc dl = Op.getDebugLoc(); 4028 EVT VT = Op.getValueType(); 4029 unsigned NumElts = VT.getVectorNumElements(); 4030 4031 SmallVector<SDValue, 2> SourceVecs; 4032 SmallVector<unsigned, 2> MinElts; 4033 SmallVector<unsigned, 2> MaxElts; 4034 4035 for (unsigned i = 0; i < NumElts; ++i) { 4036 SDValue V = Op.getOperand(i); 4037 if (V.getOpcode() == ISD::UNDEF) 4038 continue; 4039 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) { 4040 // A shuffle can only come from building a vector from various 4041 // elements of other vectors. 4042 return SDValue(); 4043 } 4044 4045 // Record this extraction against the appropriate vector if possible... 4046 SDValue SourceVec = V.getOperand(0); 4047 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue(); 4048 bool FoundSource = false; 4049 for (unsigned j = 0; j < SourceVecs.size(); ++j) { 4050 if (SourceVecs[j] == SourceVec) { 4051 if (MinElts[j] > EltNo) 4052 MinElts[j] = EltNo; 4053 if (MaxElts[j] < EltNo) 4054 MaxElts[j] = EltNo; 4055 FoundSource = true; 4056 break; 4057 } 4058 } 4059 4060 // Or record a new source if not... 4061 if (!FoundSource) { 4062 SourceVecs.push_back(SourceVec); 4063 MinElts.push_back(EltNo); 4064 MaxElts.push_back(EltNo); 4065 } 4066 } 4067 4068 // Currently only do something sane when at most two source vectors 4069 // involved. 4070 if (SourceVecs.size() > 2) 4071 return SDValue(); 4072 4073 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) }; 4074 int VEXTOffsets[2] = {0, 0}; 4075 4076 // This loop extracts the usage patterns of the source vectors 4077 // and prepares appropriate SDValues for a shuffle if possible. 4078 for (unsigned i = 0; i < SourceVecs.size(); ++i) { 4079 if (SourceVecs[i].getValueType() == VT) { 4080 // No VEXT necessary 4081 ShuffleSrcs[i] = SourceVecs[i]; 4082 VEXTOffsets[i] = 0; 4083 continue; 4084 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) { 4085 // It probably isn't worth padding out a smaller vector just to 4086 // break it down again in a shuffle. 4087 return SDValue(); 4088 } 4089 4090 // Since only 64-bit and 128-bit vectors are legal on ARM and 4091 // we've eliminated the other cases... 4092 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts && 4093 "unexpected vector sizes in ReconstructShuffle"); 4094 4095 if (MaxElts[i] - MinElts[i] >= NumElts) { 4096 // Span too large for a VEXT to cope 4097 return SDValue(); 4098 } 4099 4100 if (MinElts[i] >= NumElts) { 4101 // The extraction can just take the second half 4102 VEXTOffsets[i] = NumElts; 4103 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4104 SourceVecs[i], 4105 DAG.getIntPtrConstant(NumElts)); 4106 } else if (MaxElts[i] < NumElts) { 4107 // The extraction can just take the first half 4108 VEXTOffsets[i] = 0; 4109 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4110 SourceVecs[i], 4111 DAG.getIntPtrConstant(0)); 4112 } else { 4113 // An actual VEXT is needed 4114 VEXTOffsets[i] = MinElts[i]; 4115 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4116 SourceVecs[i], 4117 DAG.getIntPtrConstant(0)); 4118 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4119 SourceVecs[i], 4120 DAG.getIntPtrConstant(NumElts)); 4121 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2, 4122 DAG.getConstant(VEXTOffsets[i], MVT::i32)); 4123 } 4124 } 4125 4126 SmallVector<int, 8> Mask; 4127 4128 for (unsigned i = 0; i < NumElts; ++i) { 4129 SDValue Entry = Op.getOperand(i); 4130 if (Entry.getOpcode() == ISD::UNDEF) { 4131 Mask.push_back(-1); 4132 continue; 4133 } 4134 4135 SDValue ExtractVec = Entry.getOperand(0); 4136 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i) 4137 .getOperand(1))->getSExtValue(); 4138 if (ExtractVec == SourceVecs[0]) { 4139 Mask.push_back(ExtractElt - VEXTOffsets[0]); 4140 } else { 4141 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]); 4142 } 4143 } 4144 4145 // Final check before we try to produce nonsense... 4146 if (isShuffleMaskLegal(Mask, VT)) 4147 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1], 4148 &Mask[0]); 4149 4150 return SDValue(); 4151 } 4152 4153 /// isShuffleMaskLegal - Targets can use this to indicate that they only 4154 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 4155 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 4156 /// are assumed to be legal. 4157 bool 4158 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 4159 EVT VT) const { 4160 if (VT.getVectorNumElements() == 4 && 4161 (VT.is128BitVector() || VT.is64BitVector())) { 4162 unsigned PFIndexes[4]; 4163 for (unsigned i = 0; i != 4; ++i) { 4164 if (M[i] < 0) 4165 PFIndexes[i] = 8; 4166 else 4167 PFIndexes[i] = M[i]; 4168 } 4169 4170 // Compute the index in the perfect shuffle table. 4171 unsigned PFTableIndex = 4172 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 4173 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4174 unsigned Cost = (PFEntry >> 30); 4175 4176 if (Cost <= 4) 4177 return true; 4178 } 4179 4180 bool ReverseVEXT; 4181 unsigned Imm, WhichResult; 4182 4183 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4184 return (EltSize >= 32 || 4185 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 4186 isVREVMask(M, VT, 64) || 4187 isVREVMask(M, VT, 32) || 4188 isVREVMask(M, VT, 16) || 4189 isVEXTMask(M, VT, ReverseVEXT, Imm) || 4190 isVTBLMask(M, VT) || 4191 isVTRNMask(M, VT, WhichResult) || 4192 isVUZPMask(M, VT, WhichResult) || 4193 isVZIPMask(M, VT, WhichResult) || 4194 isVTRN_v_undef_Mask(M, VT, WhichResult) || 4195 isVUZP_v_undef_Mask(M, VT, WhichResult) || 4196 isVZIP_v_undef_Mask(M, VT, WhichResult)); 4197 } 4198 4199 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 4200 /// the specified operations to build the shuffle. 4201 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 4202 SDValue RHS, SelectionDAG &DAG, 4203 DebugLoc dl) { 4204 unsigned OpNum = (PFEntry >> 26) & 0x0F; 4205 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 4206 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 4207 4208 enum { 4209 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 4210 OP_VREV, 4211 OP_VDUP0, 4212 OP_VDUP1, 4213 OP_VDUP2, 4214 OP_VDUP3, 4215 OP_VEXT1, 4216 OP_VEXT2, 4217 OP_VEXT3, 4218 OP_VUZPL, // VUZP, left result 4219 OP_VUZPR, // VUZP, right result 4220 OP_VZIPL, // VZIP, left result 4221 OP_VZIPR, // VZIP, right result 4222 OP_VTRNL, // VTRN, left result 4223 OP_VTRNR // VTRN, right result 4224 }; 4225 4226 if (OpNum == OP_COPY) { 4227 if (LHSID == (1*9+2)*9+3) return LHS; 4228 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 4229 return RHS; 4230 } 4231 4232 SDValue OpLHS, OpRHS; 4233 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 4234 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 4235 EVT VT = OpLHS.getValueType(); 4236 4237 switch (OpNum) { 4238 default: llvm_unreachable("Unknown shuffle opcode!"); 4239 case OP_VREV: 4240 // VREV divides the vector in half and swaps within the half. 4241 if (VT.getVectorElementType() == MVT::i32 || 4242 VT.getVectorElementType() == MVT::f32) 4243 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); 4244 // vrev <4 x i16> -> VREV32 4245 if (VT.getVectorElementType() == MVT::i16) 4246 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS); 4247 // vrev <4 x i8> -> VREV16 4248 assert(VT.getVectorElementType() == MVT::i8); 4249 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS); 4250 case OP_VDUP0: 4251 case OP_VDUP1: 4252 case OP_VDUP2: 4253 case OP_VDUP3: 4254 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, 4255 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32)); 4256 case OP_VEXT1: 4257 case OP_VEXT2: 4258 case OP_VEXT3: 4259 return DAG.getNode(ARMISD::VEXT, dl, VT, 4260 OpLHS, OpRHS, 4261 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32)); 4262 case OP_VUZPL: 4263 case OP_VUZPR: 4264 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 4265 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL); 4266 case OP_VZIPL: 4267 case OP_VZIPR: 4268 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 4269 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL); 4270 case OP_VTRNL: 4271 case OP_VTRNR: 4272 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 4273 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL); 4274 } 4275 } 4276 4277 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op, 4278 SmallVectorImpl<int> &ShuffleMask, 4279 SelectionDAG &DAG) { 4280 // Check to see if we can use the VTBL instruction. 4281 SDValue V1 = Op.getOperand(0); 4282 SDValue V2 = Op.getOperand(1); 4283 DebugLoc DL = Op.getDebugLoc(); 4284 4285 SmallVector<SDValue, 8> VTBLMask; 4286 for (SmallVectorImpl<int>::iterator 4287 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I) 4288 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32)); 4289 4290 if (V2.getNode()->getOpcode() == ISD::UNDEF) 4291 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1, 4292 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, 4293 &VTBLMask[0], 8)); 4294 4295 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2, 4296 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, 4297 &VTBLMask[0], 8)); 4298 } 4299 4300 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { 4301 SDValue V1 = Op.getOperand(0); 4302 SDValue V2 = Op.getOperand(1); 4303 DebugLoc dl = Op.getDebugLoc(); 4304 EVT VT = Op.getValueType(); 4305 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode()); 4306 SmallVector<int, 8> ShuffleMask; 4307 4308 // Convert shuffles that are directly supported on NEON to target-specific 4309 // DAG nodes, instead of keeping them as shuffles and matching them again 4310 // during code selection. This is more efficient and avoids the possibility 4311 // of inconsistencies between legalization and selection. 4312 // FIXME: floating-point vectors should be canonicalized to integer vectors 4313 // of the same time so that they get CSEd properly. 4314 SVN->getMask(ShuffleMask); 4315 4316 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4317 if (EltSize <= 32) { 4318 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) { 4319 int Lane = SVN->getSplatIndex(); 4320 // If this is undef splat, generate it via "just" vdup, if possible. 4321 if (Lane == -1) Lane = 0; 4322 4323 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) { 4324 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0)); 4325 } 4326 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1, 4327 DAG.getConstant(Lane, MVT::i32)); 4328 } 4329 4330 bool ReverseVEXT; 4331 unsigned Imm; 4332 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) { 4333 if (ReverseVEXT) 4334 std::swap(V1, V2); 4335 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2, 4336 DAG.getConstant(Imm, MVT::i32)); 4337 } 4338 4339 if (isVREVMask(ShuffleMask, VT, 64)) 4340 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); 4341 if (isVREVMask(ShuffleMask, VT, 32)) 4342 return DAG.getNode(ARMISD::VREV32, dl, VT, V1); 4343 if (isVREVMask(ShuffleMask, VT, 16)) 4344 return DAG.getNode(ARMISD::VREV16, dl, VT, V1); 4345 4346 // Check for Neon shuffles that modify both input vectors in place. 4347 // If both results are used, i.e., if there are two shuffles with the same 4348 // source operands and with masks corresponding to both results of one of 4349 // these operations, DAG memoization will ensure that a single node is 4350 // used for both shuffles. 4351 unsigned WhichResult; 4352 if (isVTRNMask(ShuffleMask, VT, WhichResult)) 4353 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 4354 V1, V2).getValue(WhichResult); 4355 if (isVUZPMask(ShuffleMask, VT, WhichResult)) 4356 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 4357 V1, V2).getValue(WhichResult); 4358 if (isVZIPMask(ShuffleMask, VT, WhichResult)) 4359 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 4360 V1, V2).getValue(WhichResult); 4361 4362 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) 4363 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 4364 V1, V1).getValue(WhichResult); 4365 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) 4366 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 4367 V1, V1).getValue(WhichResult); 4368 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) 4369 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 4370 V1, V1).getValue(WhichResult); 4371 } 4372 4373 // If the shuffle is not directly supported and it has 4 elements, use 4374 // the PerfectShuffle-generated table to synthesize it from other shuffles. 4375 unsigned NumElts = VT.getVectorNumElements(); 4376 if (NumElts == 4) { 4377 unsigned PFIndexes[4]; 4378 for (unsigned i = 0; i != 4; ++i) { 4379 if (ShuffleMask[i] < 0) 4380 PFIndexes[i] = 8; 4381 else 4382 PFIndexes[i] = ShuffleMask[i]; 4383 } 4384 4385 // Compute the index in the perfect shuffle table. 4386 unsigned PFTableIndex = 4387 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 4388 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4389 unsigned Cost = (PFEntry >> 30); 4390 4391 if (Cost <= 4) 4392 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 4393 } 4394 4395 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs. 4396 if (EltSize >= 32) { 4397 // Do the expansion with floating-point types, since that is what the VFP 4398 // registers are defined to use, and since i64 is not legal. 4399 EVT EltVT = EVT::getFloatingPointVT(EltSize); 4400 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); 4401 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1); 4402 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2); 4403 SmallVector<SDValue, 8> Ops; 4404 for (unsigned i = 0; i < NumElts; ++i) { 4405 if (ShuffleMask[i] < 0) 4406 Ops.push_back(DAG.getUNDEF(EltVT)); 4407 else 4408 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 4409 ShuffleMask[i] < (int)NumElts ? V1 : V2, 4410 DAG.getConstant(ShuffleMask[i] & (NumElts-1), 4411 MVT::i32))); 4412 } 4413 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); 4414 return DAG.getNode(ISD::BITCAST, dl, VT, Val); 4415 } 4416 4417 if (VT == MVT::v8i8) { 4418 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG); 4419 if (NewOp.getNode()) 4420 return NewOp; 4421 } 4422 4423 return SDValue(); 4424 } 4425 4426 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4427 // EXTRACT_VECTOR_ELT is legal only for immediate indexes. 4428 SDValue Lane = Op.getOperand(1); 4429 if (!isa<ConstantSDNode>(Lane)) 4430 return SDValue(); 4431 4432 SDValue Vec = Op.getOperand(0); 4433 if (Op.getValueType() == MVT::i32 && 4434 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) { 4435 DebugLoc dl = Op.getDebugLoc(); 4436 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane); 4437 } 4438 4439 return Op; 4440 } 4441 4442 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 4443 // The only time a CONCAT_VECTORS operation can have legal types is when 4444 // two 64-bit vectors are concatenated to a 128-bit vector. 4445 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 && 4446 "unexpected CONCAT_VECTORS"); 4447 DebugLoc dl = Op.getDebugLoc(); 4448 SDValue Val = DAG.getUNDEF(MVT::v2f64); 4449 SDValue Op0 = Op.getOperand(0); 4450 SDValue Op1 = Op.getOperand(1); 4451 if (Op0.getOpcode() != ISD::UNDEF) 4452 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 4453 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0), 4454 DAG.getIntPtrConstant(0)); 4455 if (Op1.getOpcode() != ISD::UNDEF) 4456 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 4457 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1), 4458 DAG.getIntPtrConstant(1)); 4459 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val); 4460 } 4461 4462 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each 4463 /// element has been zero/sign-extended, depending on the isSigned parameter, 4464 /// from an integer type half its size. 4465 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG, 4466 bool isSigned) { 4467 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32. 4468 EVT VT = N->getValueType(0); 4469 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) { 4470 SDNode *BVN = N->getOperand(0).getNode(); 4471 if (BVN->getValueType(0) != MVT::v4i32 || 4472 BVN->getOpcode() != ISD::BUILD_VECTOR) 4473 return false; 4474 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0; 4475 unsigned HiElt = 1 - LoElt; 4476 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt)); 4477 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt)); 4478 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2)); 4479 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2)); 4480 if (!Lo0 || !Hi0 || !Lo1 || !Hi1) 4481 return false; 4482 if (isSigned) { 4483 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 && 4484 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32) 4485 return true; 4486 } else { 4487 if (Hi0->isNullValue() && Hi1->isNullValue()) 4488 return true; 4489 } 4490 return false; 4491 } 4492 4493 if (N->getOpcode() != ISD::BUILD_VECTOR) 4494 return false; 4495 4496 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 4497 SDNode *Elt = N->getOperand(i).getNode(); 4498 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) { 4499 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4500 unsigned HalfSize = EltSize / 2; 4501 if (isSigned) { 4502 int64_t SExtVal = C->getSExtValue(); 4503 if ((SExtVal >> HalfSize) != (SExtVal >> EltSize)) 4504 return false; 4505 } else { 4506 if ((C->getZExtValue() >> HalfSize) != 0) 4507 return false; 4508 } 4509 continue; 4510 } 4511 return false; 4512 } 4513 4514 return true; 4515 } 4516 4517 /// isSignExtended - Check if a node is a vector value that is sign-extended 4518 /// or a constant BUILD_VECTOR with sign-extended elements. 4519 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) { 4520 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N)) 4521 return true; 4522 if (isExtendedBUILD_VECTOR(N, DAG, true)) 4523 return true; 4524 return false; 4525 } 4526 4527 /// isZeroExtended - Check if a node is a vector value that is zero-extended 4528 /// or a constant BUILD_VECTOR with zero-extended elements. 4529 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { 4530 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N)) 4531 return true; 4532 if (isExtendedBUILD_VECTOR(N, DAG, false)) 4533 return true; 4534 return false; 4535 } 4536 4537 /// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending 4538 /// load, or BUILD_VECTOR with extended elements, return the unextended value. 4539 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) { 4540 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND) 4541 return N->getOperand(0); 4542 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) 4543 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(), 4544 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(), 4545 LD->isNonTemporal(), LD->getAlignment()); 4546 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will 4547 // have been legalized as a BITCAST from v4i32. 4548 if (N->getOpcode() == ISD::BITCAST) { 4549 SDNode *BVN = N->getOperand(0).getNode(); 4550 assert(BVN->getOpcode() == ISD::BUILD_VECTOR && 4551 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR"); 4552 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0; 4553 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32, 4554 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2)); 4555 } 4556 // Construct a new BUILD_VECTOR with elements truncated to half the size. 4557 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR"); 4558 EVT VT = N->getValueType(0); 4559 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2; 4560 unsigned NumElts = VT.getVectorNumElements(); 4561 MVT TruncVT = MVT::getIntegerVT(EltSize); 4562 SmallVector<SDValue, 8> Ops; 4563 for (unsigned i = 0; i != NumElts; ++i) { 4564 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i)); 4565 const APInt &CInt = C->getAPIntValue(); 4566 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT)); 4567 } 4568 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 4569 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts); 4570 } 4571 4572 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) { 4573 unsigned Opcode = N->getOpcode(); 4574 if (Opcode == ISD::ADD || Opcode == ISD::SUB) { 4575 SDNode *N0 = N->getOperand(0).getNode(); 4576 SDNode *N1 = N->getOperand(1).getNode(); 4577 return N0->hasOneUse() && N1->hasOneUse() && 4578 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); 4579 } 4580 return false; 4581 } 4582 4583 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) { 4584 unsigned Opcode = N->getOpcode(); 4585 if (Opcode == ISD::ADD || Opcode == ISD::SUB) { 4586 SDNode *N0 = N->getOperand(0).getNode(); 4587 SDNode *N1 = N->getOperand(1).getNode(); 4588 return N0->hasOneUse() && N1->hasOneUse() && 4589 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); 4590 } 4591 return false; 4592 } 4593 4594 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) { 4595 // Multiplications are only custom-lowered for 128-bit vectors so that 4596 // VMULL can be detected. Otherwise v2i64 multiplications are not legal. 4597 EVT VT = Op.getValueType(); 4598 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL"); 4599 SDNode *N0 = Op.getOperand(0).getNode(); 4600 SDNode *N1 = Op.getOperand(1).getNode(); 4601 unsigned NewOpc = 0; 4602 bool isMLA = false; 4603 bool isN0SExt = isSignExtended(N0, DAG); 4604 bool isN1SExt = isSignExtended(N1, DAG); 4605 if (isN0SExt && isN1SExt) 4606 NewOpc = ARMISD::VMULLs; 4607 else { 4608 bool isN0ZExt = isZeroExtended(N0, DAG); 4609 bool isN1ZExt = isZeroExtended(N1, DAG); 4610 if (isN0ZExt && isN1ZExt) 4611 NewOpc = ARMISD::VMULLu; 4612 else if (isN1SExt || isN1ZExt) { 4613 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these 4614 // into (s/zext A * s/zext C) + (s/zext B * s/zext C) 4615 if (isN1SExt && isAddSubSExt(N0, DAG)) { 4616 NewOpc = ARMISD::VMULLs; 4617 isMLA = true; 4618 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) { 4619 NewOpc = ARMISD::VMULLu; 4620 isMLA = true; 4621 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) { 4622 std::swap(N0, N1); 4623 NewOpc = ARMISD::VMULLu; 4624 isMLA = true; 4625 } 4626 } 4627 4628 if (!NewOpc) { 4629 if (VT == MVT::v2i64) 4630 // Fall through to expand this. It is not legal. 4631 return SDValue(); 4632 else 4633 // Other vector multiplications are legal. 4634 return Op; 4635 } 4636 } 4637 4638 // Legalize to a VMULL instruction. 4639 DebugLoc DL = Op.getDebugLoc(); 4640 SDValue Op0; 4641 SDValue Op1 = SkipExtension(N1, DAG); 4642 if (!isMLA) { 4643 Op0 = SkipExtension(N0, DAG); 4644 assert(Op0.getValueType().is64BitVector() && 4645 Op1.getValueType().is64BitVector() && 4646 "unexpected types for extended operands to VMULL"); 4647 return DAG.getNode(NewOpc, DL, VT, Op0, Op1); 4648 } 4649 4650 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during 4651 // isel lowering to take advantage of no-stall back to back vmul + vmla. 4652 // vmull q0, d4, d6 4653 // vmlal q0, d5, d6 4654 // is faster than 4655 // vaddl q0, d4, d5 4656 // vmovl q1, d6 4657 // vmul q0, q0, q1 4658 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG); 4659 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG); 4660 EVT Op1VT = Op1.getValueType(); 4661 return DAG.getNode(N0->getOpcode(), DL, VT, 4662 DAG.getNode(NewOpc, DL, VT, 4663 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), 4664 DAG.getNode(NewOpc, DL, VT, 4665 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); 4666 } 4667 4668 static SDValue 4669 LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) { 4670 // Convert to float 4671 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo)); 4672 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo)); 4673 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X); 4674 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y); 4675 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); 4676 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y); 4677 // Get reciprocal estimate. 4678 // float4 recip = vrecpeq_f32(yf); 4679 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4680 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y); 4681 // Because char has a smaller range than uchar, we can actually get away 4682 // without any newton steps. This requires that we use a weird bias 4683 // of 0xb000, however (again, this has been exhaustively tested). 4684 // float4 result = as_float4(as_int4(xf*recip) + 0xb000); 4685 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y); 4686 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X); 4687 Y = DAG.getConstant(0xb000, MVT::i32); 4688 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y); 4689 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y); 4690 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X); 4691 // Convert back to short. 4692 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X); 4693 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X); 4694 return X; 4695 } 4696 4697 static SDValue 4698 LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) { 4699 SDValue N2; 4700 // Convert to float. 4701 // float4 yf = vcvt_f32_s32(vmovl_s16(y)); 4702 // float4 xf = vcvt_f32_s32(vmovl_s16(x)); 4703 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0); 4704 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1); 4705 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); 4706 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); 4707 4708 // Use reciprocal estimate and one refinement step. 4709 // float4 recip = vrecpeq_f32(yf); 4710 // recip *= vrecpsq_f32(yf, recip); 4711 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4712 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1); 4713 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4714 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), 4715 N1, N2); 4716 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 4717 // Because short has a smaller range than ushort, we can actually get away 4718 // with only a single newton step. This requires that we use a weird bias 4719 // of 89, however (again, this has been exhaustively tested). 4720 // float4 result = as_float4(as_int4(xf*recip) + 0x89); 4721 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); 4722 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); 4723 N1 = DAG.getConstant(0x89, MVT::i32); 4724 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1); 4725 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); 4726 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); 4727 // Convert back to integer and return. 4728 // return vmovn_s32(vcvt_s32_f32(result)); 4729 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); 4730 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); 4731 return N0; 4732 } 4733 4734 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) { 4735 EVT VT = Op.getValueType(); 4736 assert((VT == MVT::v4i16 || VT == MVT::v8i8) && 4737 "unexpected type for custom-lowering ISD::SDIV"); 4738 4739 DebugLoc dl = Op.getDebugLoc(); 4740 SDValue N0 = Op.getOperand(0); 4741 SDValue N1 = Op.getOperand(1); 4742 SDValue N2, N3; 4743 4744 if (VT == MVT::v8i8) { 4745 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0); 4746 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1); 4747 4748 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4749 DAG.getIntPtrConstant(4)); 4750 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4751 DAG.getIntPtrConstant(4)); 4752 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4753 DAG.getIntPtrConstant(0)); 4754 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4755 DAG.getIntPtrConstant(0)); 4756 4757 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16 4758 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16 4759 4760 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); 4761 N0 = LowerCONCAT_VECTORS(N0, DAG); 4762 4763 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0); 4764 return N0; 4765 } 4766 return LowerSDIV_v4i16(N0, N1, dl, DAG); 4767 } 4768 4769 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) { 4770 EVT VT = Op.getValueType(); 4771 assert((VT == MVT::v4i16 || VT == MVT::v8i8) && 4772 "unexpected type for custom-lowering ISD::UDIV"); 4773 4774 DebugLoc dl = Op.getDebugLoc(); 4775 SDValue N0 = Op.getOperand(0); 4776 SDValue N1 = Op.getOperand(1); 4777 SDValue N2, N3; 4778 4779 if (VT == MVT::v8i8) { 4780 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0); 4781 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1); 4782 4783 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4784 DAG.getIntPtrConstant(4)); 4785 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4786 DAG.getIntPtrConstant(4)); 4787 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4788 DAG.getIntPtrConstant(0)); 4789 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4790 DAG.getIntPtrConstant(0)); 4791 4792 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16 4793 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16 4794 4795 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); 4796 N0 = LowerCONCAT_VECTORS(N0, DAG); 4797 4798 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8, 4799 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32), 4800 N0); 4801 return N0; 4802 } 4803 4804 // v4i16 sdiv ... Convert to float. 4805 // float4 yf = vcvt_f32_s32(vmovl_u16(y)); 4806 // float4 xf = vcvt_f32_s32(vmovl_u16(x)); 4807 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0); 4808 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1); 4809 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); 4810 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); 4811 4812 // Use reciprocal estimate and two refinement steps. 4813 // float4 recip = vrecpeq_f32(yf); 4814 // recip *= vrecpsq_f32(yf, recip); 4815 // recip *= vrecpsq_f32(yf, recip); 4816 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4817 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1); 4818 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4819 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), 4820 BN1, N2); 4821 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 4822 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4823 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), 4824 BN1, N2); 4825 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 4826 // Simply multiplying by the reciprocal estimate can leave us a few ulps 4827 // too low, so we add 2 ulps (exhaustive testing shows that this is enough, 4828 // and that it will never cause us to return an answer too large). 4829 // float4 result = as_float4(as_int4(xf*recip) + 2); 4830 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); 4831 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); 4832 N1 = DAG.getConstant(2, MVT::i32); 4833 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1); 4834 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); 4835 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); 4836 // Convert back to integer and return. 4837 // return vmovn_u32(vcvt_s32_f32(result)); 4838 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); 4839 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); 4840 return N0; 4841 } 4842 4843 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 4844 EVT VT = Op.getNode()->getValueType(0); 4845 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 4846 4847 unsigned Opc; 4848 bool ExtraOp = false; 4849 switch (Op.getOpcode()) { 4850 default: assert(0 && "Invalid code"); 4851 case ISD::ADDC: Opc = ARMISD::ADDC; break; 4852 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break; 4853 case ISD::SUBC: Opc = ARMISD::SUBC; break; 4854 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break; 4855 } 4856 4857 if (!ExtraOp) 4858 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 4859 Op.getOperand(1)); 4860 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 4861 Op.getOperand(1), Op.getOperand(2)); 4862 } 4863 4864 static void 4865 ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl<SDValue>& Results, 4866 SelectionDAG &DAG, unsigned NewOp) { 4867 EVT T = Node->getValueType(0); 4868 DebugLoc dl = Node->getDebugLoc(); 4869 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 4870 4871 SmallVector<SDValue, 6> Ops; 4872 Ops.push_back(Node->getOperand(0)); // Chain 4873 Ops.push_back(Node->getOperand(1)); // Ptr 4874 // Low part of Val1 4875 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4876 Node->getOperand(2), DAG.getIntPtrConstant(0))); 4877 // High part of Val1 4878 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4879 Node->getOperand(2), DAG.getIntPtrConstant(1))); 4880 if (NewOp == ARMISD::ATOMCMPXCHG64_DAG) { 4881 // High part of Val1 4882 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4883 Node->getOperand(3), DAG.getIntPtrConstant(0))); 4884 // High part of Val2 4885 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4886 Node->getOperand(3), DAG.getIntPtrConstant(1))); 4887 } 4888 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 4889 SDValue Result = 4890 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops.data(), Ops.size(), MVT::i64, 4891 cast<MemSDNode>(Node)->getMemOperand()); 4892 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1) }; 4893 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 4894 Results.push_back(Result.getValue(2)); 4895 } 4896 4897 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 4898 switch (Op.getOpcode()) { 4899 default: llvm_unreachable("Don't know how to custom lower this!"); 4900 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 4901 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 4902 case ISD::GlobalAddress: 4903 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : 4904 LowerGlobalAddressELF(Op, DAG); 4905 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 4906 case ISD::SELECT: return LowerSELECT(Op, DAG); 4907 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 4908 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 4909 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 4910 case ISD::VASTART: return LowerVASTART(Op, DAG); 4911 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget); 4912 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget); 4913 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget); 4914 case ISD::SINT_TO_FP: 4915 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); 4916 case ISD::FP_TO_SINT: 4917 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); 4918 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 4919 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 4920 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 4921 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); 4922 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG); 4923 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG); 4924 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG); 4925 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG, 4926 Subtarget); 4927 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG); 4928 case ISD::SHL: 4929 case ISD::SRL: 4930 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget); 4931 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); 4932 case ISD::SRL_PARTS: 4933 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG); 4934 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget); 4935 case ISD::SETCC: return LowerVSETCC(Op, DAG); 4936 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget); 4937 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 4938 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 4939 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 4940 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 4941 case ISD::MUL: return LowerMUL(Op, DAG); 4942 case ISD::SDIV: return LowerSDIV(Op, DAG); 4943 case ISD::UDIV: return LowerUDIV(Op, DAG); 4944 case ISD::ADDC: 4945 case ISD::ADDE: 4946 case ISD::SUBC: 4947 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 4948 } 4949 return SDValue(); 4950 } 4951 4952 /// ReplaceNodeResults - Replace the results of node with an illegal result 4953 /// type with new values built out of custom code. 4954 void ARMTargetLowering::ReplaceNodeResults(SDNode *N, 4955 SmallVectorImpl<SDValue>&Results, 4956 SelectionDAG &DAG) const { 4957 SDValue Res; 4958 switch (N->getOpcode()) { 4959 default: 4960 llvm_unreachable("Don't know how to custom expand this!"); 4961 break; 4962 case ISD::BITCAST: 4963 Res = ExpandBITCAST(N, DAG); 4964 break; 4965 case ISD::SRL: 4966 case ISD::SRA: 4967 Res = Expand64BitShift(N, DAG, Subtarget); 4968 break; 4969 case ISD::ATOMIC_LOAD_ADD: 4970 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMADD64_DAG); 4971 return; 4972 case ISD::ATOMIC_LOAD_AND: 4973 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMAND64_DAG); 4974 return; 4975 case ISD::ATOMIC_LOAD_NAND: 4976 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMNAND64_DAG); 4977 return; 4978 case ISD::ATOMIC_LOAD_OR: 4979 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMOR64_DAG); 4980 return; 4981 case ISD::ATOMIC_LOAD_SUB: 4982 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSUB64_DAG); 4983 return; 4984 case ISD::ATOMIC_LOAD_XOR: 4985 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMXOR64_DAG); 4986 return; 4987 case ISD::ATOMIC_SWAP: 4988 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSWAP64_DAG); 4989 return; 4990 case ISD::ATOMIC_CMP_SWAP: 4991 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMCMPXCHG64_DAG); 4992 return; 4993 } 4994 if (Res.getNode()) 4995 Results.push_back(Res); 4996 } 4997 4998 //===----------------------------------------------------------------------===// 4999 // ARM Scheduler Hooks 5000 //===----------------------------------------------------------------------===// 5001 5002 MachineBasicBlock * 5003 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 5004 MachineBasicBlock *BB, 5005 unsigned Size) const { 5006 unsigned dest = MI->getOperand(0).getReg(); 5007 unsigned ptr = MI->getOperand(1).getReg(); 5008 unsigned oldval = MI->getOperand(2).getReg(); 5009 unsigned newval = MI->getOperand(3).getReg(); 5010 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5011 DebugLoc dl = MI->getDebugLoc(); 5012 bool isThumb2 = Subtarget->isThumb2(); 5013 5014 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5015 unsigned scratch = 5016 MRI.createVirtualRegister(isThumb2 ? ARM::rGPRRegisterClass 5017 : ARM::GPRRegisterClass); 5018 5019 if (isThumb2) { 5020 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass); 5021 MRI.constrainRegClass(oldval, ARM::rGPRRegisterClass); 5022 MRI.constrainRegClass(newval, ARM::rGPRRegisterClass); 5023 } 5024 5025 unsigned ldrOpc, strOpc; 5026 switch (Size) { 5027 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 5028 case 1: 5029 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 5030 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 5031 break; 5032 case 2: 5033 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 5034 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 5035 break; 5036 case 4: 5037 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 5038 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 5039 break; 5040 } 5041 5042 MachineFunction *MF = BB->getParent(); 5043 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5044 MachineFunction::iterator It = BB; 5045 ++It; // insert the new blocks after the current block 5046 5047 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 5048 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 5049 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5050 MF->insert(It, loop1MBB); 5051 MF->insert(It, loop2MBB); 5052 MF->insert(It, exitMBB); 5053 5054 // Transfer the remainder of BB and its successor edges to exitMBB. 5055 exitMBB->splice(exitMBB->begin(), BB, 5056 llvm::next(MachineBasicBlock::iterator(MI)), 5057 BB->end()); 5058 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5059 5060 // thisMBB: 5061 // ... 5062 // fallthrough --> loop1MBB 5063 BB->addSuccessor(loop1MBB); 5064 5065 // loop1MBB: 5066 // ldrex dest, [ptr] 5067 // cmp dest, oldval 5068 // bne exitMBB 5069 BB = loop1MBB; 5070 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 5071 if (ldrOpc == ARM::t2LDREX) 5072 MIB.addImm(0); 5073 AddDefaultPred(MIB); 5074 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 5075 .addReg(dest).addReg(oldval)); 5076 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5077 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5078 BB->addSuccessor(loop2MBB); 5079 BB->addSuccessor(exitMBB); 5080 5081 // loop2MBB: 5082 // strex scratch, newval, [ptr] 5083 // cmp scratch, #0 5084 // bne loop1MBB 5085 BB = loop2MBB; 5086 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval).addReg(ptr); 5087 if (strOpc == ARM::t2STREX) 5088 MIB.addImm(0); 5089 AddDefaultPred(MIB); 5090 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5091 .addReg(scratch).addImm(0)); 5092 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5093 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5094 BB->addSuccessor(loop1MBB); 5095 BB->addSuccessor(exitMBB); 5096 5097 // exitMBB: 5098 // ... 5099 BB = exitMBB; 5100 5101 MI->eraseFromParent(); // The instruction is gone now. 5102 5103 return BB; 5104 } 5105 5106 MachineBasicBlock * 5107 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 5108 unsigned Size, unsigned BinOpcode) const { 5109 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 5110 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5111 5112 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5113 MachineFunction *MF = BB->getParent(); 5114 MachineFunction::iterator It = BB; 5115 ++It; 5116 5117 unsigned dest = MI->getOperand(0).getReg(); 5118 unsigned ptr = MI->getOperand(1).getReg(); 5119 unsigned incr = MI->getOperand(2).getReg(); 5120 DebugLoc dl = MI->getDebugLoc(); 5121 bool isThumb2 = Subtarget->isThumb2(); 5122 5123 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5124 if (isThumb2) { 5125 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass); 5126 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass); 5127 } 5128 5129 unsigned ldrOpc, strOpc; 5130 switch (Size) { 5131 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 5132 case 1: 5133 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 5134 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 5135 break; 5136 case 2: 5137 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 5138 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 5139 break; 5140 case 4: 5141 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 5142 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 5143 break; 5144 } 5145 5146 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5147 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5148 MF->insert(It, loopMBB); 5149 MF->insert(It, exitMBB); 5150 5151 // Transfer the remainder of BB and its successor edges to exitMBB. 5152 exitMBB->splice(exitMBB->begin(), BB, 5153 llvm::next(MachineBasicBlock::iterator(MI)), 5154 BB->end()); 5155 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5156 5157 TargetRegisterClass *TRC = 5158 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5159 unsigned scratch = MRI.createVirtualRegister(TRC); 5160 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC); 5161 5162 // thisMBB: 5163 // ... 5164 // fallthrough --> loopMBB 5165 BB->addSuccessor(loopMBB); 5166 5167 // loopMBB: 5168 // ldrex dest, ptr 5169 // <binop> scratch2, dest, incr 5170 // strex scratch, scratch2, ptr 5171 // cmp scratch, #0 5172 // bne- loopMBB 5173 // fallthrough --> exitMBB 5174 BB = loopMBB; 5175 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 5176 if (ldrOpc == ARM::t2LDREX) 5177 MIB.addImm(0); 5178 AddDefaultPred(MIB); 5179 if (BinOpcode) { 5180 // operand order needs to go the other way for NAND 5181 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr) 5182 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2). 5183 addReg(incr).addReg(dest)).addReg(0); 5184 else 5185 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2). 5186 addReg(dest).addReg(incr)).addReg(0); 5187 } 5188 5189 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr); 5190 if (strOpc == ARM::t2STREX) 5191 MIB.addImm(0); 5192 AddDefaultPred(MIB); 5193 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5194 .addReg(scratch).addImm(0)); 5195 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5196 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5197 5198 BB->addSuccessor(loopMBB); 5199 BB->addSuccessor(exitMBB); 5200 5201 // exitMBB: 5202 // ... 5203 BB = exitMBB; 5204 5205 MI->eraseFromParent(); // The instruction is gone now. 5206 5207 return BB; 5208 } 5209 5210 MachineBasicBlock * 5211 ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI, 5212 MachineBasicBlock *BB, 5213 unsigned Size, 5214 bool signExtend, 5215 ARMCC::CondCodes Cond) const { 5216 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5217 5218 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5219 MachineFunction *MF = BB->getParent(); 5220 MachineFunction::iterator It = BB; 5221 ++It; 5222 5223 unsigned dest = MI->getOperand(0).getReg(); 5224 unsigned ptr = MI->getOperand(1).getReg(); 5225 unsigned incr = MI->getOperand(2).getReg(); 5226 unsigned oldval = dest; 5227 DebugLoc dl = MI->getDebugLoc(); 5228 bool isThumb2 = Subtarget->isThumb2(); 5229 5230 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5231 if (isThumb2) { 5232 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass); 5233 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass); 5234 } 5235 5236 unsigned ldrOpc, strOpc, extendOpc; 5237 switch (Size) { 5238 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 5239 case 1: 5240 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 5241 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 5242 extendOpc = isThumb2 ? ARM::t2SXTB : ARM::SXTB; 5243 break; 5244 case 2: 5245 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 5246 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 5247 extendOpc = isThumb2 ? ARM::t2SXTH : ARM::SXTH; 5248 break; 5249 case 4: 5250 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 5251 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 5252 extendOpc = 0; 5253 break; 5254 } 5255 5256 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5257 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5258 MF->insert(It, loopMBB); 5259 MF->insert(It, exitMBB); 5260 5261 // Transfer the remainder of BB and its successor edges to exitMBB. 5262 exitMBB->splice(exitMBB->begin(), BB, 5263 llvm::next(MachineBasicBlock::iterator(MI)), 5264 BB->end()); 5265 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5266 5267 TargetRegisterClass *TRC = 5268 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5269 unsigned scratch = MRI.createVirtualRegister(TRC); 5270 unsigned scratch2 = MRI.createVirtualRegister(TRC); 5271 5272 // thisMBB: 5273 // ... 5274 // fallthrough --> loopMBB 5275 BB->addSuccessor(loopMBB); 5276 5277 // loopMBB: 5278 // ldrex dest, ptr 5279 // (sign extend dest, if required) 5280 // cmp dest, incr 5281 // cmov.cond scratch2, dest, incr 5282 // strex scratch, scratch2, ptr 5283 // cmp scratch, #0 5284 // bne- loopMBB 5285 // fallthrough --> exitMBB 5286 BB = loopMBB; 5287 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 5288 if (ldrOpc == ARM::t2LDREX) 5289 MIB.addImm(0); 5290 AddDefaultPred(MIB); 5291 5292 // Sign extend the value, if necessary. 5293 if (signExtend && extendOpc) { 5294 oldval = MRI.createVirtualRegister(ARM::GPRRegisterClass); 5295 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval) 5296 .addReg(dest) 5297 .addImm(0)); 5298 } 5299 5300 // Build compare and cmov instructions. 5301 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 5302 .addReg(oldval).addReg(incr)); 5303 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2) 5304 .addReg(oldval).addReg(incr).addImm(Cond).addReg(ARM::CPSR); 5305 5306 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr); 5307 if (strOpc == ARM::t2STREX) 5308 MIB.addImm(0); 5309 AddDefaultPred(MIB); 5310 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5311 .addReg(scratch).addImm(0)); 5312 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5313 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5314 5315 BB->addSuccessor(loopMBB); 5316 BB->addSuccessor(exitMBB); 5317 5318 // exitMBB: 5319 // ... 5320 BB = exitMBB; 5321 5322 MI->eraseFromParent(); // The instruction is gone now. 5323 5324 return BB; 5325 } 5326 5327 MachineBasicBlock * 5328 ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB, 5329 unsigned Op1, unsigned Op2, 5330 bool NeedsCarry, bool IsCmpxchg) const { 5331 // This also handles ATOMIC_SWAP, indicated by Op1==0. 5332 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5333 5334 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5335 MachineFunction *MF = BB->getParent(); 5336 MachineFunction::iterator It = BB; 5337 ++It; 5338 5339 unsigned destlo = MI->getOperand(0).getReg(); 5340 unsigned desthi = MI->getOperand(1).getReg(); 5341 unsigned ptr = MI->getOperand(2).getReg(); 5342 unsigned vallo = MI->getOperand(3).getReg(); 5343 unsigned valhi = MI->getOperand(4).getReg(); 5344 DebugLoc dl = MI->getDebugLoc(); 5345 bool isThumb2 = Subtarget->isThumb2(); 5346 5347 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5348 if (isThumb2) { 5349 MRI.constrainRegClass(destlo, ARM::rGPRRegisterClass); 5350 MRI.constrainRegClass(desthi, ARM::rGPRRegisterClass); 5351 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass); 5352 } 5353 5354 unsigned ldrOpc = isThumb2 ? ARM::t2LDREXD : ARM::LDREXD; 5355 unsigned strOpc = isThumb2 ? ARM::t2STREXD : ARM::STREXD; 5356 5357 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5358 MachineBasicBlock *contBB = 0, *cont2BB = 0; 5359 if (IsCmpxchg) { 5360 contBB = MF->CreateMachineBasicBlock(LLVM_BB); 5361 cont2BB = MF->CreateMachineBasicBlock(LLVM_BB); 5362 } 5363 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5364 MF->insert(It, loopMBB); 5365 if (IsCmpxchg) { 5366 MF->insert(It, contBB); 5367 MF->insert(It, cont2BB); 5368 } 5369 MF->insert(It, exitMBB); 5370 5371 // Transfer the remainder of BB and its successor edges to exitMBB. 5372 exitMBB->splice(exitMBB->begin(), BB, 5373 llvm::next(MachineBasicBlock::iterator(MI)), 5374 BB->end()); 5375 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5376 5377 TargetRegisterClass *TRC = 5378 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5379 unsigned storesuccess = MRI.createVirtualRegister(TRC); 5380 5381 // thisMBB: 5382 // ... 5383 // fallthrough --> loopMBB 5384 BB->addSuccessor(loopMBB); 5385 5386 // loopMBB: 5387 // ldrexd r2, r3, ptr 5388 // <binopa> r0, r2, incr 5389 // <binopb> r1, r3, incr 5390 // strexd storesuccess, r0, r1, ptr 5391 // cmp storesuccess, #0 5392 // bne- loopMBB 5393 // fallthrough --> exitMBB 5394 // 5395 // Note that the registers are explicitly specified because there is not any 5396 // way to force the register allocator to allocate a register pair. 5397 // 5398 // FIXME: The hardcoded registers are not necessary for Thumb2, but we 5399 // need to properly enforce the restriction that the two output registers 5400 // for ldrexd must be different. 5401 BB = loopMBB; 5402 // Load 5403 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc)) 5404 .addReg(ARM::R2, RegState::Define) 5405 .addReg(ARM::R3, RegState::Define).addReg(ptr)); 5406 // Copy r2/r3 into dest. (This copy will normally be coalesced.) 5407 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo).addReg(ARM::R2); 5408 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi).addReg(ARM::R3); 5409 5410 if (IsCmpxchg) { 5411 // Add early exit 5412 for (unsigned i = 0; i < 2; i++) { 5413 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : 5414 ARM::CMPrr)) 5415 .addReg(i == 0 ? destlo : desthi) 5416 .addReg(i == 0 ? vallo : valhi)); 5417 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5418 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5419 BB->addSuccessor(exitMBB); 5420 BB->addSuccessor(i == 0 ? contBB : cont2BB); 5421 BB = (i == 0 ? contBB : cont2BB); 5422 } 5423 5424 // Copy to physregs for strexd 5425 unsigned setlo = MI->getOperand(5).getReg(); 5426 unsigned sethi = MI->getOperand(6).getReg(); 5427 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(setlo); 5428 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(sethi); 5429 } else if (Op1) { 5430 // Perform binary operation 5431 AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), ARM::R0) 5432 .addReg(destlo).addReg(vallo)) 5433 .addReg(NeedsCarry ? ARM::CPSR : 0, getDefRegState(NeedsCarry)); 5434 AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), ARM::R1) 5435 .addReg(desthi).addReg(valhi)).addReg(0); 5436 } else { 5437 // Copy to physregs for strexd 5438 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(vallo); 5439 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(valhi); 5440 } 5441 5442 // Store 5443 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess) 5444 .addReg(ARM::R0).addReg(ARM::R1).addReg(ptr)); 5445 // Cmp+jump 5446 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5447 .addReg(storesuccess).addImm(0)); 5448 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5449 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5450 5451 BB->addSuccessor(loopMBB); 5452 BB->addSuccessor(exitMBB); 5453 5454 // exitMBB: 5455 // ... 5456 BB = exitMBB; 5457 5458 MI->eraseFromParent(); // The instruction is gone now. 5459 5460 return BB; 5461 } 5462 5463 static 5464 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) { 5465 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(), 5466 E = MBB->succ_end(); I != E; ++I) 5467 if (*I != Succ) 5468 return *I; 5469 llvm_unreachable("Expecting a BB with two successors!"); 5470 } 5471 5472 MachineBasicBlock * 5473 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 5474 MachineBasicBlock *BB) const { 5475 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5476 DebugLoc dl = MI->getDebugLoc(); 5477 bool isThumb2 = Subtarget->isThumb2(); 5478 switch (MI->getOpcode()) { 5479 default: { 5480 MI->dump(); 5481 llvm_unreachable("Unexpected instr type to insert"); 5482 } 5483 case ARM::STRi_preidx: 5484 case ARM::STRBi_preidx: { 5485 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ? 5486 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM; 5487 // Decode the offset. 5488 unsigned Offset = MI->getOperand(4).getImm(); 5489 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub; 5490 Offset = ARM_AM::getAM2Offset(Offset); 5491 if (isSub) 5492 Offset = -Offset; 5493 5494 MachineMemOperand *MMO = *MI->memoperands_begin(); 5495 BuildMI(*BB, MI, dl, TII->get(NewOpc)) 5496 .addOperand(MI->getOperand(0)) // Rn_wb 5497 .addOperand(MI->getOperand(1)) // Rt 5498 .addOperand(MI->getOperand(2)) // Rn 5499 .addImm(Offset) // offset (skip GPR==zero_reg) 5500 .addOperand(MI->getOperand(5)) // pred 5501 .addOperand(MI->getOperand(6)) 5502 .addMemOperand(MMO); 5503 MI->eraseFromParent(); 5504 return BB; 5505 } 5506 case ARM::STRr_preidx: 5507 case ARM::STRBr_preidx: 5508 case ARM::STRH_preidx: { 5509 unsigned NewOpc; 5510 switch (MI->getOpcode()) { 5511 default: llvm_unreachable("unexpected opcode!"); 5512 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break; 5513 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break; 5514 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break; 5515 } 5516 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc)); 5517 for (unsigned i = 0; i < MI->getNumOperands(); ++i) 5518 MIB.addOperand(MI->getOperand(i)); 5519 MI->eraseFromParent(); 5520 return BB; 5521 } 5522 case ARM::ATOMIC_LOAD_ADD_I8: 5523 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 5524 case ARM::ATOMIC_LOAD_ADD_I16: 5525 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 5526 case ARM::ATOMIC_LOAD_ADD_I32: 5527 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 5528 5529 case ARM::ATOMIC_LOAD_AND_I8: 5530 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 5531 case ARM::ATOMIC_LOAD_AND_I16: 5532 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 5533 case ARM::ATOMIC_LOAD_AND_I32: 5534 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 5535 5536 case ARM::ATOMIC_LOAD_OR_I8: 5537 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 5538 case ARM::ATOMIC_LOAD_OR_I16: 5539 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 5540 case ARM::ATOMIC_LOAD_OR_I32: 5541 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 5542 5543 case ARM::ATOMIC_LOAD_XOR_I8: 5544 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 5545 case ARM::ATOMIC_LOAD_XOR_I16: 5546 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 5547 case ARM::ATOMIC_LOAD_XOR_I32: 5548 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 5549 5550 case ARM::ATOMIC_LOAD_NAND_I8: 5551 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 5552 case ARM::ATOMIC_LOAD_NAND_I16: 5553 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 5554 case ARM::ATOMIC_LOAD_NAND_I32: 5555 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 5556 5557 case ARM::ATOMIC_LOAD_SUB_I8: 5558 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 5559 case ARM::ATOMIC_LOAD_SUB_I16: 5560 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 5561 case ARM::ATOMIC_LOAD_SUB_I32: 5562 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 5563 5564 case ARM::ATOMIC_LOAD_MIN_I8: 5565 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::LT); 5566 case ARM::ATOMIC_LOAD_MIN_I16: 5567 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::LT); 5568 case ARM::ATOMIC_LOAD_MIN_I32: 5569 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::LT); 5570 5571 case ARM::ATOMIC_LOAD_MAX_I8: 5572 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::GT); 5573 case ARM::ATOMIC_LOAD_MAX_I16: 5574 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::GT); 5575 case ARM::ATOMIC_LOAD_MAX_I32: 5576 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::GT); 5577 5578 case ARM::ATOMIC_LOAD_UMIN_I8: 5579 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::LO); 5580 case ARM::ATOMIC_LOAD_UMIN_I16: 5581 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::LO); 5582 case ARM::ATOMIC_LOAD_UMIN_I32: 5583 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::LO); 5584 5585 case ARM::ATOMIC_LOAD_UMAX_I8: 5586 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::HI); 5587 case ARM::ATOMIC_LOAD_UMAX_I16: 5588 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::HI); 5589 case ARM::ATOMIC_LOAD_UMAX_I32: 5590 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::HI); 5591 5592 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0); 5593 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0); 5594 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0); 5595 5596 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1); 5597 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2); 5598 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4); 5599 5600 5601 case ARM::ATOMADD6432: 5602 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr, 5603 isThumb2 ? ARM::t2ADCrr : ARM::ADCrr, 5604 /*NeedsCarry*/ true); 5605 case ARM::ATOMSUB6432: 5606 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr, 5607 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr, 5608 /*NeedsCarry*/ true); 5609 case ARM::ATOMOR6432: 5610 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr, 5611 isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 5612 case ARM::ATOMXOR6432: 5613 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2EORrr : ARM::EORrr, 5614 isThumb2 ? ARM::t2EORrr : ARM::EORrr); 5615 case ARM::ATOMAND6432: 5616 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr, 5617 isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 5618 case ARM::ATOMSWAP6432: 5619 return EmitAtomicBinary64(MI, BB, 0, 0, false); 5620 case ARM::ATOMCMPXCHG6432: 5621 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr, 5622 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr, 5623 /*NeedsCarry*/ false, /*IsCmpxchg*/true); 5624 5625 case ARM::tMOVCCr_pseudo: { 5626 // To "insert" a SELECT_CC instruction, we actually have to insert the 5627 // diamond control-flow pattern. The incoming instruction knows the 5628 // destination vreg to set, the condition code register to branch on, the 5629 // true/false values to select between, and a branch opcode to use. 5630 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5631 MachineFunction::iterator It = BB; 5632 ++It; 5633 5634 // thisMBB: 5635 // ... 5636 // TrueVal = ... 5637 // cmpTY ccX, r1, r2 5638 // bCC copy1MBB 5639 // fallthrough --> copy0MBB 5640 MachineBasicBlock *thisMBB = BB; 5641 MachineFunction *F = BB->getParent(); 5642 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 5643 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 5644 F->insert(It, copy0MBB); 5645 F->insert(It, sinkMBB); 5646 5647 // Transfer the remainder of BB and its successor edges to sinkMBB. 5648 sinkMBB->splice(sinkMBB->begin(), BB, 5649 llvm::next(MachineBasicBlock::iterator(MI)), 5650 BB->end()); 5651 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 5652 5653 BB->addSuccessor(copy0MBB); 5654 BB->addSuccessor(sinkMBB); 5655 5656 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB) 5657 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); 5658 5659 // copy0MBB: 5660 // %FalseValue = ... 5661 // # fallthrough to sinkMBB 5662 BB = copy0MBB; 5663 5664 // Update machine-CFG edges 5665 BB->addSuccessor(sinkMBB); 5666 5667 // sinkMBB: 5668 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 5669 // ... 5670 BB = sinkMBB; 5671 BuildMI(*BB, BB->begin(), dl, 5672 TII->get(ARM::PHI), MI->getOperand(0).getReg()) 5673 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 5674 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 5675 5676 MI->eraseFromParent(); // The pseudo instruction is gone now. 5677 return BB; 5678 } 5679 5680 case ARM::BCCi64: 5681 case ARM::BCCZi64: { 5682 // If there is an unconditional branch to the other successor, remove it. 5683 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 5684 5685 // Compare both parts that make up the double comparison separately for 5686 // equality. 5687 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64; 5688 5689 unsigned LHS1 = MI->getOperand(1).getReg(); 5690 unsigned LHS2 = MI->getOperand(2).getReg(); 5691 if (RHSisZero) { 5692 AddDefaultPred(BuildMI(BB, dl, 5693 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5694 .addReg(LHS1).addImm(0)); 5695 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5696 .addReg(LHS2).addImm(0) 5697 .addImm(ARMCC::EQ).addReg(ARM::CPSR); 5698 } else { 5699 unsigned RHS1 = MI->getOperand(3).getReg(); 5700 unsigned RHS2 = MI->getOperand(4).getReg(); 5701 AddDefaultPred(BuildMI(BB, dl, 5702 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 5703 .addReg(LHS1).addReg(RHS1)); 5704 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 5705 .addReg(LHS2).addReg(RHS2) 5706 .addImm(ARMCC::EQ).addReg(ARM::CPSR); 5707 } 5708 5709 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB(); 5710 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB); 5711 if (MI->getOperand(0).getImm() == ARMCC::NE) 5712 std::swap(destMBB, exitMBB); 5713 5714 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5715 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR); 5716 if (isThumb2) 5717 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB)); 5718 else 5719 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB); 5720 5721 MI->eraseFromParent(); // The pseudo instruction is gone now. 5722 return BB; 5723 } 5724 } 5725 } 5726 5727 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 5728 SDNode *Node) const { 5729 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, 5730 // RSB, RSC. Coming out of isel, they have an implicit CPSR def, but the 5731 // optional operand is not filled in. If the carry bit is used, then change 5732 // the optional operand to CPSR. Otherwise, remove the CPSR implicit def. 5733 const MCInstrDesc &MCID = MI->getDesc(); 5734 if (Node->hasAnyUseOfValue(1)) { 5735 MachineOperand &MO = MI->getOperand(MCID.getNumOperands() - 1); 5736 MO.setReg(ARM::CPSR); 5737 MO.setIsDef(true); 5738 } else { 5739 for (unsigned i = MCID.getNumOperands(), e = MI->getNumOperands(); 5740 i != e; ++i) { 5741 const MachineOperand &MO = MI->getOperand(i); 5742 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) { 5743 MI->RemoveOperand(i); 5744 break; 5745 } 5746 } 5747 } 5748 } 5749 5750 //===----------------------------------------------------------------------===// 5751 // ARM Optimization Hooks 5752 //===----------------------------------------------------------------------===// 5753 5754 static 5755 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 5756 TargetLowering::DAGCombinerInfo &DCI) { 5757 SelectionDAG &DAG = DCI.DAG; 5758 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 5759 EVT VT = N->getValueType(0); 5760 unsigned Opc = N->getOpcode(); 5761 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 5762 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 5763 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 5764 ISD::CondCode CC = ISD::SETCC_INVALID; 5765 5766 if (isSlctCC) { 5767 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 5768 } else { 5769 SDValue CCOp = Slct.getOperand(0); 5770 if (CCOp.getOpcode() == ISD::SETCC) 5771 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 5772 } 5773 5774 bool DoXform = false; 5775 bool InvCC = false; 5776 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 5777 "Bad input!"); 5778 5779 if (LHS.getOpcode() == ISD::Constant && 5780 cast<ConstantSDNode>(LHS)->isNullValue()) { 5781 DoXform = true; 5782 } else if (CC != ISD::SETCC_INVALID && 5783 RHS.getOpcode() == ISD::Constant && 5784 cast<ConstantSDNode>(RHS)->isNullValue()) { 5785 std::swap(LHS, RHS); 5786 SDValue Op0 = Slct.getOperand(0); 5787 EVT OpVT = isSlctCC ? Op0.getValueType() : 5788 Op0.getOperand(0).getValueType(); 5789 bool isInt = OpVT.isInteger(); 5790 CC = ISD::getSetCCInverse(CC, isInt); 5791 5792 if (!TLI.isCondCodeLegal(CC, OpVT)) 5793 return SDValue(); // Inverse operator isn't legal. 5794 5795 DoXform = true; 5796 InvCC = true; 5797 } 5798 5799 if (DoXform) { 5800 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS); 5801 if (isSlctCC) 5802 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result, 5803 Slct.getOperand(0), Slct.getOperand(1), CC); 5804 SDValue CCOp = Slct.getOperand(0); 5805 if (InvCC) 5806 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(), 5807 CCOp.getOperand(0), CCOp.getOperand(1), CC); 5808 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 5809 CCOp, OtherOp, Result); 5810 } 5811 return SDValue(); 5812 } 5813 5814 // AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction 5815 // (only after legalization). 5816 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1, 5817 TargetLowering::DAGCombinerInfo &DCI, 5818 const ARMSubtarget *Subtarget) { 5819 5820 // Only perform optimization if after legalize, and if NEON is available. We 5821 // also expected both operands to be BUILD_VECTORs. 5822 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON() 5823 || N0.getOpcode() != ISD::BUILD_VECTOR 5824 || N1.getOpcode() != ISD::BUILD_VECTOR) 5825 return SDValue(); 5826 5827 // Check output type since VPADDL operand elements can only be 8, 16, or 32. 5828 EVT VT = N->getValueType(0); 5829 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64) 5830 return SDValue(); 5831 5832 // Check that the vector operands are of the right form. 5833 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR 5834 // operands, where N is the size of the formed vector. 5835 // Each EXTRACT_VECTOR should have the same input vector and odd or even 5836 // index such that we have a pair wise add pattern. 5837 5838 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing. 5839 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 5840 return SDValue(); 5841 SDValue Vec = N0->getOperand(0)->getOperand(0); 5842 SDNode *V = Vec.getNode(); 5843 unsigned nextIndex = 0; 5844 5845 // For each operands to the ADD which are BUILD_VECTORs, 5846 // check to see if each of their operands are an EXTRACT_VECTOR with 5847 // the same vector and appropriate index. 5848 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) { 5849 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT 5850 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) { 5851 5852 SDValue ExtVec0 = N0->getOperand(i); 5853 SDValue ExtVec1 = N1->getOperand(i); 5854 5855 // First operand is the vector, verify its the same. 5856 if (V != ExtVec0->getOperand(0).getNode() || 5857 V != ExtVec1->getOperand(0).getNode()) 5858 return SDValue(); 5859 5860 // Second is the constant, verify its correct. 5861 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1)); 5862 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1)); 5863 5864 // For the constant, we want to see all the even or all the odd. 5865 if (!C0 || !C1 || C0->getZExtValue() != nextIndex 5866 || C1->getZExtValue() != nextIndex+1) 5867 return SDValue(); 5868 5869 // Increment index. 5870 nextIndex+=2; 5871 } else 5872 return SDValue(); 5873 } 5874 5875 // Create VPADDL node. 5876 SelectionDAG &DAG = DCI.DAG; 5877 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 5878 5879 // Build operand list. 5880 SmallVector<SDValue, 8> Ops; 5881 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls, 5882 TLI.getPointerTy())); 5883 5884 // Input is the vector. 5885 Ops.push_back(Vec); 5886 5887 // Get widened type and narrowed type. 5888 MVT widenType; 5889 unsigned numElem = VT.getVectorNumElements(); 5890 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) { 5891 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break; 5892 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break; 5893 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break; 5894 default: 5895 assert(0 && "Invalid vector element type for padd optimization."); 5896 } 5897 5898 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), 5899 widenType, &Ops[0], Ops.size()); 5900 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, tmp); 5901 } 5902 5903 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with 5904 /// operands N0 and N1. This is a helper for PerformADDCombine that is 5905 /// called with the default operands, and if that fails, with commuted 5906 /// operands. 5907 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, 5908 TargetLowering::DAGCombinerInfo &DCI, 5909 const ARMSubtarget *Subtarget){ 5910 5911 // Attempt to create vpaddl for this add. 5912 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget); 5913 if (Result.getNode()) 5914 return Result; 5915 5916 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 5917 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 5918 SDValue Result = combineSelectAndUse(N, N0, N1, DCI); 5919 if (Result.getNode()) return Result; 5920 } 5921 return SDValue(); 5922 } 5923 5924 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD. 5925 /// 5926 static SDValue PerformADDCombine(SDNode *N, 5927 TargetLowering::DAGCombinerInfo &DCI, 5928 const ARMSubtarget *Subtarget) { 5929 SDValue N0 = N->getOperand(0); 5930 SDValue N1 = N->getOperand(1); 5931 5932 // First try with the default operand order. 5933 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget); 5934 if (Result.getNode()) 5935 return Result; 5936 5937 // If that didn't work, try again with the operands commuted. 5938 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget); 5939 } 5940 5941 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB. 5942 /// 5943 static SDValue PerformSUBCombine(SDNode *N, 5944 TargetLowering::DAGCombinerInfo &DCI) { 5945 SDValue N0 = N->getOperand(0); 5946 SDValue N1 = N->getOperand(1); 5947 5948 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 5949 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 5950 SDValue Result = combineSelectAndUse(N, N1, N0, DCI); 5951 if (Result.getNode()) return Result; 5952 } 5953 5954 return SDValue(); 5955 } 5956 5957 /// PerformVMULCombine 5958 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the 5959 /// special multiplier accumulator forwarding. 5960 /// vmul d3, d0, d2 5961 /// vmla d3, d1, d2 5962 /// is faster than 5963 /// vadd d3, d0, d1 5964 /// vmul d3, d3, d2 5965 static SDValue PerformVMULCombine(SDNode *N, 5966 TargetLowering::DAGCombinerInfo &DCI, 5967 const ARMSubtarget *Subtarget) { 5968 if (!Subtarget->hasVMLxForwarding()) 5969 return SDValue(); 5970 5971 SelectionDAG &DAG = DCI.DAG; 5972 SDValue N0 = N->getOperand(0); 5973 SDValue N1 = N->getOperand(1); 5974 unsigned Opcode = N0.getOpcode(); 5975 if (Opcode != ISD::ADD && Opcode != ISD::SUB && 5976 Opcode != ISD::FADD && Opcode != ISD::FSUB) { 5977 Opcode = N1.getOpcode(); 5978 if (Opcode != ISD::ADD && Opcode != ISD::SUB && 5979 Opcode != ISD::FADD && Opcode != ISD::FSUB) 5980 return SDValue(); 5981 std::swap(N0, N1); 5982 } 5983 5984 EVT VT = N->getValueType(0); 5985 DebugLoc DL = N->getDebugLoc(); 5986 SDValue N00 = N0->getOperand(0); 5987 SDValue N01 = N0->getOperand(1); 5988 return DAG.getNode(Opcode, DL, VT, 5989 DAG.getNode(ISD::MUL, DL, VT, N00, N1), 5990 DAG.getNode(ISD::MUL, DL, VT, N01, N1)); 5991 } 5992 5993 static SDValue PerformMULCombine(SDNode *N, 5994 TargetLowering::DAGCombinerInfo &DCI, 5995 const ARMSubtarget *Subtarget) { 5996 SelectionDAG &DAG = DCI.DAG; 5997 5998 if (Subtarget->isThumb1Only()) 5999 return SDValue(); 6000 6001 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 6002 return SDValue(); 6003 6004 EVT VT = N->getValueType(0); 6005 if (VT.is64BitVector() || VT.is128BitVector()) 6006 return PerformVMULCombine(N, DCI, Subtarget); 6007 if (VT != MVT::i32) 6008 return SDValue(); 6009 6010 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6011 if (!C) 6012 return SDValue(); 6013 6014 uint64_t MulAmt = C->getZExtValue(); 6015 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt); 6016 ShiftAmt = ShiftAmt & (32 - 1); 6017 SDValue V = N->getOperand(0); 6018 DebugLoc DL = N->getDebugLoc(); 6019 6020 SDValue Res; 6021 MulAmt >>= ShiftAmt; 6022 if (isPowerOf2_32(MulAmt - 1)) { 6023 // (mul x, 2^N + 1) => (add (shl x, N), x) 6024 Res = DAG.getNode(ISD::ADD, DL, VT, 6025 V, DAG.getNode(ISD::SHL, DL, VT, 6026 V, DAG.getConstant(Log2_32(MulAmt-1), 6027 MVT::i32))); 6028 } else if (isPowerOf2_32(MulAmt + 1)) { 6029 // (mul x, 2^N - 1) => (sub (shl x, N), x) 6030 Res = DAG.getNode(ISD::SUB, DL, VT, 6031 DAG.getNode(ISD::SHL, DL, VT, 6032 V, DAG.getConstant(Log2_32(MulAmt+1), 6033 MVT::i32)), 6034 V); 6035 } else 6036 return SDValue(); 6037 6038 if (ShiftAmt != 0) 6039 Res = DAG.getNode(ISD::SHL, DL, VT, Res, 6040 DAG.getConstant(ShiftAmt, MVT::i32)); 6041 6042 // Do not add new nodes to DAG combiner worklist. 6043 DCI.CombineTo(N, Res, false); 6044 return SDValue(); 6045 } 6046 6047 static SDValue PerformANDCombine(SDNode *N, 6048 TargetLowering::DAGCombinerInfo &DCI) { 6049 6050 // Attempt to use immediate-form VBIC 6051 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); 6052 DebugLoc dl = N->getDebugLoc(); 6053 EVT VT = N->getValueType(0); 6054 SelectionDAG &DAG = DCI.DAG; 6055 6056 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 6057 return SDValue(); 6058 6059 APInt SplatBits, SplatUndef; 6060 unsigned SplatBitSize; 6061 bool HasAnyUndefs; 6062 if (BVN && 6063 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 6064 if (SplatBitSize <= 64) { 6065 EVT VbicVT; 6066 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(), 6067 SplatUndef.getZExtValue(), SplatBitSize, 6068 DAG, VbicVT, VT.is128BitVector(), 6069 OtherModImm); 6070 if (Val.getNode()) { 6071 SDValue Input = 6072 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0)); 6073 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val); 6074 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic); 6075 } 6076 } 6077 } 6078 6079 return SDValue(); 6080 } 6081 6082 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR 6083 static SDValue PerformORCombine(SDNode *N, 6084 TargetLowering::DAGCombinerInfo &DCI, 6085 const ARMSubtarget *Subtarget) { 6086 // Attempt to use immediate-form VORR 6087 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); 6088 DebugLoc dl = N->getDebugLoc(); 6089 EVT VT = N->getValueType(0); 6090 SelectionDAG &DAG = DCI.DAG; 6091 6092 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 6093 return SDValue(); 6094 6095 APInt SplatBits, SplatUndef; 6096 unsigned SplatBitSize; 6097 bool HasAnyUndefs; 6098 if (BVN && Subtarget->hasNEON() && 6099 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 6100 if (SplatBitSize <= 64) { 6101 EVT VorrVT; 6102 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), 6103 SplatUndef.getZExtValue(), SplatBitSize, 6104 DAG, VorrVT, VT.is128BitVector(), 6105 OtherModImm); 6106 if (Val.getNode()) { 6107 SDValue Input = 6108 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0)); 6109 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val); 6110 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr); 6111 } 6112 } 6113 } 6114 6115 SDValue N0 = N->getOperand(0); 6116 if (N0.getOpcode() != ISD::AND) 6117 return SDValue(); 6118 SDValue N1 = N->getOperand(1); 6119 6120 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant. 6121 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() && 6122 DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 6123 APInt SplatUndef; 6124 unsigned SplatBitSize; 6125 bool HasAnyUndefs; 6126 6127 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1)); 6128 APInt SplatBits0; 6129 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize, 6130 HasAnyUndefs) && !HasAnyUndefs) { 6131 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1)); 6132 APInt SplatBits1; 6133 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize, 6134 HasAnyUndefs) && !HasAnyUndefs && 6135 SplatBits0 == ~SplatBits1) { 6136 // Canonicalize the vector type to make instruction selection simpler. 6137 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; 6138 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT, 6139 N0->getOperand(1), N0->getOperand(0), 6140 N1->getOperand(0)); 6141 return DAG.getNode(ISD::BITCAST, dl, VT, Result); 6142 } 6143 } 6144 } 6145 6146 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when 6147 // reasonable. 6148 6149 // BFI is only available on V6T2+ 6150 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops()) 6151 return SDValue(); 6152 6153 DebugLoc DL = N->getDebugLoc(); 6154 // 1) or (and A, mask), val => ARMbfi A, val, mask 6155 // iff (val & mask) == val 6156 // 6157 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask 6158 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2) 6159 // && mask == ~mask2 6160 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2) 6161 // && ~mask == mask2 6162 // (i.e., copy a bitfield value into another bitfield of the same width) 6163 6164 if (VT != MVT::i32) 6165 return SDValue(); 6166 6167 SDValue N00 = N0.getOperand(0); 6168 6169 // The value and the mask need to be constants so we can verify this is 6170 // actually a bitfield set. If the mask is 0xffff, we can do better 6171 // via a movt instruction, so don't use BFI in that case. 6172 SDValue MaskOp = N0.getOperand(1); 6173 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp); 6174 if (!MaskC) 6175 return SDValue(); 6176 unsigned Mask = MaskC->getZExtValue(); 6177 if (Mask == 0xffff) 6178 return SDValue(); 6179 SDValue Res; 6180 // Case (1): or (and A, mask), val => ARMbfi A, val, mask 6181 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 6182 if (N1C) { 6183 unsigned Val = N1C->getZExtValue(); 6184 if ((Val & ~Mask) != Val) 6185 return SDValue(); 6186 6187 if (ARM::isBitFieldInvertedMask(Mask)) { 6188 Val >>= CountTrailingZeros_32(~Mask); 6189 6190 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, 6191 DAG.getConstant(Val, MVT::i32), 6192 DAG.getConstant(Mask, MVT::i32)); 6193 6194 // Do not add new nodes to DAG combiner worklist. 6195 DCI.CombineTo(N, Res, false); 6196 return SDValue(); 6197 } 6198 } else if (N1.getOpcode() == ISD::AND) { 6199 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask 6200 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 6201 if (!N11C) 6202 return SDValue(); 6203 unsigned Mask2 = N11C->getZExtValue(); 6204 6205 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern 6206 // as is to match. 6207 if (ARM::isBitFieldInvertedMask(Mask) && 6208 (Mask == ~Mask2)) { 6209 // The pack halfword instruction works better for masks that fit it, 6210 // so use that when it's available. 6211 if (Subtarget->hasT2ExtractPack() && 6212 (Mask == 0xffff || Mask == 0xffff0000)) 6213 return SDValue(); 6214 // 2a 6215 unsigned amt = CountTrailingZeros_32(Mask2); 6216 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0), 6217 DAG.getConstant(amt, MVT::i32)); 6218 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res, 6219 DAG.getConstant(Mask, MVT::i32)); 6220 // Do not add new nodes to DAG combiner worklist. 6221 DCI.CombineTo(N, Res, false); 6222 return SDValue(); 6223 } else if (ARM::isBitFieldInvertedMask(~Mask) && 6224 (~Mask == Mask2)) { 6225 // The pack halfword instruction works better for masks that fit it, 6226 // so use that when it's available. 6227 if (Subtarget->hasT2ExtractPack() && 6228 (Mask2 == 0xffff || Mask2 == 0xffff0000)) 6229 return SDValue(); 6230 // 2b 6231 unsigned lsb = CountTrailingZeros_32(Mask); 6232 Res = DAG.getNode(ISD::SRL, DL, VT, N00, 6233 DAG.getConstant(lsb, MVT::i32)); 6234 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res, 6235 DAG.getConstant(Mask2, MVT::i32)); 6236 // Do not add new nodes to DAG combiner worklist. 6237 DCI.CombineTo(N, Res, false); 6238 return SDValue(); 6239 } 6240 } 6241 6242 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) && 6243 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) && 6244 ARM::isBitFieldInvertedMask(~Mask)) { 6245 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask 6246 // where lsb(mask) == #shamt and masked bits of B are known zero. 6247 SDValue ShAmt = N00.getOperand(1); 6248 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 6249 unsigned LSB = CountTrailingZeros_32(Mask); 6250 if (ShAmtC != LSB) 6251 return SDValue(); 6252 6253 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0), 6254 DAG.getConstant(~Mask, MVT::i32)); 6255 6256 // Do not add new nodes to DAG combiner worklist. 6257 DCI.CombineTo(N, Res, false); 6258 } 6259 6260 return SDValue(); 6261 } 6262 6263 /// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff 6264 /// the bits being cleared by the AND are not demanded by the BFI. 6265 static SDValue PerformBFICombine(SDNode *N, 6266 TargetLowering::DAGCombinerInfo &DCI) { 6267 SDValue N1 = N->getOperand(1); 6268 if (N1.getOpcode() == ISD::AND) { 6269 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 6270 if (!N11C) 6271 return SDValue(); 6272 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(); 6273 unsigned LSB = CountTrailingZeros_32(~InvMask); 6274 unsigned Width = (32 - CountLeadingZeros_32(~InvMask)) - LSB; 6275 unsigned Mask = (1 << Width)-1; 6276 unsigned Mask2 = N11C->getZExtValue(); 6277 if ((Mask & (~Mask2)) == 0) 6278 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0), 6279 N->getOperand(0), N1.getOperand(0), 6280 N->getOperand(2)); 6281 } 6282 return SDValue(); 6283 } 6284 6285 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for 6286 /// ARMISD::VMOVRRD. 6287 static SDValue PerformVMOVRRDCombine(SDNode *N, 6288 TargetLowering::DAGCombinerInfo &DCI) { 6289 // vmovrrd(vmovdrr x, y) -> x,y 6290 SDValue InDouble = N->getOperand(0); 6291 if (InDouble.getOpcode() == ARMISD::VMOVDRR) 6292 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1)); 6293 6294 // vmovrrd(load f64) -> (load i32), (load i32) 6295 SDNode *InNode = InDouble.getNode(); 6296 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() && 6297 InNode->getValueType(0) == MVT::f64 && 6298 InNode->getOperand(1).getOpcode() == ISD::FrameIndex && 6299 !cast<LoadSDNode>(InNode)->isVolatile()) { 6300 // TODO: Should this be done for non-FrameIndex operands? 6301 LoadSDNode *LD = cast<LoadSDNode>(InNode); 6302 6303 SelectionDAG &DAG = DCI.DAG; 6304 DebugLoc DL = LD->getDebugLoc(); 6305 SDValue BasePtr = LD->getBasePtr(); 6306 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr, 6307 LD->getPointerInfo(), LD->isVolatile(), 6308 LD->isNonTemporal(), LD->getAlignment()); 6309 6310 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, 6311 DAG.getConstant(4, MVT::i32)); 6312 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr, 6313 LD->getPointerInfo(), LD->isVolatile(), 6314 LD->isNonTemporal(), 6315 std::min(4U, LD->getAlignment() / 2)); 6316 6317 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1)); 6318 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2); 6319 DCI.RemoveFromWorklist(LD); 6320 DAG.DeleteNode(LD); 6321 return Result; 6322 } 6323 6324 return SDValue(); 6325 } 6326 6327 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for 6328 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands. 6329 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) { 6330 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X) 6331 SDValue Op0 = N->getOperand(0); 6332 SDValue Op1 = N->getOperand(1); 6333 if (Op0.getOpcode() == ISD::BITCAST) 6334 Op0 = Op0.getOperand(0); 6335 if (Op1.getOpcode() == ISD::BITCAST) 6336 Op1 = Op1.getOperand(0); 6337 if (Op0.getOpcode() == ARMISD::VMOVRRD && 6338 Op0.getNode() == Op1.getNode() && 6339 Op0.getResNo() == 0 && Op1.getResNo() == 1) 6340 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6341 N->getValueType(0), Op0.getOperand(0)); 6342 return SDValue(); 6343 } 6344 6345 /// PerformSTORECombine - Target-specific dag combine xforms for 6346 /// ISD::STORE. 6347 static SDValue PerformSTORECombine(SDNode *N, 6348 TargetLowering::DAGCombinerInfo &DCI) { 6349 // Bitcast an i64 store extracted from a vector to f64. 6350 // Otherwise, the i64 value will be legalized to a pair of i32 values. 6351 StoreSDNode *St = cast<StoreSDNode>(N); 6352 SDValue StVal = St->getValue(); 6353 if (!ISD::isNormalStore(St) || St->isVolatile()) 6354 return SDValue(); 6355 6356 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR && 6357 StVal.getNode()->hasOneUse() && !St->isVolatile()) { 6358 SelectionDAG &DAG = DCI.DAG; 6359 DebugLoc DL = St->getDebugLoc(); 6360 SDValue BasePtr = St->getBasePtr(); 6361 SDValue NewST1 = DAG.getStore(St->getChain(), DL, 6362 StVal.getNode()->getOperand(0), BasePtr, 6363 St->getPointerInfo(), St->isVolatile(), 6364 St->isNonTemporal(), St->getAlignment()); 6365 6366 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, 6367 DAG.getConstant(4, MVT::i32)); 6368 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1), 6369 OffsetPtr, St->getPointerInfo(), St->isVolatile(), 6370 St->isNonTemporal(), 6371 std::min(4U, St->getAlignment() / 2)); 6372 } 6373 6374 if (StVal.getValueType() != MVT::i64 || 6375 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 6376 return SDValue(); 6377 6378 SelectionDAG &DAG = DCI.DAG; 6379 DebugLoc dl = StVal.getDebugLoc(); 6380 SDValue IntVec = StVal.getOperand(0); 6381 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, 6382 IntVec.getValueType().getVectorNumElements()); 6383 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec); 6384 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 6385 Vec, StVal.getOperand(1)); 6386 dl = N->getDebugLoc(); 6387 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt); 6388 // Make the DAGCombiner fold the bitcasts. 6389 DCI.AddToWorklist(Vec.getNode()); 6390 DCI.AddToWorklist(ExtElt.getNode()); 6391 DCI.AddToWorklist(V.getNode()); 6392 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(), 6393 St->getPointerInfo(), St->isVolatile(), 6394 St->isNonTemporal(), St->getAlignment(), 6395 St->getTBAAInfo()); 6396 } 6397 6398 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node 6399 /// are normal, non-volatile loads. If so, it is profitable to bitcast an 6400 /// i64 vector to have f64 elements, since the value can then be loaded 6401 /// directly into a VFP register. 6402 static bool hasNormalLoadOperand(SDNode *N) { 6403 unsigned NumElts = N->getValueType(0).getVectorNumElements(); 6404 for (unsigned i = 0; i < NumElts; ++i) { 6405 SDNode *Elt = N->getOperand(i).getNode(); 6406 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile()) 6407 return true; 6408 } 6409 return false; 6410 } 6411 6412 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for 6413 /// ISD::BUILD_VECTOR. 6414 static SDValue PerformBUILD_VECTORCombine(SDNode *N, 6415 TargetLowering::DAGCombinerInfo &DCI){ 6416 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X): 6417 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value 6418 // into a pair of GPRs, which is fine when the value is used as a scalar, 6419 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD. 6420 SelectionDAG &DAG = DCI.DAG; 6421 if (N->getNumOperands() == 2) { 6422 SDValue RV = PerformVMOVDRRCombine(N, DAG); 6423 if (RV.getNode()) 6424 return RV; 6425 } 6426 6427 // Load i64 elements as f64 values so that type legalization does not split 6428 // them up into i32 values. 6429 EVT VT = N->getValueType(0); 6430 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N)) 6431 return SDValue(); 6432 DebugLoc dl = N->getDebugLoc(); 6433 SmallVector<SDValue, 8> Ops; 6434 unsigned NumElts = VT.getVectorNumElements(); 6435 for (unsigned i = 0; i < NumElts; ++i) { 6436 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i)); 6437 Ops.push_back(V); 6438 // Make the DAGCombiner fold the bitcast. 6439 DCI.AddToWorklist(V.getNode()); 6440 } 6441 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts); 6442 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts); 6443 return DAG.getNode(ISD::BITCAST, dl, VT, BV); 6444 } 6445 6446 /// PerformInsertEltCombine - Target-specific dag combine xforms for 6447 /// ISD::INSERT_VECTOR_ELT. 6448 static SDValue PerformInsertEltCombine(SDNode *N, 6449 TargetLowering::DAGCombinerInfo &DCI) { 6450 // Bitcast an i64 load inserted into a vector to f64. 6451 // Otherwise, the i64 value will be legalized to a pair of i32 values. 6452 EVT VT = N->getValueType(0); 6453 SDNode *Elt = N->getOperand(1).getNode(); 6454 if (VT.getVectorElementType() != MVT::i64 || 6455 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile()) 6456 return SDValue(); 6457 6458 SelectionDAG &DAG = DCI.DAG; 6459 DebugLoc dl = N->getDebugLoc(); 6460 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, 6461 VT.getVectorNumElements()); 6462 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0)); 6463 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1)); 6464 // Make the DAGCombiner fold the bitcasts. 6465 DCI.AddToWorklist(Vec.getNode()); 6466 DCI.AddToWorklist(V.getNode()); 6467 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT, 6468 Vec, V, N->getOperand(2)); 6469 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt); 6470 } 6471 6472 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for 6473 /// ISD::VECTOR_SHUFFLE. 6474 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) { 6475 // The LLVM shufflevector instruction does not require the shuffle mask 6476 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does 6477 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the 6478 // operands do not match the mask length, they are extended by concatenating 6479 // them with undef vectors. That is probably the right thing for other 6480 // targets, but for NEON it is better to concatenate two double-register 6481 // size vector operands into a single quad-register size vector. Do that 6482 // transformation here: 6483 // shuffle(concat(v1, undef), concat(v2, undef)) -> 6484 // shuffle(concat(v1, v2), undef) 6485 SDValue Op0 = N->getOperand(0); 6486 SDValue Op1 = N->getOperand(1); 6487 if (Op0.getOpcode() != ISD::CONCAT_VECTORS || 6488 Op1.getOpcode() != ISD::CONCAT_VECTORS || 6489 Op0.getNumOperands() != 2 || 6490 Op1.getNumOperands() != 2) 6491 return SDValue(); 6492 SDValue Concat0Op1 = Op0.getOperand(1); 6493 SDValue Concat1Op1 = Op1.getOperand(1); 6494 if (Concat0Op1.getOpcode() != ISD::UNDEF || 6495 Concat1Op1.getOpcode() != ISD::UNDEF) 6496 return SDValue(); 6497 // Skip the transformation if any of the types are illegal. 6498 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6499 EVT VT = N->getValueType(0); 6500 if (!TLI.isTypeLegal(VT) || 6501 !TLI.isTypeLegal(Concat0Op1.getValueType()) || 6502 !TLI.isTypeLegal(Concat1Op1.getValueType())) 6503 return SDValue(); 6504 6505 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 6506 Op0.getOperand(0), Op1.getOperand(0)); 6507 // Translate the shuffle mask. 6508 SmallVector<int, 16> NewMask; 6509 unsigned NumElts = VT.getVectorNumElements(); 6510 unsigned HalfElts = NumElts/2; 6511 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 6512 for (unsigned n = 0; n < NumElts; ++n) { 6513 int MaskElt = SVN->getMaskElt(n); 6514 int NewElt = -1; 6515 if (MaskElt < (int)HalfElts) 6516 NewElt = MaskElt; 6517 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts)) 6518 NewElt = HalfElts + MaskElt - NumElts; 6519 NewMask.push_back(NewElt); 6520 } 6521 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat, 6522 DAG.getUNDEF(VT), NewMask.data()); 6523 } 6524 6525 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and 6526 /// NEON load/store intrinsics to merge base address updates. 6527 static SDValue CombineBaseUpdate(SDNode *N, 6528 TargetLowering::DAGCombinerInfo &DCI) { 6529 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 6530 return SDValue(); 6531 6532 SelectionDAG &DAG = DCI.DAG; 6533 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID || 6534 N->getOpcode() == ISD::INTRINSIC_W_CHAIN); 6535 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1); 6536 SDValue Addr = N->getOperand(AddrOpIdx); 6537 6538 // Search for a use of the address operand that is an increment. 6539 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), 6540 UE = Addr.getNode()->use_end(); UI != UE; ++UI) { 6541 SDNode *User = *UI; 6542 if (User->getOpcode() != ISD::ADD || 6543 UI.getUse().getResNo() != Addr.getResNo()) 6544 continue; 6545 6546 // Check that the add is independent of the load/store. Otherwise, folding 6547 // it would create a cycle. 6548 if (User->isPredecessorOf(N) || N->isPredecessorOf(User)) 6549 continue; 6550 6551 // Find the new opcode for the updating load/store. 6552 bool isLoad = true; 6553 bool isLaneOp = false; 6554 unsigned NewOpc = 0; 6555 unsigned NumVecs = 0; 6556 if (isIntrinsic) { 6557 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 6558 switch (IntNo) { 6559 default: assert(0 && "unexpected intrinsic for Neon base update"); 6560 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD; 6561 NumVecs = 1; break; 6562 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD; 6563 NumVecs = 2; break; 6564 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD; 6565 NumVecs = 3; break; 6566 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD; 6567 NumVecs = 4; break; 6568 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD; 6569 NumVecs = 2; isLaneOp = true; break; 6570 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD; 6571 NumVecs = 3; isLaneOp = true; break; 6572 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD; 6573 NumVecs = 4; isLaneOp = true; break; 6574 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD; 6575 NumVecs = 1; isLoad = false; break; 6576 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD; 6577 NumVecs = 2; isLoad = false; break; 6578 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD; 6579 NumVecs = 3; isLoad = false; break; 6580 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD; 6581 NumVecs = 4; isLoad = false; break; 6582 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD; 6583 NumVecs = 2; isLoad = false; isLaneOp = true; break; 6584 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD; 6585 NumVecs = 3; isLoad = false; isLaneOp = true; break; 6586 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD; 6587 NumVecs = 4; isLoad = false; isLaneOp = true; break; 6588 } 6589 } else { 6590 isLaneOp = true; 6591 switch (N->getOpcode()) { 6592 default: assert(0 && "unexpected opcode for Neon base update"); 6593 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break; 6594 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break; 6595 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break; 6596 } 6597 } 6598 6599 // Find the size of memory referenced by the load/store. 6600 EVT VecTy; 6601 if (isLoad) 6602 VecTy = N->getValueType(0); 6603 else 6604 VecTy = N->getOperand(AddrOpIdx+1).getValueType(); 6605 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8; 6606 if (isLaneOp) 6607 NumBytes /= VecTy.getVectorNumElements(); 6608 6609 // If the increment is a constant, it must match the memory ref size. 6610 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0); 6611 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) { 6612 uint64_t IncVal = CInc->getZExtValue(); 6613 if (IncVal != NumBytes) 6614 continue; 6615 } else if (NumBytes >= 3 * 16) { 6616 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two 6617 // separate instructions that make it harder to use a non-constant update. 6618 continue; 6619 } 6620 6621 // Create the new updating load/store node. 6622 EVT Tys[6]; 6623 unsigned NumResultVecs = (isLoad ? NumVecs : 0); 6624 unsigned n; 6625 for (n = 0; n < NumResultVecs; ++n) 6626 Tys[n] = VecTy; 6627 Tys[n++] = MVT::i32; 6628 Tys[n] = MVT::Other; 6629 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2); 6630 SmallVector<SDValue, 8> Ops; 6631 Ops.push_back(N->getOperand(0)); // incoming chain 6632 Ops.push_back(N->getOperand(AddrOpIdx)); 6633 Ops.push_back(Inc); 6634 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) { 6635 Ops.push_back(N->getOperand(i)); 6636 } 6637 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N); 6638 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys, 6639 Ops.data(), Ops.size(), 6640 MemInt->getMemoryVT(), 6641 MemInt->getMemOperand()); 6642 6643 // Update the uses. 6644 std::vector<SDValue> NewResults; 6645 for (unsigned i = 0; i < NumResultVecs; ++i) { 6646 NewResults.push_back(SDValue(UpdN.getNode(), i)); 6647 } 6648 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain 6649 DCI.CombineTo(N, NewResults); 6650 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs)); 6651 6652 break; 6653 } 6654 return SDValue(); 6655 } 6656 6657 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a 6658 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic 6659 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and 6660 /// return true. 6661 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { 6662 SelectionDAG &DAG = DCI.DAG; 6663 EVT VT = N->getValueType(0); 6664 // vldN-dup instructions only support 64-bit vectors for N > 1. 6665 if (!VT.is64BitVector()) 6666 return false; 6667 6668 // Check if the VDUPLANE operand is a vldN-dup intrinsic. 6669 SDNode *VLD = N->getOperand(0).getNode(); 6670 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN) 6671 return false; 6672 unsigned NumVecs = 0; 6673 unsigned NewOpc = 0; 6674 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue(); 6675 if (IntNo == Intrinsic::arm_neon_vld2lane) { 6676 NumVecs = 2; 6677 NewOpc = ARMISD::VLD2DUP; 6678 } else if (IntNo == Intrinsic::arm_neon_vld3lane) { 6679 NumVecs = 3; 6680 NewOpc = ARMISD::VLD3DUP; 6681 } else if (IntNo == Intrinsic::arm_neon_vld4lane) { 6682 NumVecs = 4; 6683 NewOpc = ARMISD::VLD4DUP; 6684 } else { 6685 return false; 6686 } 6687 6688 // First check that all the vldN-lane uses are VDUPLANEs and that the lane 6689 // numbers match the load. 6690 unsigned VLDLaneNo = 6691 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue(); 6692 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); 6693 UI != UE; ++UI) { 6694 // Ignore uses of the chain result. 6695 if (UI.getUse().getResNo() == NumVecs) 6696 continue; 6697 SDNode *User = *UI; 6698 if (User->getOpcode() != ARMISD::VDUPLANE || 6699 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue()) 6700 return false; 6701 } 6702 6703 // Create the vldN-dup node. 6704 EVT Tys[5]; 6705 unsigned n; 6706 for (n = 0; n < NumVecs; ++n) 6707 Tys[n] = VT; 6708 Tys[n] = MVT::Other; 6709 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1); 6710 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) }; 6711 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD); 6712 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys, 6713 Ops, 2, VLDMemInt->getMemoryVT(), 6714 VLDMemInt->getMemOperand()); 6715 6716 // Update the uses. 6717 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); 6718 UI != UE; ++UI) { 6719 unsigned ResNo = UI.getUse().getResNo(); 6720 // Ignore uses of the chain result. 6721 if (ResNo == NumVecs) 6722 continue; 6723 SDNode *User = *UI; 6724 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo)); 6725 } 6726 6727 // Now the vldN-lane intrinsic is dead except for its chain result. 6728 // Update uses of the chain. 6729 std::vector<SDValue> VLDDupResults; 6730 for (unsigned n = 0; n < NumVecs; ++n) 6731 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n)); 6732 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs)); 6733 DCI.CombineTo(VLD, VLDDupResults); 6734 6735 return true; 6736 } 6737 6738 /// PerformVDUPLANECombine - Target-specific dag combine xforms for 6739 /// ARMISD::VDUPLANE. 6740 static SDValue PerformVDUPLANECombine(SDNode *N, 6741 TargetLowering::DAGCombinerInfo &DCI) { 6742 SDValue Op = N->getOperand(0); 6743 6744 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses 6745 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation. 6746 if (CombineVLDDUP(N, DCI)) 6747 return SDValue(N, 0); 6748 6749 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is 6750 // redundant. Ignore bit_converts for now; element sizes are checked below. 6751 while (Op.getOpcode() == ISD::BITCAST) 6752 Op = Op.getOperand(0); 6753 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM) 6754 return SDValue(); 6755 6756 // Make sure the VMOV element size is not bigger than the VDUPLANE elements. 6757 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits(); 6758 // The canonical VMOV for a zero vector uses a 32-bit element size. 6759 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6760 unsigned EltBits; 6761 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0) 6762 EltSize = 8; 6763 EVT VT = N->getValueType(0); 6764 if (EltSize > VT.getVectorElementType().getSizeInBits()) 6765 return SDValue(); 6766 6767 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 6768 } 6769 6770 // isConstVecPow2 - Return true if each vector element is a power of 2, all 6771 // elements are the same constant, C, and Log2(C) ranges from 1 to 32. 6772 static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C) 6773 { 6774 integerPart cN; 6775 integerPart c0 = 0; 6776 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements(); 6777 I != E; I++) { 6778 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I)); 6779 if (!C) 6780 return false; 6781 6782 bool isExact; 6783 APFloat APF = C->getValueAPF(); 6784 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact) 6785 != APFloat::opOK || !isExact) 6786 return false; 6787 6788 c0 = (I == 0) ? cN : c0; 6789 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32) 6790 return false; 6791 } 6792 C = c0; 6793 return true; 6794 } 6795 6796 /// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) 6797 /// can replace combinations of VMUL and VCVT (floating-point to integer) 6798 /// when the VMUL has a constant operand that is a power of 2. 6799 /// 6800 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): 6801 /// vmul.f32 d16, d17, d16 6802 /// vcvt.s32.f32 d16, d16 6803 /// becomes: 6804 /// vcvt.s32.f32 d16, d16, #3 6805 static SDValue PerformVCVTCombine(SDNode *N, 6806 TargetLowering::DAGCombinerInfo &DCI, 6807 const ARMSubtarget *Subtarget) { 6808 SelectionDAG &DAG = DCI.DAG; 6809 SDValue Op = N->getOperand(0); 6810 6811 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() || 6812 Op.getOpcode() != ISD::FMUL) 6813 return SDValue(); 6814 6815 uint64_t C; 6816 SDValue N0 = Op->getOperand(0); 6817 SDValue ConstVec = Op->getOperand(1); 6818 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT; 6819 6820 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR || 6821 !isConstVecPow2(ConstVec, isSigned, C)) 6822 return SDValue(); 6823 6824 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs : 6825 Intrinsic::arm_neon_vcvtfp2fxu; 6826 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), 6827 N->getValueType(0), 6828 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0, 6829 DAG.getConstant(Log2_64(C), MVT::i32)); 6830 } 6831 6832 /// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD) 6833 /// can replace combinations of VCVT (integer to floating-point) and VDIV 6834 /// when the VDIV has a constant operand that is a power of 2. 6835 /// 6836 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): 6837 /// vcvt.f32.s32 d16, d16 6838 /// vdiv.f32 d16, d17, d16 6839 /// becomes: 6840 /// vcvt.f32.s32 d16, d16, #3 6841 static SDValue PerformVDIVCombine(SDNode *N, 6842 TargetLowering::DAGCombinerInfo &DCI, 6843 const ARMSubtarget *Subtarget) { 6844 SelectionDAG &DAG = DCI.DAG; 6845 SDValue Op = N->getOperand(0); 6846 unsigned OpOpcode = Op.getNode()->getOpcode(); 6847 6848 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() || 6849 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP)) 6850 return SDValue(); 6851 6852 uint64_t C; 6853 SDValue ConstVec = N->getOperand(1); 6854 bool isSigned = OpOpcode == ISD::SINT_TO_FP; 6855 6856 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR || 6857 !isConstVecPow2(ConstVec, isSigned, C)) 6858 return SDValue(); 6859 6860 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp : 6861 Intrinsic::arm_neon_vcvtfxu2fp; 6862 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), 6863 Op.getValueType(), 6864 DAG.getConstant(IntrinsicOpcode, MVT::i32), 6865 Op.getOperand(0), DAG.getConstant(Log2_64(C), MVT::i32)); 6866 } 6867 6868 /// Getvshiftimm - Check if this is a valid build_vector for the immediate 6869 /// operand of a vector shift operation, where all the elements of the 6870 /// build_vector must have the same constant integer value. 6871 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) { 6872 // Ignore bit_converts. 6873 while (Op.getOpcode() == ISD::BITCAST) 6874 Op = Op.getOperand(0); 6875 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 6876 APInt SplatBits, SplatUndef; 6877 unsigned SplatBitSize; 6878 bool HasAnyUndefs; 6879 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, 6880 HasAnyUndefs, ElementBits) || 6881 SplatBitSize > ElementBits) 6882 return false; 6883 Cnt = SplatBits.getSExtValue(); 6884 return true; 6885 } 6886 6887 /// isVShiftLImm - Check if this is a valid build_vector for the immediate 6888 /// operand of a vector shift left operation. That value must be in the range: 6889 /// 0 <= Value < ElementBits for a left shift; or 6890 /// 0 <= Value <= ElementBits for a long left shift. 6891 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) { 6892 assert(VT.isVector() && "vector shift count is not a vector type"); 6893 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 6894 if (! getVShiftImm(Op, ElementBits, Cnt)) 6895 return false; 6896 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits); 6897 } 6898 6899 /// isVShiftRImm - Check if this is a valid build_vector for the immediate 6900 /// operand of a vector shift right operation. For a shift opcode, the value 6901 /// is positive, but for an intrinsic the value count must be negative. The 6902 /// absolute value must be in the range: 6903 /// 1 <= |Value| <= ElementBits for a right shift; or 6904 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift. 6905 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, 6906 int64_t &Cnt) { 6907 assert(VT.isVector() && "vector shift count is not a vector type"); 6908 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 6909 if (! getVShiftImm(Op, ElementBits, Cnt)) 6910 return false; 6911 if (isIntrinsic) 6912 Cnt = -Cnt; 6913 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits)); 6914 } 6915 6916 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics. 6917 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { 6918 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); 6919 switch (IntNo) { 6920 default: 6921 // Don't do anything for most intrinsics. 6922 break; 6923 6924 // Vector shifts: check for immediate versions and lower them. 6925 // Note: This is done during DAG combining instead of DAG legalizing because 6926 // the build_vectors for 64-bit vector element shift counts are generally 6927 // not legal, and it is hard to see their values after they get legalized to 6928 // loads from a constant pool. 6929 case Intrinsic::arm_neon_vshifts: 6930 case Intrinsic::arm_neon_vshiftu: 6931 case Intrinsic::arm_neon_vshiftls: 6932 case Intrinsic::arm_neon_vshiftlu: 6933 case Intrinsic::arm_neon_vshiftn: 6934 case Intrinsic::arm_neon_vrshifts: 6935 case Intrinsic::arm_neon_vrshiftu: 6936 case Intrinsic::arm_neon_vrshiftn: 6937 case Intrinsic::arm_neon_vqshifts: 6938 case Intrinsic::arm_neon_vqshiftu: 6939 case Intrinsic::arm_neon_vqshiftsu: 6940 case Intrinsic::arm_neon_vqshiftns: 6941 case Intrinsic::arm_neon_vqshiftnu: 6942 case Intrinsic::arm_neon_vqshiftnsu: 6943 case Intrinsic::arm_neon_vqrshiftns: 6944 case Intrinsic::arm_neon_vqrshiftnu: 6945 case Intrinsic::arm_neon_vqrshiftnsu: { 6946 EVT VT = N->getOperand(1).getValueType(); 6947 int64_t Cnt; 6948 unsigned VShiftOpc = 0; 6949 6950 switch (IntNo) { 6951 case Intrinsic::arm_neon_vshifts: 6952 case Intrinsic::arm_neon_vshiftu: 6953 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) { 6954 VShiftOpc = ARMISD::VSHL; 6955 break; 6956 } 6957 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) { 6958 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ? 6959 ARMISD::VSHRs : ARMISD::VSHRu); 6960 break; 6961 } 6962 return SDValue(); 6963 6964 case Intrinsic::arm_neon_vshiftls: 6965 case Intrinsic::arm_neon_vshiftlu: 6966 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt)) 6967 break; 6968 llvm_unreachable("invalid shift count for vshll intrinsic"); 6969 6970 case Intrinsic::arm_neon_vrshifts: 6971 case Intrinsic::arm_neon_vrshiftu: 6972 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) 6973 break; 6974 return SDValue(); 6975 6976 case Intrinsic::arm_neon_vqshifts: 6977 case Intrinsic::arm_neon_vqshiftu: 6978 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) 6979 break; 6980 return SDValue(); 6981 6982 case Intrinsic::arm_neon_vqshiftsu: 6983 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) 6984 break; 6985 llvm_unreachable("invalid shift count for vqshlu intrinsic"); 6986 6987 case Intrinsic::arm_neon_vshiftn: 6988 case Intrinsic::arm_neon_vrshiftn: 6989 case Intrinsic::arm_neon_vqshiftns: 6990 case Intrinsic::arm_neon_vqshiftnu: 6991 case Intrinsic::arm_neon_vqshiftnsu: 6992 case Intrinsic::arm_neon_vqrshiftns: 6993 case Intrinsic::arm_neon_vqrshiftnu: 6994 case Intrinsic::arm_neon_vqrshiftnsu: 6995 // Narrowing shifts require an immediate right shift. 6996 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt)) 6997 break; 6998 llvm_unreachable("invalid shift count for narrowing vector shift " 6999 "intrinsic"); 7000 7001 default: 7002 llvm_unreachable("unhandled vector shift"); 7003 } 7004 7005 switch (IntNo) { 7006 case Intrinsic::arm_neon_vshifts: 7007 case Intrinsic::arm_neon_vshiftu: 7008 // Opcode already set above. 7009 break; 7010 case Intrinsic::arm_neon_vshiftls: 7011 case Intrinsic::arm_neon_vshiftlu: 7012 if (Cnt == VT.getVectorElementType().getSizeInBits()) 7013 VShiftOpc = ARMISD::VSHLLi; 7014 else 7015 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ? 7016 ARMISD::VSHLLs : ARMISD::VSHLLu); 7017 break; 7018 case Intrinsic::arm_neon_vshiftn: 7019 VShiftOpc = ARMISD::VSHRN; break; 7020 case Intrinsic::arm_neon_vrshifts: 7021 VShiftOpc = ARMISD::VRSHRs; break; 7022 case Intrinsic::arm_neon_vrshiftu: 7023 VShiftOpc = ARMISD::VRSHRu; break; 7024 case Intrinsic::arm_neon_vrshiftn: 7025 VShiftOpc = ARMISD::VRSHRN; break; 7026 case Intrinsic::arm_neon_vqshifts: 7027 VShiftOpc = ARMISD::VQSHLs; break; 7028 case Intrinsic::arm_neon_vqshiftu: 7029 VShiftOpc = ARMISD::VQSHLu; break; 7030 case Intrinsic::arm_neon_vqshiftsu: 7031 VShiftOpc = ARMISD::VQSHLsu; break; 7032 case Intrinsic::arm_neon_vqshiftns: 7033 VShiftOpc = ARMISD::VQSHRNs; break; 7034 case Intrinsic::arm_neon_vqshiftnu: 7035 VShiftOpc = ARMISD::VQSHRNu; break; 7036 case Intrinsic::arm_neon_vqshiftnsu: 7037 VShiftOpc = ARMISD::VQSHRNsu; break; 7038 case Intrinsic::arm_neon_vqrshiftns: 7039 VShiftOpc = ARMISD::VQRSHRNs; break; 7040 case Intrinsic::arm_neon_vqrshiftnu: 7041 VShiftOpc = ARMISD::VQRSHRNu; break; 7042 case Intrinsic::arm_neon_vqrshiftnsu: 7043 VShiftOpc = ARMISD::VQRSHRNsu; break; 7044 } 7045 7046 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), 7047 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32)); 7048 } 7049 7050 case Intrinsic::arm_neon_vshiftins: { 7051 EVT VT = N->getOperand(1).getValueType(); 7052 int64_t Cnt; 7053 unsigned VShiftOpc = 0; 7054 7055 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt)) 7056 VShiftOpc = ARMISD::VSLI; 7057 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt)) 7058 VShiftOpc = ARMISD::VSRI; 7059 else { 7060 llvm_unreachable("invalid shift count for vsli/vsri intrinsic"); 7061 } 7062 7063 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), 7064 N->getOperand(1), N->getOperand(2), 7065 DAG.getConstant(Cnt, MVT::i32)); 7066 } 7067 7068 case Intrinsic::arm_neon_vqrshifts: 7069 case Intrinsic::arm_neon_vqrshiftu: 7070 // No immediate versions of these to check for. 7071 break; 7072 } 7073 7074 return SDValue(); 7075 } 7076 7077 /// PerformShiftCombine - Checks for immediate versions of vector shifts and 7078 /// lowers them. As with the vector shift intrinsics, this is done during DAG 7079 /// combining instead of DAG legalizing because the build_vectors for 64-bit 7080 /// vector element shift counts are generally not legal, and it is hard to see 7081 /// their values after they get legalized to loads from a constant pool. 7082 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, 7083 const ARMSubtarget *ST) { 7084 EVT VT = N->getValueType(0); 7085 7086 // Nothing to be done for scalar shifts. 7087 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7088 if (!VT.isVector() || !TLI.isTypeLegal(VT)) 7089 return SDValue(); 7090 7091 assert(ST->hasNEON() && "unexpected vector shift"); 7092 int64_t Cnt; 7093 7094 switch (N->getOpcode()) { 7095 default: llvm_unreachable("unexpected shift opcode"); 7096 7097 case ISD::SHL: 7098 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) 7099 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0), 7100 DAG.getConstant(Cnt, MVT::i32)); 7101 break; 7102 7103 case ISD::SRA: 7104 case ISD::SRL: 7105 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) { 7106 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ? 7107 ARMISD::VSHRs : ARMISD::VSHRu); 7108 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0), 7109 DAG.getConstant(Cnt, MVT::i32)); 7110 } 7111 } 7112 return SDValue(); 7113 } 7114 7115 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, 7116 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND. 7117 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG, 7118 const ARMSubtarget *ST) { 7119 SDValue N0 = N->getOperand(0); 7120 7121 // Check for sign- and zero-extensions of vector extract operations of 8- 7122 // and 16-bit vector elements. NEON supports these directly. They are 7123 // handled during DAG combining because type legalization will promote them 7124 // to 32-bit types and it is messy to recognize the operations after that. 7125 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { 7126 SDValue Vec = N0.getOperand(0); 7127 SDValue Lane = N0.getOperand(1); 7128 EVT VT = N->getValueType(0); 7129 EVT EltVT = N0.getValueType(); 7130 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7131 7132 if (VT == MVT::i32 && 7133 (EltVT == MVT::i8 || EltVT == MVT::i16) && 7134 TLI.isTypeLegal(Vec.getValueType()) && 7135 isa<ConstantSDNode>(Lane)) { 7136 7137 unsigned Opc = 0; 7138 switch (N->getOpcode()) { 7139 default: llvm_unreachable("unexpected opcode"); 7140 case ISD::SIGN_EXTEND: 7141 Opc = ARMISD::VGETLANEs; 7142 break; 7143 case ISD::ZERO_EXTEND: 7144 case ISD::ANY_EXTEND: 7145 Opc = ARMISD::VGETLANEu; 7146 break; 7147 } 7148 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane); 7149 } 7150 } 7151 7152 return SDValue(); 7153 } 7154 7155 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC 7156 /// to match f32 max/min patterns to use NEON vmax/vmin instructions. 7157 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG, 7158 const ARMSubtarget *ST) { 7159 // If the target supports NEON, try to use vmax/vmin instructions for f32 7160 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set, 7161 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is 7162 // a NaN; only do the transformation when it matches that behavior. 7163 7164 // For now only do this when using NEON for FP operations; if using VFP, it 7165 // is not obvious that the benefit outweighs the cost of switching to the 7166 // NEON pipeline. 7167 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() || 7168 N->getValueType(0) != MVT::f32) 7169 return SDValue(); 7170 7171 SDValue CondLHS = N->getOperand(0); 7172 SDValue CondRHS = N->getOperand(1); 7173 SDValue LHS = N->getOperand(2); 7174 SDValue RHS = N->getOperand(3); 7175 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); 7176 7177 unsigned Opcode = 0; 7178 bool IsReversed; 7179 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) { 7180 IsReversed = false; // x CC y ? x : y 7181 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) { 7182 IsReversed = true ; // x CC y ? y : x 7183 } else { 7184 return SDValue(); 7185 } 7186 7187 bool IsUnordered; 7188 switch (CC) { 7189 default: break; 7190 case ISD::SETOLT: 7191 case ISD::SETOLE: 7192 case ISD::SETLT: 7193 case ISD::SETLE: 7194 case ISD::SETULT: 7195 case ISD::SETULE: 7196 // If LHS is NaN, an ordered comparison will be false and the result will 7197 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS 7198 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN. 7199 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE); 7200 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) 7201 break; 7202 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin 7203 // will return -0, so vmin can only be used for unsafe math or if one of 7204 // the operands is known to be nonzero. 7205 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) && 7206 !UnsafeFPMath && 7207 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 7208 break; 7209 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN; 7210 break; 7211 7212 case ISD::SETOGT: 7213 case ISD::SETOGE: 7214 case ISD::SETGT: 7215 case ISD::SETGE: 7216 case ISD::SETUGT: 7217 case ISD::SETUGE: 7218 // If LHS is NaN, an ordered comparison will be false and the result will 7219 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS 7220 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN. 7221 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE); 7222 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) 7223 break; 7224 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax 7225 // will return +0, so vmax can only be used for unsafe math or if one of 7226 // the operands is known to be nonzero. 7227 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) && 7228 !UnsafeFPMath && 7229 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 7230 break; 7231 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX; 7232 break; 7233 } 7234 7235 if (!Opcode) 7236 return SDValue(); 7237 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS); 7238 } 7239 7240 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV. 7241 SDValue 7242 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const { 7243 SDValue Cmp = N->getOperand(4); 7244 if (Cmp.getOpcode() != ARMISD::CMPZ) 7245 // Only looking at EQ and NE cases. 7246 return SDValue(); 7247 7248 EVT VT = N->getValueType(0); 7249 DebugLoc dl = N->getDebugLoc(); 7250 SDValue LHS = Cmp.getOperand(0); 7251 SDValue RHS = Cmp.getOperand(1); 7252 SDValue FalseVal = N->getOperand(0); 7253 SDValue TrueVal = N->getOperand(1); 7254 SDValue ARMcc = N->getOperand(2); 7255 ARMCC::CondCodes CC = 7256 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue(); 7257 7258 // Simplify 7259 // mov r1, r0 7260 // cmp r1, x 7261 // mov r0, y 7262 // moveq r0, x 7263 // to 7264 // cmp r0, x 7265 // movne r0, y 7266 // 7267 // mov r1, r0 7268 // cmp r1, x 7269 // mov r0, x 7270 // movne r0, y 7271 // to 7272 // cmp r0, x 7273 // movne r0, y 7274 /// FIXME: Turn this into a target neutral optimization? 7275 SDValue Res; 7276 if (CC == ARMCC::NE && FalseVal == RHS) { 7277 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc, 7278 N->getOperand(3), Cmp); 7279 } else if (CC == ARMCC::EQ && TrueVal == RHS) { 7280 SDValue ARMcc; 7281 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl); 7282 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc, 7283 N->getOperand(3), NewCmp); 7284 } 7285 7286 if (Res.getNode()) { 7287 APInt KnownZero, KnownOne; 7288 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 7289 DAG.ComputeMaskedBits(SDValue(N,0), Mask, KnownZero, KnownOne); 7290 // Capture demanded bits information that would be otherwise lost. 7291 if (KnownZero == 0xfffffffe) 7292 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, 7293 DAG.getValueType(MVT::i1)); 7294 else if (KnownZero == 0xffffff00) 7295 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, 7296 DAG.getValueType(MVT::i8)); 7297 else if (KnownZero == 0xffff0000) 7298 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, 7299 DAG.getValueType(MVT::i16)); 7300 } 7301 7302 return Res; 7303 } 7304 7305 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N, 7306 DAGCombinerInfo &DCI) const { 7307 switch (N->getOpcode()) { 7308 default: break; 7309 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget); 7310 case ISD::SUB: return PerformSUBCombine(N, DCI); 7311 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); 7312 case ISD::OR: return PerformORCombine(N, DCI, Subtarget); 7313 case ISD::AND: return PerformANDCombine(N, DCI); 7314 case ARMISD::BFI: return PerformBFICombine(N, DCI); 7315 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI); 7316 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG); 7317 case ISD::STORE: return PerformSTORECombine(N, DCI); 7318 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI); 7319 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI); 7320 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG); 7321 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI); 7322 case ISD::FP_TO_SINT: 7323 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget); 7324 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget); 7325 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG); 7326 case ISD::SHL: 7327 case ISD::SRA: 7328 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget); 7329 case ISD::SIGN_EXTEND: 7330 case ISD::ZERO_EXTEND: 7331 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget); 7332 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget); 7333 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG); 7334 case ARMISD::VLD2DUP: 7335 case ARMISD::VLD3DUP: 7336 case ARMISD::VLD4DUP: 7337 return CombineBaseUpdate(N, DCI); 7338 case ISD::INTRINSIC_VOID: 7339 case ISD::INTRINSIC_W_CHAIN: 7340 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) { 7341 case Intrinsic::arm_neon_vld1: 7342 case Intrinsic::arm_neon_vld2: 7343 case Intrinsic::arm_neon_vld3: 7344 case Intrinsic::arm_neon_vld4: 7345 case Intrinsic::arm_neon_vld2lane: 7346 case Intrinsic::arm_neon_vld3lane: 7347 case Intrinsic::arm_neon_vld4lane: 7348 case Intrinsic::arm_neon_vst1: 7349 case Intrinsic::arm_neon_vst2: 7350 case Intrinsic::arm_neon_vst3: 7351 case Intrinsic::arm_neon_vst4: 7352 case Intrinsic::arm_neon_vst2lane: 7353 case Intrinsic::arm_neon_vst3lane: 7354 case Intrinsic::arm_neon_vst4lane: 7355 return CombineBaseUpdate(N, DCI); 7356 default: break; 7357 } 7358 break; 7359 } 7360 return SDValue(); 7361 } 7362 7363 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc, 7364 EVT VT) const { 7365 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE); 7366 } 7367 7368 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { 7369 if (!Subtarget->allowsUnalignedMem()) 7370 return false; 7371 7372 switch (VT.getSimpleVT().SimpleTy) { 7373 default: 7374 return false; 7375 case MVT::i8: 7376 case MVT::i16: 7377 case MVT::i32: 7378 return true; 7379 // FIXME: VLD1 etc with standard alignment is legal. 7380 } 7381 } 7382 7383 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) { 7384 if (V < 0) 7385 return false; 7386 7387 unsigned Scale = 1; 7388 switch (VT.getSimpleVT().SimpleTy) { 7389 default: return false; 7390 case MVT::i1: 7391 case MVT::i8: 7392 // Scale == 1; 7393 break; 7394 case MVT::i16: 7395 // Scale == 2; 7396 Scale = 2; 7397 break; 7398 case MVT::i32: 7399 // Scale == 4; 7400 Scale = 4; 7401 break; 7402 } 7403 7404 if ((V & (Scale - 1)) != 0) 7405 return false; 7406 V /= Scale; 7407 return V == (V & ((1LL << 5) - 1)); 7408 } 7409 7410 static bool isLegalT2AddressImmediate(int64_t V, EVT VT, 7411 const ARMSubtarget *Subtarget) { 7412 bool isNeg = false; 7413 if (V < 0) { 7414 isNeg = true; 7415 V = - V; 7416 } 7417 7418 switch (VT.getSimpleVT().SimpleTy) { 7419 default: return false; 7420 case MVT::i1: 7421 case MVT::i8: 7422 case MVT::i16: 7423 case MVT::i32: 7424 // + imm12 or - imm8 7425 if (isNeg) 7426 return V == (V & ((1LL << 8) - 1)); 7427 return V == (V & ((1LL << 12) - 1)); 7428 case MVT::f32: 7429 case MVT::f64: 7430 // Same as ARM mode. FIXME: NEON? 7431 if (!Subtarget->hasVFP2()) 7432 return false; 7433 if ((V & 3) != 0) 7434 return false; 7435 V >>= 2; 7436 return V == (V & ((1LL << 8) - 1)); 7437 } 7438 } 7439 7440 /// isLegalAddressImmediate - Return true if the integer value can be used 7441 /// as the offset of the target addressing mode for load / store of the 7442 /// given type. 7443 static bool isLegalAddressImmediate(int64_t V, EVT VT, 7444 const ARMSubtarget *Subtarget) { 7445 if (V == 0) 7446 return true; 7447 7448 if (!VT.isSimple()) 7449 return false; 7450 7451 if (Subtarget->isThumb1Only()) 7452 return isLegalT1AddressImmediate(V, VT); 7453 else if (Subtarget->isThumb2()) 7454 return isLegalT2AddressImmediate(V, VT, Subtarget); 7455 7456 // ARM mode. 7457 if (V < 0) 7458 V = - V; 7459 switch (VT.getSimpleVT().SimpleTy) { 7460 default: return false; 7461 case MVT::i1: 7462 case MVT::i8: 7463 case MVT::i32: 7464 // +- imm12 7465 return V == (V & ((1LL << 12) - 1)); 7466 case MVT::i16: 7467 // +- imm8 7468 return V == (V & ((1LL << 8) - 1)); 7469 case MVT::f32: 7470 case MVT::f64: 7471 if (!Subtarget->hasVFP2()) // FIXME: NEON? 7472 return false; 7473 if ((V & 3) != 0) 7474 return false; 7475 V >>= 2; 7476 return V == (V & ((1LL << 8) - 1)); 7477 } 7478 } 7479 7480 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM, 7481 EVT VT) const { 7482 int Scale = AM.Scale; 7483 if (Scale < 0) 7484 return false; 7485 7486 switch (VT.getSimpleVT().SimpleTy) { 7487 default: return false; 7488 case MVT::i1: 7489 case MVT::i8: 7490 case MVT::i16: 7491 case MVT::i32: 7492 if (Scale == 1) 7493 return true; 7494 // r + r << imm 7495 Scale = Scale & ~1; 7496 return Scale == 2 || Scale == 4 || Scale == 8; 7497 case MVT::i64: 7498 // r + r 7499 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 7500 return true; 7501 return false; 7502 case MVT::isVoid: 7503 // Note, we allow "void" uses (basically, uses that aren't loads or 7504 // stores), because arm allows folding a scale into many arithmetic 7505 // operations. This should be made more precise and revisited later. 7506 7507 // Allow r << imm, but the imm has to be a multiple of two. 7508 if (Scale & 1) return false; 7509 return isPowerOf2_32(Scale); 7510 } 7511 } 7512 7513 /// isLegalAddressingMode - Return true if the addressing mode represented 7514 /// by AM is legal for this target, for a load/store of the specified type. 7515 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, 7516 Type *Ty) const { 7517 EVT VT = getValueType(Ty, true); 7518 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) 7519 return false; 7520 7521 // Can never fold addr of global into load/store. 7522 if (AM.BaseGV) 7523 return false; 7524 7525 switch (AM.Scale) { 7526 case 0: // no scale reg, must be "r+i" or "r", or "i". 7527 break; 7528 case 1: 7529 if (Subtarget->isThumb1Only()) 7530 return false; 7531 // FALL THROUGH. 7532 default: 7533 // ARM doesn't support any R+R*scale+imm addr modes. 7534 if (AM.BaseOffs) 7535 return false; 7536 7537 if (!VT.isSimple()) 7538 return false; 7539 7540 if (Subtarget->isThumb2()) 7541 return isLegalT2ScaledAddressingMode(AM, VT); 7542 7543 int Scale = AM.Scale; 7544 switch (VT.getSimpleVT().SimpleTy) { 7545 default: return false; 7546 case MVT::i1: 7547 case MVT::i8: 7548 case MVT::i32: 7549 if (Scale < 0) Scale = -Scale; 7550 if (Scale == 1) 7551 return true; 7552 // r + r << imm 7553 return isPowerOf2_32(Scale & ~1); 7554 case MVT::i16: 7555 case MVT::i64: 7556 // r + r 7557 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 7558 return true; 7559 return false; 7560 7561 case MVT::isVoid: 7562 // Note, we allow "void" uses (basically, uses that aren't loads or 7563 // stores), because arm allows folding a scale into many arithmetic 7564 // operations. This should be made more precise and revisited later. 7565 7566 // Allow r << imm, but the imm has to be a multiple of two. 7567 if (Scale & 1) return false; 7568 return isPowerOf2_32(Scale); 7569 } 7570 break; 7571 } 7572 return true; 7573 } 7574 7575 /// isLegalICmpImmediate - Return true if the specified immediate is legal 7576 /// icmp immediate, that is the target has icmp instructions which can compare 7577 /// a register against the immediate without having to materialize the 7578 /// immediate into a register. 7579 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const { 7580 if (!Subtarget->isThumb()) 7581 return ARM_AM::getSOImmVal(Imm) != -1; 7582 if (Subtarget->isThumb2()) 7583 return ARM_AM::getT2SOImmVal(Imm) != -1; 7584 return Imm >= 0 && Imm <= 255; 7585 } 7586 7587 /// isLegalAddImmediate - Return true if the specified immediate is legal 7588 /// add immediate, that is the target has add instructions which can add 7589 /// a register with the immediate without having to materialize the 7590 /// immediate into a register. 7591 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const { 7592 return ARM_AM::getSOImmVal(Imm) != -1; 7593 } 7594 7595 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT, 7596 bool isSEXTLoad, SDValue &Base, 7597 SDValue &Offset, bool &isInc, 7598 SelectionDAG &DAG) { 7599 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 7600 return false; 7601 7602 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { 7603 // AddressingMode 3 7604 Base = Ptr->getOperand(0); 7605 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 7606 int RHSC = (int)RHS->getZExtValue(); 7607 if (RHSC < 0 && RHSC > -256) { 7608 assert(Ptr->getOpcode() == ISD::ADD); 7609 isInc = false; 7610 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 7611 return true; 7612 } 7613 } 7614 isInc = (Ptr->getOpcode() == ISD::ADD); 7615 Offset = Ptr->getOperand(1); 7616 return true; 7617 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { 7618 // AddressingMode 2 7619 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 7620 int RHSC = (int)RHS->getZExtValue(); 7621 if (RHSC < 0 && RHSC > -0x1000) { 7622 assert(Ptr->getOpcode() == ISD::ADD); 7623 isInc = false; 7624 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 7625 Base = Ptr->getOperand(0); 7626 return true; 7627 } 7628 } 7629 7630 if (Ptr->getOpcode() == ISD::ADD) { 7631 isInc = true; 7632 ARM_AM::ShiftOpc ShOpcVal= 7633 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode()); 7634 if (ShOpcVal != ARM_AM::no_shift) { 7635 Base = Ptr->getOperand(1); 7636 Offset = Ptr->getOperand(0); 7637 } else { 7638 Base = Ptr->getOperand(0); 7639 Offset = Ptr->getOperand(1); 7640 } 7641 return true; 7642 } 7643 7644 isInc = (Ptr->getOpcode() == ISD::ADD); 7645 Base = Ptr->getOperand(0); 7646 Offset = Ptr->getOperand(1); 7647 return true; 7648 } 7649 7650 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store. 7651 return false; 7652 } 7653 7654 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT, 7655 bool isSEXTLoad, SDValue &Base, 7656 SDValue &Offset, bool &isInc, 7657 SelectionDAG &DAG) { 7658 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 7659 return false; 7660 7661 Base = Ptr->getOperand(0); 7662 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 7663 int RHSC = (int)RHS->getZExtValue(); 7664 if (RHSC < 0 && RHSC > -0x100) { // 8 bits. 7665 assert(Ptr->getOpcode() == ISD::ADD); 7666 isInc = false; 7667 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 7668 return true; 7669 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero. 7670 isInc = Ptr->getOpcode() == ISD::ADD; 7671 Offset = DAG.getConstant(RHSC, RHS->getValueType(0)); 7672 return true; 7673 } 7674 } 7675 7676 return false; 7677 } 7678 7679 /// getPreIndexedAddressParts - returns true by value, base pointer and 7680 /// offset pointer and addressing mode by reference if the node's address 7681 /// can be legally represented as pre-indexed load / store address. 7682 bool 7683 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 7684 SDValue &Offset, 7685 ISD::MemIndexedMode &AM, 7686 SelectionDAG &DAG) const { 7687 if (Subtarget->isThumb1Only()) 7688 return false; 7689 7690 EVT VT; 7691 SDValue Ptr; 7692 bool isSEXTLoad = false; 7693 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 7694 Ptr = LD->getBasePtr(); 7695 VT = LD->getMemoryVT(); 7696 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 7697 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 7698 Ptr = ST->getBasePtr(); 7699 VT = ST->getMemoryVT(); 7700 } else 7701 return false; 7702 7703 bool isInc; 7704 bool isLegal = false; 7705 if (Subtarget->isThumb2()) 7706 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 7707 Offset, isInc, DAG); 7708 else 7709 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 7710 Offset, isInc, DAG); 7711 if (!isLegal) 7712 return false; 7713 7714 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; 7715 return true; 7716 } 7717 7718 /// getPostIndexedAddressParts - returns true by value, base pointer and 7719 /// offset pointer and addressing mode by reference if this node can be 7720 /// combined with a load / store to form a post-indexed load / store. 7721 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 7722 SDValue &Base, 7723 SDValue &Offset, 7724 ISD::MemIndexedMode &AM, 7725 SelectionDAG &DAG) const { 7726 if (Subtarget->isThumb1Only()) 7727 return false; 7728 7729 EVT VT; 7730 SDValue Ptr; 7731 bool isSEXTLoad = false; 7732 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 7733 VT = LD->getMemoryVT(); 7734 Ptr = LD->getBasePtr(); 7735 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 7736 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 7737 VT = ST->getMemoryVT(); 7738 Ptr = ST->getBasePtr(); 7739 } else 7740 return false; 7741 7742 bool isInc; 7743 bool isLegal = false; 7744 if (Subtarget->isThumb2()) 7745 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 7746 isInc, DAG); 7747 else 7748 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 7749 isInc, DAG); 7750 if (!isLegal) 7751 return false; 7752 7753 if (Ptr != Base) { 7754 // Swap base ptr and offset to catch more post-index load / store when 7755 // it's legal. In Thumb2 mode, offset must be an immediate. 7756 if (Ptr == Offset && Op->getOpcode() == ISD::ADD && 7757 !Subtarget->isThumb2()) 7758 std::swap(Base, Offset); 7759 7760 // Post-indexed load / store update the base pointer. 7761 if (Ptr != Base) 7762 return false; 7763 } 7764 7765 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 7766 return true; 7767 } 7768 7769 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 7770 const APInt &Mask, 7771 APInt &KnownZero, 7772 APInt &KnownOne, 7773 const SelectionDAG &DAG, 7774 unsigned Depth) const { 7775 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 7776 switch (Op.getOpcode()) { 7777 default: break; 7778 case ARMISD::CMOV: { 7779 // Bits are known zero/one if known on the LHS and RHS. 7780 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 7781 if (KnownZero == 0 && KnownOne == 0) return; 7782 7783 APInt KnownZeroRHS, KnownOneRHS; 7784 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, 7785 KnownZeroRHS, KnownOneRHS, Depth+1); 7786 KnownZero &= KnownZeroRHS; 7787 KnownOne &= KnownOneRHS; 7788 return; 7789 } 7790 } 7791 } 7792 7793 //===----------------------------------------------------------------------===// 7794 // ARM Inline Assembly Support 7795 //===----------------------------------------------------------------------===// 7796 7797 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const { 7798 // Looking for "rev" which is V6+. 7799 if (!Subtarget->hasV6Ops()) 7800 return false; 7801 7802 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 7803 std::string AsmStr = IA->getAsmString(); 7804 SmallVector<StringRef, 4> AsmPieces; 7805 SplitString(AsmStr, AsmPieces, ";\n"); 7806 7807 switch (AsmPieces.size()) { 7808 default: return false; 7809 case 1: 7810 AsmStr = AsmPieces[0]; 7811 AsmPieces.clear(); 7812 SplitString(AsmStr, AsmPieces, " \t,"); 7813 7814 // rev $0, $1 7815 if (AsmPieces.size() == 3 && 7816 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" && 7817 IA->getConstraintString().compare(0, 4, "=l,l") == 0) { 7818 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 7819 if (Ty && Ty->getBitWidth() == 32) 7820 return IntrinsicLowering::LowerToByteSwap(CI); 7821 } 7822 break; 7823 } 7824 7825 return false; 7826 } 7827 7828 /// getConstraintType - Given a constraint letter, return the type of 7829 /// constraint it is for this target. 7830 ARMTargetLowering::ConstraintType 7831 ARMTargetLowering::getConstraintType(const std::string &Constraint) const { 7832 if (Constraint.size() == 1) { 7833 switch (Constraint[0]) { 7834 default: break; 7835 case 'l': return C_RegisterClass; 7836 case 'w': return C_RegisterClass; 7837 case 'h': return C_RegisterClass; 7838 case 'x': return C_RegisterClass; 7839 case 't': return C_RegisterClass; 7840 case 'j': return C_Other; // Constant for movw. 7841 // An address with a single base register. Due to the way we 7842 // currently handle addresses it is the same as an 'r' memory constraint. 7843 case 'Q': return C_Memory; 7844 } 7845 } else if (Constraint.size() == 2) { 7846 switch (Constraint[0]) { 7847 default: break; 7848 // All 'U+' constraints are addresses. 7849 case 'U': return C_Memory; 7850 } 7851 } 7852 return TargetLowering::getConstraintType(Constraint); 7853 } 7854 7855 /// Examine constraint type and operand type and determine a weight value. 7856 /// This object must already have been set up with the operand type 7857 /// and the current alternative constraint selected. 7858 TargetLowering::ConstraintWeight 7859 ARMTargetLowering::getSingleConstraintMatchWeight( 7860 AsmOperandInfo &info, const char *constraint) const { 7861 ConstraintWeight weight = CW_Invalid; 7862 Value *CallOperandVal = info.CallOperandVal; 7863 // If we don't have a value, we can't do a match, 7864 // but allow it at the lowest weight. 7865 if (CallOperandVal == NULL) 7866 return CW_Default; 7867 Type *type = CallOperandVal->getType(); 7868 // Look at the constraint type. 7869 switch (*constraint) { 7870 default: 7871 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 7872 break; 7873 case 'l': 7874 if (type->isIntegerTy()) { 7875 if (Subtarget->isThumb()) 7876 weight = CW_SpecificReg; 7877 else 7878 weight = CW_Register; 7879 } 7880 break; 7881 case 'w': 7882 if (type->isFloatingPointTy()) 7883 weight = CW_Register; 7884 break; 7885 } 7886 return weight; 7887 } 7888 7889 typedef std::pair<unsigned, const TargetRegisterClass*> RCPair; 7890 RCPair 7891 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 7892 EVT VT) const { 7893 if (Constraint.size() == 1) { 7894 // GCC ARM Constraint Letters 7895 switch (Constraint[0]) { 7896 case 'l': // Low regs or general regs. 7897 if (Subtarget->isThumb()) 7898 return RCPair(0U, ARM::tGPRRegisterClass); 7899 else 7900 return RCPair(0U, ARM::GPRRegisterClass); 7901 case 'h': // High regs or no regs. 7902 if (Subtarget->isThumb()) 7903 return RCPair(0U, ARM::hGPRRegisterClass); 7904 break; 7905 case 'r': 7906 return RCPair(0U, ARM::GPRRegisterClass); 7907 case 'w': 7908 if (VT == MVT::f32) 7909 return RCPair(0U, ARM::SPRRegisterClass); 7910 if (VT.getSizeInBits() == 64) 7911 return RCPair(0U, ARM::DPRRegisterClass); 7912 if (VT.getSizeInBits() == 128) 7913 return RCPair(0U, ARM::QPRRegisterClass); 7914 break; 7915 case 'x': 7916 if (VT == MVT::f32) 7917 return RCPair(0U, ARM::SPR_8RegisterClass); 7918 if (VT.getSizeInBits() == 64) 7919 return RCPair(0U, ARM::DPR_8RegisterClass); 7920 if (VT.getSizeInBits() == 128) 7921 return RCPair(0U, ARM::QPR_8RegisterClass); 7922 break; 7923 case 't': 7924 if (VT == MVT::f32) 7925 return RCPair(0U, ARM::SPRRegisterClass); 7926 break; 7927 } 7928 } 7929 if (StringRef("{cc}").equals_lower(Constraint)) 7930 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass); 7931 7932 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 7933 } 7934 7935 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 7936 /// vector. If it is invalid, don't add anything to Ops. 7937 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 7938 std::string &Constraint, 7939 std::vector<SDValue>&Ops, 7940 SelectionDAG &DAG) const { 7941 SDValue Result(0, 0); 7942 7943 // Currently only support length 1 constraints. 7944 if (Constraint.length() != 1) return; 7945 7946 char ConstraintLetter = Constraint[0]; 7947 switch (ConstraintLetter) { 7948 default: break; 7949 case 'j': 7950 case 'I': case 'J': case 'K': case 'L': 7951 case 'M': case 'N': case 'O': 7952 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 7953 if (!C) 7954 return; 7955 7956 int64_t CVal64 = C->getSExtValue(); 7957 int CVal = (int) CVal64; 7958 // None of these constraints allow values larger than 32 bits. Check 7959 // that the value fits in an int. 7960 if (CVal != CVal64) 7961 return; 7962 7963 switch (ConstraintLetter) { 7964 case 'j': 7965 // Constant suitable for movw, must be between 0 and 7966 // 65535. 7967 if (Subtarget->hasV6T2Ops()) 7968 if (CVal >= 0 && CVal <= 65535) 7969 break; 7970 return; 7971 case 'I': 7972 if (Subtarget->isThumb1Only()) { 7973 // This must be a constant between 0 and 255, for ADD 7974 // immediates. 7975 if (CVal >= 0 && CVal <= 255) 7976 break; 7977 } else if (Subtarget->isThumb2()) { 7978 // A constant that can be used as an immediate value in a 7979 // data-processing instruction. 7980 if (ARM_AM::getT2SOImmVal(CVal) != -1) 7981 break; 7982 } else { 7983 // A constant that can be used as an immediate value in a 7984 // data-processing instruction. 7985 if (ARM_AM::getSOImmVal(CVal) != -1) 7986 break; 7987 } 7988 return; 7989 7990 case 'J': 7991 if (Subtarget->isThumb()) { // FIXME thumb2 7992 // This must be a constant between -255 and -1, for negated ADD 7993 // immediates. This can be used in GCC with an "n" modifier that 7994 // prints the negated value, for use with SUB instructions. It is 7995 // not useful otherwise but is implemented for compatibility. 7996 if (CVal >= -255 && CVal <= -1) 7997 break; 7998 } else { 7999 // This must be a constant between -4095 and 4095. It is not clear 8000 // what this constraint is intended for. Implemented for 8001 // compatibility with GCC. 8002 if (CVal >= -4095 && CVal <= 4095) 8003 break; 8004 } 8005 return; 8006 8007 case 'K': 8008 if (Subtarget->isThumb1Only()) { 8009 // A 32-bit value where only one byte has a nonzero value. Exclude 8010 // zero to match GCC. This constraint is used by GCC internally for 8011 // constants that can be loaded with a move/shift combination. 8012 // It is not useful otherwise but is implemented for compatibility. 8013 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal)) 8014 break; 8015 } else if (Subtarget->isThumb2()) { 8016 // A constant whose bitwise inverse can be used as an immediate 8017 // value in a data-processing instruction. This can be used in GCC 8018 // with a "B" modifier that prints the inverted value, for use with 8019 // BIC and MVN instructions. It is not useful otherwise but is 8020 // implemented for compatibility. 8021 if (ARM_AM::getT2SOImmVal(~CVal) != -1) 8022 break; 8023 } else { 8024 // A constant whose bitwise inverse can be used as an immediate 8025 // value in a data-processing instruction. This can be used in GCC 8026 // with a "B" modifier that prints the inverted value, for use with 8027 // BIC and MVN instructions. It is not useful otherwise but is 8028 // implemented for compatibility. 8029 if (ARM_AM::getSOImmVal(~CVal) != -1) 8030 break; 8031 } 8032 return; 8033 8034 case 'L': 8035 if (Subtarget->isThumb1Only()) { 8036 // This must be a constant between -7 and 7, 8037 // for 3-operand ADD/SUB immediate instructions. 8038 if (CVal >= -7 && CVal < 7) 8039 break; 8040 } else if (Subtarget->isThumb2()) { 8041 // A constant whose negation can be used as an immediate value in a 8042 // data-processing instruction. This can be used in GCC with an "n" 8043 // modifier that prints the negated value, for use with SUB 8044 // instructions. It is not useful otherwise but is implemented for 8045 // compatibility. 8046 if (ARM_AM::getT2SOImmVal(-CVal) != -1) 8047 break; 8048 } else { 8049 // A constant whose negation can be used as an immediate value in a 8050 // data-processing instruction. This can be used in GCC with an "n" 8051 // modifier that prints the negated value, for use with SUB 8052 // instructions. It is not useful otherwise but is implemented for 8053 // compatibility. 8054 if (ARM_AM::getSOImmVal(-CVal) != -1) 8055 break; 8056 } 8057 return; 8058 8059 case 'M': 8060 if (Subtarget->isThumb()) { // FIXME thumb2 8061 // This must be a multiple of 4 between 0 and 1020, for 8062 // ADD sp + immediate. 8063 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0)) 8064 break; 8065 } else { 8066 // A power of two or a constant between 0 and 32. This is used in 8067 // GCC for the shift amount on shifted register operands, but it is 8068 // useful in general for any shift amounts. 8069 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0)) 8070 break; 8071 } 8072 return; 8073 8074 case 'N': 8075 if (Subtarget->isThumb()) { // FIXME thumb2 8076 // This must be a constant between 0 and 31, for shift amounts. 8077 if (CVal >= 0 && CVal <= 31) 8078 break; 8079 } 8080 return; 8081 8082 case 'O': 8083 if (Subtarget->isThumb()) { // FIXME thumb2 8084 // This must be a multiple of 4 between -508 and 508, for 8085 // ADD/SUB sp = sp + immediate. 8086 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0)) 8087 break; 8088 } 8089 return; 8090 } 8091 Result = DAG.getTargetConstant(CVal, Op.getValueType()); 8092 break; 8093 } 8094 8095 if (Result.getNode()) { 8096 Ops.push_back(Result); 8097 return; 8098 } 8099 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 8100 } 8101 8102 bool 8103 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 8104 // The ARM target isn't yet aware of offsets. 8105 return false; 8106 } 8107 8108 int ARM::getVFPf32Imm(const APFloat &FPImm) { 8109 APInt Imm = FPImm.bitcastToAPInt(); 8110 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1; 8111 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127 8112 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits 8113 8114 // We can handle 4 bits of mantissa. 8115 // mantissa = (16+UInt(e:f:g:h))/16. 8116 if (Mantissa & 0x7ffff) 8117 return -1; 8118 Mantissa >>= 19; 8119 if ((Mantissa & 0xf) != Mantissa) 8120 return -1; 8121 8122 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3 8123 if (Exp < -3 || Exp > 4) 8124 return -1; 8125 Exp = ((Exp+3) & 0x7) ^ 4; 8126 8127 return ((int)Sign << 7) | (Exp << 4) | Mantissa; 8128 } 8129 8130 int ARM::getVFPf64Imm(const APFloat &FPImm) { 8131 APInt Imm = FPImm.bitcastToAPInt(); 8132 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1; 8133 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023 8134 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL; 8135 8136 // We can handle 4 bits of mantissa. 8137 // mantissa = (16+UInt(e:f:g:h))/16. 8138 if (Mantissa & 0xffffffffffffLL) 8139 return -1; 8140 Mantissa >>= 48; 8141 if ((Mantissa & 0xf) != Mantissa) 8142 return -1; 8143 8144 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3 8145 if (Exp < -3 || Exp > 4) 8146 return -1; 8147 Exp = ((Exp+3) & 0x7) ^ 4; 8148 8149 return ((int)Sign << 7) | (Exp << 4) | Mantissa; 8150 } 8151 8152 bool ARM::isBitFieldInvertedMask(unsigned v) { 8153 if (v == 0xffffffff) 8154 return 0; 8155 // there can be 1's on either or both "outsides", all the "inside" 8156 // bits must be 0's 8157 unsigned int lsb = 0, msb = 31; 8158 while (v & (1 << msb)) --msb; 8159 while (v & (1 << lsb)) ++lsb; 8160 for (unsigned int i = lsb; i <= msb; ++i) { 8161 if (v & (1 << i)) 8162 return 0; 8163 } 8164 return 1; 8165 } 8166 8167 /// isFPImmLegal - Returns true if the target can instruction select the 8168 /// specified FP immediate natively. If false, the legalizer will 8169 /// materialize the FP immediate as a load from a constant pool. 8170 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 8171 if (!Subtarget->hasVFP3()) 8172 return false; 8173 if (VT == MVT::f32) 8174 return ARM::getVFPf32Imm(Imm) != -1; 8175 if (VT == MVT::f64) 8176 return ARM::getVFPf64Imm(Imm) != -1; 8177 return false; 8178 } 8179 8180 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as 8181 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment 8182 /// specified in the intrinsic calls. 8183 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, 8184 const CallInst &I, 8185 unsigned Intrinsic) const { 8186 switch (Intrinsic) { 8187 case Intrinsic::arm_neon_vld1: 8188 case Intrinsic::arm_neon_vld2: 8189 case Intrinsic::arm_neon_vld3: 8190 case Intrinsic::arm_neon_vld4: 8191 case Intrinsic::arm_neon_vld2lane: 8192 case Intrinsic::arm_neon_vld3lane: 8193 case Intrinsic::arm_neon_vld4lane: { 8194 Info.opc = ISD::INTRINSIC_W_CHAIN; 8195 // Conservatively set memVT to the entire set of vectors loaded. 8196 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8; 8197 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); 8198 Info.ptrVal = I.getArgOperand(0); 8199 Info.offset = 0; 8200 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1); 8201 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue(); 8202 Info.vol = false; // volatile loads with NEON intrinsics not supported 8203 Info.readMem = true; 8204 Info.writeMem = false; 8205 return true; 8206 } 8207 case Intrinsic::arm_neon_vst1: 8208 case Intrinsic::arm_neon_vst2: 8209 case Intrinsic::arm_neon_vst3: 8210 case Intrinsic::arm_neon_vst4: 8211 case Intrinsic::arm_neon_vst2lane: 8212 case Intrinsic::arm_neon_vst3lane: 8213 case Intrinsic::arm_neon_vst4lane: { 8214 Info.opc = ISD::INTRINSIC_VOID; 8215 // Conservatively set memVT to the entire set of vectors stored. 8216 unsigned NumElts = 0; 8217 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) { 8218 Type *ArgTy = I.getArgOperand(ArgI)->getType(); 8219 if (!ArgTy->isVectorTy()) 8220 break; 8221 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8; 8222 } 8223 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); 8224 Info.ptrVal = I.getArgOperand(0); 8225 Info.offset = 0; 8226 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1); 8227 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue(); 8228 Info.vol = false; // volatile stores with NEON intrinsics not supported 8229 Info.readMem = false; 8230 Info.writeMem = true; 8231 return true; 8232 } 8233 case Intrinsic::arm_strexd: { 8234 Info.opc = ISD::INTRINSIC_W_CHAIN; 8235 Info.memVT = MVT::i64; 8236 Info.ptrVal = I.getArgOperand(2); 8237 Info.offset = 0; 8238 Info.align = 8; 8239 Info.vol = true; 8240 Info.readMem = false; 8241 Info.writeMem = true; 8242 return true; 8243 } 8244 case Intrinsic::arm_ldrexd: { 8245 Info.opc = ISD::INTRINSIC_W_CHAIN; 8246 Info.memVT = MVT::i64; 8247 Info.ptrVal = I.getArgOperand(0); 8248 Info.offset = 0; 8249 Info.align = 8; 8250 Info.vol = true; 8251 Info.readMem = true; 8252 Info.writeMem = false; 8253 return true; 8254 } 8255 default: 8256 break; 8257 } 8258 8259 return false; 8260 } 8261