1 //===-- ARMHazardRecognizer.cpp - ARM postra hazard recognizer ------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "ARMHazardRecognizer.h"
11 #include "ARMBaseInstrInfo.h"
12 #include "ARMSubtarget.h"
13 #include "llvm/CodeGen/MachineInstr.h"
14 #include "llvm/CodeGen/ScheduleDAG.h"
15 #include "llvm/Target/TargetRegisterInfo.h"
16 using namespace llvm;
17 
18 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI,
19                          const TargetRegisterInfo &TRI) {
20   // FIXME: Detect integer instructions properly.
21   const TargetInstrDesc &TID = MI->getDesc();
22   unsigned Domain = TID.TSFlags & ARMII::DomainMask;
23   if (Domain == ARMII::DomainVFP) {
24     unsigned Opcode = MI->getOpcode();
25     if (Opcode == ARM::VSTRS || Opcode == ARM::VSTRD ||
26         Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
27       return false;
28   } else if (Domain == ARMII::DomainNEON) {
29     if (MI->getDesc().mayStore() || MI->getDesc().mayLoad())
30       return false;
31   } else
32     return false;
33   return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
34 }
35 
36 ScheduleHazardRecognizer::HazardType
37 ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
38   assert(Stalls == 0 && "ARM hazards don't support scoreboard lookahead");
39 
40   MachineInstr *MI = SU->getInstr();
41 
42   if (!MI->isDebugValue()) {
43     if (ITBlockSize && MI != ITBlockMIs[ITBlockSize-1])
44       return Hazard;
45 
46     // Look for special VMLA / VMLS hazards. A VMUL / VADD / VSUB following
47     // a VMLA / VMLS will cause 4 cycle stall.
48     const TargetInstrDesc &TID = MI->getDesc();
49     if (LastMI && (TID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
50       MachineInstr *DefMI = LastMI;
51       const TargetInstrDesc &LastTID = LastMI->getDesc();
52       // Skip over one non-VFP / NEON instruction.
53       if (!LastTID.isBarrier() &&
54           (LastTID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) {
55         MachineBasicBlock::iterator I = LastMI;
56         if (I != LastMI->getParent()->begin()) {
57           I = llvm::prior(I);
58           DefMI = &*I;
59         }
60       }
61 
62       if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
63           (TII.canCauseFpMLxStall(MI->getOpcode()) ||
64            hasRAWHazard(DefMI, MI, TRI))) {
65         // Try to schedule another instruction for the next 4 cycles.
66         if (FpMLxStalls == 0)
67           FpMLxStalls = 4;
68         return Hazard;
69       }
70     }
71   }
72 
73   return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
74 }
75 
76 void ARMHazardRecognizer::Reset() {
77   LastMI = 0;
78   FpMLxStalls = 0;
79   ITBlockSize = 0;
80   ScoreboardHazardRecognizer::Reset();
81 }
82 
83 void ARMHazardRecognizer::EmitInstruction(SUnit *SU) {
84   MachineInstr *MI = SU->getInstr();
85   unsigned Opcode = MI->getOpcode();
86   if (ITBlockSize) {
87     --ITBlockSize;
88   } else if (Opcode == ARM::t2IT) {
89     unsigned Mask = MI->getOperand(1).getImm();
90     unsigned NumTZ = CountTrailingZeros_32(Mask);
91     assert(NumTZ <= 3 && "Invalid IT mask!");
92     ITBlockSize = 4 - NumTZ;
93     MachineBasicBlock::iterator I = MI;
94     for (unsigned i = 0; i < ITBlockSize; ++i) {
95       // Advance to the next instruction, skipping any dbg_value instructions.
96       do {
97         ++I;
98       } while (I->isDebugValue());
99       ITBlockMIs[ITBlockSize-1-i] = &*I;
100     }
101   }
102 
103   if (!MI->isDebugValue()) {
104     LastMI = MI;
105     FpMLxStalls = 0;
106   }
107 
108   ScoreboardHazardRecognizer::EmitInstruction(SU);
109 }
110 
111 void ARMHazardRecognizer::AdvanceCycle() {
112   if (FpMLxStalls && --FpMLxStalls == 0)
113     // Stalled for 4 cycles but still can't schedule any other instructions.
114     LastMI = 0;
115   ScoreboardHazardRecognizer::AdvanceCycle();
116 }
117 
118 void ARMHazardRecognizer::RecedeCycle() {
119   llvm_unreachable("reverse ARM hazard checking unsupported");
120 }
121