1 //===-- ARMHazardRecognizer.cpp - ARM postra hazard recognizer ------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "ARMHazardRecognizer.h"
11 #include "ARMBaseInstrInfo.h"
12 #include "ARMBaseRegisterInfo.h"
13 #include "ARMSubtarget.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/CodeGen/ScheduleDAG.h"
16 #include "llvm/Target/TargetRegisterInfo.h"
17 using namespace llvm;
18 
19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI,
20                          const TargetRegisterInfo &TRI) {
21   // FIXME: Detect integer instructions properly.
22   const TargetInstrDesc &TID = MI->getDesc();
23   unsigned Domain = TID.TSFlags & ARMII::DomainMask;
24   if (TID.mayStore())
25     return false;
26   unsigned Opcode = TID.getOpcode();
27   if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
28     return false;
29   if ((Domain & ARMII::DomainVFP) || (Domain & ARMII::DomainNEON))
30     return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
31   return false;
32 }
33 
34 ScheduleHazardRecognizer::HazardType
35 ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
36   assert(Stalls == 0 && "ARM hazards don't support scoreboard lookahead");
37 
38   MachineInstr *MI = SU->getInstr();
39 
40   if (!MI->isDebugValue()) {
41     if (ITBlockSize && MI != ITBlockMIs[ITBlockSize-1])
42       return Hazard;
43 
44     // Look for special VMLA / VMLS hazards. A VMUL / VADD / VSUB following
45     // a VMLA / VMLS will cause 4 cycle stall.
46     const TargetInstrDesc &TID = MI->getDesc();
47     if (LastMI && (TID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
48       MachineInstr *DefMI = LastMI;
49       const TargetInstrDesc &LastTID = LastMI->getDesc();
50       // Skip over one non-VFP / NEON instruction.
51       if (!LastTID.isBarrier() &&
52           (LastTID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) {
53         MachineBasicBlock::iterator I = LastMI;
54         if (I != LastMI->getParent()->begin()) {
55           I = llvm::prior(I);
56           DefMI = &*I;
57         }
58       }
59 
60       if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
61           (TII.canCauseFpMLxStall(MI->getOpcode()) ||
62            hasRAWHazard(DefMI, MI, TRI))) {
63         // Try to schedule another instruction for the next 4 cycles.
64         if (FpMLxStalls == 0)
65           FpMLxStalls = 4;
66         return Hazard;
67       }
68     }
69   }
70 
71   return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
72 }
73 
74 void ARMHazardRecognizer::Reset() {
75   LastMI = 0;
76   FpMLxStalls = 0;
77   ITBlockSize = 0;
78   ScoreboardHazardRecognizer::Reset();
79 }
80 
81 void ARMHazardRecognizer::EmitInstruction(SUnit *SU) {
82   MachineInstr *MI = SU->getInstr();
83   unsigned Opcode = MI->getOpcode();
84   if (ITBlockSize) {
85     --ITBlockSize;
86   } else if (Opcode == ARM::t2IT) {
87     unsigned Mask = MI->getOperand(1).getImm();
88     unsigned NumTZ = CountTrailingZeros_32(Mask);
89     assert(NumTZ <= 3 && "Invalid IT mask!");
90     ITBlockSize = 4 - NumTZ;
91     MachineBasicBlock::iterator I = MI;
92     for (unsigned i = 0; i < ITBlockSize; ++i) {
93       // Advance to the next instruction, skipping any dbg_value instructions.
94       do {
95         ++I;
96       } while (I->isDebugValue());
97       ITBlockMIs[ITBlockSize-1-i] = &*I;
98     }
99   }
100 
101   if (!MI->isDebugValue()) {
102     LastMI = MI;
103     FpMLxStalls = 0;
104   }
105 
106   ScoreboardHazardRecognizer::EmitInstruction(SU);
107 }
108 
109 void ARMHazardRecognizer::AdvanceCycle() {
110   if (FpMLxStalls && --FpMLxStalls == 0)
111     // Stalled for 4 cycles but still can't schedule any other instructions.
112     LastMI = 0;
113   ScoreboardHazardRecognizer::AdvanceCycle();
114 }
115 
116 void ARMHazardRecognizer::RecedeCycle() {
117   llvm_unreachable("reverse ARM hazard checking unsupported");
118 }
119