1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "ARM.h"
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/DataLayout.h"
35 #include "llvm/IR/DerivedTypes.h"
36 #include "llvm/IR/GlobalVariable.h"
37 #include "llvm/IR/Instructions.h"
38 #include "llvm/IR/IntrinsicInst.h"
39 #include "llvm/IR/Module.h"
40 #include "llvm/IR/Operator.h"
41 #include "llvm/Support/CallSite.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/GetElementPtrTypeIterator.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetLowering.h"
47 #include "llvm/Target/TargetMachine.h"
48 #include "llvm/Target/TargetOptions.h"
49 using namespace llvm;
50 
51 extern cl::opt<bool> EnableARMLongCalls;
52 
53 namespace {
54 
55   // All possible address modes, plus some.
56   typedef struct Address {
57     enum {
58       RegBase,
59       FrameIndexBase
60     } BaseType;
61 
62     union {
63       unsigned Reg;
64       int FI;
65     } Base;
66 
67     int Offset;
68 
69     // Innocuous defaults for our address.
70     Address()
71      : BaseType(RegBase), Offset(0) {
72        Base.Reg = 0;
73      }
74   } Address;
75 
76 class ARMFastISel : public FastISel {
77 
78   /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
79   /// make the right decision when generating code for different targets.
80   const ARMSubtarget *Subtarget;
81   const TargetMachine &TM;
82   const TargetInstrInfo &TII;
83   const TargetLowering &TLI;
84   ARMFunctionInfo *AFI;
85 
86   // Convenience variables to avoid some queries.
87   bool isThumb2;
88   LLVMContext *Context;
89 
90   public:
91     explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
92                          const TargetLibraryInfo *libInfo)
93     : FastISel(funcInfo, libInfo),
94       TM(funcInfo.MF->getTarget()),
95       TII(*TM.getInstrInfo()),
96       TLI(*TM.getTargetLowering()) {
97       Subtarget = &TM.getSubtarget<ARMSubtarget>();
98       AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
99       isThumb2 = AFI->isThumbFunction();
100       Context = &funcInfo.Fn->getContext();
101     }
102 
103     // Code from FastISel.cpp.
104   private:
105     unsigned FastEmitInst_(unsigned MachineInstOpcode,
106                            const TargetRegisterClass *RC);
107     unsigned FastEmitInst_r(unsigned MachineInstOpcode,
108                             const TargetRegisterClass *RC,
109                             unsigned Op0, bool Op0IsKill);
110     unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
111                              const TargetRegisterClass *RC,
112                              unsigned Op0, bool Op0IsKill,
113                              unsigned Op1, bool Op1IsKill);
114     unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
115                               const TargetRegisterClass *RC,
116                               unsigned Op0, bool Op0IsKill,
117                               unsigned Op1, bool Op1IsKill,
118                               unsigned Op2, bool Op2IsKill);
119     unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
120                              const TargetRegisterClass *RC,
121                              unsigned Op0, bool Op0IsKill,
122                              uint64_t Imm);
123     unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
124                              const TargetRegisterClass *RC,
125                              unsigned Op0, bool Op0IsKill,
126                              const ConstantFP *FPImm);
127     unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
128                               const TargetRegisterClass *RC,
129                               unsigned Op0, bool Op0IsKill,
130                               unsigned Op1, bool Op1IsKill,
131                               uint64_t Imm);
132     unsigned FastEmitInst_i(unsigned MachineInstOpcode,
133                             const TargetRegisterClass *RC,
134                             uint64_t Imm);
135     unsigned FastEmitInst_ii(unsigned MachineInstOpcode,
136                              const TargetRegisterClass *RC,
137                              uint64_t Imm1, uint64_t Imm2);
138 
139     unsigned FastEmitInst_extractsubreg(MVT RetVT,
140                                         unsigned Op0, bool Op0IsKill,
141                                         uint32_t Idx);
142 
143     // Backend specific FastISel code.
144   private:
145     virtual bool TargetSelectInstruction(const Instruction *I);
146     virtual unsigned TargetMaterializeConstant(const Constant *C);
147     virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
148     virtual bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
149                                      const LoadInst *LI);
150     virtual bool FastLowerArguments();
151   private:
152   #include "ARMGenFastISel.inc"
153 
154     // Instruction selection routines.
155   private:
156     bool SelectLoad(const Instruction *I);
157     bool SelectStore(const Instruction *I);
158     bool SelectBranch(const Instruction *I);
159     bool SelectIndirectBr(const Instruction *I);
160     bool SelectCmp(const Instruction *I);
161     bool SelectFPExt(const Instruction *I);
162     bool SelectFPTrunc(const Instruction *I);
163     bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
164     bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
165     bool SelectIToFP(const Instruction *I, bool isSigned);
166     bool SelectFPToI(const Instruction *I, bool isSigned);
167     bool SelectDiv(const Instruction *I, bool isSigned);
168     bool SelectRem(const Instruction *I, bool isSigned);
169     bool SelectCall(const Instruction *I, const char *IntrMemName);
170     bool SelectIntrinsicCall(const IntrinsicInst &I);
171     bool SelectSelect(const Instruction *I);
172     bool SelectRet(const Instruction *I);
173     bool SelectTrunc(const Instruction *I);
174     bool SelectIntExt(const Instruction *I);
175     bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
176 
177     // Utility routines.
178   private:
179     unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned OpNum,
180                                       unsigned Op);
181     bool isTypeLegal(Type *Ty, MVT &VT);
182     bool isLoadTypeLegal(Type *Ty, MVT &VT);
183     bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
184                     bool isZExt);
185     bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
186                      unsigned Alignment = 0, bool isZExt = true,
187                      bool allocReg = true);
188     bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
189                       unsigned Alignment = 0);
190     bool ARMComputeAddress(const Value *Obj, Address &Addr);
191     void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
192     bool ARMIsMemCpySmall(uint64_t Len);
193     bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
194                                unsigned Alignment);
195     unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
196     unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
197     unsigned ARMMaterializeInt(const Constant *C, MVT VT);
198     unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
199     unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
200     unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
201     unsigned ARMSelectCallOp(bool UseReg);
202     unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT);
203 
204     // Call handling routines.
205   private:
206     CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
207                                   bool Return,
208                                   bool isVarArg);
209     bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
210                          SmallVectorImpl<unsigned> &ArgRegs,
211                          SmallVectorImpl<MVT> &ArgVTs,
212                          SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
213                          SmallVectorImpl<unsigned> &RegArgs,
214                          CallingConv::ID CC,
215                          unsigned &NumBytes,
216                          bool isVarArg);
217     unsigned getLibcallReg(const Twine &Name);
218     bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
219                     const Instruction *I, CallingConv::ID CC,
220                     unsigned &NumBytes, bool isVarArg);
221     bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
222 
223     // OptionalDef handling routines.
224   private:
225     bool isARMNEONPred(const MachineInstr *MI);
226     bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
227     const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
228     void AddLoadStoreOperands(MVT VT, Address &Addr,
229                               const MachineInstrBuilder &MIB,
230                               unsigned Flags, bool useAM3);
231 };
232 
233 } // end anonymous namespace
234 
235 #include "ARMGenCallingConv.inc"
236 
237 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
238 // we don't care about implicit defs here, just places we'll need to add a
239 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
240 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
241   if (!MI->hasOptionalDef())
242     return false;
243 
244   // Look to see if our OptionalDef is defining CPSR or CCR.
245   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
246     const MachineOperand &MO = MI->getOperand(i);
247     if (!MO.isReg() || !MO.isDef()) continue;
248     if (MO.getReg() == ARM::CPSR)
249       *CPSR = true;
250   }
251   return true;
252 }
253 
254 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
255   const MCInstrDesc &MCID = MI->getDesc();
256 
257   // If we're a thumb2 or not NEON function we were handled via isPredicable.
258   if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
259        AFI->isThumb2Function())
260     return false;
261 
262   for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
263     if (MCID.OpInfo[i].isPredicate())
264       return true;
265 
266   return false;
267 }
268 
269 // If the machine is predicable go ahead and add the predicate operands, if
270 // it needs default CC operands add those.
271 // TODO: If we want to support thumb1 then we'll need to deal with optional
272 // CPSR defs that need to be added before the remaining operands. See s_cc_out
273 // for descriptions why.
274 const MachineInstrBuilder &
275 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
276   MachineInstr *MI = &*MIB;
277 
278   // Do we use a predicate? or...
279   // Are we NEON in ARM mode and have a predicate operand? If so, I know
280   // we're not predicable but add it anyways.
281   if (TII.isPredicable(MI) || isARMNEONPred(MI))
282     AddDefaultPred(MIB);
283 
284   // Do we optionally set a predicate?  Preds is size > 0 iff the predicate
285   // defines CPSR. All other OptionalDefines in ARM are the CCR register.
286   bool CPSR = false;
287   if (DefinesOptionalPredicate(MI, &CPSR)) {
288     if (CPSR)
289       AddDefaultT1CC(MIB);
290     else
291       AddDefaultCC(MIB);
292   }
293   return MIB;
294 }
295 
296 unsigned ARMFastISel::constrainOperandRegClass(const MCInstrDesc &II,
297                                                unsigned Op, unsigned OpNum) {
298   if (TargetRegisterInfo::isVirtualRegister(Op)) {
299     const TargetRegisterClass *RegClass =
300         TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF);
301     if (!MRI.constrainRegClass(Op, RegClass)) {
302       // If it's not legal to COPY between the register classes, something
303       // has gone very wrong before we got here.
304       unsigned NewOp = createResultReg(RegClass);
305       AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
306                               TII.get(TargetOpcode::COPY), NewOp).addReg(Op));
307       return NewOp;
308     }
309   }
310   return Op;
311 }
312 
313 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
314                                     const TargetRegisterClass* RC) {
315   unsigned ResultReg = createResultReg(RC);
316   const MCInstrDesc &II = TII.get(MachineInstOpcode);
317 
318   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
319   return ResultReg;
320 }
321 
322 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
323                                      const TargetRegisterClass *RC,
324                                      unsigned Op0, bool Op0IsKill) {
325   unsigned ResultReg = createResultReg(RC);
326   const MCInstrDesc &II = TII.get(MachineInstOpcode);
327 
328   // Make sure the input operand is sufficiently constrained to be legal
329   // for this instruction.
330   Op0 = constrainOperandRegClass(II, Op0, 1);
331   if (II.getNumDefs() >= 1) {
332     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
333                    .addReg(Op0, Op0IsKill * RegState::Kill));
334   } else {
335     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
336                    .addReg(Op0, Op0IsKill * RegState::Kill));
337     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
338                    TII.get(TargetOpcode::COPY), ResultReg)
339                    .addReg(II.ImplicitDefs[0]));
340   }
341   return ResultReg;
342 }
343 
344 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
345                                       const TargetRegisterClass *RC,
346                                       unsigned Op0, bool Op0IsKill,
347                                       unsigned Op1, bool Op1IsKill) {
348   unsigned ResultReg = createResultReg(RC);
349   const MCInstrDesc &II = TII.get(MachineInstOpcode);
350 
351   // Make sure the input operands are sufficiently constrained to be legal
352   // for this instruction.
353   Op0 = constrainOperandRegClass(II, Op0, 1);
354   Op1 = constrainOperandRegClass(II, Op1, 2);
355 
356   if (II.getNumDefs() >= 1) {
357     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
358                    .addReg(Op0, Op0IsKill * RegState::Kill)
359                    .addReg(Op1, Op1IsKill * RegState::Kill));
360   } else {
361     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
362                    .addReg(Op0, Op0IsKill * RegState::Kill)
363                    .addReg(Op1, Op1IsKill * RegState::Kill));
364     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
365                            TII.get(TargetOpcode::COPY), ResultReg)
366                    .addReg(II.ImplicitDefs[0]));
367   }
368   return ResultReg;
369 }
370 
371 unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
372                                        const TargetRegisterClass *RC,
373                                        unsigned Op0, bool Op0IsKill,
374                                        unsigned Op1, bool Op1IsKill,
375                                        unsigned Op2, bool Op2IsKill) {
376   unsigned ResultReg = createResultReg(RC);
377   const MCInstrDesc &II = TII.get(MachineInstOpcode);
378 
379   // Make sure the input operands are sufficiently constrained to be legal
380   // for this instruction.
381   Op0 = constrainOperandRegClass(II, Op0, 1);
382   Op1 = constrainOperandRegClass(II, Op1, 2);
383   Op2 = constrainOperandRegClass(II, Op1, 3);
384 
385   if (II.getNumDefs() >= 1) {
386     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
387                    .addReg(Op0, Op0IsKill * RegState::Kill)
388                    .addReg(Op1, Op1IsKill * RegState::Kill)
389                    .addReg(Op2, Op2IsKill * RegState::Kill));
390   } else {
391     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
392                    .addReg(Op0, Op0IsKill * RegState::Kill)
393                    .addReg(Op1, Op1IsKill * RegState::Kill)
394                    .addReg(Op2, Op2IsKill * RegState::Kill));
395     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
396                            TII.get(TargetOpcode::COPY), ResultReg)
397                    .addReg(II.ImplicitDefs[0]));
398   }
399   return ResultReg;
400 }
401 
402 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
403                                       const TargetRegisterClass *RC,
404                                       unsigned Op0, bool Op0IsKill,
405                                       uint64_t Imm) {
406   unsigned ResultReg = createResultReg(RC);
407   const MCInstrDesc &II = TII.get(MachineInstOpcode);
408 
409   // Make sure the input operand is sufficiently constrained to be legal
410   // for this instruction.
411   Op0 = constrainOperandRegClass(II, Op0, 1);
412   if (II.getNumDefs() >= 1) {
413     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
414                    .addReg(Op0, Op0IsKill * RegState::Kill)
415                    .addImm(Imm));
416   } else {
417     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
418                    .addReg(Op0, Op0IsKill * RegState::Kill)
419                    .addImm(Imm));
420     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
421                            TII.get(TargetOpcode::COPY), ResultReg)
422                    .addReg(II.ImplicitDefs[0]));
423   }
424   return ResultReg;
425 }
426 
427 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
428                                       const TargetRegisterClass *RC,
429                                       unsigned Op0, bool Op0IsKill,
430                                       const ConstantFP *FPImm) {
431   unsigned ResultReg = createResultReg(RC);
432   const MCInstrDesc &II = TII.get(MachineInstOpcode);
433 
434   // Make sure the input operand is sufficiently constrained to be legal
435   // for this instruction.
436   Op0 = constrainOperandRegClass(II, Op0, 1);
437   if (II.getNumDefs() >= 1) {
438     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
439                    .addReg(Op0, Op0IsKill * RegState::Kill)
440                    .addFPImm(FPImm));
441   } else {
442     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
443                    .addReg(Op0, Op0IsKill * RegState::Kill)
444                    .addFPImm(FPImm));
445     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
446                            TII.get(TargetOpcode::COPY), ResultReg)
447                    .addReg(II.ImplicitDefs[0]));
448   }
449   return ResultReg;
450 }
451 
452 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
453                                        const TargetRegisterClass *RC,
454                                        unsigned Op0, bool Op0IsKill,
455                                        unsigned Op1, bool Op1IsKill,
456                                        uint64_t Imm) {
457   unsigned ResultReg = createResultReg(RC);
458   const MCInstrDesc &II = TII.get(MachineInstOpcode);
459 
460   // Make sure the input operands are sufficiently constrained to be legal
461   // for this instruction.
462   Op0 = constrainOperandRegClass(II, Op0, 1);
463   Op1 = constrainOperandRegClass(II, Op1, 2);
464   if (II.getNumDefs() >= 1) {
465     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
466                    .addReg(Op0, Op0IsKill * RegState::Kill)
467                    .addReg(Op1, Op1IsKill * RegState::Kill)
468                    .addImm(Imm));
469   } else {
470     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
471                    .addReg(Op0, Op0IsKill * RegState::Kill)
472                    .addReg(Op1, Op1IsKill * RegState::Kill)
473                    .addImm(Imm));
474     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
475                            TII.get(TargetOpcode::COPY), ResultReg)
476                    .addReg(II.ImplicitDefs[0]));
477   }
478   return ResultReg;
479 }
480 
481 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
482                                      const TargetRegisterClass *RC,
483                                      uint64_t Imm) {
484   unsigned ResultReg = createResultReg(RC);
485   const MCInstrDesc &II = TII.get(MachineInstOpcode);
486 
487   if (II.getNumDefs() >= 1) {
488     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
489                    .addImm(Imm));
490   } else {
491     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
492                    .addImm(Imm));
493     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
494                            TII.get(TargetOpcode::COPY), ResultReg)
495                    .addReg(II.ImplicitDefs[0]));
496   }
497   return ResultReg;
498 }
499 
500 unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
501                                       const TargetRegisterClass *RC,
502                                       uint64_t Imm1, uint64_t Imm2) {
503   unsigned ResultReg = createResultReg(RC);
504   const MCInstrDesc &II = TII.get(MachineInstOpcode);
505 
506   if (II.getNumDefs() >= 1) {
507     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
508                     .addImm(Imm1).addImm(Imm2));
509   } else {
510     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
511                     .addImm(Imm1).addImm(Imm2));
512     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
513                             TII.get(TargetOpcode::COPY),
514                             ResultReg)
515                     .addReg(II.ImplicitDefs[0]));
516   }
517   return ResultReg;
518 }
519 
520 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
521                                                  unsigned Op0, bool Op0IsKill,
522                                                  uint32_t Idx) {
523   unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
524   assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
525          "Cannot yet extract from physregs");
526 
527   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
528                           DL, TII.get(TargetOpcode::COPY), ResultReg)
529                   .addReg(Op0, getKillRegState(Op0IsKill), Idx));
530   return ResultReg;
531 }
532 
533 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
534 // checks from the various callers.
535 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
536   if (VT == MVT::f64) return 0;
537 
538   unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
539   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
540                           TII.get(ARM::VMOVSR), MoveReg)
541                   .addReg(SrcReg));
542   return MoveReg;
543 }
544 
545 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) {
546   if (VT == MVT::i64) return 0;
547 
548   unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
549   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
550                           TII.get(ARM::VMOVRS), MoveReg)
551                   .addReg(SrcReg));
552   return MoveReg;
553 }
554 
555 // For double width floating point we need to materialize two constants
556 // (the high and the low) into integer registers then use a move to get
557 // the combined constant into an FP reg.
558 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
559   const APFloat Val = CFP->getValueAPF();
560   bool is64bit = VT == MVT::f64;
561 
562   // This checks to see if we can use VFP3 instructions to materialize
563   // a constant, otherwise we have to go through the constant pool.
564   if (TLI.isFPImmLegal(Val, VT)) {
565     int Imm;
566     unsigned Opc;
567     if (is64bit) {
568       Imm = ARM_AM::getFP64Imm(Val);
569       Opc = ARM::FCONSTD;
570     } else {
571       Imm = ARM_AM::getFP32Imm(Val);
572       Opc = ARM::FCONSTS;
573     }
574     unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
575     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
576                             DestReg)
577                     .addImm(Imm));
578     return DestReg;
579   }
580 
581   // Require VFP2 for loading fp constants.
582   if (!Subtarget->hasVFP2()) return false;
583 
584   // MachineConstantPool wants an explicit alignment.
585   unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
586   if (Align == 0) {
587     // TODO: Figure out if this is correct.
588     Align = TD.getTypeAllocSize(CFP->getType());
589   }
590   unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
591   unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
592   unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
593 
594   // The extra reg is for addrmode5.
595   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
596                           DestReg)
597                   .addConstantPoolIndex(Idx)
598                   .addReg(0));
599   return DestReg;
600 }
601 
602 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
603 
604   if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
605     return false;
606 
607   // If we can do this in a single instruction without a constant pool entry
608   // do so now.
609   const ConstantInt *CI = cast<ConstantInt>(C);
610   if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
611     unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
612     const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
613       &ARM::GPRRegClass;
614     unsigned ImmReg = createResultReg(RC);
615     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
616                             TII.get(Opc), ImmReg)
617                     .addImm(CI->getZExtValue()));
618     return ImmReg;
619   }
620 
621   // Use MVN to emit negative constants.
622   if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
623     unsigned Imm = (unsigned)~(CI->getSExtValue());
624     bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
625       (ARM_AM::getSOImmVal(Imm) != -1);
626     if (UseImm) {
627       unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
628       unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
629       AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
630                               TII.get(Opc), ImmReg)
631                       .addImm(Imm));
632       return ImmReg;
633     }
634   }
635 
636   // Load from constant pool.  For now 32-bit only.
637   if (VT != MVT::i32)
638     return false;
639 
640   unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
641 
642   // MachineConstantPool wants an explicit alignment.
643   unsigned Align = TD.getPrefTypeAlignment(C->getType());
644   if (Align == 0) {
645     // TODO: Figure out if this is correct.
646     Align = TD.getTypeAllocSize(C->getType());
647   }
648   unsigned Idx = MCP.getConstantPoolIndex(C, Align);
649 
650   if (isThumb2)
651     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
652                             TII.get(ARM::t2LDRpci), DestReg)
653                     .addConstantPoolIndex(Idx));
654   else
655     // The extra immediate is for addrmode2.
656     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
657                             TII.get(ARM::LDRcp), DestReg)
658                     .addConstantPoolIndex(Idx)
659                     .addImm(0));
660 
661   return DestReg;
662 }
663 
664 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
665   // For now 32-bit only.
666   if (VT != MVT::i32) return 0;
667 
668   Reloc::Model RelocM = TM.getRelocationModel();
669   bool IsIndirect = Subtarget->GVIsIndirectSymbol(GV, RelocM);
670   const TargetRegisterClass *RC = isThumb2 ?
671     (const TargetRegisterClass*)&ARM::rGPRRegClass :
672     (const TargetRegisterClass*)&ARM::GPRRegClass;
673   unsigned DestReg = createResultReg(RC);
674 
675   // FastISel TLS support on non-Darwin is broken, punt to SelectionDAG.
676   const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
677   bool IsThreadLocal = GVar && GVar->isThreadLocal();
678   if (!Subtarget->isTargetDarwin() && IsThreadLocal) return 0;
679 
680   // Use movw+movt when possible, it avoids constant pool entries.
681   // Darwin targets don't support movt with Reloc::Static, see
682   // ARMTargetLowering::LowerGlobalAddressDarwin.  Other targets only support
683   // static movt relocations.
684   if (Subtarget->useMovt() &&
685       Subtarget->isTargetDarwin() == (RelocM != Reloc::Static)) {
686     unsigned Opc;
687     switch (RelocM) {
688     case Reloc::PIC_:
689       Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
690       break;
691     case Reloc::DynamicNoPIC:
692       Opc = isThumb2 ? ARM::t2MOV_ga_dyn : ARM::MOV_ga_dyn;
693       break;
694     default:
695       Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
696       break;
697     }
698     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
699                             DestReg).addGlobalAddress(GV));
700   } else {
701     // MachineConstantPool wants an explicit alignment.
702     unsigned Align = TD.getPrefTypeAlignment(GV->getType());
703     if (Align == 0) {
704       // TODO: Figure out if this is correct.
705       Align = TD.getTypeAllocSize(GV->getType());
706     }
707 
708     if (Subtarget->isTargetELF() && RelocM == Reloc::PIC_)
709       return ARMLowerPICELF(GV, Align, VT);
710 
711     // Grab index.
712     unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 :
713       (Subtarget->isThumb() ? 4 : 8);
714     unsigned Id = AFI->createPICLabelUId();
715     ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id,
716                                                                 ARMCP::CPValue,
717                                                                 PCAdj);
718     unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
719 
720     // Load value.
721     MachineInstrBuilder MIB;
722     if (isThumb2) {
723       unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
724       MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
725         .addConstantPoolIndex(Idx);
726       if (RelocM == Reloc::PIC_)
727         MIB.addImm(Id);
728       AddOptionalDefs(MIB);
729     } else {
730       // The extra immediate is for addrmode2.
731       MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
732                     DestReg)
733         .addConstantPoolIndex(Idx)
734         .addImm(0);
735       AddOptionalDefs(MIB);
736 
737       if (RelocM == Reloc::PIC_) {
738         unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
739         unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
740 
741         MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
742                                           DL, TII.get(Opc), NewDestReg)
743                                   .addReg(DestReg)
744                                   .addImm(Id);
745         AddOptionalDefs(MIB);
746         return NewDestReg;
747       }
748     }
749   }
750 
751   if (IsIndirect) {
752     MachineInstrBuilder MIB;
753     unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
754     if (isThumb2)
755       MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
756                     TII.get(ARM::t2LDRi12), NewDestReg)
757             .addReg(DestReg)
758             .addImm(0);
759     else
760       MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
761                     NewDestReg)
762             .addReg(DestReg)
763             .addImm(0);
764     DestReg = NewDestReg;
765     AddOptionalDefs(MIB);
766   }
767 
768   return DestReg;
769 }
770 
771 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
772   EVT CEVT = TLI.getValueType(C->getType(), true);
773 
774   // Only handle simple types.
775   if (!CEVT.isSimple()) return 0;
776   MVT VT = CEVT.getSimpleVT();
777 
778   if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
779     return ARMMaterializeFP(CFP, VT);
780   else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
781     return ARMMaterializeGV(GV, VT);
782   else if (isa<ConstantInt>(C))
783     return ARMMaterializeInt(C, VT);
784 
785   return 0;
786 }
787 
788 // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
789 
790 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
791   // Don't handle dynamic allocas.
792   if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
793 
794   MVT VT;
795   if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
796 
797   DenseMap<const AllocaInst*, int>::iterator SI =
798     FuncInfo.StaticAllocaMap.find(AI);
799 
800   // This will get lowered later into the correct offsets and registers
801   // via rewriteXFrameIndex.
802   if (SI != FuncInfo.StaticAllocaMap.end()) {
803     const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
804     unsigned ResultReg = createResultReg(RC);
805     unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
806     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
807                             TII.get(Opc), ResultReg)
808                             .addFrameIndex(SI->second)
809                             .addImm(0));
810     return ResultReg;
811   }
812 
813   return 0;
814 }
815 
816 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
817   EVT evt = TLI.getValueType(Ty, true);
818 
819   // Only handle simple types.
820   if (evt == MVT::Other || !evt.isSimple()) return false;
821   VT = evt.getSimpleVT();
822 
823   // Handle all legal types, i.e. a register that will directly hold this
824   // value.
825   return TLI.isTypeLegal(VT);
826 }
827 
828 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
829   if (isTypeLegal(Ty, VT)) return true;
830 
831   // If this is a type than can be sign or zero-extended to a basic operation
832   // go ahead and accept it now.
833   if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
834     return true;
835 
836   return false;
837 }
838 
839 // Computes the address to get to an object.
840 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
841   // Some boilerplate from the X86 FastISel.
842   const User *U = NULL;
843   unsigned Opcode = Instruction::UserOp1;
844   if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
845     // Don't walk into other basic blocks unless the object is an alloca from
846     // another block, otherwise it may not have a virtual register assigned.
847     if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
848         FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
849       Opcode = I->getOpcode();
850       U = I;
851     }
852   } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
853     Opcode = C->getOpcode();
854     U = C;
855   }
856 
857   if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
858     if (Ty->getAddressSpace() > 255)
859       // Fast instruction selection doesn't support the special
860       // address spaces.
861       return false;
862 
863   switch (Opcode) {
864     default:
865     break;
866     case Instruction::BitCast:
867       // Look through bitcasts.
868       return ARMComputeAddress(U->getOperand(0), Addr);
869     case Instruction::IntToPtr:
870       // Look past no-op inttoptrs.
871       if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
872         return ARMComputeAddress(U->getOperand(0), Addr);
873       break;
874     case Instruction::PtrToInt:
875       // Look past no-op ptrtoints.
876       if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
877         return ARMComputeAddress(U->getOperand(0), Addr);
878       break;
879     case Instruction::GetElementPtr: {
880       Address SavedAddr = Addr;
881       int TmpOffset = Addr.Offset;
882 
883       // Iterate through the GEP folding the constants into offsets where
884       // we can.
885       gep_type_iterator GTI = gep_type_begin(U);
886       for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
887            i != e; ++i, ++GTI) {
888         const Value *Op = *i;
889         if (StructType *STy = dyn_cast<StructType>(*GTI)) {
890           const StructLayout *SL = TD.getStructLayout(STy);
891           unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
892           TmpOffset += SL->getElementOffset(Idx);
893         } else {
894           uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
895           for (;;) {
896             if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
897               // Constant-offset addressing.
898               TmpOffset += CI->getSExtValue() * S;
899               break;
900             }
901             if (isa<AddOperator>(Op) &&
902                 (!isa<Instruction>(Op) ||
903                  FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
904                  == FuncInfo.MBB) &&
905                 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
906               // An add (in the same block) with a constant operand. Fold the
907               // constant.
908               ConstantInt *CI =
909               cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
910               TmpOffset += CI->getSExtValue() * S;
911               // Iterate on the other operand.
912               Op = cast<AddOperator>(Op)->getOperand(0);
913               continue;
914             }
915             // Unsupported
916             goto unsupported_gep;
917           }
918         }
919       }
920 
921       // Try to grab the base operand now.
922       Addr.Offset = TmpOffset;
923       if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
924 
925       // We failed, restore everything and try the other options.
926       Addr = SavedAddr;
927 
928       unsupported_gep:
929       break;
930     }
931     case Instruction::Alloca: {
932       const AllocaInst *AI = cast<AllocaInst>(Obj);
933       DenseMap<const AllocaInst*, int>::iterator SI =
934         FuncInfo.StaticAllocaMap.find(AI);
935       if (SI != FuncInfo.StaticAllocaMap.end()) {
936         Addr.BaseType = Address::FrameIndexBase;
937         Addr.Base.FI = SI->second;
938         return true;
939       }
940       break;
941     }
942   }
943 
944   // Try to get this in a register if nothing else has worked.
945   if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
946   return Addr.Base.Reg != 0;
947 }
948 
949 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
950   bool needsLowering = false;
951   switch (VT.SimpleTy) {
952     default: llvm_unreachable("Unhandled load/store type!");
953     case MVT::i1:
954     case MVT::i8:
955     case MVT::i16:
956     case MVT::i32:
957       if (!useAM3) {
958         // Integer loads/stores handle 12-bit offsets.
959         needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
960         // Handle negative offsets.
961         if (needsLowering && isThumb2)
962           needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
963                             Addr.Offset > -256);
964       } else {
965         // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
966         needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
967       }
968       break;
969     case MVT::f32:
970     case MVT::f64:
971       // Floating point operands handle 8-bit offsets.
972       needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
973       break;
974   }
975 
976   // If this is a stack pointer and the offset needs to be simplified then
977   // put the alloca address into a register, set the base type back to
978   // register and continue. This should almost never happen.
979   if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
980     const TargetRegisterClass *RC = isThumb2 ?
981       (const TargetRegisterClass*)&ARM::tGPRRegClass :
982       (const TargetRegisterClass*)&ARM::GPRRegClass;
983     unsigned ResultReg = createResultReg(RC);
984     unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
985     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
986                             TII.get(Opc), ResultReg)
987                             .addFrameIndex(Addr.Base.FI)
988                             .addImm(0));
989     Addr.Base.Reg = ResultReg;
990     Addr.BaseType = Address::RegBase;
991   }
992 
993   // Since the offset is too large for the load/store instruction
994   // get the reg+offset into a register.
995   if (needsLowering) {
996     Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
997                                  /*Op0IsKill*/false, Addr.Offset, MVT::i32);
998     Addr.Offset = 0;
999   }
1000 }
1001 
1002 void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
1003                                        const MachineInstrBuilder &MIB,
1004                                        unsigned Flags, bool useAM3) {
1005   // addrmode5 output depends on the selection dag addressing dividing the
1006   // offset by 4 that it then later multiplies. Do this here as well.
1007   if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64)
1008     Addr.Offset /= 4;
1009 
1010   // Frame base works a bit differently. Handle it separately.
1011   if (Addr.BaseType == Address::FrameIndexBase) {
1012     int FI = Addr.Base.FI;
1013     int Offset = Addr.Offset;
1014     MachineMemOperand *MMO =
1015           FuncInfo.MF->getMachineMemOperand(
1016                                   MachinePointerInfo::getFixedStack(FI, Offset),
1017                                   Flags,
1018                                   MFI.getObjectSize(FI),
1019                                   MFI.getObjectAlignment(FI));
1020     // Now add the rest of the operands.
1021     MIB.addFrameIndex(FI);
1022 
1023     // ARM halfword load/stores and signed byte loads need an additional
1024     // operand.
1025     if (useAM3) {
1026       signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
1027       MIB.addReg(0);
1028       MIB.addImm(Imm);
1029     } else {
1030       MIB.addImm(Addr.Offset);
1031     }
1032     MIB.addMemOperand(MMO);
1033   } else {
1034     // Now add the rest of the operands.
1035     MIB.addReg(Addr.Base.Reg);
1036 
1037     // ARM halfword load/stores and signed byte loads need an additional
1038     // operand.
1039     if (useAM3) {
1040       signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
1041       MIB.addReg(0);
1042       MIB.addImm(Imm);
1043     } else {
1044       MIB.addImm(Addr.Offset);
1045     }
1046   }
1047   AddOptionalDefs(MIB);
1048 }
1049 
1050 bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
1051                               unsigned Alignment, bool isZExt, bool allocReg) {
1052   unsigned Opc;
1053   bool useAM3 = false;
1054   bool needVMOV = false;
1055   const TargetRegisterClass *RC;
1056   switch (VT.SimpleTy) {
1057     // This is mostly going to be Neon/vector support.
1058     default: return false;
1059     case MVT::i1:
1060     case MVT::i8:
1061       if (isThumb2) {
1062         if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1063           Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
1064         else
1065           Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
1066       } else {
1067         if (isZExt) {
1068           Opc = ARM::LDRBi12;
1069         } else {
1070           Opc = ARM::LDRSB;
1071           useAM3 = true;
1072         }
1073       }
1074       RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1075       break;
1076     case MVT::i16:
1077       if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1078         return false;
1079 
1080       if (isThumb2) {
1081         if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1082           Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
1083         else
1084           Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
1085       } else {
1086         Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
1087         useAM3 = true;
1088       }
1089       RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1090       break;
1091     case MVT::i32:
1092       if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1093         return false;
1094 
1095       if (isThumb2) {
1096         if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1097           Opc = ARM::t2LDRi8;
1098         else
1099           Opc = ARM::t2LDRi12;
1100       } else {
1101         Opc = ARM::LDRi12;
1102       }
1103       RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1104       break;
1105     case MVT::f32:
1106       if (!Subtarget->hasVFP2()) return false;
1107       // Unaligned loads need special handling. Floats require word-alignment.
1108       if (Alignment && Alignment < 4) {
1109         needVMOV = true;
1110         VT = MVT::i32;
1111         Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
1112         RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1113       } else {
1114         Opc = ARM::VLDRS;
1115         RC = TLI.getRegClassFor(VT);
1116       }
1117       break;
1118     case MVT::f64:
1119       if (!Subtarget->hasVFP2()) return false;
1120       // FIXME: Unaligned loads need special handling.  Doublewords require
1121       // word-alignment.
1122       if (Alignment && Alignment < 4)
1123         return false;
1124 
1125       Opc = ARM::VLDRD;
1126       RC = TLI.getRegClassFor(VT);
1127       break;
1128   }
1129   // Simplify this down to something we can handle.
1130   ARMSimplifyAddress(Addr, VT, useAM3);
1131 
1132   // Create the base instruction, then add the operands.
1133   if (allocReg)
1134     ResultReg = createResultReg(RC);
1135   assert (ResultReg > 255 && "Expected an allocated virtual register.");
1136   MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1137                                     TII.get(Opc), ResultReg);
1138   AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1139 
1140   // If we had an unaligned load of a float we've converted it to an regular
1141   // load.  Now we must move from the GRP to the FP register.
1142   if (needVMOV) {
1143     unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1144     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1145                             TII.get(ARM::VMOVSR), MoveReg)
1146                     .addReg(ResultReg));
1147     ResultReg = MoveReg;
1148   }
1149   return true;
1150 }
1151 
1152 bool ARMFastISel::SelectLoad(const Instruction *I) {
1153   // Atomic loads need special handling.
1154   if (cast<LoadInst>(I)->isAtomic())
1155     return false;
1156 
1157   // Verify we have a legal type before going any further.
1158   MVT VT;
1159   if (!isLoadTypeLegal(I->getType(), VT))
1160     return false;
1161 
1162   // See if we can handle this address.
1163   Address Addr;
1164   if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
1165 
1166   unsigned ResultReg;
1167   if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
1168     return false;
1169   UpdateValueMap(I, ResultReg);
1170   return true;
1171 }
1172 
1173 bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
1174                                unsigned Alignment) {
1175   unsigned StrOpc;
1176   bool useAM3 = false;
1177   switch (VT.SimpleTy) {
1178     // This is mostly going to be Neon/vector support.
1179     default: return false;
1180     case MVT::i1: {
1181       unsigned Res = createResultReg(isThumb2 ?
1182         (const TargetRegisterClass*)&ARM::tGPRRegClass :
1183         (const TargetRegisterClass*)&ARM::GPRRegClass);
1184       unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1185       AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1186                               TII.get(Opc), Res)
1187                       .addReg(SrcReg).addImm(1));
1188       SrcReg = Res;
1189     } // Fallthrough here.
1190     case MVT::i8:
1191       if (isThumb2) {
1192         if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1193           StrOpc = ARM::t2STRBi8;
1194         else
1195           StrOpc = ARM::t2STRBi12;
1196       } else {
1197         StrOpc = ARM::STRBi12;
1198       }
1199       break;
1200     case MVT::i16:
1201       if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1202         return false;
1203 
1204       if (isThumb2) {
1205         if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1206           StrOpc = ARM::t2STRHi8;
1207         else
1208           StrOpc = ARM::t2STRHi12;
1209       } else {
1210         StrOpc = ARM::STRH;
1211         useAM3 = true;
1212       }
1213       break;
1214     case MVT::i32:
1215       if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1216         return false;
1217 
1218       if (isThumb2) {
1219         if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1220           StrOpc = ARM::t2STRi8;
1221         else
1222           StrOpc = ARM::t2STRi12;
1223       } else {
1224         StrOpc = ARM::STRi12;
1225       }
1226       break;
1227     case MVT::f32:
1228       if (!Subtarget->hasVFP2()) return false;
1229       // Unaligned stores need special handling. Floats require word-alignment.
1230       if (Alignment && Alignment < 4) {
1231         unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1232         AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1233                                 TII.get(ARM::VMOVRS), MoveReg)
1234                         .addReg(SrcReg));
1235         SrcReg = MoveReg;
1236         VT = MVT::i32;
1237         StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1238       } else {
1239         StrOpc = ARM::VSTRS;
1240       }
1241       break;
1242     case MVT::f64:
1243       if (!Subtarget->hasVFP2()) return false;
1244       // FIXME: Unaligned stores need special handling.  Doublewords require
1245       // word-alignment.
1246       if (Alignment && Alignment < 4)
1247           return false;
1248 
1249       StrOpc = ARM::VSTRD;
1250       break;
1251   }
1252   // Simplify this down to something we can handle.
1253   ARMSimplifyAddress(Addr, VT, useAM3);
1254 
1255   // Create the base instruction, then add the operands.
1256   MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1257                                     TII.get(StrOpc))
1258                             .addReg(SrcReg);
1259   AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1260   return true;
1261 }
1262 
1263 bool ARMFastISel::SelectStore(const Instruction *I) {
1264   Value *Op0 = I->getOperand(0);
1265   unsigned SrcReg = 0;
1266 
1267   // Atomic stores need special handling.
1268   if (cast<StoreInst>(I)->isAtomic())
1269     return false;
1270 
1271   // Verify we have a legal type before going any further.
1272   MVT VT;
1273   if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1274     return false;
1275 
1276   // Get the value to be stored into a register.
1277   SrcReg = getRegForValue(Op0);
1278   if (SrcReg == 0) return false;
1279 
1280   // See if we can handle this address.
1281   Address Addr;
1282   if (!ARMComputeAddress(I->getOperand(1), Addr))
1283     return false;
1284 
1285   if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
1286     return false;
1287   return true;
1288 }
1289 
1290 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1291   switch (Pred) {
1292     // Needs two compares...
1293     case CmpInst::FCMP_ONE:
1294     case CmpInst::FCMP_UEQ:
1295     default:
1296       // AL is our "false" for now. The other two need more compares.
1297       return ARMCC::AL;
1298     case CmpInst::ICMP_EQ:
1299     case CmpInst::FCMP_OEQ:
1300       return ARMCC::EQ;
1301     case CmpInst::ICMP_SGT:
1302     case CmpInst::FCMP_OGT:
1303       return ARMCC::GT;
1304     case CmpInst::ICMP_SGE:
1305     case CmpInst::FCMP_OGE:
1306       return ARMCC::GE;
1307     case CmpInst::ICMP_UGT:
1308     case CmpInst::FCMP_UGT:
1309       return ARMCC::HI;
1310     case CmpInst::FCMP_OLT:
1311       return ARMCC::MI;
1312     case CmpInst::ICMP_ULE:
1313     case CmpInst::FCMP_OLE:
1314       return ARMCC::LS;
1315     case CmpInst::FCMP_ORD:
1316       return ARMCC::VC;
1317     case CmpInst::FCMP_UNO:
1318       return ARMCC::VS;
1319     case CmpInst::FCMP_UGE:
1320       return ARMCC::PL;
1321     case CmpInst::ICMP_SLT:
1322     case CmpInst::FCMP_ULT:
1323       return ARMCC::LT;
1324     case CmpInst::ICMP_SLE:
1325     case CmpInst::FCMP_ULE:
1326       return ARMCC::LE;
1327     case CmpInst::FCMP_UNE:
1328     case CmpInst::ICMP_NE:
1329       return ARMCC::NE;
1330     case CmpInst::ICMP_UGE:
1331       return ARMCC::HS;
1332     case CmpInst::ICMP_ULT:
1333       return ARMCC::LO;
1334   }
1335 }
1336 
1337 bool ARMFastISel::SelectBranch(const Instruction *I) {
1338   const BranchInst *BI = cast<BranchInst>(I);
1339   MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1340   MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1341 
1342   // Simple branch support.
1343 
1344   // If we can, avoid recomputing the compare - redoing it could lead to wonky
1345   // behavior.
1346   if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1347     if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1348 
1349       // Get the compare predicate.
1350       // Try to take advantage of fallthrough opportunities.
1351       CmpInst::Predicate Predicate = CI->getPredicate();
1352       if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1353         std::swap(TBB, FBB);
1354         Predicate = CmpInst::getInversePredicate(Predicate);
1355       }
1356 
1357       ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1358 
1359       // We may not handle every CC for now.
1360       if (ARMPred == ARMCC::AL) return false;
1361 
1362       // Emit the compare.
1363       if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1364         return false;
1365 
1366       unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1367       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1368       .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1369       FastEmitBranch(FBB, DL);
1370       FuncInfo.MBB->addSuccessor(TBB);
1371       return true;
1372     }
1373   } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1374     MVT SourceVT;
1375     if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1376         (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1377       unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1378       unsigned OpReg = getRegForValue(TI->getOperand(0));
1379       AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1380                               TII.get(TstOpc))
1381                       .addReg(OpReg).addImm(1));
1382 
1383       unsigned CCMode = ARMCC::NE;
1384       if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1385         std::swap(TBB, FBB);
1386         CCMode = ARMCC::EQ;
1387       }
1388 
1389       unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1390       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1391       .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1392 
1393       FastEmitBranch(FBB, DL);
1394       FuncInfo.MBB->addSuccessor(TBB);
1395       return true;
1396     }
1397   } else if (const ConstantInt *CI =
1398              dyn_cast<ConstantInt>(BI->getCondition())) {
1399     uint64_t Imm = CI->getZExtValue();
1400     MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1401     FastEmitBranch(Target, DL);
1402     return true;
1403   }
1404 
1405   unsigned CmpReg = getRegForValue(BI->getCondition());
1406   if (CmpReg == 0) return false;
1407 
1408   // We've been divorced from our compare!  Our block was split, and
1409   // now our compare lives in a predecessor block.  We musn't
1410   // re-compare here, as the children of the compare aren't guaranteed
1411   // live across the block boundary (we *could* check for this).
1412   // Regardless, the compare has been done in the predecessor block,
1413   // and it left a value for us in a virtual register.  Ergo, we test
1414   // the one-bit value left in the virtual register.
1415   unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1416   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc))
1417                   .addReg(CmpReg).addImm(1));
1418 
1419   unsigned CCMode = ARMCC::NE;
1420   if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1421     std::swap(TBB, FBB);
1422     CCMode = ARMCC::EQ;
1423   }
1424 
1425   unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1426   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1427                   .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1428   FastEmitBranch(FBB, DL);
1429   FuncInfo.MBB->addSuccessor(TBB);
1430   return true;
1431 }
1432 
1433 bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
1434   unsigned AddrReg = getRegForValue(I->getOperand(0));
1435   if (AddrReg == 0) return false;
1436 
1437   unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1438   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
1439                   .addReg(AddrReg));
1440 
1441   const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1442   for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
1443     FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
1444 
1445   return true;
1446 }
1447 
1448 bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1449                              bool isZExt) {
1450   Type *Ty = Src1Value->getType();
1451   EVT SrcEVT = TLI.getValueType(Ty, true);
1452   if (!SrcEVT.isSimple()) return false;
1453   MVT SrcVT = SrcEVT.getSimpleVT();
1454 
1455   bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
1456   if (isFloat && !Subtarget->hasVFP2())
1457     return false;
1458 
1459   // Check to see if the 2nd operand is a constant that we can encode directly
1460   // in the compare.
1461   int Imm = 0;
1462   bool UseImm = false;
1463   bool isNegativeImm = false;
1464   // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1465   // Thus, Src1Value may be a ConstantInt, but we're missing it.
1466   if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
1467     if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1468         SrcVT == MVT::i1) {
1469       const APInt &CIVal = ConstInt->getValue();
1470       Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1471       // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather
1472       // then a cmn, because there is no way to represent 2147483648 as a
1473       // signed 32-bit int.
1474       if (Imm < 0 && Imm != (int)0x80000000) {
1475         isNegativeImm = true;
1476         Imm = -Imm;
1477       }
1478       UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1479         (ARM_AM::getSOImmVal(Imm) != -1);
1480     }
1481   } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
1482     if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1483       if (ConstFP->isZero() && !ConstFP->isNegative())
1484         UseImm = true;
1485   }
1486 
1487   unsigned CmpOpc;
1488   bool isICmp = true;
1489   bool needsExt = false;
1490   switch (SrcVT.SimpleTy) {
1491     default: return false;
1492     // TODO: Verify compares.
1493     case MVT::f32:
1494       isICmp = false;
1495       CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
1496       break;
1497     case MVT::f64:
1498       isICmp = false;
1499       CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
1500       break;
1501     case MVT::i1:
1502     case MVT::i8:
1503     case MVT::i16:
1504       needsExt = true;
1505     // Intentional fall-through.
1506     case MVT::i32:
1507       if (isThumb2) {
1508         if (!UseImm)
1509           CmpOpc = ARM::t2CMPrr;
1510         else
1511           CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
1512       } else {
1513         if (!UseImm)
1514           CmpOpc = ARM::CMPrr;
1515         else
1516           CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
1517       }
1518       break;
1519   }
1520 
1521   unsigned SrcReg1 = getRegForValue(Src1Value);
1522   if (SrcReg1 == 0) return false;
1523 
1524   unsigned SrcReg2 = 0;
1525   if (!UseImm) {
1526     SrcReg2 = getRegForValue(Src2Value);
1527     if (SrcReg2 == 0) return false;
1528   }
1529 
1530   // We have i1, i8, or i16, we need to either zero extend or sign extend.
1531   if (needsExt) {
1532     SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1533     if (SrcReg1 == 0) return false;
1534     if (!UseImm) {
1535       SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1536       if (SrcReg2 == 0) return false;
1537     }
1538   }
1539 
1540   const MCInstrDesc &II = TII.get(CmpOpc);
1541   SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);
1542   if (!UseImm) {
1543     SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
1544     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1545                     .addReg(SrcReg1).addReg(SrcReg2));
1546   } else {
1547     MachineInstrBuilder MIB;
1548     MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1549       .addReg(SrcReg1);
1550 
1551     // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1552     if (isICmp)
1553       MIB.addImm(Imm);
1554     AddOptionalDefs(MIB);
1555   }
1556 
1557   // For floating point we need to move the result to a comparison register
1558   // that we can then use for branches.
1559   if (Ty->isFloatTy() || Ty->isDoubleTy())
1560     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1561                             TII.get(ARM::FMSTAT)));
1562   return true;
1563 }
1564 
1565 bool ARMFastISel::SelectCmp(const Instruction *I) {
1566   const CmpInst *CI = cast<CmpInst>(I);
1567 
1568   // Get the compare predicate.
1569   ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1570 
1571   // We may not handle every CC for now.
1572   if (ARMPred == ARMCC::AL) return false;
1573 
1574   // Emit the compare.
1575   if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1576     return false;
1577 
1578   // Now set a register based on the comparison. Explicitly set the predicates
1579   // here.
1580   unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1581   const TargetRegisterClass *RC = isThumb2 ?
1582     (const TargetRegisterClass*)&ARM::rGPRRegClass :
1583     (const TargetRegisterClass*)&ARM::GPRRegClass;
1584   unsigned DestReg = createResultReg(RC);
1585   Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1586   unsigned ZeroReg = TargetMaterializeConstant(Zero);
1587   // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
1588   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1589           .addReg(ZeroReg).addImm(1)
1590           .addImm(ARMPred).addReg(ARM::CPSR);
1591 
1592   UpdateValueMap(I, DestReg);
1593   return true;
1594 }
1595 
1596 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1597   // Make sure we have VFP and that we're extending float to double.
1598   if (!Subtarget->hasVFP2()) return false;
1599 
1600   Value *V = I->getOperand(0);
1601   if (!I->getType()->isDoubleTy() ||
1602       !V->getType()->isFloatTy()) return false;
1603 
1604   unsigned Op = getRegForValue(V);
1605   if (Op == 0) return false;
1606 
1607   unsigned Result = createResultReg(&ARM::DPRRegClass);
1608   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1609                           TII.get(ARM::VCVTDS), Result)
1610                   .addReg(Op));
1611   UpdateValueMap(I, Result);
1612   return true;
1613 }
1614 
1615 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1616   // Make sure we have VFP and that we're truncating double to float.
1617   if (!Subtarget->hasVFP2()) return false;
1618 
1619   Value *V = I->getOperand(0);
1620   if (!(I->getType()->isFloatTy() &&
1621         V->getType()->isDoubleTy())) return false;
1622 
1623   unsigned Op = getRegForValue(V);
1624   if (Op == 0) return false;
1625 
1626   unsigned Result = createResultReg(&ARM::SPRRegClass);
1627   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1628                           TII.get(ARM::VCVTSD), Result)
1629                   .addReg(Op));
1630   UpdateValueMap(I, Result);
1631   return true;
1632 }
1633 
1634 bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
1635   // Make sure we have VFP.
1636   if (!Subtarget->hasVFP2()) return false;
1637 
1638   MVT DstVT;
1639   Type *Ty = I->getType();
1640   if (!isTypeLegal(Ty, DstVT))
1641     return false;
1642 
1643   Value *Src = I->getOperand(0);
1644   EVT SrcEVT = TLI.getValueType(Src->getType(), true);
1645   if (!SrcEVT.isSimple())
1646     return false;
1647   MVT SrcVT = SrcEVT.getSimpleVT();
1648   if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1649     return false;
1650 
1651   unsigned SrcReg = getRegForValue(Src);
1652   if (SrcReg == 0) return false;
1653 
1654   // Handle sign-extension.
1655   if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1656     SrcReg = ARMEmitIntExt(SrcVT, SrcReg, MVT::i32,
1657                                        /*isZExt*/!isSigned);
1658     if (SrcReg == 0) return false;
1659   }
1660 
1661   // The conversion routine works on fp-reg to fp-reg and the operand above
1662   // was an integer, move it to the fp registers if possible.
1663   unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1664   if (FP == 0) return false;
1665 
1666   unsigned Opc;
1667   if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1668   else if (Ty->isDoubleTy()) Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1669   else return false;
1670 
1671   unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1672   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1673                           ResultReg)
1674                   .addReg(FP));
1675   UpdateValueMap(I, ResultReg);
1676   return true;
1677 }
1678 
1679 bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
1680   // Make sure we have VFP.
1681   if (!Subtarget->hasVFP2()) return false;
1682 
1683   MVT DstVT;
1684   Type *RetTy = I->getType();
1685   if (!isTypeLegal(RetTy, DstVT))
1686     return false;
1687 
1688   unsigned Op = getRegForValue(I->getOperand(0));
1689   if (Op == 0) return false;
1690 
1691   unsigned Opc;
1692   Type *OpTy = I->getOperand(0)->getType();
1693   if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1694   else if (OpTy->isDoubleTy()) Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1695   else return false;
1696 
1697   // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
1698   unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1699   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1700                           ResultReg)
1701                   .addReg(Op));
1702 
1703   // This result needs to be in an integer register, but the conversion only
1704   // takes place in fp-regs.
1705   unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1706   if (IntReg == 0) return false;
1707 
1708   UpdateValueMap(I, IntReg);
1709   return true;
1710 }
1711 
1712 bool ARMFastISel::SelectSelect(const Instruction *I) {
1713   MVT VT;
1714   if (!isTypeLegal(I->getType(), VT))
1715     return false;
1716 
1717   // Things need to be register sized for register moves.
1718   if (VT != MVT::i32) return false;
1719 
1720   unsigned CondReg = getRegForValue(I->getOperand(0));
1721   if (CondReg == 0) return false;
1722   unsigned Op1Reg = getRegForValue(I->getOperand(1));
1723   if (Op1Reg == 0) return false;
1724 
1725   // Check to see if we can use an immediate in the conditional move.
1726   int Imm = 0;
1727   bool UseImm = false;
1728   bool isNegativeImm = false;
1729   if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) {
1730     assert (VT == MVT::i32 && "Expecting an i32.");
1731     Imm = (int)ConstInt->getValue().getZExtValue();
1732     if (Imm < 0) {
1733       isNegativeImm = true;
1734       Imm = ~Imm;
1735     }
1736     UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1737       (ARM_AM::getSOImmVal(Imm) != -1);
1738   }
1739 
1740   unsigned Op2Reg = 0;
1741   if (!UseImm) {
1742     Op2Reg = getRegForValue(I->getOperand(2));
1743     if (Op2Reg == 0) return false;
1744   }
1745 
1746   unsigned CmpOpc = isThumb2 ? ARM::t2CMPri : ARM::CMPri;
1747   CondReg = constrainOperandRegClass(TII.get(CmpOpc), CondReg, 0);
1748   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1749                   .addReg(CondReg).addImm(0));
1750 
1751   unsigned MovCCOpc;
1752   const TargetRegisterClass *RC;
1753   if (!UseImm) {
1754     RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
1755     MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1756   } else {
1757     RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
1758     if (!isNegativeImm)
1759       MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1760     else
1761       MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1762   }
1763   unsigned ResultReg = createResultReg(RC);
1764   if (!UseImm) {
1765     Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);
1766     Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2);
1767     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1768     .addReg(Op2Reg).addReg(Op1Reg).addImm(ARMCC::NE).addReg(ARM::CPSR);
1769   } else {
1770     Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);
1771     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1772     .addReg(Op1Reg).addImm(Imm).addImm(ARMCC::EQ).addReg(ARM::CPSR);
1773   }
1774   UpdateValueMap(I, ResultReg);
1775   return true;
1776 }
1777 
1778 bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
1779   MVT VT;
1780   Type *Ty = I->getType();
1781   if (!isTypeLegal(Ty, VT))
1782     return false;
1783 
1784   // If we have integer div support we should have selected this automagically.
1785   // In case we have a real miss go ahead and return false and we'll pick
1786   // it up later.
1787   if (Subtarget->hasDivide()) return false;
1788 
1789   // Otherwise emit a libcall.
1790   RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1791   if (VT == MVT::i8)
1792     LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8;
1793   else if (VT == MVT::i16)
1794     LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16;
1795   else if (VT == MVT::i32)
1796     LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32;
1797   else if (VT == MVT::i64)
1798     LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64;
1799   else if (VT == MVT::i128)
1800     LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128;
1801   assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1802 
1803   return ARMEmitLibcall(I, LC);
1804 }
1805 
1806 bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
1807   MVT VT;
1808   Type *Ty = I->getType();
1809   if (!isTypeLegal(Ty, VT))
1810     return false;
1811 
1812   RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1813   if (VT == MVT::i8)
1814     LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8;
1815   else if (VT == MVT::i16)
1816     LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16;
1817   else if (VT == MVT::i32)
1818     LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32;
1819   else if (VT == MVT::i64)
1820     LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64;
1821   else if (VT == MVT::i128)
1822     LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128;
1823   assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1824 
1825   return ARMEmitLibcall(I, LC);
1826 }
1827 
1828 bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1829   EVT DestVT  = TLI.getValueType(I->getType(), true);
1830 
1831   // We can get here in the case when we have a binary operation on a non-legal
1832   // type and the target independent selector doesn't know how to handle it.
1833   if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1834     return false;
1835 
1836   unsigned Opc;
1837   switch (ISDOpcode) {
1838     default: return false;
1839     case ISD::ADD:
1840       Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1841       break;
1842     case ISD::OR:
1843       Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1844       break;
1845     case ISD::SUB:
1846       Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1847       break;
1848   }
1849 
1850   unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1851   if (SrcReg1 == 0) return false;
1852 
1853   // TODO: Often the 2nd operand is an immediate, which can be encoded directly
1854   // in the instruction, rather then materializing the value in a register.
1855   unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1856   if (SrcReg2 == 0) return false;
1857 
1858   unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
1859   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1860                           TII.get(Opc), ResultReg)
1861                   .addReg(SrcReg1).addReg(SrcReg2));
1862   UpdateValueMap(I, ResultReg);
1863   return true;
1864 }
1865 
1866 bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
1867   EVT FPVT = TLI.getValueType(I->getType(), true);
1868   if (!FPVT.isSimple()) return false;
1869   MVT VT = FPVT.getSimpleVT();
1870 
1871   // We can get here in the case when we want to use NEON for our fp
1872   // operations, but can't figure out how to. Just use the vfp instructions
1873   // if we have them.
1874   // FIXME: It'd be nice to use NEON instructions.
1875   Type *Ty = I->getType();
1876   bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1877   if (isFloat && !Subtarget->hasVFP2())
1878     return false;
1879 
1880   unsigned Opc;
1881   bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1882   switch (ISDOpcode) {
1883     default: return false;
1884     case ISD::FADD:
1885       Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1886       break;
1887     case ISD::FSUB:
1888       Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1889       break;
1890     case ISD::FMUL:
1891       Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1892       break;
1893   }
1894   unsigned Op1 = getRegForValue(I->getOperand(0));
1895   if (Op1 == 0) return false;
1896 
1897   unsigned Op2 = getRegForValue(I->getOperand(1));
1898   if (Op2 == 0) return false;
1899 
1900   unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
1901   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1902                           TII.get(Opc), ResultReg)
1903                   .addReg(Op1).addReg(Op2));
1904   UpdateValueMap(I, ResultReg);
1905   return true;
1906 }
1907 
1908 // Call Handling Code
1909 
1910 // This is largely taken directly from CCAssignFnForNode
1911 // TODO: We may not support all of this.
1912 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
1913                                            bool Return,
1914                                            bool isVarArg) {
1915   switch (CC) {
1916   default:
1917     llvm_unreachable("Unsupported calling convention");
1918   case CallingConv::Fast:
1919     if (Subtarget->hasVFP2() && !isVarArg) {
1920       if (!Subtarget->isAAPCS_ABI())
1921         return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1922       // For AAPCS ABI targets, just use VFP variant of the calling convention.
1923       return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1924     }
1925     // Fallthrough
1926   case CallingConv::C:
1927     // Use target triple & subtarget features to do actual dispatch.
1928     if (Subtarget->isAAPCS_ABI()) {
1929       if (Subtarget->hasVFP2() &&
1930           TM.Options.FloatABIType == FloatABI::Hard && !isVarArg)
1931         return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1932       else
1933         return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1934     } else
1935         return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1936   case CallingConv::ARM_AAPCS_VFP:
1937     if (!isVarArg)
1938       return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1939     // Fall through to soft float variant, variadic functions don't
1940     // use hard floating point ABI.
1941   case CallingConv::ARM_AAPCS:
1942     return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1943   case CallingConv::ARM_APCS:
1944     return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1945   case CallingConv::GHC:
1946     if (Return)
1947       llvm_unreachable("Can't return in GHC call convention");
1948     else
1949       return CC_ARM_APCS_GHC;
1950   }
1951 }
1952 
1953 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1954                                   SmallVectorImpl<unsigned> &ArgRegs,
1955                                   SmallVectorImpl<MVT> &ArgVTs,
1956                                   SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1957                                   SmallVectorImpl<unsigned> &RegArgs,
1958                                   CallingConv::ID CC,
1959                                   unsigned &NumBytes,
1960                                   bool isVarArg) {
1961   SmallVector<CCValAssign, 16> ArgLocs;
1962   CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, ArgLocs, *Context);
1963   CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags,
1964                              CCAssignFnForCall(CC, false, isVarArg));
1965 
1966   // Check that we can handle all of the arguments. If we can't, then bail out
1967   // now before we add code to the MBB.
1968   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1969     CCValAssign &VA = ArgLocs[i];
1970     MVT ArgVT = ArgVTs[VA.getValNo()];
1971 
1972     // We don't handle NEON/vector parameters yet.
1973     if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1974       return false;
1975 
1976     // Now copy/store arg to correct locations.
1977     if (VA.isRegLoc() && !VA.needsCustom()) {
1978       continue;
1979     } else if (VA.needsCustom()) {
1980       // TODO: We need custom lowering for vector (v2f64) args.
1981       if (VA.getLocVT() != MVT::f64 ||
1982           // TODO: Only handle register args for now.
1983           !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1984         return false;
1985     } else {
1986       switch (ArgVT.SimpleTy) {
1987       default:
1988         return false;
1989       case MVT::i1:
1990       case MVT::i8:
1991       case MVT::i16:
1992       case MVT::i32:
1993         break;
1994       case MVT::f32:
1995         if (!Subtarget->hasVFP2())
1996           return false;
1997         break;
1998       case MVT::f64:
1999         if (!Subtarget->hasVFP2())
2000           return false;
2001         break;
2002       }
2003     }
2004   }
2005 
2006   // At the point, we are able to handle the call's arguments in fast isel.
2007 
2008   // Get a count of how many bytes are to be pushed on the stack.
2009   NumBytes = CCInfo.getNextStackOffset();
2010 
2011   // Issue CALLSEQ_START
2012   unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
2013   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2014                           TII.get(AdjStackDown))
2015                   .addImm(NumBytes));
2016 
2017   // Process the args.
2018   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2019     CCValAssign &VA = ArgLocs[i];
2020     unsigned Arg = ArgRegs[VA.getValNo()];
2021     MVT ArgVT = ArgVTs[VA.getValNo()];
2022 
2023     assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) &&
2024            "We don't handle NEON/vector parameters yet.");
2025 
2026     // Handle arg promotion, etc.
2027     switch (VA.getLocInfo()) {
2028       case CCValAssign::Full: break;
2029       case CCValAssign::SExt: {
2030         MVT DestVT = VA.getLocVT();
2031         Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
2032         assert (Arg != 0 && "Failed to emit a sext");
2033         ArgVT = DestVT;
2034         break;
2035       }
2036       case CCValAssign::AExt:
2037         // Intentional fall-through.  Handle AExt and ZExt.
2038       case CCValAssign::ZExt: {
2039         MVT DestVT = VA.getLocVT();
2040         Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
2041         assert (Arg != 0 && "Failed to emit a zext");
2042         ArgVT = DestVT;
2043         break;
2044       }
2045       case CCValAssign::BCvt: {
2046         unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
2047                                  /*TODO: Kill=*/false);
2048         assert(BC != 0 && "Failed to emit a bitcast!");
2049         Arg = BC;
2050         ArgVT = VA.getLocVT();
2051         break;
2052       }
2053       default: llvm_unreachable("Unknown arg promotion!");
2054     }
2055 
2056     // Now copy/store arg to correct locations.
2057     if (VA.isRegLoc() && !VA.needsCustom()) {
2058       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2059               VA.getLocReg())
2060         .addReg(Arg);
2061       RegArgs.push_back(VA.getLocReg());
2062     } else if (VA.needsCustom()) {
2063       // TODO: We need custom lowering for vector (v2f64) args.
2064       assert(VA.getLocVT() == MVT::f64 &&
2065              "Custom lowering for v2f64 args not available");
2066 
2067       CCValAssign &NextVA = ArgLocs[++i];
2068 
2069       assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2070              "We only handle register args!");
2071 
2072       AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2073                               TII.get(ARM::VMOVRRD), VA.getLocReg())
2074                       .addReg(NextVA.getLocReg(), RegState::Define)
2075                       .addReg(Arg));
2076       RegArgs.push_back(VA.getLocReg());
2077       RegArgs.push_back(NextVA.getLocReg());
2078     } else {
2079       assert(VA.isMemLoc());
2080       // Need to store on the stack.
2081       Address Addr;
2082       Addr.BaseType = Address::RegBase;
2083       Addr.Base.Reg = ARM::SP;
2084       Addr.Offset = VA.getLocMemOffset();
2085 
2086       bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
2087       assert(EmitRet && "Could not emit a store for argument!");
2088     }
2089   }
2090 
2091   return true;
2092 }
2093 
2094 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2095                              const Instruction *I, CallingConv::ID CC,
2096                              unsigned &NumBytes, bool isVarArg) {
2097   // Issue CALLSEQ_END
2098   unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2099   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2100                           TII.get(AdjStackUp))
2101                   .addImm(NumBytes).addImm(0));
2102 
2103   // Now the return value.
2104   if (RetVT != MVT::isVoid) {
2105     SmallVector<CCValAssign, 16> RVLocs;
2106     CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
2107     CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2108 
2109     // Copy all of the result registers out of their specified physreg.
2110     if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2111       // For this move we copy into two registers and then move into the
2112       // double fp reg we want.
2113       MVT DestVT = RVLocs[0].getValVT();
2114       const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
2115       unsigned ResultReg = createResultReg(DstRC);
2116       AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2117                               TII.get(ARM::VMOVDRR), ResultReg)
2118                       .addReg(RVLocs[0].getLocReg())
2119                       .addReg(RVLocs[1].getLocReg()));
2120 
2121       UsedRegs.push_back(RVLocs[0].getLocReg());
2122       UsedRegs.push_back(RVLocs[1].getLocReg());
2123 
2124       // Finally update the result.
2125       UpdateValueMap(I, ResultReg);
2126     } else {
2127       assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2128       MVT CopyVT = RVLocs[0].getValVT();
2129 
2130       // Special handling for extended integers.
2131       if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2132         CopyVT = MVT::i32;
2133 
2134       const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
2135 
2136       unsigned ResultReg = createResultReg(DstRC);
2137       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2138               ResultReg).addReg(RVLocs[0].getLocReg());
2139       UsedRegs.push_back(RVLocs[0].getLocReg());
2140 
2141       // Finally update the result.
2142       UpdateValueMap(I, ResultReg);
2143     }
2144   }
2145 
2146   return true;
2147 }
2148 
2149 bool ARMFastISel::SelectRet(const Instruction *I) {
2150   const ReturnInst *Ret = cast<ReturnInst>(I);
2151   const Function &F = *I->getParent()->getParent();
2152 
2153   if (!FuncInfo.CanLowerReturn)
2154     return false;
2155 
2156   // Build a list of return value registers.
2157   SmallVector<unsigned, 4> RetRegs;
2158 
2159   CallingConv::ID CC = F.getCallingConv();
2160   if (Ret->getNumOperands() > 0) {
2161     SmallVector<ISD::OutputArg, 4> Outs;
2162     GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
2163 
2164     // Analyze operands of the call, assigning locations to each operand.
2165     SmallVector<CCValAssign, 16> ValLocs;
2166     CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,I->getContext());
2167     CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
2168                                                  F.isVarArg()));
2169 
2170     const Value *RV = Ret->getOperand(0);
2171     unsigned Reg = getRegForValue(RV);
2172     if (Reg == 0)
2173       return false;
2174 
2175     // Only handle a single return value for now.
2176     if (ValLocs.size() != 1)
2177       return false;
2178 
2179     CCValAssign &VA = ValLocs[0];
2180 
2181     // Don't bother handling odd stuff for now.
2182     if (VA.getLocInfo() != CCValAssign::Full)
2183       return false;
2184     // Only handle register returns for now.
2185     if (!VA.isRegLoc())
2186       return false;
2187 
2188     unsigned SrcReg = Reg + VA.getValNo();
2189     EVT RVEVT = TLI.getValueType(RV->getType());
2190     if (!RVEVT.isSimple()) return false;
2191     MVT RVVT = RVEVT.getSimpleVT();
2192     MVT DestVT = VA.getValVT();
2193     // Special handling for extended integers.
2194     if (RVVT != DestVT) {
2195       if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
2196         return false;
2197 
2198       assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2199 
2200       // Perform extension if flagged as either zext or sext.  Otherwise, do
2201       // nothing.
2202       if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2203         SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
2204         if (SrcReg == 0) return false;
2205       }
2206     }
2207 
2208     // Make the copy.
2209     unsigned DstReg = VA.getLocReg();
2210     const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
2211     // Avoid a cross-class copy. This is very unlikely.
2212     if (!SrcRC->contains(DstReg))
2213       return false;
2214     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2215             DstReg).addReg(SrcReg);
2216 
2217     // Add register to return instruction.
2218     RetRegs.push_back(VA.getLocReg());
2219   }
2220 
2221   unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
2222   MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2223                                     TII.get(RetOpc));
2224   AddOptionalDefs(MIB);
2225   for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
2226     MIB.addReg(RetRegs[i], RegState::Implicit);
2227   return true;
2228 }
2229 
2230 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
2231   if (UseReg)
2232     return isThumb2 ? ARM::tBLXr : ARM::BLX;
2233   else
2234     return isThumb2 ? ARM::tBL : ARM::BL;
2235 }
2236 
2237 unsigned ARMFastISel::getLibcallReg(const Twine &Name) {
2238   // Manually compute the global's type to avoid building it when unnecessary.
2239   Type *GVTy = Type::getInt32PtrTy(*Context, /*AS=*/0);
2240   EVT LCREVT = TLI.getValueType(GVTy);
2241   if (!LCREVT.isSimple()) return 0;
2242 
2243   GlobalValue *GV = new GlobalVariable(Type::getInt32Ty(*Context), false,
2244                                        GlobalValue::ExternalLinkage, 0, Name);
2245   assert(GV->getType() == GVTy && "We miscomputed the type for the global!");
2246   return ARMMaterializeGV(GV, LCREVT.getSimpleVT());
2247 }
2248 
2249 // A quick function that will emit a call for a named libcall in F with the
2250 // vector of passed arguments for the Instruction in I. We can assume that we
2251 // can emit a call for any libcall we can produce. This is an abridged version
2252 // of the full call infrastructure since we won't need to worry about things
2253 // like computed function pointers or strange arguments at call sites.
2254 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
2255 // with X86.
2256 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2257   CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
2258 
2259   // Handle *simple* calls for now.
2260   Type *RetTy = I->getType();
2261   MVT RetVT;
2262   if (RetTy->isVoidTy())
2263     RetVT = MVT::isVoid;
2264   else if (!isTypeLegal(RetTy, RetVT))
2265     return false;
2266 
2267   // Can't handle non-double multi-reg retvals.
2268   if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
2269     SmallVector<CCValAssign, 16> RVLocs;
2270     CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
2271     CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
2272     if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2273       return false;
2274   }
2275 
2276   // Set up the argument vectors.
2277   SmallVector<Value*, 8> Args;
2278   SmallVector<unsigned, 8> ArgRegs;
2279   SmallVector<MVT, 8> ArgVTs;
2280   SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2281   Args.reserve(I->getNumOperands());
2282   ArgRegs.reserve(I->getNumOperands());
2283   ArgVTs.reserve(I->getNumOperands());
2284   ArgFlags.reserve(I->getNumOperands());
2285   for (unsigned i = 0; i < I->getNumOperands(); ++i) {
2286     Value *Op = I->getOperand(i);
2287     unsigned Arg = getRegForValue(Op);
2288     if (Arg == 0) return false;
2289 
2290     Type *ArgTy = Op->getType();
2291     MVT ArgVT;
2292     if (!isTypeLegal(ArgTy, ArgVT)) return false;
2293 
2294     ISD::ArgFlagsTy Flags;
2295     unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2296     Flags.setOrigAlign(OriginalAlignment);
2297 
2298     Args.push_back(Op);
2299     ArgRegs.push_back(Arg);
2300     ArgVTs.push_back(ArgVT);
2301     ArgFlags.push_back(Flags);
2302   }
2303 
2304   // Handle the arguments now that we've gotten them.
2305   SmallVector<unsigned, 4> RegArgs;
2306   unsigned NumBytes;
2307   if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2308                        RegArgs, CC, NumBytes, false))
2309     return false;
2310 
2311   unsigned CalleeReg = 0;
2312   if (EnableARMLongCalls) {
2313     CalleeReg = getLibcallReg(TLI.getLibcallName(Call));
2314     if (CalleeReg == 0) return false;
2315   }
2316 
2317   // Issue the call.
2318   unsigned CallOpc = ARMSelectCallOp(EnableARMLongCalls);
2319   MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2320                                     DL, TII.get(CallOpc));
2321   // BL / BLX don't take a predicate, but tBL / tBLX do.
2322   if (isThumb2)
2323     AddDefaultPred(MIB);
2324   if (EnableARMLongCalls)
2325     MIB.addReg(CalleeReg);
2326   else
2327     MIB.addExternalSymbol(TLI.getLibcallName(Call));
2328 
2329   // Add implicit physical register uses to the call.
2330   for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2331     MIB.addReg(RegArgs[i], RegState::Implicit);
2332 
2333   // Add a register mask with the call-preserved registers.
2334   // Proper defs for return values will be added by setPhysRegsDeadExcept().
2335   MIB.addRegMask(TRI.getCallPreservedMask(CC));
2336 
2337   // Finish off the call including any return values.
2338   SmallVector<unsigned, 4> UsedRegs;
2339   if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false;
2340 
2341   // Set all unused physreg defs as dead.
2342   static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2343 
2344   return true;
2345 }
2346 
2347 bool ARMFastISel::SelectCall(const Instruction *I,
2348                              const char *IntrMemName = 0) {
2349   const CallInst *CI = cast<CallInst>(I);
2350   const Value *Callee = CI->getCalledValue();
2351 
2352   // Can't handle inline asm.
2353   if (isa<InlineAsm>(Callee)) return false;
2354 
2355   // Allow SelectionDAG isel to handle tail calls.
2356   if (CI->isTailCall()) return false;
2357 
2358   // Check the calling convention.
2359   ImmutableCallSite CS(CI);
2360   CallingConv::ID CC = CS.getCallingConv();
2361 
2362   // TODO: Avoid some calling conventions?
2363 
2364   PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
2365   FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2366   bool isVarArg = FTy->isVarArg();
2367 
2368   // Handle *simple* calls for now.
2369   Type *RetTy = I->getType();
2370   MVT RetVT;
2371   if (RetTy->isVoidTy())
2372     RetVT = MVT::isVoid;
2373   else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2374            RetVT != MVT::i8  && RetVT != MVT::i1)
2375     return false;
2376 
2377   // Can't handle non-double multi-reg retvals.
2378   if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
2379       RetVT != MVT::i16 && RetVT != MVT::i32) {
2380     SmallVector<CCValAssign, 16> RVLocs;
2381     CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
2382     CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2383     if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2384       return false;
2385   }
2386 
2387   // Set up the argument vectors.
2388   SmallVector<Value*, 8> Args;
2389   SmallVector<unsigned, 8> ArgRegs;
2390   SmallVector<MVT, 8> ArgVTs;
2391   SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2392   unsigned arg_size = CS.arg_size();
2393   Args.reserve(arg_size);
2394   ArgRegs.reserve(arg_size);
2395   ArgVTs.reserve(arg_size);
2396   ArgFlags.reserve(arg_size);
2397   for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2398        i != e; ++i) {
2399     // If we're lowering a memory intrinsic instead of a regular call, skip the
2400     // last two arguments, which shouldn't be passed to the underlying function.
2401     if (IntrMemName && e-i <= 2)
2402       break;
2403 
2404     ISD::ArgFlagsTy Flags;
2405     unsigned AttrInd = i - CS.arg_begin() + 1;
2406     if (CS.paramHasAttr(AttrInd, Attribute::SExt))
2407       Flags.setSExt();
2408     if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
2409       Flags.setZExt();
2410 
2411     // FIXME: Only handle *easy* calls for now.
2412     if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
2413         CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
2414         CS.paramHasAttr(AttrInd, Attribute::Nest) ||
2415         CS.paramHasAttr(AttrInd, Attribute::ByVal))
2416       return false;
2417 
2418     Type *ArgTy = (*i)->getType();
2419     MVT ArgVT;
2420     if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
2421         ArgVT != MVT::i1)
2422       return false;
2423 
2424     unsigned Arg = getRegForValue(*i);
2425     if (Arg == 0)
2426       return false;
2427 
2428     unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2429     Flags.setOrigAlign(OriginalAlignment);
2430 
2431     Args.push_back(*i);
2432     ArgRegs.push_back(Arg);
2433     ArgVTs.push_back(ArgVT);
2434     ArgFlags.push_back(Flags);
2435   }
2436 
2437   // Handle the arguments now that we've gotten them.
2438   SmallVector<unsigned, 4> RegArgs;
2439   unsigned NumBytes;
2440   if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2441                        RegArgs, CC, NumBytes, isVarArg))
2442     return false;
2443 
2444   bool UseReg = false;
2445   const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
2446   if (!GV || EnableARMLongCalls) UseReg = true;
2447 
2448   unsigned CalleeReg = 0;
2449   if (UseReg) {
2450     if (IntrMemName)
2451       CalleeReg = getLibcallReg(IntrMemName);
2452     else
2453       CalleeReg = getRegForValue(Callee);
2454 
2455     if (CalleeReg == 0) return false;
2456   }
2457 
2458   // Issue the call.
2459   unsigned CallOpc = ARMSelectCallOp(UseReg);
2460   MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2461                                     DL, TII.get(CallOpc));
2462 
2463   // ARM calls don't take a predicate, but tBL / tBLX do.
2464   if(isThumb2)
2465     AddDefaultPred(MIB);
2466   if (UseReg)
2467     MIB.addReg(CalleeReg);
2468   else if (!IntrMemName)
2469     MIB.addGlobalAddress(GV, 0, 0);
2470   else
2471     MIB.addExternalSymbol(IntrMemName, 0);
2472 
2473   // Add implicit physical register uses to the call.
2474   for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2475     MIB.addReg(RegArgs[i], RegState::Implicit);
2476 
2477   // Add a register mask with the call-preserved registers.
2478   // Proper defs for return values will be added by setPhysRegsDeadExcept().
2479   MIB.addRegMask(TRI.getCallPreservedMask(CC));
2480 
2481   // Finish off the call including any return values.
2482   SmallVector<unsigned, 4> UsedRegs;
2483   if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
2484     return false;
2485 
2486   // Set all unused physreg defs as dead.
2487   static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2488 
2489   return true;
2490 }
2491 
2492 bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2493   return Len <= 16;
2494 }
2495 
2496 bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src,
2497                                         uint64_t Len, unsigned Alignment) {
2498   // Make sure we don't bloat code by inlining very large memcpy's.
2499   if (!ARMIsMemCpySmall(Len))
2500     return false;
2501 
2502   while (Len) {
2503     MVT VT;
2504     if (!Alignment || Alignment >= 4) {
2505       if (Len >= 4)
2506         VT = MVT::i32;
2507       else if (Len >= 2)
2508         VT = MVT::i16;
2509       else {
2510         assert (Len == 1 && "Expected a length of 1!");
2511         VT = MVT::i8;
2512       }
2513     } else {
2514       // Bound based on alignment.
2515       if (Len >= 2 && Alignment == 2)
2516         VT = MVT::i16;
2517       else {
2518         VT = MVT::i8;
2519       }
2520     }
2521 
2522     bool RV;
2523     unsigned ResultReg;
2524     RV = ARMEmitLoad(VT, ResultReg, Src);
2525     assert (RV == true && "Should be able to handle this load.");
2526     RV = ARMEmitStore(VT, ResultReg, Dest);
2527     assert (RV == true && "Should be able to handle this store.");
2528     (void)RV;
2529 
2530     unsigned Size = VT.getSizeInBits()/8;
2531     Len -= Size;
2532     Dest.Offset += Size;
2533     Src.Offset += Size;
2534   }
2535 
2536   return true;
2537 }
2538 
2539 bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2540   // FIXME: Handle more intrinsics.
2541   switch (I.getIntrinsicID()) {
2542   default: return false;
2543   case Intrinsic::frameaddress: {
2544     MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
2545     MFI->setFrameAddressIsTaken(true);
2546 
2547     unsigned LdrOpc;
2548     const TargetRegisterClass *RC;
2549     if (isThumb2) {
2550       LdrOpc =  ARM::t2LDRi12;
2551       RC = (const TargetRegisterClass*)&ARM::tGPRRegClass;
2552     } else {
2553       LdrOpc =  ARM::LDRi12;
2554       RC = (const TargetRegisterClass*)&ARM::GPRRegClass;
2555     }
2556 
2557     const ARMBaseRegisterInfo *RegInfo =
2558           static_cast<const ARMBaseRegisterInfo*>(TM.getRegisterInfo());
2559     unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
2560     unsigned SrcReg = FramePtr;
2561 
2562     // Recursively load frame address
2563     // ldr r0 [fp]
2564     // ldr r0 [r0]
2565     // ldr r0 [r0]
2566     // ...
2567     unsigned DestReg;
2568     unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue();
2569     while (Depth--) {
2570       DestReg = createResultReg(RC);
2571       AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2572                               TII.get(LdrOpc), DestReg)
2573                       .addReg(SrcReg).addImm(0));
2574       SrcReg = DestReg;
2575     }
2576     UpdateValueMap(&I, SrcReg);
2577     return true;
2578   }
2579   case Intrinsic::memcpy:
2580   case Intrinsic::memmove: {
2581     const MemTransferInst &MTI = cast<MemTransferInst>(I);
2582     // Don't handle volatile.
2583     if (MTI.isVolatile())
2584       return false;
2585 
2586     // Disable inlining for memmove before calls to ComputeAddress.  Otherwise,
2587     // we would emit dead code because we don't currently handle memmoves.
2588     bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2589     if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
2590       // Small memcpy's are common enough that we want to do them without a call
2591       // if possible.
2592       uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
2593       if (ARMIsMemCpySmall(Len)) {
2594         Address Dest, Src;
2595         if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
2596             !ARMComputeAddress(MTI.getRawSource(), Src))
2597           return false;
2598         unsigned Alignment = MTI.getAlignment();
2599         if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment))
2600           return true;
2601       }
2602     }
2603 
2604     if (!MTI.getLength()->getType()->isIntegerTy(32))
2605       return false;
2606 
2607     if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
2608       return false;
2609 
2610     const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
2611     return SelectCall(&I, IntrMemName);
2612   }
2613   case Intrinsic::memset: {
2614     const MemSetInst &MSI = cast<MemSetInst>(I);
2615     // Don't handle volatile.
2616     if (MSI.isVolatile())
2617       return false;
2618 
2619     if (!MSI.getLength()->getType()->isIntegerTy(32))
2620       return false;
2621 
2622     if (MSI.getDestAddressSpace() > 255)
2623       return false;
2624 
2625     return SelectCall(&I, "memset");
2626   }
2627   case Intrinsic::trap: {
2628     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(
2629       Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP));
2630     return true;
2631   }
2632   }
2633 }
2634 
2635 bool ARMFastISel::SelectTrunc(const Instruction *I) {
2636   // The high bits for a type smaller than the register size are assumed to be
2637   // undefined.
2638   Value *Op = I->getOperand(0);
2639 
2640   EVT SrcVT, DestVT;
2641   SrcVT = TLI.getValueType(Op->getType(), true);
2642   DestVT = TLI.getValueType(I->getType(), true);
2643 
2644   if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2645     return false;
2646   if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2647     return false;
2648 
2649   unsigned SrcReg = getRegForValue(Op);
2650   if (!SrcReg) return false;
2651 
2652   // Because the high bits are undefined, a truncate doesn't generate
2653   // any code.
2654   UpdateValueMap(I, SrcReg);
2655   return true;
2656 }
2657 
2658 unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
2659                                     bool isZExt) {
2660   if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2661     return 0;
2662   if (SrcVT != MVT::i16 && SrcVT != MVT::i8 && SrcVT != MVT::i1)
2663     return 0;
2664 
2665   // Table of which combinations can be emitted as a single instruction,
2666   // and which will require two.
2667   static const uint8_t isSingleInstrTbl[3][2][2][2] = {
2668     //            ARM                     Thumb
2669     //           !hasV6Ops  hasV6Ops     !hasV6Ops  hasV6Ops
2670     //    ext:     s  z      s  z          s  z      s  z
2671     /*  1 */ { { { 0, 1 }, { 0, 1 } }, { { 0, 0 }, { 0, 1 } } },
2672     /*  8 */ { { { 0, 1 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } },
2673     /* 16 */ { { { 0, 0 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } }
2674   };
2675 
2676   // Target registers for:
2677   //  - For ARM can never be PC.
2678   //  - For 16-bit Thumb are restricted to lower 8 registers.
2679   //  - For 32-bit Thumb are restricted to non-SP and non-PC.
2680   static const TargetRegisterClass *RCTbl[2][2] = {
2681     // Instructions: Two                     Single
2682     /* ARM      */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass },
2683     /* Thumb    */ { &ARM::tGPRRegClass,    &ARM::rGPRRegClass    }
2684   };
2685 
2686   // Table governing the instruction(s) to be emitted.
2687   static const struct InstructionTable {
2688     uint32_t Opc   : 16;
2689     uint32_t hasS  :  1; // Some instructions have an S bit, always set it to 0.
2690     uint32_t Shift :  7; // For shift operand addressing mode, used by MOVsi.
2691     uint32_t Imm   :  8; // All instructions have either a shift or a mask.
2692   } IT[2][2][3][2] = {
2693     { // Two instructions (first is left shift, second is in this table).
2694       { // ARM                Opc           S  Shift             Imm
2695         /*  1 bit sext */ { { ARM::MOVsi  , 1, ARM_AM::asr     ,  31 },
2696         /*  1 bit zext */   { ARM::MOVsi  , 1, ARM_AM::lsr     ,  31 } },
2697         /*  8 bit sext */ { { ARM::MOVsi  , 1, ARM_AM::asr     ,  24 },
2698         /*  8 bit zext */   { ARM::MOVsi  , 1, ARM_AM::lsr     ,  24 } },
2699         /* 16 bit sext */ { { ARM::MOVsi  , 1, ARM_AM::asr     ,  16 },
2700         /* 16 bit zext */   { ARM::MOVsi  , 1, ARM_AM::lsr     ,  16 } }
2701       },
2702       { // Thumb              Opc           S  Shift             Imm
2703         /*  1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  31 },
2704         /*  1 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  31 } },
2705         /*  8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  24 },
2706         /*  8 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  24 } },
2707         /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  16 },
2708         /* 16 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  16 } }
2709       }
2710     },
2711     { // Single instruction.
2712       { // ARM                Opc           S  Shift             Imm
2713         /*  1 bit sext */ { { ARM::KILL   , 0, ARM_AM::no_shift,   0 },
2714         /*  1 bit zext */   { ARM::ANDri  , 1, ARM_AM::no_shift,   1 } },
2715         /*  8 bit sext */ { { ARM::SXTB   , 0, ARM_AM::no_shift,   0 },
2716         /*  8 bit zext */   { ARM::ANDri  , 1, ARM_AM::no_shift, 255 } },
2717         /* 16 bit sext */ { { ARM::SXTH   , 0, ARM_AM::no_shift,   0 },
2718         /* 16 bit zext */   { ARM::UXTH   , 0, ARM_AM::no_shift,   0 } }
2719       },
2720       { // Thumb              Opc           S  Shift             Imm
2721         /*  1 bit sext */ { { ARM::KILL   , 0, ARM_AM::no_shift,   0 },
2722         /*  1 bit zext */   { ARM::t2ANDri, 1, ARM_AM::no_shift,   1 } },
2723         /*  8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift,   0 },
2724         /*  8 bit zext */   { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
2725         /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift,   0 },
2726         /* 16 bit zext */   { ARM::t2UXTH , 0, ARM_AM::no_shift,   0 } }
2727       }
2728     }
2729   };
2730 
2731   unsigned SrcBits = SrcVT.getSizeInBits();
2732   unsigned DestBits = DestVT.getSizeInBits();
2733   (void) DestBits;
2734   assert((SrcBits < DestBits) && "can only extend to larger types");
2735   assert((DestBits == 32 || DestBits == 16 || DestBits == 8) &&
2736          "other sizes unimplemented");
2737   assert((SrcBits == 16 || SrcBits == 8 || SrcBits == 1) &&
2738          "other sizes unimplemented");
2739 
2740   bool hasV6Ops = Subtarget->hasV6Ops();
2741   unsigned Bitness = SrcBits / 8;  // {1,8,16}=>{0,1,2}
2742   assert((Bitness < 3) && "sanity-check table bounds");
2743 
2744   bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];
2745   const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr];
2746   const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];
2747   unsigned Opc = ITP->Opc;
2748   assert(ARM::KILL != Opc && "Invalid table entry");
2749   unsigned hasS = ITP->hasS;
2750   ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift;
2751   assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2752          "only MOVsi has shift operand addressing mode");
2753   unsigned Imm = ITP->Imm;
2754 
2755   // 16-bit Thumb instructions always set CPSR (unless they're in an IT block).
2756   bool setsCPSR = &ARM::tGPRRegClass == RC;
2757   unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;
2758   unsigned ResultReg;
2759   // MOVsi encodes shift and immediate in shift operand addressing mode.
2760   // The following condition has the same value when emitting two
2761   // instruction sequences: both are shifts.
2762   bool ImmIsSO = (Shift != ARM_AM::no_shift);
2763 
2764   // Either one or two instructions are emitted.
2765   // They're always of the form:
2766   //   dst = in OP imm
2767   // CPSR is set only by 16-bit Thumb instructions.
2768   // Predicate, if any, is AL.
2769   // S bit, if available, is always 0.
2770   // When two are emitted the first's result will feed as the second's input,
2771   // that value is then dead.
2772   unsigned NumInstrsEmitted = isSingleInstr ? 1 : 2;
2773   for (unsigned Instr = 0; Instr != NumInstrsEmitted; ++Instr) {
2774     ResultReg = createResultReg(RC);
2775     bool isLsl = (0 == Instr) && !isSingleInstr;
2776     unsigned Opcode = isLsl ? LSLOpc : Opc;
2777     ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
2778     unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShiftAM, Imm) : Imm;
2779     bool isKill = 1 == Instr;
2780     MachineInstrBuilder MIB = BuildMI(
2781         *FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opcode), ResultReg);
2782     if (setsCPSR)
2783       MIB.addReg(ARM::CPSR, RegState::Define);
2784     SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);
2785     AddDefaultPred(MIB.addReg(SrcReg, isKill * RegState::Kill).addImm(ImmEnc));
2786     if (hasS)
2787       AddDefaultCC(MIB);
2788     // Second instruction consumes the first's result.
2789     SrcReg = ResultReg;
2790   }
2791 
2792   return ResultReg;
2793 }
2794 
2795 bool ARMFastISel::SelectIntExt(const Instruction *I) {
2796   // On ARM, in general, integer casts don't involve legal types; this code
2797   // handles promotable integers.
2798   Type *DestTy = I->getType();
2799   Value *Src = I->getOperand(0);
2800   Type *SrcTy = Src->getType();
2801 
2802   bool isZExt = isa<ZExtInst>(I);
2803   unsigned SrcReg = getRegForValue(Src);
2804   if (!SrcReg) return false;
2805 
2806   EVT SrcEVT, DestEVT;
2807   SrcEVT = TLI.getValueType(SrcTy, true);
2808   DestEVT = TLI.getValueType(DestTy, true);
2809   if (!SrcEVT.isSimple()) return false;
2810   if (!DestEVT.isSimple()) return false;
2811 
2812   MVT SrcVT = SrcEVT.getSimpleVT();
2813   MVT DestVT = DestEVT.getSimpleVT();
2814   unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2815   if (ResultReg == 0) return false;
2816   UpdateValueMap(I, ResultReg);
2817   return true;
2818 }
2819 
2820 bool ARMFastISel::SelectShift(const Instruction *I,
2821                               ARM_AM::ShiftOpc ShiftTy) {
2822   // We handle thumb2 mode by target independent selector
2823   // or SelectionDAG ISel.
2824   if (isThumb2)
2825     return false;
2826 
2827   // Only handle i32 now.
2828   EVT DestVT = TLI.getValueType(I->getType(), true);
2829   if (DestVT != MVT::i32)
2830     return false;
2831 
2832   unsigned Opc = ARM::MOVsr;
2833   unsigned ShiftImm;
2834   Value *Src2Value = I->getOperand(1);
2835   if (const ConstantInt *CI = dyn_cast<ConstantInt>(Src2Value)) {
2836     ShiftImm = CI->getZExtValue();
2837 
2838     // Fall back to selection DAG isel if the shift amount
2839     // is zero or greater than the width of the value type.
2840     if (ShiftImm == 0 || ShiftImm >=32)
2841       return false;
2842 
2843     Opc = ARM::MOVsi;
2844   }
2845 
2846   Value *Src1Value = I->getOperand(0);
2847   unsigned Reg1 = getRegForValue(Src1Value);
2848   if (Reg1 == 0) return false;
2849 
2850   unsigned Reg2 = 0;
2851   if (Opc == ARM::MOVsr) {
2852     Reg2 = getRegForValue(Src2Value);
2853     if (Reg2 == 0) return false;
2854   }
2855 
2856   unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
2857   if(ResultReg == 0) return false;
2858 
2859   MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2860                                     TII.get(Opc), ResultReg)
2861                             .addReg(Reg1);
2862 
2863   if (Opc == ARM::MOVsi)
2864     MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2865   else if (Opc == ARM::MOVsr) {
2866     MIB.addReg(Reg2);
2867     MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2868   }
2869 
2870   AddOptionalDefs(MIB);
2871   UpdateValueMap(I, ResultReg);
2872   return true;
2873 }
2874 
2875 // TODO: SoftFP support.
2876 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
2877 
2878   switch (I->getOpcode()) {
2879     case Instruction::Load:
2880       return SelectLoad(I);
2881     case Instruction::Store:
2882       return SelectStore(I);
2883     case Instruction::Br:
2884       return SelectBranch(I);
2885     case Instruction::IndirectBr:
2886       return SelectIndirectBr(I);
2887     case Instruction::ICmp:
2888     case Instruction::FCmp:
2889       return SelectCmp(I);
2890     case Instruction::FPExt:
2891       return SelectFPExt(I);
2892     case Instruction::FPTrunc:
2893       return SelectFPTrunc(I);
2894     case Instruction::SIToFP:
2895       return SelectIToFP(I, /*isSigned*/ true);
2896     case Instruction::UIToFP:
2897       return SelectIToFP(I, /*isSigned*/ false);
2898     case Instruction::FPToSI:
2899       return SelectFPToI(I, /*isSigned*/ true);
2900     case Instruction::FPToUI:
2901       return SelectFPToI(I, /*isSigned*/ false);
2902     case Instruction::Add:
2903       return SelectBinaryIntOp(I, ISD::ADD);
2904     case Instruction::Or:
2905       return SelectBinaryIntOp(I, ISD::OR);
2906     case Instruction::Sub:
2907       return SelectBinaryIntOp(I, ISD::SUB);
2908     case Instruction::FAdd:
2909       return SelectBinaryFPOp(I, ISD::FADD);
2910     case Instruction::FSub:
2911       return SelectBinaryFPOp(I, ISD::FSUB);
2912     case Instruction::FMul:
2913       return SelectBinaryFPOp(I, ISD::FMUL);
2914     case Instruction::SDiv:
2915       return SelectDiv(I, /*isSigned*/ true);
2916     case Instruction::UDiv:
2917       return SelectDiv(I, /*isSigned*/ false);
2918     case Instruction::SRem:
2919       return SelectRem(I, /*isSigned*/ true);
2920     case Instruction::URem:
2921       return SelectRem(I, /*isSigned*/ false);
2922     case Instruction::Call:
2923       if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
2924         return SelectIntrinsicCall(*II);
2925       return SelectCall(I);
2926     case Instruction::Select:
2927       return SelectSelect(I);
2928     case Instruction::Ret:
2929       return SelectRet(I);
2930     case Instruction::Trunc:
2931       return SelectTrunc(I);
2932     case Instruction::ZExt:
2933     case Instruction::SExt:
2934       return SelectIntExt(I);
2935     case Instruction::Shl:
2936       return SelectShift(I, ARM_AM::lsl);
2937     case Instruction::LShr:
2938       return SelectShift(I, ARM_AM::lsr);
2939     case Instruction::AShr:
2940       return SelectShift(I, ARM_AM::asr);
2941     default: break;
2942   }
2943   return false;
2944 }
2945 
2946 namespace {
2947 // This table describes sign- and zero-extend instructions which can be
2948 // folded into a preceding load. All of these extends have an immediate
2949 // (sometimes a mask and sometimes a shift) that's applied after
2950 // extension.
2951 const struct FoldableLoadExtendsStruct {
2952   uint16_t Opc[2];  // ARM, Thumb.
2953   uint8_t ExpectedImm;
2954   uint8_t isZExt     : 1;
2955   uint8_t ExpectedVT : 7;
2956 } FoldableLoadExtends[] = {
2957   { { ARM::SXTH,  ARM::t2SXTH  },   0, 0, MVT::i16 },
2958   { { ARM::UXTH,  ARM::t2UXTH  },   0, 1, MVT::i16 },
2959   { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8  },
2960   { { ARM::SXTB,  ARM::t2SXTB  },   0, 0, MVT::i8  },
2961   { { ARM::UXTB,  ARM::t2UXTB  },   0, 1, MVT::i8  }
2962 };
2963 }
2964 
2965 /// \brief The specified machine instr operand is a vreg, and that
2966 /// vreg is being provided by the specified load instruction.  If possible,
2967 /// try to fold the load as an operand to the instruction, returning true if
2968 /// successful.
2969 bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2970                                       const LoadInst *LI) {
2971   // Verify we have a legal type before going any further.
2972   MVT VT;
2973   if (!isLoadTypeLegal(LI->getType(), VT))
2974     return false;
2975 
2976   // Combine load followed by zero- or sign-extend.
2977   // ldrb r1, [r0]       ldrb r1, [r0]
2978   // uxtb r2, r1     =>
2979   // mov  r3, r2         mov  r3, r1
2980   if (MI->getNumOperands() < 3 || !MI->getOperand(2).isImm())
2981     return false;
2982   const uint64_t Imm = MI->getOperand(2).getImm();
2983 
2984   bool Found = false;
2985   bool isZExt;
2986   for (unsigned i = 0, e = array_lengthof(FoldableLoadExtends);
2987        i != e; ++i) {
2988     if (FoldableLoadExtends[i].Opc[isThumb2] == MI->getOpcode() &&
2989         (uint64_t)FoldableLoadExtends[i].ExpectedImm == Imm &&
2990         MVT((MVT::SimpleValueType)FoldableLoadExtends[i].ExpectedVT) == VT) {
2991       Found = true;
2992       isZExt = FoldableLoadExtends[i].isZExt;
2993     }
2994   }
2995   if (!Found) return false;
2996 
2997   // See if we can handle this address.
2998   Address Addr;
2999   if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
3000 
3001   unsigned ResultReg = MI->getOperand(0).getReg();
3002   if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
3003     return false;
3004   MI->eraseFromParent();
3005   return true;
3006 }
3007 
3008 unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV,
3009                                      unsigned Align, MVT VT) {
3010   bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
3011   ARMConstantPoolConstant *CPV =
3012     ARMConstantPoolConstant::Create(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
3013   unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
3014 
3015   unsigned Opc;
3016   unsigned DestReg1 = createResultReg(TLI.getRegClassFor(VT));
3017   // Load value.
3018   if (isThumb2) {
3019     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
3020                             TII.get(ARM::t2LDRpci), DestReg1)
3021                     .addConstantPoolIndex(Idx));
3022     Opc = UseGOTOFF ? ARM::t2ADDrr : ARM::t2LDRs;
3023   } else {
3024     // The extra immediate is for addrmode2.
3025     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
3026                             DL, TII.get(ARM::LDRcp), DestReg1)
3027                     .addConstantPoolIndex(Idx).addImm(0));
3028     Opc = UseGOTOFF ? ARM::ADDrr : ARM::LDRrs;
3029   }
3030 
3031   unsigned GlobalBaseReg = AFI->getGlobalBaseReg();
3032   if (GlobalBaseReg == 0) {
3033     GlobalBaseReg = MRI.createVirtualRegister(TLI.getRegClassFor(VT));
3034     AFI->setGlobalBaseReg(GlobalBaseReg);
3035   }
3036 
3037   unsigned DestReg2 = createResultReg(TLI.getRegClassFor(VT));
3038   MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
3039                                     DL, TII.get(Opc), DestReg2)
3040                             .addReg(DestReg1)
3041                             .addReg(GlobalBaseReg);
3042   if (!UseGOTOFF)
3043     MIB.addImm(0);
3044   AddOptionalDefs(MIB);
3045 
3046   return DestReg2;
3047 }
3048 
3049 bool ARMFastISel::FastLowerArguments() {
3050   if (!FuncInfo.CanLowerReturn)
3051     return false;
3052 
3053   const Function *F = FuncInfo.Fn;
3054   if (F->isVarArg())
3055     return false;
3056 
3057   CallingConv::ID CC = F->getCallingConv();
3058   switch (CC) {
3059   default:
3060     return false;
3061   case CallingConv::Fast:
3062   case CallingConv::C:
3063   case CallingConv::ARM_AAPCS_VFP:
3064   case CallingConv::ARM_AAPCS:
3065   case CallingConv::ARM_APCS:
3066     break;
3067   }
3068 
3069   // Only handle simple cases. i.e. Up to 4 i8/i16/i32 scalar arguments
3070   // which are passed in r0 - r3.
3071   unsigned Idx = 1;
3072   for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
3073        I != E; ++I, ++Idx) {
3074     if (Idx > 4)
3075       return false;
3076 
3077     if (F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
3078         F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
3079         F->getAttributes().hasAttribute(Idx, Attribute::ByVal))
3080       return false;
3081 
3082     Type *ArgTy = I->getType();
3083     if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
3084       return false;
3085 
3086     EVT ArgVT = TLI.getValueType(ArgTy);
3087     if (!ArgVT.isSimple()) return false;
3088     switch (ArgVT.getSimpleVT().SimpleTy) {
3089     case MVT::i8:
3090     case MVT::i16:
3091     case MVT::i32:
3092       break;
3093     default:
3094       return false;
3095     }
3096   }
3097 
3098 
3099   static const uint16_t GPRArgRegs[] = {
3100     ARM::R0, ARM::R1, ARM::R2, ARM::R3
3101   };
3102 
3103   const TargetRegisterClass *RC = &ARM::rGPRRegClass;
3104   Idx = 0;
3105   for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
3106        I != E; ++I, ++Idx) {
3107     unsigned SrcReg = GPRArgRegs[Idx];
3108     unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
3109     // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
3110     // Without this, EmitLiveInCopies may eliminate the livein if its only
3111     // use is a bitcast (which isn't turned into an instruction).
3112     unsigned ResultReg = createResultReg(RC);
3113     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
3114             ResultReg).addReg(DstReg, getKillRegState(true));
3115     UpdateValueMap(I, ResultReg);
3116   }
3117 
3118   return true;
3119 }
3120 
3121 namespace llvm {
3122   FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
3123                                 const TargetLibraryInfo *libInfo) {
3124     const TargetMachine &TM = funcInfo.MF->getTarget();
3125 
3126     const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
3127     // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
3128     bool UseFastISel = false;
3129     UseFastISel |= Subtarget->isTargetIOS() && !Subtarget->isThumb1Only();
3130     UseFastISel |= Subtarget->isTargetLinux() && !Subtarget->isThumb();
3131     UseFastISel |= Subtarget->isTargetNaCl() && !Subtarget->isThumb();
3132 
3133     if (UseFastISel) {
3134       // iOS always has a FP for backtracking, force other targets
3135       // to keep their FP when doing FastISel. The emitted code is
3136       // currently superior, and in cases like test-suite's lencod
3137       // FastISel isn't quite correct when FP is eliminated.
3138       TM.Options.NoFramePointerElim = true;
3139       return new ARMFastISel(funcInfo, libInfo);
3140     }
3141     return 0;
3142   }
3143 }
3144