1 //===- llvm/lib/Target/ARM/ARMCallLowering.cpp - Call lowering ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "ARMCallLowering.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMISelLowering.h"
18 #include "ARMSubtarget.h"
19 #include "Utils/ARMBaseInfo.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/Analysis.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
24 #include "llvm/CodeGen/GlobalISel/Utils.h"
25 #include "llvm/CodeGen/LowLevelType.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineOperand.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/TargetRegisterInfo.h"
34 #include "llvm/CodeGen/TargetSubtargetInfo.h"
35 #include "llvm/CodeGen/ValueTypes.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/DataLayout.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/Type.h"
41 #include "llvm/IR/Value.h"
42 #include "llvm/Support/Casting.h"
43 #include "llvm/Support/LowLevelTypeImpl.h"
44 #include "llvm/Support/MachineValueType.h"
45 #include <algorithm>
46 #include <cassert>
47 #include <cstdint>
48 #include <utility>
49 
50 using namespace llvm;
51 
52 ARMCallLowering::ARMCallLowering(const ARMTargetLowering &TLI)
53     : CallLowering(&TLI) {}
54 
55 static bool isSupportedType(const DataLayout &DL, const ARMTargetLowering &TLI,
56                             Type *T) {
57   if (T->isArrayTy())
58     return isSupportedType(DL, TLI, T->getArrayElementType());
59 
60   if (T->isStructTy()) {
61     // For now we only allow homogeneous structs that we can manipulate with
62     // G_MERGE_VALUES and G_UNMERGE_VALUES
63     auto StructT = cast<StructType>(T);
64     for (unsigned i = 1, e = StructT->getNumElements(); i != e; ++i)
65       if (StructT->getElementType(i) != StructT->getElementType(0))
66         return false;
67     return isSupportedType(DL, TLI, StructT->getElementType(0));
68   }
69 
70   EVT VT = TLI.getValueType(DL, T, true);
71   if (!VT.isSimple() || VT.isVector() ||
72       !(VT.isInteger() || VT.isFloatingPoint()))
73     return false;
74 
75   unsigned VTSize = VT.getSimpleVT().getSizeInBits();
76 
77   if (VTSize == 64)
78     // FIXME: Support i64 too
79     return VT.isFloatingPoint();
80 
81   return VTSize == 1 || VTSize == 8 || VTSize == 16 || VTSize == 32;
82 }
83 
84 namespace {
85 
86 /// Helper class for values going out through an ABI boundary (used for handling
87 /// function return values and call parameters).
88 struct ARMOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
89   ARMOutgoingValueHandler(MachineIRBuilder &MIRBuilder,
90                           MachineRegisterInfo &MRI, MachineInstrBuilder &MIB)
91       : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
92 
93   Register getStackAddress(uint64_t Size, int64_t Offset,
94                            MachinePointerInfo &MPO,
95                            ISD::ArgFlagsTy Flags) override {
96     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
97            "Unsupported size");
98 
99     LLT p0 = LLT::pointer(0, 32);
100     LLT s32 = LLT::scalar(32);
101     auto SPReg = MIRBuilder.buildCopy(p0, Register(ARM::SP));
102 
103     auto OffsetReg = MIRBuilder.buildConstant(s32, Offset);
104 
105     auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
106 
107     MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
108     return AddrReg.getReg(0);
109   }
110 
111   void assignValueToReg(Register ValVReg, Register PhysReg,
112                         CCValAssign &VA) override {
113     assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
114     assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
115 
116     assert(VA.getValVT().getSizeInBits() <= 64 && "Unsupported value size");
117     assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size");
118 
119     Register ExtReg = extendRegister(ValVReg, VA);
120     MIRBuilder.buildCopy(PhysReg, ExtReg);
121     MIB.addUse(PhysReg, RegState::Implicit);
122   }
123 
124   void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
125                             MachinePointerInfo &MPO, CCValAssign &VA) override {
126     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
127            "Unsupported size");
128 
129     Register ExtReg = extendRegister(ValVReg, VA);
130     auto MMO = MIRBuilder.getMF().getMachineMemOperand(
131         MPO, MachineMemOperand::MOStore, LLT(VA.getLocVT()), Align(1));
132     MIRBuilder.buildStore(ExtReg, Addr, *MMO);
133   }
134 
135   unsigned assignCustomValue(const CallLowering::ArgInfo &Arg,
136                              ArrayRef<CCValAssign> VAs) override {
137     assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
138 
139     CCValAssign VA = VAs[0];
140     assert(VA.needsCustom() && "Value doesn't need custom handling");
141 
142     // Custom lowering for other types, such as f16, is currently not supported
143     if (VA.getValVT() != MVT::f64)
144       return 0;
145 
146     CCValAssign NextVA = VAs[1];
147     assert(NextVA.needsCustom() && "Value doesn't need custom handling");
148     assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
149 
150     assert(VA.getValNo() == NextVA.getValNo() &&
151            "Values belong to different arguments");
152 
153     assert(VA.isRegLoc() && "Value should be in reg");
154     assert(NextVA.isRegLoc() && "Value should be in reg");
155 
156     Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
157                           MRI.createGenericVirtualRegister(LLT::scalar(32))};
158     MIRBuilder.buildUnmerge(NewRegs, Arg.Regs[0]);
159 
160     bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
161     if (!IsLittle)
162       std::swap(NewRegs[0], NewRegs[1]);
163 
164     assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
165     assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
166 
167     return 1;
168   }
169 
170   MachineInstrBuilder MIB;
171 };
172 
173 } // end anonymous namespace
174 
175 /// Lower the return value for the already existing \p Ret. This assumes that
176 /// \p MIRBuilder's insertion point is correct.
177 bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
178                                      const Value *Val, ArrayRef<Register> VRegs,
179                                      MachineInstrBuilder &Ret) const {
180   if (!Val)
181     // Nothing to do here.
182     return true;
183 
184   auto &MF = MIRBuilder.getMF();
185   const auto &F = MF.getFunction();
186 
187   const auto &DL = MF.getDataLayout();
188   auto &TLI = *getTLI<ARMTargetLowering>();
189   if (!isSupportedType(DL, TLI, Val->getType()))
190     return false;
191 
192   ArgInfo OrigRetInfo(VRegs, Val->getType());
193   setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F);
194 
195   SmallVector<ArgInfo, 4> SplitRetInfos;
196   splitToValueTypes(OrigRetInfo, SplitRetInfos, DL, F.getCallingConv());
197 
198   CCAssignFn *AssignFn =
199       TLI.CCAssignFnForReturn(F.getCallingConv(), F.isVarArg());
200 
201   OutgoingValueAssigner RetAssigner(AssignFn);
202   ARMOutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret);
203   return determineAndHandleAssignments(RetHandler, RetAssigner, SplitRetInfos,
204                                        MIRBuilder, F.getCallingConv(),
205                                        F.isVarArg());
206 }
207 
208 bool ARMCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
209                                   const Value *Val, ArrayRef<Register> VRegs,
210                                   FunctionLoweringInfo &FLI) const {
211   assert(!Val == VRegs.empty() && "Return value without a vreg");
212 
213   auto const &ST = MIRBuilder.getMF().getSubtarget<ARMSubtarget>();
214   unsigned Opcode = ST.getReturnOpcode();
215   auto Ret = MIRBuilder.buildInstrNoInsert(Opcode).add(predOps(ARMCC::AL));
216 
217   if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret))
218     return false;
219 
220   MIRBuilder.insertInstr(Ret);
221   return true;
222 }
223 
224 namespace {
225 
226 /// Helper class for values coming in through an ABI boundary (used for handling
227 /// formal arguments and call return values).
228 struct ARMIncomingValueHandler : public CallLowering::IncomingValueHandler {
229   ARMIncomingValueHandler(MachineIRBuilder &MIRBuilder,
230                           MachineRegisterInfo &MRI)
231       : IncomingValueHandler(MIRBuilder, MRI) {}
232 
233   Register getStackAddress(uint64_t Size, int64_t Offset,
234                            MachinePointerInfo &MPO,
235                            ISD::ArgFlagsTy Flags) override {
236     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
237            "Unsupported size");
238 
239     auto &MFI = MIRBuilder.getMF().getFrameInfo();
240 
241     // Byval is assumed to be writable memory, but other stack passed arguments
242     // are not.
243     const bool IsImmutable = !Flags.isByVal();
244 
245     int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
246     MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
247 
248     return MIRBuilder.buildFrameIndex(LLT::pointer(MPO.getAddrSpace(), 32), FI)
249         .getReg(0);
250   }
251 
252   void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
253                             MachinePointerInfo &MPO, CCValAssign &VA) override {
254     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
255            "Unsupported size");
256 
257     if (VA.getLocInfo() == CCValAssign::SExt ||
258         VA.getLocInfo() == CCValAssign::ZExt) {
259       // If the value is zero- or sign-extended, its size becomes 4 bytes, so
260       // that's what we should load.
261       Size = 4;
262       assert(MRI.getType(ValVReg).isScalar() && "Only scalars supported atm");
263 
264       auto LoadVReg = buildLoad(LLT::scalar(32), Addr, Size, MPO);
265       MIRBuilder.buildTrunc(ValVReg, LoadVReg);
266     } else {
267       // If the value is not extended, a simple load will suffice.
268       buildLoad(ValVReg, Addr, Size, MPO);
269     }
270   }
271 
272   MachineInstrBuilder buildLoad(const DstOp &Res, Register Addr, uint64_t Size,
273                                 MachinePointerInfo &MPO) {
274     MachineFunction &MF = MIRBuilder.getMF();
275 
276     auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, Size,
277                                        inferAlignFromPtrInfo(MF, MPO));
278     return MIRBuilder.buildLoad(Res, Addr, *MMO);
279   }
280 
281   void assignValueToReg(Register ValVReg, Register PhysReg,
282                         CCValAssign &VA) override {
283     assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
284     assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
285 
286     uint64_t ValSize = VA.getValVT().getFixedSizeInBits();
287     uint64_t LocSize = VA.getLocVT().getFixedSizeInBits();
288 
289     assert(ValSize <= 64 && "Unsupported value size");
290     assert(LocSize <= 64 && "Unsupported location size");
291 
292     markPhysRegUsed(PhysReg);
293     if (ValSize == LocSize) {
294       MIRBuilder.buildCopy(ValVReg, PhysReg);
295     } else {
296       assert(ValSize < LocSize && "Extensions not supported");
297 
298       // We cannot create a truncating copy, nor a trunc of a physical register.
299       // Therefore, we need to copy the content of the physical register into a
300       // virtual one and then truncate that.
301       auto PhysRegToVReg = MIRBuilder.buildCopy(LLT::scalar(LocSize), PhysReg);
302       MIRBuilder.buildTrunc(ValVReg, PhysRegToVReg);
303     }
304   }
305 
306   unsigned assignCustomValue(const ARMCallLowering::ArgInfo &Arg,
307                              ArrayRef<CCValAssign> VAs) override {
308     assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
309 
310     CCValAssign VA = VAs[0];
311     assert(VA.needsCustom() && "Value doesn't need custom handling");
312 
313     // Custom lowering for other types, such as f16, is currently not supported
314     if (VA.getValVT() != MVT::f64)
315       return 0;
316 
317     CCValAssign NextVA = VAs[1];
318     assert(NextVA.needsCustom() && "Value doesn't need custom handling");
319     assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
320 
321     assert(VA.getValNo() == NextVA.getValNo() &&
322            "Values belong to different arguments");
323 
324     assert(VA.isRegLoc() && "Value should be in reg");
325     assert(NextVA.isRegLoc() && "Value should be in reg");
326 
327     Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
328                           MRI.createGenericVirtualRegister(LLT::scalar(32))};
329 
330     assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
331     assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
332 
333     bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
334     if (!IsLittle)
335       std::swap(NewRegs[0], NewRegs[1]);
336 
337     MIRBuilder.buildMerge(Arg.Regs[0], NewRegs);
338 
339     return 1;
340   }
341 
342   /// Marking a physical register as used is different between formal
343   /// parameters, where it's a basic block live-in, and call returns, where it's
344   /// an implicit-def of the call instruction.
345   virtual void markPhysRegUsed(unsigned PhysReg) = 0;
346 };
347 
348 struct FormalArgHandler : public ARMIncomingValueHandler {
349   FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
350       : ARMIncomingValueHandler(MIRBuilder, MRI) {}
351 
352   void markPhysRegUsed(unsigned PhysReg) override {
353     MIRBuilder.getMRI()->addLiveIn(PhysReg);
354     MIRBuilder.getMBB().addLiveIn(PhysReg);
355   }
356 };
357 
358 } // end anonymous namespace
359 
360 bool ARMCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
361                                            const Function &F,
362                                            ArrayRef<ArrayRef<Register>> VRegs,
363                                            FunctionLoweringInfo &FLI) const {
364   auto &TLI = *getTLI<ARMTargetLowering>();
365   auto Subtarget = TLI.getSubtarget();
366 
367   if (Subtarget->isThumb1Only())
368     return false;
369 
370   // Quick exit if there aren't any args
371   if (F.arg_empty())
372     return true;
373 
374   if (F.isVarArg())
375     return false;
376 
377   auto &MF = MIRBuilder.getMF();
378   auto &MBB = MIRBuilder.getMBB();
379   const auto &DL = MF.getDataLayout();
380 
381   for (auto &Arg : F.args()) {
382     if (!isSupportedType(DL, TLI, Arg.getType()))
383       return false;
384     if (Arg.hasPassPointeeByValueCopyAttr())
385       return false;
386   }
387 
388   CCAssignFn *AssignFn =
389       TLI.CCAssignFnForCall(F.getCallingConv(), F.isVarArg());
390 
391   OutgoingValueAssigner ArgAssigner(AssignFn);
392   FormalArgHandler ArgHandler(MIRBuilder, MIRBuilder.getMF().getRegInfo());
393 
394   SmallVector<ArgInfo, 8> SplitArgInfos;
395   unsigned Idx = 0;
396   for (auto &Arg : F.args()) {
397     ArgInfo OrigArgInfo(VRegs[Idx], Arg.getType());
398 
399     setArgFlags(OrigArgInfo, Idx + AttributeList::FirstArgIndex, DL, F);
400     splitToValueTypes(OrigArgInfo, SplitArgInfos, DL, F.getCallingConv());
401 
402     Idx++;
403   }
404 
405   if (!MBB.empty())
406     MIRBuilder.setInstr(*MBB.begin());
407 
408   if (!determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgInfos,
409                                      MIRBuilder, F.getCallingConv(),
410                                      F.isVarArg()))
411     return false;
412 
413   // Move back to the end of the basic block.
414   MIRBuilder.setMBB(MBB);
415   return true;
416 }
417 
418 namespace {
419 
420 struct CallReturnHandler : public ARMIncomingValueHandler {
421   CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
422                     MachineInstrBuilder MIB)
423       : ARMIncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
424 
425   void markPhysRegUsed(unsigned PhysReg) override {
426     MIB.addDef(PhysReg, RegState::Implicit);
427   }
428 
429   MachineInstrBuilder MIB;
430 };
431 
432 // FIXME: This should move to the ARMSubtarget when it supports all the opcodes.
433 unsigned getCallOpcode(const MachineFunction &MF, const ARMSubtarget &STI,
434                        bool isDirect) {
435   if (isDirect)
436     return STI.isThumb() ? ARM::tBL : ARM::BL;
437 
438   if (STI.isThumb())
439     return gettBLXrOpcode(MF);
440 
441   if (STI.hasV5TOps())
442     return getBLXOpcode(MF);
443 
444   if (STI.hasV4TOps())
445     return ARM::BX_CALL;
446 
447   return ARM::BMOVPCRX_CALL;
448 }
449 } // end anonymous namespace
450 
451 bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const {
452   MachineFunction &MF = MIRBuilder.getMF();
453   const auto &TLI = *getTLI<ARMTargetLowering>();
454   const auto &DL = MF.getDataLayout();
455   const auto &STI = MF.getSubtarget<ARMSubtarget>();
456   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
457   MachineRegisterInfo &MRI = MF.getRegInfo();
458 
459   if (STI.genLongCalls())
460     return false;
461 
462   if (STI.isThumb1Only())
463     return false;
464 
465   auto CallSeqStart = MIRBuilder.buildInstr(ARM::ADJCALLSTACKDOWN);
466 
467   // Create the call instruction so we can add the implicit uses of arg
468   // registers, but don't insert it yet.
469   bool IsDirect = !Info.Callee.isReg();
470   auto CallOpcode = getCallOpcode(MF, STI, IsDirect);
471   auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode);
472 
473   bool IsThumb = STI.isThumb();
474   if (IsThumb)
475     MIB.add(predOps(ARMCC::AL));
476 
477   MIB.add(Info.Callee);
478   if (!IsDirect) {
479     auto CalleeReg = Info.Callee.getReg();
480     if (CalleeReg && !Register::isPhysicalRegister(CalleeReg)) {
481       unsigned CalleeIdx = IsThumb ? 2 : 0;
482       MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass(
483           MF, *TRI, MRI, *STI.getInstrInfo(), *STI.getRegBankInfo(),
484           *MIB.getInstr(), MIB->getDesc(), Info.Callee, CalleeIdx));
485     }
486   }
487 
488   MIB.addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
489 
490   SmallVector<ArgInfo, 8> ArgInfos;
491   for (auto Arg : Info.OrigArgs) {
492     if (!isSupportedType(DL, TLI, Arg.Ty))
493       return false;
494 
495     if (Arg.Flags[0].isByVal())
496       return false;
497 
498     splitToValueTypes(Arg, ArgInfos, DL, Info.CallConv);
499   }
500 
501   auto ArgAssignFn = TLI.CCAssignFnForCall(Info.CallConv, Info.IsVarArg);
502   OutgoingValueAssigner ArgAssigner(ArgAssignFn);
503   ARMOutgoingValueHandler ArgHandler(MIRBuilder, MRI, MIB);
504   if (!determineAndHandleAssignments(ArgHandler, ArgAssigner, ArgInfos,
505                                      MIRBuilder, Info.CallConv, Info.IsVarArg))
506     return false;
507 
508   // Now we can add the actual call instruction to the correct basic block.
509   MIRBuilder.insertInstr(MIB);
510 
511   if (!Info.OrigRet.Ty->isVoidTy()) {
512     if (!isSupportedType(DL, TLI, Info.OrigRet.Ty))
513       return false;
514 
515     ArgInfos.clear();
516     splitToValueTypes(Info.OrigRet, ArgInfos, DL, Info.CallConv);
517     auto RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv, Info.IsVarArg);
518     OutgoingValueAssigner Assigner(RetAssignFn);
519     CallReturnHandler RetHandler(MIRBuilder, MRI, MIB);
520     if (!determineAndHandleAssignments(RetHandler, Assigner, ArgInfos,
521                                        MIRBuilder, Info.CallConv,
522                                        Info.IsVarArg))
523       return false;
524   }
525 
526   // We now know the size of the stack - update the ADJCALLSTACKDOWN
527   // accordingly.
528   CallSeqStart.addImm(ArgAssigner.StackOffset)
529       .addImm(0)
530       .add(predOps(ARMCC::AL));
531 
532   MIRBuilder.buildInstr(ARM::ADJCALLSTACKUP)
533       .addImm(ArgAssigner.StackOffset)
534       .addImm(0)
535       .add(predOps(ARMCC::AL));
536 
537   return true;
538 }
539