1 //===- llvm/lib/Target/ARM/ARMCallLowering.cpp - Call lowering ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "ARMCallLowering.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMISelLowering.h"
18 #include "ARMSubtarget.h"
19 #include "Utils/ARMBaseInfo.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/Analysis.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
24 #include "llvm/CodeGen/GlobalISel/Utils.h"
25 #include "llvm/CodeGen/LowLevelType.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineOperand.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/TargetRegisterInfo.h"
34 #include "llvm/CodeGen/TargetSubtargetInfo.h"
35 #include "llvm/CodeGen/ValueTypes.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/DataLayout.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/Type.h"
41 #include "llvm/IR/Value.h"
42 #include "llvm/Support/Casting.h"
43 #include "llvm/Support/LowLevelTypeImpl.h"
44 #include "llvm/Support/MachineValueType.h"
45 #include <algorithm>
46 #include <cassert>
47 #include <cstdint>
48 #include <utility>
49 
50 using namespace llvm;
51 
52 ARMCallLowering::ARMCallLowering(const ARMTargetLowering &TLI)
53     : CallLowering(&TLI) {}
54 
55 static bool isSupportedType(const DataLayout &DL, const ARMTargetLowering &TLI,
56                             Type *T) {
57   if (T->isArrayTy())
58     return isSupportedType(DL, TLI, T->getArrayElementType());
59 
60   if (T->isStructTy()) {
61     // For now we only allow homogeneous structs that we can manipulate with
62     // G_MERGE_VALUES and G_UNMERGE_VALUES
63     auto StructT = cast<StructType>(T);
64     for (unsigned i = 1, e = StructT->getNumElements(); i != e; ++i)
65       if (StructT->getElementType(i) != StructT->getElementType(0))
66         return false;
67     return isSupportedType(DL, TLI, StructT->getElementType(0));
68   }
69 
70   EVT VT = TLI.getValueType(DL, T, true);
71   if (!VT.isSimple() || VT.isVector() ||
72       !(VT.isInteger() || VT.isFloatingPoint()))
73     return false;
74 
75   unsigned VTSize = VT.getSimpleVT().getSizeInBits();
76 
77   if (VTSize == 64)
78     // FIXME: Support i64 too
79     return VT.isFloatingPoint();
80 
81   return VTSize == 1 || VTSize == 8 || VTSize == 16 || VTSize == 32;
82 }
83 
84 namespace {
85 
86 /// Helper class for values going out through an ABI boundary (used for handling
87 /// function return values and call parameters).
88 struct ARMOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
89   ARMOutgoingValueHandler(MachineIRBuilder &MIRBuilder,
90                           MachineRegisterInfo &MRI, MachineInstrBuilder &MIB,
91                           CCAssignFn *AssignFn)
92       : OutgoingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
93 
94   Register getStackAddress(uint64_t Size, int64_t Offset,
95                            MachinePointerInfo &MPO) override {
96     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
97            "Unsupported size");
98 
99     LLT p0 = LLT::pointer(0, 32);
100     LLT s32 = LLT::scalar(32);
101     auto SPReg = MIRBuilder.buildCopy(p0, Register(ARM::SP));
102 
103     auto OffsetReg = MIRBuilder.buildConstant(s32, Offset);
104 
105     auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
106 
107     MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
108     return AddrReg.getReg(0);
109   }
110 
111   void assignValueToReg(Register ValVReg, Register PhysReg,
112                         CCValAssign &VA) override {
113     assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
114     assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
115 
116     assert(VA.getValVT().getSizeInBits() <= 64 && "Unsupported value size");
117     assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size");
118 
119     Register ExtReg = extendRegister(ValVReg, VA);
120     MIRBuilder.buildCopy(PhysReg, ExtReg);
121     MIB.addUse(PhysReg, RegState::Implicit);
122   }
123 
124   void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
125                             MachinePointerInfo &MPO, CCValAssign &VA) override {
126     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
127            "Unsupported size");
128 
129     Register ExtReg = extendRegister(ValVReg, VA);
130     auto MMO = MIRBuilder.getMF().getMachineMemOperand(
131         MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(),
132         Align(1));
133     MIRBuilder.buildStore(ExtReg, Addr, *MMO);
134   }
135 
136   unsigned assignCustomValue(const CallLowering::ArgInfo &Arg,
137                              ArrayRef<CCValAssign> VAs) override {
138     assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
139 
140     CCValAssign VA = VAs[0];
141     assert(VA.needsCustom() && "Value doesn't need custom handling");
142 
143     // Custom lowering for other types, such as f16, is currently not supported
144     if (VA.getValVT() != MVT::f64)
145       return 0;
146 
147     CCValAssign NextVA = VAs[1];
148     assert(NextVA.needsCustom() && "Value doesn't need custom handling");
149     assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
150 
151     assert(VA.getValNo() == NextVA.getValNo() &&
152            "Values belong to different arguments");
153 
154     assert(VA.isRegLoc() && "Value should be in reg");
155     assert(NextVA.isRegLoc() && "Value should be in reg");
156 
157     Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
158                           MRI.createGenericVirtualRegister(LLT::scalar(32))};
159     MIRBuilder.buildUnmerge(NewRegs, Arg.Regs[0]);
160 
161     bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
162     if (!IsLittle)
163       std::swap(NewRegs[0], NewRegs[1]);
164 
165     assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
166     assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
167 
168     return 1;
169   }
170 
171   bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
172                  CCValAssign::LocInfo LocInfo,
173                  const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
174                  CCState &State) override {
175     if (AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State))
176       return true;
177 
178     StackSize =
179         std::max(StackSize, static_cast<uint64_t>(State.getNextStackOffset()));
180     return false;
181   }
182 
183   MachineInstrBuilder &MIB;
184   uint64_t StackSize = 0;
185 };
186 
187 } // end anonymous namespace
188 
189 /// Lower the return value for the already existing \p Ret. This assumes that
190 /// \p MIRBuilder's insertion point is correct.
191 bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
192                                      const Value *Val, ArrayRef<Register> VRegs,
193                                      MachineInstrBuilder &Ret) const {
194   if (!Val)
195     // Nothing to do here.
196     return true;
197 
198   auto &MF = MIRBuilder.getMF();
199   const auto &F = MF.getFunction();
200 
201   const auto &DL = MF.getDataLayout();
202   auto &TLI = *getTLI<ARMTargetLowering>();
203   if (!isSupportedType(DL, TLI, Val->getType()))
204     return false;
205 
206   ArgInfo OrigRetInfo(VRegs, Val->getType());
207   setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F);
208 
209   SmallVector<ArgInfo, 4> SplitRetInfos;
210   splitToValueTypes(OrigRetInfo, SplitRetInfos, DL, F.getCallingConv());
211 
212   CCAssignFn *AssignFn =
213       TLI.CCAssignFnForReturn(F.getCallingConv(), F.isVarArg());
214 
215   ARMOutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret,
216                                      AssignFn);
217   return handleAssignments(MIRBuilder, SplitRetInfos, RetHandler,
218                            F.getCallingConv(), F.isVarArg());
219 }
220 
221 bool ARMCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
222                                   const Value *Val, ArrayRef<Register> VRegs,
223                                   FunctionLoweringInfo &FLI) const {
224   assert(!Val == VRegs.empty() && "Return value without a vreg");
225 
226   auto const &ST = MIRBuilder.getMF().getSubtarget<ARMSubtarget>();
227   unsigned Opcode = ST.getReturnOpcode();
228   auto Ret = MIRBuilder.buildInstrNoInsert(Opcode).add(predOps(ARMCC::AL));
229 
230   if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret))
231     return false;
232 
233   MIRBuilder.insertInstr(Ret);
234   return true;
235 }
236 
237 namespace {
238 
239 /// Helper class for values coming in through an ABI boundary (used for handling
240 /// formal arguments and call return values).
241 struct ARMIncomingValueHandler : public CallLowering::IncomingValueHandler {
242   ARMIncomingValueHandler(MachineIRBuilder &MIRBuilder,
243                           MachineRegisterInfo &MRI, CCAssignFn AssignFn)
244       : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
245 
246   Register getStackAddress(uint64_t Size, int64_t Offset,
247                            MachinePointerInfo &MPO) override {
248     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
249            "Unsupported size");
250 
251     auto &MFI = MIRBuilder.getMF().getFrameInfo();
252 
253     int FI = MFI.CreateFixedObject(Size, Offset, true);
254     MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
255 
256     return MIRBuilder.buildFrameIndex(LLT::pointer(MPO.getAddrSpace(), 32), FI)
257         .getReg(0);
258   }
259 
260   void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
261                             MachinePointerInfo &MPO, CCValAssign &VA) override {
262     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
263            "Unsupported size");
264 
265     if (VA.getLocInfo() == CCValAssign::SExt ||
266         VA.getLocInfo() == CCValAssign::ZExt) {
267       // If the value is zero- or sign-extended, its size becomes 4 bytes, so
268       // that's what we should load.
269       Size = 4;
270       assert(MRI.getType(ValVReg).isScalar() && "Only scalars supported atm");
271 
272       auto LoadVReg = buildLoad(LLT::scalar(32), Addr, Size, MPO);
273       MIRBuilder.buildTrunc(ValVReg, LoadVReg);
274     } else {
275       // If the value is not extended, a simple load will suffice.
276       buildLoad(ValVReg, Addr, Size, MPO);
277     }
278   }
279 
280   MachineInstrBuilder buildLoad(const DstOp &Res, Register Addr, uint64_t Size,
281                                 MachinePointerInfo &MPO) {
282     MachineFunction &MF = MIRBuilder.getMF();
283 
284     auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, Size,
285                                        inferAlignFromPtrInfo(MF, MPO));
286     return MIRBuilder.buildLoad(Res, Addr, *MMO);
287   }
288 
289   void assignValueToReg(Register ValVReg, Register PhysReg,
290                         CCValAssign &VA) override {
291     assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
292     assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
293 
294     uint64_t ValSize = VA.getValVT().getFixedSizeInBits();
295     uint64_t LocSize = VA.getLocVT().getFixedSizeInBits();
296 
297     assert(ValSize <= 64 && "Unsupported value size");
298     assert(LocSize <= 64 && "Unsupported location size");
299 
300     markPhysRegUsed(PhysReg);
301     if (ValSize == LocSize) {
302       MIRBuilder.buildCopy(ValVReg, PhysReg);
303     } else {
304       assert(ValSize < LocSize && "Extensions not supported");
305 
306       // We cannot create a truncating copy, nor a trunc of a physical register.
307       // Therefore, we need to copy the content of the physical register into a
308       // virtual one and then truncate that.
309       auto PhysRegToVReg = MIRBuilder.buildCopy(LLT::scalar(LocSize), PhysReg);
310       MIRBuilder.buildTrunc(ValVReg, PhysRegToVReg);
311     }
312   }
313 
314   unsigned assignCustomValue(const ARMCallLowering::ArgInfo &Arg,
315                              ArrayRef<CCValAssign> VAs) override {
316     assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
317 
318     CCValAssign VA = VAs[0];
319     assert(VA.needsCustom() && "Value doesn't need custom handling");
320 
321     // Custom lowering for other types, such as f16, is currently not supported
322     if (VA.getValVT() != MVT::f64)
323       return 0;
324 
325     CCValAssign NextVA = VAs[1];
326     assert(NextVA.needsCustom() && "Value doesn't need custom handling");
327     assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
328 
329     assert(VA.getValNo() == NextVA.getValNo() &&
330            "Values belong to different arguments");
331 
332     assert(VA.isRegLoc() && "Value should be in reg");
333     assert(NextVA.isRegLoc() && "Value should be in reg");
334 
335     Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
336                           MRI.createGenericVirtualRegister(LLT::scalar(32))};
337 
338     assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
339     assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
340 
341     bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
342     if (!IsLittle)
343       std::swap(NewRegs[0], NewRegs[1]);
344 
345     MIRBuilder.buildMerge(Arg.Regs[0], NewRegs);
346 
347     return 1;
348   }
349 
350   /// Marking a physical register as used is different between formal
351   /// parameters, where it's a basic block live-in, and call returns, where it's
352   /// an implicit-def of the call instruction.
353   virtual void markPhysRegUsed(unsigned PhysReg) = 0;
354 };
355 
356 struct FormalArgHandler : public ARMIncomingValueHandler {
357   FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
358                    CCAssignFn AssignFn)
359       : ARMIncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
360 
361   void markPhysRegUsed(unsigned PhysReg) override {
362     MIRBuilder.getMRI()->addLiveIn(PhysReg);
363     MIRBuilder.getMBB().addLiveIn(PhysReg);
364   }
365 };
366 
367 } // end anonymous namespace
368 
369 bool ARMCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
370                                            const Function &F,
371                                            ArrayRef<ArrayRef<Register>> VRegs,
372                                            FunctionLoweringInfo &FLI) const {
373   auto &TLI = *getTLI<ARMTargetLowering>();
374   auto Subtarget = TLI.getSubtarget();
375 
376   if (Subtarget->isThumb1Only())
377     return false;
378 
379   // Quick exit if there aren't any args
380   if (F.arg_empty())
381     return true;
382 
383   if (F.isVarArg())
384     return false;
385 
386   auto &MF = MIRBuilder.getMF();
387   auto &MBB = MIRBuilder.getMBB();
388   const auto &DL = MF.getDataLayout();
389 
390   for (auto &Arg : F.args()) {
391     if (!isSupportedType(DL, TLI, Arg.getType()))
392       return false;
393     if (Arg.hasPassPointeeByValueCopyAttr())
394       return false;
395   }
396 
397   CCAssignFn *AssignFn =
398       TLI.CCAssignFnForCall(F.getCallingConv(), F.isVarArg());
399 
400   FormalArgHandler ArgHandler(MIRBuilder, MIRBuilder.getMF().getRegInfo(),
401                               AssignFn);
402 
403   SmallVector<ArgInfo, 8> SplitArgInfos;
404   unsigned Idx = 0;
405   for (auto &Arg : F.args()) {
406     ArgInfo OrigArgInfo(VRegs[Idx], Arg.getType());
407 
408     setArgFlags(OrigArgInfo, Idx + AttributeList::FirstArgIndex, DL, F);
409     splitToValueTypes(OrigArgInfo, SplitArgInfos, DL, F.getCallingConv());
410 
411     Idx++;
412   }
413 
414   if (!MBB.empty())
415     MIRBuilder.setInstr(*MBB.begin());
416 
417   if (!handleAssignments(MIRBuilder, SplitArgInfos, ArgHandler,
418                          F.getCallingConv(), F.isVarArg()))
419     return false;
420 
421   // Move back to the end of the basic block.
422   MIRBuilder.setMBB(MBB);
423   return true;
424 }
425 
426 namespace {
427 
428 struct CallReturnHandler : public ARMIncomingValueHandler {
429   CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
430                     MachineInstrBuilder MIB, CCAssignFn *AssignFn)
431       : ARMIncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
432 
433   void markPhysRegUsed(unsigned PhysReg) override {
434     MIB.addDef(PhysReg, RegState::Implicit);
435   }
436 
437   MachineInstrBuilder MIB;
438 };
439 
440 // FIXME: This should move to the ARMSubtarget when it supports all the opcodes.
441 unsigned getCallOpcode(const MachineFunction &MF, const ARMSubtarget &STI,
442                        bool isDirect) {
443   if (isDirect)
444     return STI.isThumb() ? ARM::tBL : ARM::BL;
445 
446   if (STI.isThumb())
447     return gettBLXrOpcode(MF);
448 
449   if (STI.hasV5TOps())
450     return getBLXOpcode(MF);
451 
452   if (STI.hasV4TOps())
453     return ARM::BX_CALL;
454 
455   return ARM::BMOVPCRX_CALL;
456 }
457 } // end anonymous namespace
458 
459 bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const {
460   MachineFunction &MF = MIRBuilder.getMF();
461   const auto &TLI = *getTLI<ARMTargetLowering>();
462   const auto &DL = MF.getDataLayout();
463   const auto &STI = MF.getSubtarget<ARMSubtarget>();
464   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
465   MachineRegisterInfo &MRI = MF.getRegInfo();
466 
467   if (STI.genLongCalls())
468     return false;
469 
470   if (STI.isThumb1Only())
471     return false;
472 
473   auto CallSeqStart = MIRBuilder.buildInstr(ARM::ADJCALLSTACKDOWN);
474 
475   // Create the call instruction so we can add the implicit uses of arg
476   // registers, but don't insert it yet.
477   bool IsDirect = !Info.Callee.isReg();
478   auto CallOpcode = getCallOpcode(MF, STI, IsDirect);
479   auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode);
480 
481   bool IsThumb = STI.isThumb();
482   if (IsThumb)
483     MIB.add(predOps(ARMCC::AL));
484 
485   MIB.add(Info.Callee);
486   if (!IsDirect) {
487     auto CalleeReg = Info.Callee.getReg();
488     if (CalleeReg && !Register::isPhysicalRegister(CalleeReg)) {
489       unsigned CalleeIdx = IsThumb ? 2 : 0;
490       MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass(
491           MF, *TRI, MRI, *STI.getInstrInfo(), *STI.getRegBankInfo(),
492           *MIB.getInstr(), MIB->getDesc(), Info.Callee, CalleeIdx));
493     }
494   }
495 
496   MIB.addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
497 
498   SmallVector<ArgInfo, 8> ArgInfos;
499   for (auto Arg : Info.OrigArgs) {
500     if (!isSupportedType(DL, TLI, Arg.Ty))
501       return false;
502 
503     if (Arg.Flags[0].isByVal())
504       return false;
505 
506     splitToValueTypes(Arg, ArgInfos, DL, Info.CallConv);
507   }
508 
509   auto ArgAssignFn = TLI.CCAssignFnForCall(Info.CallConv, Info.IsVarArg);
510   ARMOutgoingValueHandler ArgHandler(MIRBuilder, MRI, MIB, ArgAssignFn);
511   if (!handleAssignments(MIRBuilder, ArgInfos, ArgHandler, Info.CallConv,
512                          Info.IsVarArg))
513     return false;
514 
515   // Now we can add the actual call instruction to the correct basic block.
516   MIRBuilder.insertInstr(MIB);
517 
518   if (!Info.OrigRet.Ty->isVoidTy()) {
519     if (!isSupportedType(DL, TLI, Info.OrigRet.Ty))
520       return false;
521 
522     ArgInfos.clear();
523     splitToValueTypes(Info.OrigRet, ArgInfos, DL, Info.CallConv);
524     auto RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv, Info.IsVarArg);
525     CallReturnHandler RetHandler(MIRBuilder, MRI, MIB, RetAssignFn);
526     if (!handleAssignments(MIRBuilder, ArgInfos, RetHandler, Info.CallConv,
527                            Info.IsVarArg))
528       return false;
529   }
530 
531   // We now know the size of the stack - update the ADJCALLSTACKDOWN
532   // accordingly.
533   CallSeqStart.addImm(ArgHandler.StackSize).addImm(0).add(predOps(ARMCC::AL));
534 
535   MIRBuilder.buildInstr(ARM::ADJCALLSTACKUP)
536       .addImm(ArgHandler.StackSize)
537       .addImm(0)
538       .add(predOps(ARMCC::AL));
539 
540   return true;
541 }
542