1 //===- llvm/lib/Target/ARM/ARMCallLowering.cpp - Call lowering ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "ARMCallLowering.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMISelLowering.h"
18 #include "ARMSubtarget.h"
19 #include "Utils/ARMBaseInfo.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/Analysis.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
24 #include "llvm/CodeGen/GlobalISel/Utils.h"
25 #include "llvm/CodeGen/LowLevelType.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineOperand.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/TargetRegisterInfo.h"
34 #include "llvm/CodeGen/TargetSubtargetInfo.h"
35 #include "llvm/CodeGen/ValueTypes.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/DataLayout.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/Type.h"
41 #include "llvm/IR/Value.h"
42 #include "llvm/Support/Casting.h"
43 #include "llvm/Support/LowLevelTypeImpl.h"
44 #include "llvm/Support/MachineValueType.h"
45 #include <algorithm>
46 #include <cassert>
47 #include <cstdint>
48 #include <utility>
49 
50 using namespace llvm;
51 
52 ARMCallLowering::ARMCallLowering(const ARMTargetLowering &TLI)
53     : CallLowering(&TLI) {}
54 
55 static bool isSupportedType(const DataLayout &DL, const ARMTargetLowering &TLI,
56                             Type *T) {
57   if (T->isArrayTy())
58     return isSupportedType(DL, TLI, T->getArrayElementType());
59 
60   if (T->isStructTy()) {
61     // For now we only allow homogeneous structs that we can manipulate with
62     // G_MERGE_VALUES and G_UNMERGE_VALUES
63     auto StructT = cast<StructType>(T);
64     for (unsigned i = 1, e = StructT->getNumElements(); i != e; ++i)
65       if (StructT->getElementType(i) != StructT->getElementType(0))
66         return false;
67     return isSupportedType(DL, TLI, StructT->getElementType(0));
68   }
69 
70   EVT VT = TLI.getValueType(DL, T, true);
71   if (!VT.isSimple() || VT.isVector() ||
72       !(VT.isInteger() || VT.isFloatingPoint()))
73     return false;
74 
75   unsigned VTSize = VT.getSimpleVT().getSizeInBits();
76 
77   if (VTSize == 64)
78     // FIXME: Support i64 too
79     return VT.isFloatingPoint();
80 
81   return VTSize == 1 || VTSize == 8 || VTSize == 16 || VTSize == 32;
82 }
83 
84 namespace {
85 
86 /// Helper class for values going out through an ABI boundary (used for handling
87 /// function return values and call parameters).
88 struct ARMOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
89   ARMOutgoingValueHandler(MachineIRBuilder &MIRBuilder,
90                           MachineRegisterInfo &MRI, MachineInstrBuilder &MIB,
91                           CCAssignFn *AssignFn)
92       : OutgoingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
93 
94   Register getStackAddress(uint64_t Size, int64_t Offset,
95                            MachinePointerInfo &MPO,
96                            ISD::ArgFlagsTy Flags) override {
97     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
98            "Unsupported size");
99 
100     LLT p0 = LLT::pointer(0, 32);
101     LLT s32 = LLT::scalar(32);
102     auto SPReg = MIRBuilder.buildCopy(p0, Register(ARM::SP));
103 
104     auto OffsetReg = MIRBuilder.buildConstant(s32, Offset);
105 
106     auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
107 
108     MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
109     return AddrReg.getReg(0);
110   }
111 
112   void assignValueToReg(Register ValVReg, Register PhysReg,
113                         CCValAssign &VA) override {
114     assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
115     assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
116 
117     assert(VA.getValVT().getSizeInBits() <= 64 && "Unsupported value size");
118     assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size");
119 
120     Register ExtReg = extendRegister(ValVReg, VA);
121     MIRBuilder.buildCopy(PhysReg, ExtReg);
122     MIB.addUse(PhysReg, RegState::Implicit);
123   }
124 
125   void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
126                             MachinePointerInfo &MPO, CCValAssign &VA) override {
127     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
128            "Unsupported size");
129 
130     Register ExtReg = extendRegister(ValVReg, VA);
131     auto MMO = MIRBuilder.getMF().getMachineMemOperand(
132         MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(),
133         Align(1));
134     MIRBuilder.buildStore(ExtReg, Addr, *MMO);
135   }
136 
137   unsigned assignCustomValue(const CallLowering::ArgInfo &Arg,
138                              ArrayRef<CCValAssign> VAs) override {
139     assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
140 
141     CCValAssign VA = VAs[0];
142     assert(VA.needsCustom() && "Value doesn't need custom handling");
143 
144     // Custom lowering for other types, such as f16, is currently not supported
145     if (VA.getValVT() != MVT::f64)
146       return 0;
147 
148     CCValAssign NextVA = VAs[1];
149     assert(NextVA.needsCustom() && "Value doesn't need custom handling");
150     assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
151 
152     assert(VA.getValNo() == NextVA.getValNo() &&
153            "Values belong to different arguments");
154 
155     assert(VA.isRegLoc() && "Value should be in reg");
156     assert(NextVA.isRegLoc() && "Value should be in reg");
157 
158     Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
159                           MRI.createGenericVirtualRegister(LLT::scalar(32))};
160     MIRBuilder.buildUnmerge(NewRegs, Arg.Regs[0]);
161 
162     bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
163     if (!IsLittle)
164       std::swap(NewRegs[0], NewRegs[1]);
165 
166     assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
167     assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
168 
169     return 1;
170   }
171 
172   bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
173                  CCValAssign::LocInfo LocInfo,
174                  const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
175                  CCState &State) override {
176     if (AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State))
177       return true;
178 
179     StackSize =
180         std::max(StackSize, static_cast<uint64_t>(State.getNextStackOffset()));
181     return false;
182   }
183 
184   MachineInstrBuilder &MIB;
185   uint64_t StackSize = 0;
186 };
187 
188 } // end anonymous namespace
189 
190 /// Lower the return value for the already existing \p Ret. This assumes that
191 /// \p MIRBuilder's insertion point is correct.
192 bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
193                                      const Value *Val, ArrayRef<Register> VRegs,
194                                      MachineInstrBuilder &Ret) const {
195   if (!Val)
196     // Nothing to do here.
197     return true;
198 
199   auto &MF = MIRBuilder.getMF();
200   const auto &F = MF.getFunction();
201 
202   const auto &DL = MF.getDataLayout();
203   auto &TLI = *getTLI<ARMTargetLowering>();
204   if (!isSupportedType(DL, TLI, Val->getType()))
205     return false;
206 
207   ArgInfo OrigRetInfo(VRegs, Val->getType());
208   setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F);
209 
210   SmallVector<ArgInfo, 4> SplitRetInfos;
211   splitToValueTypes(OrigRetInfo, SplitRetInfos, DL, F.getCallingConv());
212 
213   CCAssignFn *AssignFn =
214       TLI.CCAssignFnForReturn(F.getCallingConv(), F.isVarArg());
215 
216   ARMOutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret,
217                                      AssignFn);
218   return handleAssignments(MIRBuilder, SplitRetInfos, RetHandler,
219                            F.getCallingConv(), F.isVarArg());
220 }
221 
222 bool ARMCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
223                                   const Value *Val, ArrayRef<Register> VRegs,
224                                   FunctionLoweringInfo &FLI) const {
225   assert(!Val == VRegs.empty() && "Return value without a vreg");
226 
227   auto const &ST = MIRBuilder.getMF().getSubtarget<ARMSubtarget>();
228   unsigned Opcode = ST.getReturnOpcode();
229   auto Ret = MIRBuilder.buildInstrNoInsert(Opcode).add(predOps(ARMCC::AL));
230 
231   if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret))
232     return false;
233 
234   MIRBuilder.insertInstr(Ret);
235   return true;
236 }
237 
238 namespace {
239 
240 /// Helper class for values coming in through an ABI boundary (used for handling
241 /// formal arguments and call return values).
242 struct ARMIncomingValueHandler : public CallLowering::IncomingValueHandler {
243   ARMIncomingValueHandler(MachineIRBuilder &MIRBuilder,
244                           MachineRegisterInfo &MRI, CCAssignFn AssignFn)
245       : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
246 
247   Register getStackAddress(uint64_t Size, int64_t Offset,
248                            MachinePointerInfo &MPO,
249                            ISD::ArgFlagsTy Flags) override {
250     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
251            "Unsupported size");
252 
253     auto &MFI = MIRBuilder.getMF().getFrameInfo();
254 
255     // Byval is assumed to be writable memory, but other stack passed arguments
256     // are not.
257     const bool IsImmutable = !Flags.isByVal();
258 
259     int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
260     MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
261 
262     return MIRBuilder.buildFrameIndex(LLT::pointer(MPO.getAddrSpace(), 32), FI)
263         .getReg(0);
264   }
265 
266   void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
267                             MachinePointerInfo &MPO, CCValAssign &VA) override {
268     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
269            "Unsupported size");
270 
271     if (VA.getLocInfo() == CCValAssign::SExt ||
272         VA.getLocInfo() == CCValAssign::ZExt) {
273       // If the value is zero- or sign-extended, its size becomes 4 bytes, so
274       // that's what we should load.
275       Size = 4;
276       assert(MRI.getType(ValVReg).isScalar() && "Only scalars supported atm");
277 
278       auto LoadVReg = buildLoad(LLT::scalar(32), Addr, Size, MPO);
279       MIRBuilder.buildTrunc(ValVReg, LoadVReg);
280     } else {
281       // If the value is not extended, a simple load will suffice.
282       buildLoad(ValVReg, Addr, Size, MPO);
283     }
284   }
285 
286   MachineInstrBuilder buildLoad(const DstOp &Res, Register Addr, uint64_t Size,
287                                 MachinePointerInfo &MPO) {
288     MachineFunction &MF = MIRBuilder.getMF();
289 
290     auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, Size,
291                                        inferAlignFromPtrInfo(MF, MPO));
292     return MIRBuilder.buildLoad(Res, Addr, *MMO);
293   }
294 
295   void assignValueToReg(Register ValVReg, Register PhysReg,
296                         CCValAssign &VA) override {
297     assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
298     assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
299 
300     uint64_t ValSize = VA.getValVT().getFixedSizeInBits();
301     uint64_t LocSize = VA.getLocVT().getFixedSizeInBits();
302 
303     assert(ValSize <= 64 && "Unsupported value size");
304     assert(LocSize <= 64 && "Unsupported location size");
305 
306     markPhysRegUsed(PhysReg);
307     if (ValSize == LocSize) {
308       MIRBuilder.buildCopy(ValVReg, PhysReg);
309     } else {
310       assert(ValSize < LocSize && "Extensions not supported");
311 
312       // We cannot create a truncating copy, nor a trunc of a physical register.
313       // Therefore, we need to copy the content of the physical register into a
314       // virtual one and then truncate that.
315       auto PhysRegToVReg = MIRBuilder.buildCopy(LLT::scalar(LocSize), PhysReg);
316       MIRBuilder.buildTrunc(ValVReg, PhysRegToVReg);
317     }
318   }
319 
320   unsigned assignCustomValue(const ARMCallLowering::ArgInfo &Arg,
321                              ArrayRef<CCValAssign> VAs) override {
322     assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
323 
324     CCValAssign VA = VAs[0];
325     assert(VA.needsCustom() && "Value doesn't need custom handling");
326 
327     // Custom lowering for other types, such as f16, is currently not supported
328     if (VA.getValVT() != MVT::f64)
329       return 0;
330 
331     CCValAssign NextVA = VAs[1];
332     assert(NextVA.needsCustom() && "Value doesn't need custom handling");
333     assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
334 
335     assert(VA.getValNo() == NextVA.getValNo() &&
336            "Values belong to different arguments");
337 
338     assert(VA.isRegLoc() && "Value should be in reg");
339     assert(NextVA.isRegLoc() && "Value should be in reg");
340 
341     Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
342                           MRI.createGenericVirtualRegister(LLT::scalar(32))};
343 
344     assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
345     assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
346 
347     bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
348     if (!IsLittle)
349       std::swap(NewRegs[0], NewRegs[1]);
350 
351     MIRBuilder.buildMerge(Arg.Regs[0], NewRegs);
352 
353     return 1;
354   }
355 
356   /// Marking a physical register as used is different between formal
357   /// parameters, where it's a basic block live-in, and call returns, where it's
358   /// an implicit-def of the call instruction.
359   virtual void markPhysRegUsed(unsigned PhysReg) = 0;
360 };
361 
362 struct FormalArgHandler : public ARMIncomingValueHandler {
363   FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
364                    CCAssignFn AssignFn)
365       : ARMIncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
366 
367   void markPhysRegUsed(unsigned PhysReg) override {
368     MIRBuilder.getMRI()->addLiveIn(PhysReg);
369     MIRBuilder.getMBB().addLiveIn(PhysReg);
370   }
371 };
372 
373 } // end anonymous namespace
374 
375 bool ARMCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
376                                            const Function &F,
377                                            ArrayRef<ArrayRef<Register>> VRegs,
378                                            FunctionLoweringInfo &FLI) const {
379   auto &TLI = *getTLI<ARMTargetLowering>();
380   auto Subtarget = TLI.getSubtarget();
381 
382   if (Subtarget->isThumb1Only())
383     return false;
384 
385   // Quick exit if there aren't any args
386   if (F.arg_empty())
387     return true;
388 
389   if (F.isVarArg())
390     return false;
391 
392   auto &MF = MIRBuilder.getMF();
393   auto &MBB = MIRBuilder.getMBB();
394   const auto &DL = MF.getDataLayout();
395 
396   for (auto &Arg : F.args()) {
397     if (!isSupportedType(DL, TLI, Arg.getType()))
398       return false;
399     if (Arg.hasPassPointeeByValueCopyAttr())
400       return false;
401   }
402 
403   CCAssignFn *AssignFn =
404       TLI.CCAssignFnForCall(F.getCallingConv(), F.isVarArg());
405 
406   FormalArgHandler ArgHandler(MIRBuilder, MIRBuilder.getMF().getRegInfo(),
407                               AssignFn);
408 
409   SmallVector<ArgInfo, 8> SplitArgInfos;
410   unsigned Idx = 0;
411   for (auto &Arg : F.args()) {
412     ArgInfo OrigArgInfo(VRegs[Idx], Arg.getType());
413 
414     setArgFlags(OrigArgInfo, Idx + AttributeList::FirstArgIndex, DL, F);
415     splitToValueTypes(OrigArgInfo, SplitArgInfos, DL, F.getCallingConv());
416 
417     Idx++;
418   }
419 
420   if (!MBB.empty())
421     MIRBuilder.setInstr(*MBB.begin());
422 
423   if (!handleAssignments(MIRBuilder, SplitArgInfos, ArgHandler,
424                          F.getCallingConv(), F.isVarArg()))
425     return false;
426 
427   // Move back to the end of the basic block.
428   MIRBuilder.setMBB(MBB);
429   return true;
430 }
431 
432 namespace {
433 
434 struct CallReturnHandler : public ARMIncomingValueHandler {
435   CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
436                     MachineInstrBuilder MIB, CCAssignFn *AssignFn)
437       : ARMIncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
438 
439   void markPhysRegUsed(unsigned PhysReg) override {
440     MIB.addDef(PhysReg, RegState::Implicit);
441   }
442 
443   MachineInstrBuilder MIB;
444 };
445 
446 // FIXME: This should move to the ARMSubtarget when it supports all the opcodes.
447 unsigned getCallOpcode(const MachineFunction &MF, const ARMSubtarget &STI,
448                        bool isDirect) {
449   if (isDirect)
450     return STI.isThumb() ? ARM::tBL : ARM::BL;
451 
452   if (STI.isThumb())
453     return gettBLXrOpcode(MF);
454 
455   if (STI.hasV5TOps())
456     return getBLXOpcode(MF);
457 
458   if (STI.hasV4TOps())
459     return ARM::BX_CALL;
460 
461   return ARM::BMOVPCRX_CALL;
462 }
463 } // end anonymous namespace
464 
465 bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const {
466   MachineFunction &MF = MIRBuilder.getMF();
467   const auto &TLI = *getTLI<ARMTargetLowering>();
468   const auto &DL = MF.getDataLayout();
469   const auto &STI = MF.getSubtarget<ARMSubtarget>();
470   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
471   MachineRegisterInfo &MRI = MF.getRegInfo();
472 
473   if (STI.genLongCalls())
474     return false;
475 
476   if (STI.isThumb1Only())
477     return false;
478 
479   auto CallSeqStart = MIRBuilder.buildInstr(ARM::ADJCALLSTACKDOWN);
480 
481   // Create the call instruction so we can add the implicit uses of arg
482   // registers, but don't insert it yet.
483   bool IsDirect = !Info.Callee.isReg();
484   auto CallOpcode = getCallOpcode(MF, STI, IsDirect);
485   auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode);
486 
487   bool IsThumb = STI.isThumb();
488   if (IsThumb)
489     MIB.add(predOps(ARMCC::AL));
490 
491   MIB.add(Info.Callee);
492   if (!IsDirect) {
493     auto CalleeReg = Info.Callee.getReg();
494     if (CalleeReg && !Register::isPhysicalRegister(CalleeReg)) {
495       unsigned CalleeIdx = IsThumb ? 2 : 0;
496       MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass(
497           MF, *TRI, MRI, *STI.getInstrInfo(), *STI.getRegBankInfo(),
498           *MIB.getInstr(), MIB->getDesc(), Info.Callee, CalleeIdx));
499     }
500   }
501 
502   MIB.addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
503 
504   SmallVector<ArgInfo, 8> ArgInfos;
505   for (auto Arg : Info.OrigArgs) {
506     if (!isSupportedType(DL, TLI, Arg.Ty))
507       return false;
508 
509     if (Arg.Flags[0].isByVal())
510       return false;
511 
512     splitToValueTypes(Arg, ArgInfos, DL, Info.CallConv);
513   }
514 
515   auto ArgAssignFn = TLI.CCAssignFnForCall(Info.CallConv, Info.IsVarArg);
516   ARMOutgoingValueHandler ArgHandler(MIRBuilder, MRI, MIB, ArgAssignFn);
517   if (!handleAssignments(MIRBuilder, ArgInfos, ArgHandler, Info.CallConv,
518                          Info.IsVarArg))
519     return false;
520 
521   // Now we can add the actual call instruction to the correct basic block.
522   MIRBuilder.insertInstr(MIB);
523 
524   if (!Info.OrigRet.Ty->isVoidTy()) {
525     if (!isSupportedType(DL, TLI, Info.OrigRet.Ty))
526       return false;
527 
528     ArgInfos.clear();
529     splitToValueTypes(Info.OrigRet, ArgInfos, DL, Info.CallConv);
530     auto RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv, Info.IsVarArg);
531     CallReturnHandler RetHandler(MIRBuilder, MRI, MIB, RetAssignFn);
532     if (!handleAssignments(MIRBuilder, ArgInfos, RetHandler, Info.CallConv,
533                            Info.IsVarArg))
534       return false;
535   }
536 
537   // We now know the size of the stack - update the ADJCALLSTACKDOWN
538   // accordingly.
539   CallSeqStart.addImm(ArgHandler.StackSize).addImm(0).add(predOps(ARMCC::AL));
540 
541   MIRBuilder.buildInstr(ARM::ADJCALLSTACKUP)
542       .addImm(ArgHandler.StackSize)
543       .addImm(0)
544       .add(predOps(ARMCC::AL));
545 
546   return true;
547 }
548