1 //===- llvm/lib/Target/ARM/ARMCallLowering.cpp - Call lowering ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "ARMCallLowering.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMISelLowering.h"
18 #include "ARMSubtarget.h"
19 #include "Utils/ARMBaseInfo.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/Analysis.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
24 #include "llvm/CodeGen/GlobalISel/Utils.h"
25 #include "llvm/CodeGen/LowLevelType.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineOperand.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/TargetRegisterInfo.h"
34 #include "llvm/CodeGen/TargetSubtargetInfo.h"
35 #include "llvm/CodeGen/ValueTypes.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/DataLayout.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/Type.h"
41 #include "llvm/IR/Value.h"
42 #include "llvm/Support/Casting.h"
43 #include "llvm/Support/LowLevelTypeImpl.h"
44 #include "llvm/Support/MachineValueType.h"
45 #include <algorithm>
46 #include <cassert>
47 #include <cstdint>
48 #include <utility>
49 
50 using namespace llvm;
51 
52 ARMCallLowering::ARMCallLowering(const ARMTargetLowering &TLI)
53     : CallLowering(&TLI) {}
54 
55 static bool isSupportedType(const DataLayout &DL, const ARMTargetLowering &TLI,
56                             Type *T) {
57   if (T->isArrayTy())
58     return isSupportedType(DL, TLI, T->getArrayElementType());
59 
60   if (T->isStructTy()) {
61     // For now we only allow homogeneous structs that we can manipulate with
62     // G_MERGE_VALUES and G_UNMERGE_VALUES
63     auto StructT = cast<StructType>(T);
64     for (unsigned i = 1, e = StructT->getNumElements(); i != e; ++i)
65       if (StructT->getElementType(i) != StructT->getElementType(0))
66         return false;
67     return isSupportedType(DL, TLI, StructT->getElementType(0));
68   }
69 
70   EVT VT = TLI.getValueType(DL, T, true);
71   if (!VT.isSimple() || VT.isVector() ||
72       !(VT.isInteger() || VT.isFloatingPoint()))
73     return false;
74 
75   unsigned VTSize = VT.getSimpleVT().getSizeInBits();
76 
77   if (VTSize == 64)
78     // FIXME: Support i64 too
79     return VT.isFloatingPoint();
80 
81   return VTSize == 1 || VTSize == 8 || VTSize == 16 || VTSize == 32;
82 }
83 
84 namespace {
85 
86 /// Helper class for values going out through an ABI boundary (used for handling
87 /// function return values and call parameters).
88 struct OutgoingValueHandler : public CallLowering::ValueHandler {
89   OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
90                        MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
91       : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
92 
93   Register getStackAddress(uint64_t Size, int64_t Offset,
94                            MachinePointerInfo &MPO) override {
95     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
96            "Unsupported size");
97 
98     LLT p0 = LLT::pointer(0, 32);
99     LLT s32 = LLT::scalar(32);
100     Register SPReg = MRI.createGenericVirtualRegister(p0);
101     MIRBuilder.buildCopy(SPReg, Register(ARM::SP));
102 
103     Register OffsetReg = MRI.createGenericVirtualRegister(s32);
104     MIRBuilder.buildConstant(OffsetReg, Offset);
105 
106     Register AddrReg = MRI.createGenericVirtualRegister(p0);
107     MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
108 
109     MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
110     return AddrReg;
111   }
112 
113   void assignValueToReg(Register ValVReg, Register PhysReg,
114                         CCValAssign &VA) override {
115     assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
116     assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
117 
118     assert(VA.getValVT().getSizeInBits() <= 64 && "Unsupported value size");
119     assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size");
120 
121     Register ExtReg = extendRegister(ValVReg, VA);
122     MIRBuilder.buildCopy(PhysReg, ExtReg);
123     MIB.addUse(PhysReg, RegState::Implicit);
124   }
125 
126   void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
127                             MachinePointerInfo &MPO, CCValAssign &VA) override {
128     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
129            "Unsupported size");
130 
131     Register ExtReg = extendRegister(ValVReg, VA);
132     auto MMO = MIRBuilder.getMF().getMachineMemOperand(
133         MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(),
134         /* Alignment */ 1);
135     MIRBuilder.buildStore(ExtReg, Addr, *MMO);
136   }
137 
138   unsigned assignCustomValue(const CallLowering::ArgInfo &Arg,
139                              ArrayRef<CCValAssign> VAs) override {
140     assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
141 
142     CCValAssign VA = VAs[0];
143     assert(VA.needsCustom() && "Value doesn't need custom handling");
144     assert(VA.getValVT() == MVT::f64 && "Unsupported type");
145 
146     CCValAssign NextVA = VAs[1];
147     assert(NextVA.needsCustom() && "Value doesn't need custom handling");
148     assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
149 
150     assert(VA.getValNo() == NextVA.getValNo() &&
151            "Values belong to different arguments");
152 
153     assert(VA.isRegLoc() && "Value should be in reg");
154     assert(NextVA.isRegLoc() && "Value should be in reg");
155 
156     Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
157                           MRI.createGenericVirtualRegister(LLT::scalar(32))};
158     MIRBuilder.buildUnmerge(NewRegs, Arg.Regs[0]);
159 
160     bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
161     if (!IsLittle)
162       std::swap(NewRegs[0], NewRegs[1]);
163 
164     assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
165     assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
166 
167     return 1;
168   }
169 
170   bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
171                  CCValAssign::LocInfo LocInfo,
172                  const CallLowering::ArgInfo &Info, CCState &State) override {
173     if (AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State))
174       return true;
175 
176     StackSize =
177         std::max(StackSize, static_cast<uint64_t>(State.getNextStackOffset()));
178     return false;
179   }
180 
181   MachineInstrBuilder &MIB;
182   uint64_t StackSize = 0;
183 };
184 
185 } // end anonymous namespace
186 
187 void ARMCallLowering::splitToValueTypes(
188     const ArgInfo &OrigArg, SmallVectorImpl<ArgInfo> &SplitArgs,
189     MachineFunction &MF, const SplitArgTy &PerformArgSplit) const {
190   const ARMTargetLowering &TLI = *getTLI<ARMTargetLowering>();
191   LLVMContext &Ctx = OrigArg.Ty->getContext();
192   const DataLayout &DL = MF.getDataLayout();
193   MachineRegisterInfo &MRI = MF.getRegInfo();
194   const Function &F = MF.getFunction();
195 
196   SmallVector<EVT, 4> SplitVTs;
197   ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, nullptr, nullptr, 0);
198 
199   if (SplitVTs.size() == 1) {
200     // Even if there is no splitting to do, we still want to replace the
201     // original type (e.g. pointer type -> integer).
202     assert(OrigArg.Regs.size() == 1 && "Regs / types mismatch");
203     auto Flags = OrigArg.Flags;
204     unsigned OriginalAlignment = DL.getABITypeAlignment(OrigArg.Ty);
205     Flags.setOrigAlign(OriginalAlignment);
206     SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),
207                            Flags, OrigArg.IsFixed);
208     return;
209   }
210 
211   if (OrigArg.Regs.size() > 1) {
212     // Create one ArgInfo for each virtual register.
213     assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch");
214     for (unsigned i = 0, e = SplitVTs.size(); i != e; ++i) {
215       EVT SplitVT = SplitVTs[i];
216       Type *SplitTy = SplitVT.getTypeForEVT(Ctx);
217       auto Flags = OrigArg.Flags;
218 
219       unsigned OriginalAlignment = DL.getABITypeAlignment(SplitTy);
220       Flags.setOrigAlign(OriginalAlignment);
221 
222       bool NeedsConsecutiveRegisters =
223           TLI.functionArgumentNeedsConsecutiveRegisters(
224               SplitTy, F.getCallingConv(), F.isVarArg());
225       if (NeedsConsecutiveRegisters) {
226         Flags.setInConsecutiveRegs();
227         if (i == e - 1)
228           Flags.setInConsecutiveRegsLast();
229       }
230 
231       // FIXME: We also want to split SplitTy further.
232       Register PartReg = OrigArg.Regs[i];
233       SplitArgs.emplace_back(PartReg, SplitTy, Flags, OrigArg.IsFixed);
234     }
235 
236     return;
237   }
238 
239   for (unsigned i = 0, e = SplitVTs.size(); i != e; ++i) {
240     EVT SplitVT = SplitVTs[i];
241     Type *SplitTy = SplitVT.getTypeForEVT(Ctx);
242     auto Flags = OrigArg.Flags;
243 
244     unsigned OriginalAlignment = DL.getABITypeAlignment(SplitTy);
245     Flags.setOrigAlign(OriginalAlignment);
246 
247     bool NeedsConsecutiveRegisters =
248         TLI.functionArgumentNeedsConsecutiveRegisters(
249             SplitTy, F.getCallingConv(), F.isVarArg());
250     if (NeedsConsecutiveRegisters) {
251       Flags.setInConsecutiveRegs();
252       if (i == e - 1)
253         Flags.setInConsecutiveRegsLast();
254     }
255 
256     Register PartReg =
257         MRI.createGenericVirtualRegister(getLLTForType(*SplitTy, DL));
258     SplitArgs.push_back(ArgInfo{PartReg, SplitTy, Flags, OrigArg.IsFixed});
259     PerformArgSplit(PartReg);
260   }
261 }
262 
263 /// Lower the return value for the already existing \p Ret. This assumes that
264 /// \p MIRBuilder's insertion point is correct.
265 bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
266                                      const Value *Val, ArrayRef<Register> VRegs,
267                                      MachineInstrBuilder &Ret) const {
268   if (!Val)
269     // Nothing to do here.
270     return true;
271 
272   auto &MF = MIRBuilder.getMF();
273   const auto &F = MF.getFunction();
274 
275   auto DL = MF.getDataLayout();
276   auto &TLI = *getTLI<ARMTargetLowering>();
277   if (!isSupportedType(DL, TLI, Val->getType()))
278     return false;
279 
280   SmallVector<EVT, 4> SplitEVTs;
281   ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
282   assert(VRegs.size() == SplitEVTs.size() &&
283          "For each split Type there should be exactly one VReg.");
284 
285   SmallVector<ArgInfo, 4> SplitVTs;
286   LLVMContext &Ctx = Val->getType()->getContext();
287   for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
288     ArgInfo CurArgInfo(VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx));
289     setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
290 
291     SmallVector<Register, 4> Regs;
292     splitToValueTypes(CurArgInfo, SplitVTs, MF,
293                       [&](Register Reg) { Regs.push_back(Reg); });
294     if (Regs.size() > 1)
295       MIRBuilder.buildUnmerge(Regs, VRegs[i]);
296   }
297 
298   CCAssignFn *AssignFn =
299       TLI.CCAssignFnForReturn(F.getCallingConv(), F.isVarArg());
300 
301   OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret, AssignFn);
302   return handleAssignments(MIRBuilder, SplitVTs, RetHandler);
303 }
304 
305 bool ARMCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
306                                   const Value *Val,
307                                   ArrayRef<Register> VRegs) const {
308   assert(!Val == VRegs.empty() && "Return value without a vreg");
309 
310   auto const &ST = MIRBuilder.getMF().getSubtarget<ARMSubtarget>();
311   unsigned Opcode = ST.getReturnOpcode();
312   auto Ret = MIRBuilder.buildInstrNoInsert(Opcode).add(predOps(ARMCC::AL));
313 
314   if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret))
315     return false;
316 
317   MIRBuilder.insertInstr(Ret);
318   return true;
319 }
320 
321 namespace {
322 
323 /// Helper class for values coming in through an ABI boundary (used for handling
324 /// formal arguments and call return values).
325 struct IncomingValueHandler : public CallLowering::ValueHandler {
326   IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
327                        CCAssignFn AssignFn)
328       : ValueHandler(MIRBuilder, MRI, AssignFn) {}
329 
330   bool isArgumentHandler() const override { return true; }
331 
332   Register getStackAddress(uint64_t Size, int64_t Offset,
333                            MachinePointerInfo &MPO) override {
334     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
335            "Unsupported size");
336 
337     auto &MFI = MIRBuilder.getMF().getFrameInfo();
338 
339     int FI = MFI.CreateFixedObject(Size, Offset, true);
340     MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
341 
342     unsigned AddrReg =
343         MRI.createGenericVirtualRegister(LLT::pointer(MPO.getAddrSpace(), 32));
344     MIRBuilder.buildFrameIndex(AddrReg, FI);
345 
346     return AddrReg;
347   }
348 
349   void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
350                             MachinePointerInfo &MPO, CCValAssign &VA) override {
351     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
352            "Unsupported size");
353 
354     if (VA.getLocInfo() == CCValAssign::SExt ||
355         VA.getLocInfo() == CCValAssign::ZExt) {
356       // If the value is zero- or sign-extended, its size becomes 4 bytes, so
357       // that's what we should load.
358       Size = 4;
359       assert(MRI.getType(ValVReg).isScalar() && "Only scalars supported atm");
360 
361       auto LoadVReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
362       buildLoad(LoadVReg, Addr, Size, /* Alignment */ 1, MPO);
363       MIRBuilder.buildTrunc(ValVReg, LoadVReg);
364     } else {
365       // If the value is not extended, a simple load will suffice.
366       buildLoad(ValVReg, Addr, Size, /* Alignment */ 1, MPO);
367     }
368   }
369 
370   void buildLoad(Register Val, Register Addr, uint64_t Size, unsigned Alignment,
371                  MachinePointerInfo &MPO) {
372     auto MMO = MIRBuilder.getMF().getMachineMemOperand(
373         MPO, MachineMemOperand::MOLoad, Size, Alignment);
374     MIRBuilder.buildLoad(Val, Addr, *MMO);
375   }
376 
377   void assignValueToReg(Register ValVReg, Register PhysReg,
378                         CCValAssign &VA) override {
379     assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
380     assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
381 
382     auto ValSize = VA.getValVT().getSizeInBits();
383     auto LocSize = VA.getLocVT().getSizeInBits();
384 
385     assert(ValSize <= 64 && "Unsupported value size");
386     assert(LocSize <= 64 && "Unsupported location size");
387 
388     markPhysRegUsed(PhysReg);
389     if (ValSize == LocSize) {
390       MIRBuilder.buildCopy(ValVReg, PhysReg);
391     } else {
392       assert(ValSize < LocSize && "Extensions not supported");
393 
394       // We cannot create a truncating copy, nor a trunc of a physical register.
395       // Therefore, we need to copy the content of the physical register into a
396       // virtual one and then truncate that.
397       auto PhysRegToVReg =
398           MRI.createGenericVirtualRegister(LLT::scalar(LocSize));
399       MIRBuilder.buildCopy(PhysRegToVReg, PhysReg);
400       MIRBuilder.buildTrunc(ValVReg, PhysRegToVReg);
401     }
402   }
403 
404   unsigned assignCustomValue(const ARMCallLowering::ArgInfo &Arg,
405                              ArrayRef<CCValAssign> VAs) override {
406     assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
407 
408     CCValAssign VA = VAs[0];
409     assert(VA.needsCustom() && "Value doesn't need custom handling");
410     assert(VA.getValVT() == MVT::f64 && "Unsupported type");
411 
412     CCValAssign NextVA = VAs[1];
413     assert(NextVA.needsCustom() && "Value doesn't need custom handling");
414     assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
415 
416     assert(VA.getValNo() == NextVA.getValNo() &&
417            "Values belong to different arguments");
418 
419     assert(VA.isRegLoc() && "Value should be in reg");
420     assert(NextVA.isRegLoc() && "Value should be in reg");
421 
422     Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
423                           MRI.createGenericVirtualRegister(LLT::scalar(32))};
424 
425     assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
426     assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
427 
428     bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
429     if (!IsLittle)
430       std::swap(NewRegs[0], NewRegs[1]);
431 
432     MIRBuilder.buildMerge(Arg.Regs[0], NewRegs);
433 
434     return 1;
435   }
436 
437   /// Marking a physical register as used is different between formal
438   /// parameters, where it's a basic block live-in, and call returns, where it's
439   /// an implicit-def of the call instruction.
440   virtual void markPhysRegUsed(unsigned PhysReg) = 0;
441 };
442 
443 struct FormalArgHandler : public IncomingValueHandler {
444   FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
445                    CCAssignFn AssignFn)
446       : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
447 
448   void markPhysRegUsed(unsigned PhysReg) override {
449     MIRBuilder.getMBB().addLiveIn(PhysReg);
450   }
451 };
452 
453 } // end anonymous namespace
454 
455 bool ARMCallLowering::lowerFormalArguments(
456     MachineIRBuilder &MIRBuilder, const Function &F,
457     ArrayRef<ArrayRef<Register>> VRegs) const {
458   auto &TLI = *getTLI<ARMTargetLowering>();
459   auto Subtarget = TLI.getSubtarget();
460 
461   if (Subtarget->isThumb1Only())
462     return false;
463 
464   // Quick exit if there aren't any args
465   if (F.arg_empty())
466     return true;
467 
468   if (F.isVarArg())
469     return false;
470 
471   auto &MF = MIRBuilder.getMF();
472   auto &MBB = MIRBuilder.getMBB();
473   auto DL = MF.getDataLayout();
474 
475   for (auto &Arg : F.args()) {
476     if (!isSupportedType(DL, TLI, Arg.getType()))
477       return false;
478     if (Arg.hasByValOrInAllocaAttr())
479       return false;
480   }
481 
482   CCAssignFn *AssignFn =
483       TLI.CCAssignFnForCall(F.getCallingConv(), F.isVarArg());
484 
485   FormalArgHandler ArgHandler(MIRBuilder, MIRBuilder.getMF().getRegInfo(),
486                               AssignFn);
487 
488   SmallVector<ArgInfo, 8> SplitArgInfos;
489   unsigned Idx = 0;
490   for (auto &Arg : F.args()) {
491     ArgInfo OrigArgInfo(VRegs[Idx], Arg.getType());
492     setArgFlags(OrigArgInfo, Idx + AttributeList::FirstArgIndex, DL, F);
493 
494     splitToValueTypes(OrigArgInfo, SplitArgInfos, MF, [&](Register Reg) {
495       llvm_unreachable("Args should already be split");
496     });
497 
498     Idx++;
499   }
500 
501   if (!MBB.empty())
502     MIRBuilder.setInstr(*MBB.begin());
503 
504   if (!handleAssignments(MIRBuilder, SplitArgInfos, ArgHandler))
505     return false;
506 
507   // Move back to the end of the basic block.
508   MIRBuilder.setMBB(MBB);
509   return true;
510 }
511 
512 namespace {
513 
514 struct CallReturnHandler : public IncomingValueHandler {
515   CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
516                     MachineInstrBuilder MIB, CCAssignFn *AssignFn)
517       : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
518 
519   void markPhysRegUsed(unsigned PhysReg) override {
520     MIB.addDef(PhysReg, RegState::Implicit);
521   }
522 
523   MachineInstrBuilder MIB;
524 };
525 
526 // FIXME: This should move to the ARMSubtarget when it supports all the opcodes.
527 unsigned getCallOpcode(const ARMSubtarget &STI, bool isDirect) {
528   if (isDirect)
529     return STI.isThumb() ? ARM::tBL : ARM::BL;
530 
531   if (STI.isThumb())
532     return ARM::tBLXr;
533 
534   if (STI.hasV5TOps())
535     return ARM::BLX;
536 
537   if (STI.hasV4TOps())
538     return ARM::BX_CALL;
539 
540   return ARM::BMOVPCRX_CALL;
541 }
542 } // end anonymous namespace
543 
544 bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
545                                 CallingConv::ID CallConv,
546                                 const MachineOperand &Callee,
547                                 const ArgInfo &OrigRet,
548                                 ArrayRef<ArgInfo> OrigArgs) const {
549   MachineFunction &MF = MIRBuilder.getMF();
550   const auto &TLI = *getTLI<ARMTargetLowering>();
551   const auto &DL = MF.getDataLayout();
552   const auto &STI = MF.getSubtarget<ARMSubtarget>();
553   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
554   MachineRegisterInfo &MRI = MF.getRegInfo();
555 
556   if (STI.genLongCalls())
557     return false;
558 
559   if (STI.isThumb1Only())
560     return false;
561 
562   auto CallSeqStart = MIRBuilder.buildInstr(ARM::ADJCALLSTACKDOWN);
563 
564   // Create the call instruction so we can add the implicit uses of arg
565   // registers, but don't insert it yet.
566   bool IsDirect = !Callee.isReg();
567   auto CallOpcode = getCallOpcode(STI, IsDirect);
568   auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode);
569 
570   bool IsThumb = STI.isThumb();
571   if (IsThumb)
572     MIB.add(predOps(ARMCC::AL));
573 
574   MIB.add(Callee);
575   if (!IsDirect) {
576     auto CalleeReg = Callee.getReg();
577     if (CalleeReg && !TRI->isPhysicalRegister(CalleeReg)) {
578       unsigned CalleeIdx = IsThumb ? 2 : 0;
579       MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass(
580           MF, *TRI, MRI, *STI.getInstrInfo(), *STI.getRegBankInfo(),
581           *MIB.getInstr(), MIB->getDesc(), Callee, CalleeIdx));
582     }
583   }
584 
585   MIB.addRegMask(TRI->getCallPreservedMask(MF, CallConv));
586 
587   bool IsVarArg = false;
588   SmallVector<ArgInfo, 8> ArgInfos;
589   for (auto Arg : OrigArgs) {
590     if (!isSupportedType(DL, TLI, Arg.Ty))
591       return false;
592 
593     if (!Arg.IsFixed)
594       IsVarArg = true;
595 
596     if (Arg.Flags.isByVal())
597       return false;
598 
599     splitToValueTypes(Arg, ArgInfos, MF, [&](Register Reg) {
600       llvm_unreachable("Function args should already be split");
601     });
602   }
603 
604   auto ArgAssignFn = TLI.CCAssignFnForCall(CallConv, IsVarArg);
605   OutgoingValueHandler ArgHandler(MIRBuilder, MRI, MIB, ArgAssignFn);
606   if (!handleAssignments(MIRBuilder, ArgInfos, ArgHandler))
607     return false;
608 
609   // Now we can add the actual call instruction to the correct basic block.
610   MIRBuilder.insertInstr(MIB);
611 
612   if (!OrigRet.Ty->isVoidTy()) {
613     if (!isSupportedType(DL, TLI, OrigRet.Ty))
614       return false;
615 
616     ArgInfos.clear();
617     splitToValueTypes(OrigRet, ArgInfos, MF, [&](Register Reg) {
618       llvm_unreachable("Call results should already be split");
619     });
620 
621     auto RetAssignFn = TLI.CCAssignFnForReturn(CallConv, IsVarArg);
622     CallReturnHandler RetHandler(MIRBuilder, MRI, MIB, RetAssignFn);
623     if (!handleAssignments(MIRBuilder, ArgInfos, RetHandler))
624       return false;
625   }
626 
627   // We now know the size of the stack - update the ADJCALLSTACKDOWN
628   // accordingly.
629   CallSeqStart.addImm(ArgHandler.StackSize).addImm(0).add(predOps(ARMCC::AL));
630 
631   MIRBuilder.buildInstr(ARM::ADJCALLSTACKUP)
632       .addImm(ArgHandler.StackSize)
633       .addImm(0)
634       .add(predOps(ARMCC::AL));
635 
636   return true;
637 }
638