1 //===- llvm/lib/Target/ARM/ARMCallLowering.cpp - Call lowering ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "ARMCallLowering.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMISelLowering.h"
18 #include "ARMSubtarget.h"
19 #include "Utils/ARMBaseInfo.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/Analysis.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
24 #include "llvm/CodeGen/GlobalISel/Utils.h"
25 #include "llvm/CodeGen/LowLevelType.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineOperand.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/TargetRegisterInfo.h"
34 #include "llvm/CodeGen/TargetSubtargetInfo.h"
35 #include "llvm/CodeGen/ValueTypes.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/DataLayout.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/Type.h"
41 #include "llvm/IR/Value.h"
42 #include "llvm/Support/Casting.h"
43 #include "llvm/Support/LowLevelTypeImpl.h"
44 #include "llvm/Support/MachineValueType.h"
45 #include <algorithm>
46 #include <cassert>
47 #include <cstdint>
48 #include <utility>
49 
50 using namespace llvm;
51 
52 ARMCallLowering::ARMCallLowering(const ARMTargetLowering &TLI)
53     : CallLowering(&TLI) {}
54 
55 static bool isSupportedType(const DataLayout &DL, const ARMTargetLowering &TLI,
56                             Type *T) {
57   if (T->isArrayTy())
58     return isSupportedType(DL, TLI, T->getArrayElementType());
59 
60   if (T->isStructTy()) {
61     // For now we only allow homogeneous structs that we can manipulate with
62     // G_MERGE_VALUES and G_UNMERGE_VALUES
63     auto StructT = cast<StructType>(T);
64     for (unsigned i = 1, e = StructT->getNumElements(); i != e; ++i)
65       if (StructT->getElementType(i) != StructT->getElementType(0))
66         return false;
67     return isSupportedType(DL, TLI, StructT->getElementType(0));
68   }
69 
70   EVT VT = TLI.getValueType(DL, T, true);
71   if (!VT.isSimple() || VT.isVector() ||
72       !(VT.isInteger() || VT.isFloatingPoint()))
73     return false;
74 
75   unsigned VTSize = VT.getSimpleVT().getSizeInBits();
76 
77   if (VTSize == 64)
78     // FIXME: Support i64 too
79     return VT.isFloatingPoint();
80 
81   return VTSize == 1 || VTSize == 8 || VTSize == 16 || VTSize == 32;
82 }
83 
84 namespace {
85 
86 /// Helper class for values going out through an ABI boundary (used for handling
87 /// function return values and call parameters).
88 struct OutgoingValueHandler : public CallLowering::ValueHandler {
89   OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
90                        MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
91       : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
92 
93   bool isIncomingArgumentHandler() const override { return false; }
94 
95   Register getStackAddress(uint64_t Size, int64_t Offset,
96                            MachinePointerInfo &MPO) override {
97     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
98            "Unsupported size");
99 
100     LLT p0 = LLT::pointer(0, 32);
101     LLT s32 = LLT::scalar(32);
102     auto SPReg = MIRBuilder.buildCopy(p0, Register(ARM::SP));
103 
104     auto OffsetReg = MIRBuilder.buildConstant(s32, Offset);
105 
106     auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
107 
108     MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
109     return AddrReg.getReg(0);
110   }
111 
112   void assignValueToReg(Register ValVReg, Register PhysReg,
113                         CCValAssign &VA) override {
114     assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
115     assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
116 
117     assert(VA.getValVT().getSizeInBits() <= 64 && "Unsupported value size");
118     assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size");
119 
120     Register ExtReg = extendRegister(ValVReg, VA);
121     MIRBuilder.buildCopy(PhysReg, ExtReg);
122     MIB.addUse(PhysReg, RegState::Implicit);
123   }
124 
125   void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
126                             MachinePointerInfo &MPO, CCValAssign &VA) override {
127     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
128            "Unsupported size");
129 
130     Register ExtReg = extendRegister(ValVReg, VA);
131     auto MMO = MIRBuilder.getMF().getMachineMemOperand(
132         MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(),
133         /* Alignment */ 1);
134     MIRBuilder.buildStore(ExtReg, Addr, *MMO);
135   }
136 
137   unsigned assignCustomValue(const CallLowering::ArgInfo &Arg,
138                              ArrayRef<CCValAssign> VAs) override {
139     assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
140 
141     CCValAssign VA = VAs[0];
142     assert(VA.needsCustom() && "Value doesn't need custom handling");
143     assert(VA.getValVT() == MVT::f64 && "Unsupported type");
144 
145     CCValAssign NextVA = VAs[1];
146     assert(NextVA.needsCustom() && "Value doesn't need custom handling");
147     assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
148 
149     assert(VA.getValNo() == NextVA.getValNo() &&
150            "Values belong to different arguments");
151 
152     assert(VA.isRegLoc() && "Value should be in reg");
153     assert(NextVA.isRegLoc() && "Value should be in reg");
154 
155     Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
156                           MRI.createGenericVirtualRegister(LLT::scalar(32))};
157     MIRBuilder.buildUnmerge(NewRegs, Arg.Regs[0]);
158 
159     bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
160     if (!IsLittle)
161       std::swap(NewRegs[0], NewRegs[1]);
162 
163     assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
164     assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
165 
166     return 1;
167   }
168 
169   bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
170                  CCValAssign::LocInfo LocInfo,
171                  const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
172                  CCState &State) override {
173     if (AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State))
174       return true;
175 
176     StackSize =
177         std::max(StackSize, static_cast<uint64_t>(State.getNextStackOffset()));
178     return false;
179   }
180 
181   MachineInstrBuilder &MIB;
182   uint64_t StackSize = 0;
183 };
184 
185 } // end anonymous namespace
186 
187 void ARMCallLowering::splitToValueTypes(const ArgInfo &OrigArg,
188                                         SmallVectorImpl<ArgInfo> &SplitArgs,
189                                         MachineFunction &MF) const {
190   const ARMTargetLowering &TLI = *getTLI<ARMTargetLowering>();
191   LLVMContext &Ctx = OrigArg.Ty->getContext();
192   const DataLayout &DL = MF.getDataLayout();
193   const Function &F = MF.getFunction();
194 
195   SmallVector<EVT, 4> SplitVTs;
196   ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, nullptr, nullptr, 0);
197   assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch");
198 
199   if (SplitVTs.size() == 1) {
200     // Even if there is no splitting to do, we still want to replace the
201     // original type (e.g. pointer type -> integer).
202     auto Flags = OrigArg.Flags[0];
203     Flags.setOrigAlign(Align(DL.getABITypeAlignment(OrigArg.Ty)));
204     SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),
205                            Flags, OrigArg.IsFixed);
206     return;
207   }
208 
209   // Create one ArgInfo for each virtual register.
210   for (unsigned i = 0, e = SplitVTs.size(); i != e; ++i) {
211     EVT SplitVT = SplitVTs[i];
212     Type *SplitTy = SplitVT.getTypeForEVT(Ctx);
213     auto Flags = OrigArg.Flags[0];
214 
215     Flags.setOrigAlign(Align(DL.getABITypeAlignment(SplitTy)));
216 
217     bool NeedsConsecutiveRegisters =
218         TLI.functionArgumentNeedsConsecutiveRegisters(
219             SplitTy, F.getCallingConv(), F.isVarArg());
220     if (NeedsConsecutiveRegisters) {
221       Flags.setInConsecutiveRegs();
222       if (i == e - 1)
223         Flags.setInConsecutiveRegsLast();
224     }
225 
226     // FIXME: We also want to split SplitTy further.
227     Register PartReg = OrigArg.Regs[i];
228     SplitArgs.emplace_back(PartReg, SplitTy, Flags, OrigArg.IsFixed);
229   }
230 }
231 
232 /// Lower the return value for the already existing \p Ret. This assumes that
233 /// \p MIRBuilder's insertion point is correct.
234 bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
235                                      const Value *Val, ArrayRef<Register> VRegs,
236                                      MachineInstrBuilder &Ret) const {
237   if (!Val)
238     // Nothing to do here.
239     return true;
240 
241   auto &MF = MIRBuilder.getMF();
242   const auto &F = MF.getFunction();
243 
244   auto DL = MF.getDataLayout();
245   auto &TLI = *getTLI<ARMTargetLowering>();
246   if (!isSupportedType(DL, TLI, Val->getType()))
247     return false;
248 
249   ArgInfo OrigRetInfo(VRegs, Val->getType());
250   setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F);
251 
252   SmallVector<ArgInfo, 4> SplitRetInfos;
253   splitToValueTypes(OrigRetInfo, SplitRetInfos, MF);
254 
255   CCAssignFn *AssignFn =
256       TLI.CCAssignFnForReturn(F.getCallingConv(), F.isVarArg());
257 
258   OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret, AssignFn);
259   return handleAssignments(MIRBuilder, SplitRetInfos, RetHandler);
260 }
261 
262 bool ARMCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
263                                   const Value *Val,
264                                   ArrayRef<Register> VRegs) const {
265   assert(!Val == VRegs.empty() && "Return value without a vreg");
266 
267   auto const &ST = MIRBuilder.getMF().getSubtarget<ARMSubtarget>();
268   unsigned Opcode = ST.getReturnOpcode();
269   auto Ret = MIRBuilder.buildInstrNoInsert(Opcode).add(predOps(ARMCC::AL));
270 
271   if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret))
272     return false;
273 
274   MIRBuilder.insertInstr(Ret);
275   return true;
276 }
277 
278 namespace {
279 
280 /// Helper class for values coming in through an ABI boundary (used for handling
281 /// formal arguments and call return values).
282 struct IncomingValueHandler : public CallLowering::ValueHandler {
283   IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
284                        CCAssignFn AssignFn)
285       : ValueHandler(MIRBuilder, MRI, AssignFn) {}
286 
287   bool isIncomingArgumentHandler() const override { return true; }
288 
289   Register getStackAddress(uint64_t Size, int64_t Offset,
290                            MachinePointerInfo &MPO) override {
291     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
292            "Unsupported size");
293 
294     auto &MFI = MIRBuilder.getMF().getFrameInfo();
295 
296     int FI = MFI.CreateFixedObject(Size, Offset, true);
297     MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
298 
299     return MIRBuilder.buildFrameIndex(LLT::pointer(MPO.getAddrSpace(), 32), FI)
300         .getReg(0);
301   }
302 
303   void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
304                             MachinePointerInfo &MPO, CCValAssign &VA) override {
305     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
306            "Unsupported size");
307 
308     if (VA.getLocInfo() == CCValAssign::SExt ||
309         VA.getLocInfo() == CCValAssign::ZExt) {
310       // If the value is zero- or sign-extended, its size becomes 4 bytes, so
311       // that's what we should load.
312       Size = 4;
313       assert(MRI.getType(ValVReg).isScalar() && "Only scalars supported atm");
314 
315       auto LoadVReg = buildLoad(LLT::scalar(32), Addr, Size, MPO);
316       MIRBuilder.buildTrunc(ValVReg, LoadVReg);
317     } else {
318       // If the value is not extended, a simple load will suffice.
319       buildLoad(ValVReg, Addr, Size, MPO);
320     }
321   }
322 
323   MachineInstrBuilder buildLoad(const DstOp &Res, Register Addr, uint64_t Size,
324                                 MachinePointerInfo &MPO) {
325     MachineFunction &MF = MIRBuilder.getMF();
326     unsigned Alignment = inferAlignmentFromPtrInfo(MF, MPO);
327 
328     auto MMO = MF.getMachineMemOperand(
329         MPO, MachineMemOperand::MOLoad, Size, Alignment);
330     return MIRBuilder.buildLoad(Res, Addr, *MMO);
331   }
332 
333   void assignValueToReg(Register ValVReg, Register PhysReg,
334                         CCValAssign &VA) override {
335     assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
336     assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
337 
338     auto ValSize = VA.getValVT().getSizeInBits();
339     auto LocSize = VA.getLocVT().getSizeInBits();
340 
341     assert(ValSize <= 64 && "Unsupported value size");
342     assert(LocSize <= 64 && "Unsupported location size");
343 
344     markPhysRegUsed(PhysReg);
345     if (ValSize == LocSize) {
346       MIRBuilder.buildCopy(ValVReg, PhysReg);
347     } else {
348       assert(ValSize < LocSize && "Extensions not supported");
349 
350       // We cannot create a truncating copy, nor a trunc of a physical register.
351       // Therefore, we need to copy the content of the physical register into a
352       // virtual one and then truncate that.
353       auto PhysRegToVReg = MIRBuilder.buildCopy(LLT::scalar(LocSize), PhysReg);
354       MIRBuilder.buildTrunc(ValVReg, PhysRegToVReg);
355     }
356   }
357 
358   unsigned assignCustomValue(const ARMCallLowering::ArgInfo &Arg,
359                              ArrayRef<CCValAssign> VAs) override {
360     assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
361 
362     CCValAssign VA = VAs[0];
363     assert(VA.needsCustom() && "Value doesn't need custom handling");
364     assert(VA.getValVT() == MVT::f64 && "Unsupported type");
365 
366     CCValAssign NextVA = VAs[1];
367     assert(NextVA.needsCustom() && "Value doesn't need custom handling");
368     assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
369 
370     assert(VA.getValNo() == NextVA.getValNo() &&
371            "Values belong to different arguments");
372 
373     assert(VA.isRegLoc() && "Value should be in reg");
374     assert(NextVA.isRegLoc() && "Value should be in reg");
375 
376     Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
377                           MRI.createGenericVirtualRegister(LLT::scalar(32))};
378 
379     assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
380     assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
381 
382     bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
383     if (!IsLittle)
384       std::swap(NewRegs[0], NewRegs[1]);
385 
386     MIRBuilder.buildMerge(Arg.Regs[0], NewRegs);
387 
388     return 1;
389   }
390 
391   /// Marking a physical register as used is different between formal
392   /// parameters, where it's a basic block live-in, and call returns, where it's
393   /// an implicit-def of the call instruction.
394   virtual void markPhysRegUsed(unsigned PhysReg) = 0;
395 };
396 
397 struct FormalArgHandler : public IncomingValueHandler {
398   FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
399                    CCAssignFn AssignFn)
400       : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
401 
402   void markPhysRegUsed(unsigned PhysReg) override {
403     MIRBuilder.getMRI()->addLiveIn(PhysReg);
404     MIRBuilder.getMBB().addLiveIn(PhysReg);
405   }
406 };
407 
408 } // end anonymous namespace
409 
410 bool ARMCallLowering::lowerFormalArguments(
411     MachineIRBuilder &MIRBuilder, const Function &F,
412     ArrayRef<ArrayRef<Register>> VRegs) const {
413   auto &TLI = *getTLI<ARMTargetLowering>();
414   auto Subtarget = TLI.getSubtarget();
415 
416   if (Subtarget->isThumb1Only())
417     return false;
418 
419   // Quick exit if there aren't any args
420   if (F.arg_empty())
421     return true;
422 
423   if (F.isVarArg())
424     return false;
425 
426   auto &MF = MIRBuilder.getMF();
427   auto &MBB = MIRBuilder.getMBB();
428   auto DL = MF.getDataLayout();
429 
430   for (auto &Arg : F.args()) {
431     if (!isSupportedType(DL, TLI, Arg.getType()))
432       return false;
433     if (Arg.hasByValOrInAllocaAttr())
434       return false;
435   }
436 
437   CCAssignFn *AssignFn =
438       TLI.CCAssignFnForCall(F.getCallingConv(), F.isVarArg());
439 
440   FormalArgHandler ArgHandler(MIRBuilder, MIRBuilder.getMF().getRegInfo(),
441                               AssignFn);
442 
443   SmallVector<ArgInfo, 8> SplitArgInfos;
444   unsigned Idx = 0;
445   for (auto &Arg : F.args()) {
446     ArgInfo OrigArgInfo(VRegs[Idx], Arg.getType());
447 
448     setArgFlags(OrigArgInfo, Idx + AttributeList::FirstArgIndex, DL, F);
449     splitToValueTypes(OrigArgInfo, SplitArgInfos, MF);
450 
451     Idx++;
452   }
453 
454   if (!MBB.empty())
455     MIRBuilder.setInstr(*MBB.begin());
456 
457   if (!handleAssignments(MIRBuilder, SplitArgInfos, ArgHandler))
458     return false;
459 
460   // Move back to the end of the basic block.
461   MIRBuilder.setMBB(MBB);
462   return true;
463 }
464 
465 namespace {
466 
467 struct CallReturnHandler : public IncomingValueHandler {
468   CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
469                     MachineInstrBuilder MIB, CCAssignFn *AssignFn)
470       : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
471 
472   void markPhysRegUsed(unsigned PhysReg) override {
473     MIB.addDef(PhysReg, RegState::Implicit);
474   }
475 
476   MachineInstrBuilder MIB;
477 };
478 
479 // FIXME: This should move to the ARMSubtarget when it supports all the opcodes.
480 unsigned getCallOpcode(const ARMSubtarget &STI, bool isDirect) {
481   if (isDirect)
482     return STI.isThumb() ? ARM::tBL : ARM::BL;
483 
484   if (STI.isThumb())
485     return ARM::tBLXr;
486 
487   if (STI.hasV5TOps())
488     return ARM::BLX;
489 
490   if (STI.hasV4TOps())
491     return ARM::BX_CALL;
492 
493   return ARM::BMOVPCRX_CALL;
494 }
495 } // end anonymous namespace
496 
497 bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const {
498   MachineFunction &MF = MIRBuilder.getMF();
499   const auto &TLI = *getTLI<ARMTargetLowering>();
500   const auto &DL = MF.getDataLayout();
501   const auto &STI = MF.getSubtarget<ARMSubtarget>();
502   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
503   MachineRegisterInfo &MRI = MF.getRegInfo();
504 
505   if (STI.genLongCalls())
506     return false;
507 
508   if (STI.isThumb1Only())
509     return false;
510 
511   auto CallSeqStart = MIRBuilder.buildInstr(ARM::ADJCALLSTACKDOWN);
512 
513   // Create the call instruction so we can add the implicit uses of arg
514   // registers, but don't insert it yet.
515   bool IsDirect = !Info.Callee.isReg();
516   auto CallOpcode = getCallOpcode(STI, IsDirect);
517   auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode);
518 
519   bool IsThumb = STI.isThumb();
520   if (IsThumb)
521     MIB.add(predOps(ARMCC::AL));
522 
523   MIB.add(Info.Callee);
524   if (!IsDirect) {
525     auto CalleeReg = Info.Callee.getReg();
526     if (CalleeReg && !Register::isPhysicalRegister(CalleeReg)) {
527       unsigned CalleeIdx = IsThumb ? 2 : 0;
528       MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass(
529           MF, *TRI, MRI, *STI.getInstrInfo(), *STI.getRegBankInfo(),
530           *MIB.getInstr(), MIB->getDesc(), Info.Callee, CalleeIdx));
531     }
532   }
533 
534   MIB.addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
535 
536   bool IsVarArg = false;
537   SmallVector<ArgInfo, 8> ArgInfos;
538   for (auto Arg : Info.OrigArgs) {
539     if (!isSupportedType(DL, TLI, Arg.Ty))
540       return false;
541 
542     if (!Arg.IsFixed)
543       IsVarArg = true;
544 
545     if (Arg.Flags[0].isByVal())
546       return false;
547 
548     splitToValueTypes(Arg, ArgInfos, MF);
549   }
550 
551   auto ArgAssignFn = TLI.CCAssignFnForCall(Info.CallConv, IsVarArg);
552   OutgoingValueHandler ArgHandler(MIRBuilder, MRI, MIB, ArgAssignFn);
553   if (!handleAssignments(MIRBuilder, ArgInfos, ArgHandler))
554     return false;
555 
556   // Now we can add the actual call instruction to the correct basic block.
557   MIRBuilder.insertInstr(MIB);
558 
559   if (!Info.OrigRet.Ty->isVoidTy()) {
560     if (!isSupportedType(DL, TLI, Info.OrigRet.Ty))
561       return false;
562 
563     ArgInfos.clear();
564     splitToValueTypes(Info.OrigRet, ArgInfos, MF);
565     auto RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv, IsVarArg);
566     CallReturnHandler RetHandler(MIRBuilder, MRI, MIB, RetAssignFn);
567     if (!handleAssignments(MIRBuilder, ArgInfos, RetHandler))
568       return false;
569   }
570 
571   // We now know the size of the stack - update the ADJCALLSTACKDOWN
572   // accordingly.
573   CallSeqStart.addImm(ArgHandler.StackSize).addImm(0).add(predOps(ARMCC::AL));
574 
575   MIRBuilder.buildInstr(ARM::ADJCALLSTACKUP)
576       .addImm(ArgHandler.StackSize)
577       .addImm(0)
578       .add(predOps(ARMCC::AL));
579 
580   return true;
581 }
582