1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARM.h"
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMFrameLowering.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMSubtarget.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/LLVMContext.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/RegisterScavenging.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/BitVector.h"
40 #include "llvm/ADT/SmallVector.h"
41 #include "llvm/Support/CommandLine.h"
42 
43 using namespace llvm;
44 
45 static cl::opt<bool>
46 ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
47           cl::desc("Force use of virtual base registers for stack load/store"));
48 static cl::opt<bool>
49 EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
50           cl::desc("Enable pre-regalloc stack frame index allocation"));
51 static cl::opt<bool>
52 EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
53           cl::desc("Enable use of a base pointer for complex stack frames"));
54 
55 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
56                                          const ARMSubtarget &sti)
57   : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
58     TII(tii), STI(sti),
59     FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
60     BasePtr(ARM::R6) {
61 }
62 
63 const unsigned*
64 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
65   static const unsigned CalleeSavedRegs[] = {
66     ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
67     ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
68 
69     ARM::D15, ARM::D14, ARM::D13, ARM::D12,
70     ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
71     0
72   };
73 
74   static const unsigned DarwinCalleeSavedRegs[] = {
75     // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
76     // register.
77     ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
78     ARM::R11, ARM::R10, ARM::R8,
79 
80     ARM::D15, ARM::D14, ARM::D13, ARM::D12,
81     ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
82     0
83   };
84   return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
85 }
86 
87 BitVector ARMBaseRegisterInfo::
88 getReservedRegs(const MachineFunction &MF) const {
89   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
90 
91   // FIXME: avoid re-calculating this every time.
92   BitVector Reserved(getNumRegs());
93   Reserved.set(ARM::SP);
94   Reserved.set(ARM::PC);
95   Reserved.set(ARM::FPSCR);
96   if (TFI->hasFP(MF))
97     Reserved.set(FramePtr);
98   if (hasBasePointer(MF))
99     Reserved.set(BasePtr);
100   // Some targets reserve R9.
101   if (STI.isR9Reserved())
102     Reserved.set(ARM::R9);
103   return Reserved;
104 }
105 
106 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
107                                         unsigned Reg) const {
108   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
109 
110   switch (Reg) {
111   default: break;
112   case ARM::SP:
113   case ARM::PC:
114     return true;
115   case ARM::R6:
116     if (hasBasePointer(MF))
117       return true;
118     break;
119   case ARM::R7:
120   case ARM::R11:
121     if (FramePtr == Reg && TFI->hasFP(MF))
122       return true;
123     break;
124   case ARM::R9:
125     return STI.isR9Reserved();
126   }
127 
128   return false;
129 }
130 
131 const TargetRegisterClass *
132 ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
133                                               const TargetRegisterClass *B,
134                                               unsigned SubIdx) const {
135   switch (SubIdx) {
136   default: return 0;
137   case ARM::ssub_0:
138   case ARM::ssub_1:
139   case ARM::ssub_2:
140   case ARM::ssub_3: {
141     // S sub-registers.
142     if (A->getSize() == 8) {
143       if (B == &ARM::SPR_8RegClass)
144         return &ARM::DPR_8RegClass;
145       assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
146       if (A == &ARM::DPR_8RegClass)
147         return A;
148       return &ARM::DPR_VFP2RegClass;
149     }
150 
151     if (A->getSize() == 16) {
152       if (B == &ARM::SPR_8RegClass)
153         return &ARM::QPR_8RegClass;
154       return &ARM::QPR_VFP2RegClass;
155     }
156 
157     if (A->getSize() == 32) {
158       if (B == &ARM::SPR_8RegClass)
159         return 0;  // Do not allow coalescing!
160       return &ARM::QQPR_VFP2RegClass;
161     }
162 
163     assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
164     return 0;  // Do not allow coalescing!
165   }
166   case ARM::dsub_0:
167   case ARM::dsub_1:
168   case ARM::dsub_2:
169   case ARM::dsub_3: {
170     // D sub-registers.
171     if (A->getSize() == 16) {
172       if (B == &ARM::DPR_VFP2RegClass)
173         return &ARM::QPR_VFP2RegClass;
174       if (B == &ARM::DPR_8RegClass)
175         return 0;  // Do not allow coalescing!
176       return A;
177     }
178 
179     if (A->getSize() == 32) {
180       if (B == &ARM::DPR_VFP2RegClass)
181         return &ARM::QQPR_VFP2RegClass;
182       if (B == &ARM::DPR_8RegClass)
183         return 0;  // Do not allow coalescing!
184       return A;
185     }
186 
187     assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
188     if (B != &ARM::DPRRegClass)
189       return 0;  // Do not allow coalescing!
190     return A;
191   }
192   case ARM::dsub_4:
193   case ARM::dsub_5:
194   case ARM::dsub_6:
195   case ARM::dsub_7: {
196     // D sub-registers of QQQQ registers.
197     if (A->getSize() == 64 && B == &ARM::DPRRegClass)
198       return A;
199     return 0;  // Do not allow coalescing!
200   }
201 
202   case ARM::qsub_0:
203   case ARM::qsub_1: {
204     // Q sub-registers.
205     if (A->getSize() == 32) {
206       if (B == &ARM::QPR_VFP2RegClass)
207         return &ARM::QQPR_VFP2RegClass;
208       if (B == &ARM::QPR_8RegClass)
209         return 0;  // Do not allow coalescing!
210       return A;
211     }
212 
213     assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
214     if (B == &ARM::QPRRegClass)
215       return A;
216     return 0;  // Do not allow coalescing!
217   }
218   case ARM::qsub_2:
219   case ARM::qsub_3: {
220     // Q sub-registers of QQQQ registers.
221     if (A->getSize() == 64 && B == &ARM::QPRRegClass)
222       return A;
223     return 0;  // Do not allow coalescing!
224   }
225   }
226   return 0;
227 }
228 
229 bool
230 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
231                                           SmallVectorImpl<unsigned> &SubIndices,
232                                           unsigned &NewSubIdx) const {
233 
234   unsigned Size = RC->getSize() * 8;
235   if (Size < 6)
236     return 0;
237 
238   NewSubIdx = 0;  // Whole register.
239   unsigned NumRegs = SubIndices.size();
240   if (NumRegs == 8) {
241     // 8 D registers -> 1 QQQQ register.
242     return (Size == 512 &&
243             SubIndices[0] == ARM::dsub_0 &&
244             SubIndices[1] == ARM::dsub_1 &&
245             SubIndices[2] == ARM::dsub_2 &&
246             SubIndices[3] == ARM::dsub_3 &&
247             SubIndices[4] == ARM::dsub_4 &&
248             SubIndices[5] == ARM::dsub_5 &&
249             SubIndices[6] == ARM::dsub_6 &&
250             SubIndices[7] == ARM::dsub_7);
251   } else if (NumRegs == 4) {
252     if (SubIndices[0] == ARM::qsub_0) {
253       // 4 Q registers -> 1 QQQQ register.
254       return (Size == 512 &&
255               SubIndices[1] == ARM::qsub_1 &&
256               SubIndices[2] == ARM::qsub_2 &&
257               SubIndices[3] == ARM::qsub_3);
258     } else if (SubIndices[0] == ARM::dsub_0) {
259       // 4 D registers -> 1 QQ register.
260       if (Size >= 256 &&
261           SubIndices[1] == ARM::dsub_1 &&
262           SubIndices[2] == ARM::dsub_2 &&
263           SubIndices[3] == ARM::dsub_3) {
264         if (Size == 512)
265           NewSubIdx = ARM::qqsub_0;
266         return true;
267       }
268     } else if (SubIndices[0] == ARM::dsub_4) {
269       // 4 D registers -> 1 QQ register (2nd).
270       if (Size == 512 &&
271           SubIndices[1] == ARM::dsub_5 &&
272           SubIndices[2] == ARM::dsub_6 &&
273           SubIndices[3] == ARM::dsub_7) {
274         NewSubIdx = ARM::qqsub_1;
275         return true;
276       }
277     } else if (SubIndices[0] == ARM::ssub_0) {
278       // 4 S registers -> 1 Q register.
279       if (Size >= 128 &&
280           SubIndices[1] == ARM::ssub_1 &&
281           SubIndices[2] == ARM::ssub_2 &&
282           SubIndices[3] == ARM::ssub_3) {
283         if (Size >= 256)
284           NewSubIdx = ARM::qsub_0;
285         return true;
286       }
287     }
288   } else if (NumRegs == 2) {
289     if (SubIndices[0] == ARM::qsub_0) {
290       // 2 Q registers -> 1 QQ register.
291       if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
292         if (Size == 512)
293           NewSubIdx = ARM::qqsub_0;
294         return true;
295       }
296     } else if (SubIndices[0] == ARM::qsub_2) {
297       // 2 Q registers -> 1 QQ register (2nd).
298       if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
299         NewSubIdx = ARM::qqsub_1;
300         return true;
301       }
302     } else if (SubIndices[0] == ARM::dsub_0) {
303       // 2 D registers -> 1 Q register.
304       if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
305         if (Size >= 256)
306           NewSubIdx = ARM::qsub_0;
307         return true;
308       }
309     } else if (SubIndices[0] == ARM::dsub_2) {
310       // 2 D registers -> 1 Q register (2nd).
311       if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
312         NewSubIdx = ARM::qsub_1;
313         return true;
314       }
315     } else if (SubIndices[0] == ARM::dsub_4) {
316       // 2 D registers -> 1 Q register (3rd).
317       if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
318         NewSubIdx = ARM::qsub_2;
319         return true;
320       }
321     } else if (SubIndices[0] == ARM::dsub_6) {
322       // 2 D registers -> 1 Q register (3rd).
323       if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
324         NewSubIdx = ARM::qsub_3;
325         return true;
326       }
327     } else if (SubIndices[0] == ARM::ssub_0) {
328       // 2 S registers -> 1 D register.
329       if (SubIndices[1] == ARM::ssub_1) {
330         if (Size >= 128)
331           NewSubIdx = ARM::dsub_0;
332         return true;
333       }
334     } else if (SubIndices[0] == ARM::ssub_2) {
335       // 2 S registers -> 1 D register (2nd).
336       if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
337         NewSubIdx = ARM::dsub_1;
338         return true;
339       }
340     }
341   }
342   return false;
343 }
344 
345 
346 const TargetRegisterClass *
347 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
348   return ARM::GPRRegisterClass;
349 }
350 
351 unsigned
352 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
353                                          MachineFunction &MF) const {
354   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
355 
356   switch (RC->getID()) {
357   default:
358     return 0;
359   case ARM::tGPRRegClassID:
360     return TFI->hasFP(MF) ? 4 : 5;
361   case ARM::GPRRegClassID: {
362     unsigned FP = TFI->hasFP(MF) ? 1 : 0;
363     return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
364   }
365   case ARM::SPRRegClassID:  // Currently not used as 'rep' register class.
366   case ARM::DPRRegClassID:
367     return 32 - 10;
368   }
369 }
370 
371 /// getAllocationOrder - Returns the register allocation order for a specified
372 /// register class in the form of a pair of TargetRegisterClass iterators.
373 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
374 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
375                                         unsigned HintType, unsigned HintReg,
376                                         const MachineFunction &MF) const {
377   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
378   // Alternative register allocation orders when favoring even / odd registers
379   // of register pairs.
380 
381   // No FP, R9 is available.
382   static const unsigned GPREven1[] = {
383     ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
384     ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
385     ARM::R9, ARM::R11
386   };
387   static const unsigned GPROdd1[] = {
388     ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
389     ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
390     ARM::R8, ARM::R10
391   };
392 
393   // FP is R7, R9 is available.
394   static const unsigned GPREven2[] = {
395     ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
396     ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
397     ARM::R9, ARM::R11
398   };
399   static const unsigned GPROdd2[] = {
400     ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
401     ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
402     ARM::R8, ARM::R10
403   };
404 
405   // FP is R11, R9 is available.
406   static const unsigned GPREven3[] = {
407     ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
408     ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
409     ARM::R9
410   };
411   static const unsigned GPROdd3[] = {
412     ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
413     ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
414     ARM::R8
415   };
416 
417   // No FP, R9 is not available.
418   static const unsigned GPREven4[] = {
419     ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
420     ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
421     ARM::R11
422   };
423   static const unsigned GPROdd4[] = {
424     ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
425     ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
426     ARM::R10
427   };
428 
429   // FP is R7, R9 is not available.
430   static const unsigned GPREven5[] = {
431     ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
432     ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
433     ARM::R11
434   };
435   static const unsigned GPROdd5[] = {
436     ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
437     ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
438     ARM::R10
439   };
440 
441   // FP is R11, R9 is not available.
442   static const unsigned GPREven6[] = {
443     ARM::R0, ARM::R2, ARM::R4, ARM::R6,
444     ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
445   };
446   static const unsigned GPROdd6[] = {
447     ARM::R1, ARM::R3, ARM::R5, ARM::R7,
448     ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
449   };
450 
451   // We only support even/odd hints for GPR and rGPR.
452   if (RC != ARM::GPRRegisterClass && RC != ARM::rGPRRegisterClass)
453     return std::make_pair(RC->allocation_order_begin(MF),
454                           RC->allocation_order_end(MF));
455 
456   if (HintType == ARMRI::RegPairEven) {
457     if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
458       // It's no longer possible to fulfill this hint. Return the default
459       // allocation order.
460       return std::make_pair(RC->allocation_order_begin(MF),
461                             RC->allocation_order_end(MF));
462 
463     if (!TFI->hasFP(MF)) {
464       if (!STI.isR9Reserved())
465         return std::make_pair(GPREven1,
466                               GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
467       else
468         return std::make_pair(GPREven4,
469                               GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
470     } else if (FramePtr == ARM::R7) {
471       if (!STI.isR9Reserved())
472         return std::make_pair(GPREven2,
473                               GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
474       else
475         return std::make_pair(GPREven5,
476                               GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
477     } else { // FramePtr == ARM::R11
478       if (!STI.isR9Reserved())
479         return std::make_pair(GPREven3,
480                               GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
481       else
482         return std::make_pair(GPREven6,
483                               GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
484     }
485   } else if (HintType == ARMRI::RegPairOdd) {
486     if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
487       // It's no longer possible to fulfill this hint. Return the default
488       // allocation order.
489       return std::make_pair(RC->allocation_order_begin(MF),
490                             RC->allocation_order_end(MF));
491 
492     if (!TFI->hasFP(MF)) {
493       if (!STI.isR9Reserved())
494         return std::make_pair(GPROdd1,
495                               GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
496       else
497         return std::make_pair(GPROdd4,
498                               GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
499     } else if (FramePtr == ARM::R7) {
500       if (!STI.isR9Reserved())
501         return std::make_pair(GPROdd2,
502                               GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
503       else
504         return std::make_pair(GPROdd5,
505                               GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
506     } else { // FramePtr == ARM::R11
507       if (!STI.isR9Reserved())
508         return std::make_pair(GPROdd3,
509                               GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
510       else
511         return std::make_pair(GPROdd6,
512                               GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
513     }
514   }
515   return std::make_pair(RC->allocation_order_begin(MF),
516                         RC->allocation_order_end(MF));
517 }
518 
519 /// ResolveRegAllocHint - Resolves the specified register allocation hint
520 /// to a physical register. Returns the physical register if it is successful.
521 unsigned
522 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
523                                          const MachineFunction &MF) const {
524   if (Reg == 0 || !isPhysicalRegister(Reg))
525     return 0;
526   if (Type == 0)
527     return Reg;
528   else if (Type == (unsigned)ARMRI::RegPairOdd)
529     // Odd register.
530     return getRegisterPairOdd(Reg, MF);
531   else if (Type == (unsigned)ARMRI::RegPairEven)
532     // Even register.
533     return getRegisterPairEven(Reg, MF);
534   return 0;
535 }
536 
537 void
538 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
539                                         MachineFunction &MF) const {
540   MachineRegisterInfo *MRI = &MF.getRegInfo();
541   std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
542   if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
543        Hint.first == (unsigned)ARMRI::RegPairEven) &&
544       TargetRegisterInfo::isVirtualRegister(Hint.second)) {
545     // If 'Reg' is one of the even / odd register pair and it's now changed
546     // (e.g. coalesced) into a different register. The other register of the
547     // pair allocation hint must be updated to reflect the relationship
548     // change.
549     unsigned OtherReg = Hint.second;
550     Hint = MRI->getRegAllocationHint(OtherReg);
551     if (Hint.second == Reg)
552       // Make sure the pair has not already divorced.
553       MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
554   }
555 }
556 
557 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
558   const MachineFrameInfo *MFI = MF.getFrameInfo();
559   const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
560 
561   if (!EnableBasePointer)
562     return false;
563 
564   if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
565     return true;
566 
567   // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
568   // negative range for ldr/str (255), and thumb1 is positive offsets only.
569   // It's going to be better to use the SP or Base Pointer instead. When there
570   // are variable sized objects, we can't reference off of the SP, so we
571   // reserve a Base Pointer.
572   if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
573     // Conservatively estimate whether the negative offset from the frame
574     // pointer will be sufficient to reach. If a function has a smallish
575     // frame, it's less likely to have lots of spills and callee saved
576     // space, so it's all more likely to be within range of the frame pointer.
577     // If it's wrong, the scavenger will still enable access to work, it just
578     // won't be optimal.
579     if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
580       return false;
581     return true;
582   }
583 
584   return false;
585 }
586 
587 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
588   const MachineFrameInfo *MFI = MF.getFrameInfo();
589   const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
590   // We can't realign the stack if:
591   // 1. Dynamic stack realignment is explicitly disabled,
592   // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
593   // 3. There are VLAs in the function and the base pointer is disabled.
594   return (RealignStack && !AFI->isThumb1OnlyFunction() &&
595           (!MFI->hasVarSizedObjects() || EnableBasePointer));
596 }
597 
598 bool ARMBaseRegisterInfo::
599 needsStackRealignment(const MachineFunction &MF) const {
600   const MachineFrameInfo *MFI = MF.getFrameInfo();
601   const Function *F = MF.getFunction();
602   unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
603   bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
604                                F->hasFnAttr(Attribute::StackAlignment));
605 
606   return requiresRealignment && canRealignStack(MF);
607 }
608 
609 bool ARMBaseRegisterInfo::
610 cannotEliminateFrame(const MachineFunction &MF) const {
611   const MachineFrameInfo *MFI = MF.getFrameInfo();
612   if (DisableFramePointerElim(MF) && MFI->adjustsStack())
613     return true;
614   return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
615     || needsStackRealignment(MF);
616 }
617 
618 unsigned ARMBaseRegisterInfo::getRARegister() const {
619   return ARM::LR;
620 }
621 
622 unsigned
623 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
624   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
625 
626   if (TFI->hasFP(MF))
627     return FramePtr;
628   return ARM::SP;
629 }
630 
631 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
632   llvm_unreachable("What is the exception register");
633   return 0;
634 }
635 
636 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
637   llvm_unreachable("What is the exception handler register");
638   return 0;
639 }
640 
641 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
642   return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
643 }
644 
645 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
646                                               const MachineFunction &MF) const {
647   switch (Reg) {
648   default: break;
649   // Return 0 if either register of the pair is a special register.
650   // So no R12, etc.
651   case ARM::R1:
652     return ARM::R0;
653   case ARM::R3:
654     return ARM::R2;
655   case ARM::R5:
656     return ARM::R4;
657   case ARM::R7:
658     return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
659       ? 0 : ARM::R6;
660   case ARM::R9:
661     return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
662   case ARM::R11:
663     return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
664 
665   case ARM::S1:
666     return ARM::S0;
667   case ARM::S3:
668     return ARM::S2;
669   case ARM::S5:
670     return ARM::S4;
671   case ARM::S7:
672     return ARM::S6;
673   case ARM::S9:
674     return ARM::S8;
675   case ARM::S11:
676     return ARM::S10;
677   case ARM::S13:
678     return ARM::S12;
679   case ARM::S15:
680     return ARM::S14;
681   case ARM::S17:
682     return ARM::S16;
683   case ARM::S19:
684     return ARM::S18;
685   case ARM::S21:
686     return ARM::S20;
687   case ARM::S23:
688     return ARM::S22;
689   case ARM::S25:
690     return ARM::S24;
691   case ARM::S27:
692     return ARM::S26;
693   case ARM::S29:
694     return ARM::S28;
695   case ARM::S31:
696     return ARM::S30;
697 
698   case ARM::D1:
699     return ARM::D0;
700   case ARM::D3:
701     return ARM::D2;
702   case ARM::D5:
703     return ARM::D4;
704   case ARM::D7:
705     return ARM::D6;
706   case ARM::D9:
707     return ARM::D8;
708   case ARM::D11:
709     return ARM::D10;
710   case ARM::D13:
711     return ARM::D12;
712   case ARM::D15:
713     return ARM::D14;
714   case ARM::D17:
715     return ARM::D16;
716   case ARM::D19:
717     return ARM::D18;
718   case ARM::D21:
719     return ARM::D20;
720   case ARM::D23:
721     return ARM::D22;
722   case ARM::D25:
723     return ARM::D24;
724   case ARM::D27:
725     return ARM::D26;
726   case ARM::D29:
727     return ARM::D28;
728   case ARM::D31:
729     return ARM::D30;
730   }
731 
732   return 0;
733 }
734 
735 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
736                                              const MachineFunction &MF) const {
737   switch (Reg) {
738   default: break;
739   // Return 0 if either register of the pair is a special register.
740   // So no R12, etc.
741   case ARM::R0:
742     return ARM::R1;
743   case ARM::R2:
744     return ARM::R3;
745   case ARM::R4:
746     return ARM::R5;
747   case ARM::R6:
748     return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
749       ? 0 : ARM::R7;
750   case ARM::R8:
751     return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
752   case ARM::R10:
753     return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
754 
755   case ARM::S0:
756     return ARM::S1;
757   case ARM::S2:
758     return ARM::S3;
759   case ARM::S4:
760     return ARM::S5;
761   case ARM::S6:
762     return ARM::S7;
763   case ARM::S8:
764     return ARM::S9;
765   case ARM::S10:
766     return ARM::S11;
767   case ARM::S12:
768     return ARM::S13;
769   case ARM::S14:
770     return ARM::S15;
771   case ARM::S16:
772     return ARM::S17;
773   case ARM::S18:
774     return ARM::S19;
775   case ARM::S20:
776     return ARM::S21;
777   case ARM::S22:
778     return ARM::S23;
779   case ARM::S24:
780     return ARM::S25;
781   case ARM::S26:
782     return ARM::S27;
783   case ARM::S28:
784     return ARM::S29;
785   case ARM::S30:
786     return ARM::S31;
787 
788   case ARM::D0:
789     return ARM::D1;
790   case ARM::D2:
791     return ARM::D3;
792   case ARM::D4:
793     return ARM::D5;
794   case ARM::D6:
795     return ARM::D7;
796   case ARM::D8:
797     return ARM::D9;
798   case ARM::D10:
799     return ARM::D11;
800   case ARM::D12:
801     return ARM::D13;
802   case ARM::D14:
803     return ARM::D15;
804   case ARM::D16:
805     return ARM::D17;
806   case ARM::D18:
807     return ARM::D19;
808   case ARM::D20:
809     return ARM::D21;
810   case ARM::D22:
811     return ARM::D23;
812   case ARM::D24:
813     return ARM::D25;
814   case ARM::D26:
815     return ARM::D27;
816   case ARM::D28:
817     return ARM::D29;
818   case ARM::D30:
819     return ARM::D31;
820   }
821 
822   return 0;
823 }
824 
825 /// emitLoadConstPool - Emits a load from constpool to materialize the
826 /// specified immediate.
827 void ARMBaseRegisterInfo::
828 emitLoadConstPool(MachineBasicBlock &MBB,
829                   MachineBasicBlock::iterator &MBBI,
830                   DebugLoc dl,
831                   unsigned DestReg, unsigned SubIdx, int Val,
832                   ARMCC::CondCodes Pred,
833                   unsigned PredReg, unsigned MIFlags) const {
834   MachineFunction &MF = *MBB.getParent();
835   MachineConstantPool *ConstantPool = MF.getConstantPool();
836   const Constant *C =
837         ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
838   unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
839 
840   BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
841     .addReg(DestReg, getDefRegState(true), SubIdx)
842     .addConstantPoolIndex(Idx)
843     .addImm(0).addImm(Pred).addReg(PredReg)
844     .setMIFlags(MIFlags);
845 }
846 
847 bool ARMBaseRegisterInfo::
848 requiresRegisterScavenging(const MachineFunction &MF) const {
849   return true;
850 }
851 
852 bool ARMBaseRegisterInfo::
853 requiresFrameIndexScavenging(const MachineFunction &MF) const {
854   return true;
855 }
856 
857 bool ARMBaseRegisterInfo::
858 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
859   return EnableLocalStackAlloc;
860 }
861 
862 static void
863 emitSPUpdate(bool isARM,
864              MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
865              DebugLoc dl, const ARMBaseInstrInfo &TII,
866              int NumBytes,
867              ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
868   if (isARM)
869     emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
870                             Pred, PredReg, TII);
871   else
872     emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
873                            Pred, PredReg, TII);
874 }
875 
876 
877 void ARMBaseRegisterInfo::
878 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
879                               MachineBasicBlock::iterator I) const {
880   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
881   if (!TFI->hasReservedCallFrame(MF)) {
882     // If we have alloca, convert as follows:
883     // ADJCALLSTACKDOWN -> sub, sp, sp, amount
884     // ADJCALLSTACKUP   -> add, sp, sp, amount
885     MachineInstr *Old = I;
886     DebugLoc dl = Old->getDebugLoc();
887     unsigned Amount = Old->getOperand(0).getImm();
888     if (Amount != 0) {
889       // We need to keep the stack aligned properly.  To do this, we round the
890       // amount of space needed for the outgoing arguments up to the next
891       // alignment boundary.
892       unsigned Align = TFI->getStackAlignment();
893       Amount = (Amount+Align-1)/Align*Align;
894 
895       ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
896       assert(!AFI->isThumb1OnlyFunction() &&
897              "This eliminateCallFramePseudoInstr does not support Thumb1!");
898       bool isARM = !AFI->isThumbFunction();
899 
900       // Replace the pseudo instruction with a new instruction...
901       unsigned Opc = Old->getOpcode();
902       int PIdx = Old->findFirstPredOperandIdx();
903       ARMCC::CondCodes Pred = (PIdx == -1)
904         ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
905       if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
906         // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
907         unsigned PredReg = Old->getOperand(2).getReg();
908         emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
909       } else {
910         // Note: PredReg is operand 3 for ADJCALLSTACKUP.
911         unsigned PredReg = Old->getOperand(3).getReg();
912         assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
913         emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
914       }
915     }
916   }
917   MBB.erase(I);
918 }
919 
920 int64_t ARMBaseRegisterInfo::
921 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
922   const TargetInstrDesc &Desc = MI->getDesc();
923   unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
924   int64_t InstrOffs = 0;;
925   int Scale = 1;
926   unsigned ImmIdx = 0;
927   switch (AddrMode) {
928   case ARMII::AddrModeT2_i8:
929   case ARMII::AddrModeT2_i12:
930   case ARMII::AddrMode_i12:
931     InstrOffs = MI->getOperand(Idx+1).getImm();
932     Scale = 1;
933     break;
934   case ARMII::AddrMode5: {
935     // VFP address mode.
936     const MachineOperand &OffOp = MI->getOperand(Idx+1);
937     InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
938     if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
939       InstrOffs = -InstrOffs;
940     Scale = 4;
941     break;
942   }
943   case ARMII::AddrMode2: {
944     ImmIdx = Idx+2;
945     InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
946     if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
947       InstrOffs = -InstrOffs;
948     break;
949   }
950   case ARMII::AddrMode3: {
951     ImmIdx = Idx+2;
952     InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
953     if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
954       InstrOffs = -InstrOffs;
955     break;
956   }
957   case ARMII::AddrModeT1_s: {
958     ImmIdx = Idx+1;
959     InstrOffs = MI->getOperand(ImmIdx).getImm();
960     Scale = 4;
961     break;
962   }
963   default:
964     llvm_unreachable("Unsupported addressing mode!");
965     break;
966   }
967 
968   return InstrOffs * Scale;
969 }
970 
971 /// needsFrameBaseReg - Returns true if the instruction's frame index
972 /// reference would be better served by a base register other than FP
973 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
974 /// references it should create new base registers for.
975 bool ARMBaseRegisterInfo::
976 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
977   for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
978     assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
979   }
980 
981   // It's the load/store FI references that cause issues, as it can be difficult
982   // to materialize the offset if it won't fit in the literal field. Estimate
983   // based on the size of the local frame and some conservative assumptions
984   // about the rest of the stack frame (note, this is pre-regalloc, so
985   // we don't know everything for certain yet) whether this offset is likely
986   // to be out of range of the immediate. Return true if so.
987 
988   // We only generate virtual base registers for loads and stores, so
989   // return false for everything else.
990   unsigned Opc = MI->getOpcode();
991   switch (Opc) {
992   case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
993   case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
994   case ARM::t2LDRi12: case ARM::t2LDRi8:
995   case ARM::t2STRi12: case ARM::t2STRi8:
996   case ARM::VLDRS: case ARM::VLDRD:
997   case ARM::VSTRS: case ARM::VSTRD:
998   case ARM::tSTRspi: case ARM::tLDRspi:
999     if (ForceAllBaseRegAlloc)
1000       return true;
1001     break;
1002   default:
1003     return false;
1004   }
1005 
1006   // Without a virtual base register, if the function has variable sized
1007   // objects, all fixed-size local references will be via the frame pointer,
1008   // Approximate the offset and see if it's legal for the instruction.
1009   // Note that the incoming offset is based on the SP value at function entry,
1010   // so it'll be negative.
1011   MachineFunction &MF = *MI->getParent()->getParent();
1012   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
1013   MachineFrameInfo *MFI = MF.getFrameInfo();
1014   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1015 
1016   // Estimate an offset from the frame pointer.
1017   // Conservatively assume all callee-saved registers get pushed. R4-R6
1018   // will be earlier than the FP, so we ignore those.
1019   // R7, LR
1020   int64_t FPOffset = Offset - 8;
1021   // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
1022   if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
1023     FPOffset -= 80;
1024   // Estimate an offset from the stack pointer.
1025   // The incoming offset is relating to the SP at the start of the function,
1026   // but when we access the local it'll be relative to the SP after local
1027   // allocation, so adjust our SP-relative offset by that allocation size.
1028   Offset = -Offset;
1029   Offset += MFI->getLocalFrameSize();
1030   // Assume that we'll have at least some spill slots allocated.
1031   // FIXME: This is a total SWAG number. We should run some statistics
1032   //        and pick a real one.
1033   Offset += 128; // 128 bytes of spill slots
1034 
1035   // If there is a frame pointer, try using it.
1036   // The FP is only available if there is no dynamic realignment. We
1037   // don't know for sure yet whether we'll need that, so we guess based
1038   // on whether there are any local variables that would trigger it.
1039   unsigned StackAlign = TFI->getStackAlignment();
1040   if (TFI->hasFP(MF) &&
1041       !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
1042     if (isFrameOffsetLegal(MI, FPOffset))
1043       return false;
1044   }
1045   // If we can reference via the stack pointer, try that.
1046   // FIXME: This (and the code that resolves the references) can be improved
1047   //        to only disallow SP relative references in the live range of
1048   //        the VLA(s). In practice, it's unclear how much difference that
1049   //        would make, but it may be worth doing.
1050   if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
1051     return false;
1052 
1053   // The offset likely isn't legal, we want to allocate a virtual base register.
1054   return true;
1055 }
1056 
1057 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
1058 /// be a pointer to FrameIdx at the beginning of the basic block.
1059 void ARMBaseRegisterInfo::
1060 materializeFrameBaseRegister(MachineBasicBlock *MBB,
1061                              unsigned BaseReg, int FrameIdx,
1062                              int64_t Offset) const {
1063   ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
1064   unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
1065     (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
1066 
1067   MachineBasicBlock::iterator Ins = MBB->begin();
1068   DebugLoc DL;                  // Defaults to "unknown"
1069   if (Ins != MBB->end())
1070     DL = Ins->getDebugLoc();
1071 
1072   MachineInstrBuilder MIB =
1073     BuildMI(*MBB, Ins, DL, TII.get(ADDriOpc), BaseReg)
1074     .addFrameIndex(FrameIdx).addImm(Offset);
1075 
1076   if (!AFI->isThumb1OnlyFunction())
1077     AddDefaultCC(AddDefaultPred(MIB));
1078 }
1079 
1080 void
1081 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
1082                                        unsigned BaseReg, int64_t Offset) const {
1083   MachineInstr &MI = *I;
1084   MachineBasicBlock &MBB = *MI.getParent();
1085   MachineFunction &MF = *MBB.getParent();
1086   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1087   int Off = Offset; // ARM doesn't need the general 64-bit offsets
1088   unsigned i = 0;
1089 
1090   assert(!AFI->isThumb1OnlyFunction() &&
1091          "This resolveFrameIndex does not support Thumb1!");
1092 
1093   while (!MI.getOperand(i).isFI()) {
1094     ++i;
1095     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1096   }
1097   bool Done = false;
1098   if (!AFI->isThumbFunction())
1099     Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
1100   else {
1101     assert(AFI->isThumb2Function());
1102     Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
1103   }
1104   assert (Done && "Unable to resolve frame index!");
1105 }
1106 
1107 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1108                                              int64_t Offset) const {
1109   const TargetInstrDesc &Desc = MI->getDesc();
1110   unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1111   unsigned i = 0;
1112 
1113   while (!MI->getOperand(i).isFI()) {
1114     ++i;
1115     assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1116   }
1117 
1118   // AddrMode4 and AddrMode6 cannot handle any offset.
1119   if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1120     return Offset == 0;
1121 
1122   unsigned NumBits = 0;
1123   unsigned Scale = 1;
1124   bool isSigned = true;
1125   switch (AddrMode) {
1126   case ARMII::AddrModeT2_i8:
1127   case ARMII::AddrModeT2_i12:
1128     // i8 supports only negative, and i12 supports only positive, so
1129     // based on Offset sign, consider the appropriate instruction
1130     Scale = 1;
1131     if (Offset < 0) {
1132       NumBits = 8;
1133       Offset = -Offset;
1134     } else {
1135       NumBits = 12;
1136     }
1137     break;
1138   case ARMII::AddrMode5:
1139     // VFP address mode.
1140     NumBits = 8;
1141     Scale = 4;
1142     break;
1143   case ARMII::AddrMode_i12:
1144   case ARMII::AddrMode2:
1145     NumBits = 12;
1146     break;
1147   case ARMII::AddrMode3:
1148     NumBits = 8;
1149     break;
1150   case ARMII::AddrModeT1_s:
1151     NumBits = 5;
1152     Scale = 4;
1153     isSigned = false;
1154     break;
1155   default:
1156     llvm_unreachable("Unsupported addressing mode!");
1157     break;
1158   }
1159 
1160   Offset += getFrameIndexInstrOffset(MI, i);
1161   // Make sure the offset is encodable for instructions that scale the
1162   // immediate.
1163   if ((Offset & (Scale-1)) != 0)
1164     return false;
1165 
1166   if (isSigned && Offset < 0)
1167     Offset = -Offset;
1168 
1169   unsigned Mask = (1 << NumBits) - 1;
1170   if ((unsigned)Offset <= Mask * Scale)
1171     return true;
1172 
1173   return false;
1174 }
1175 
1176 void
1177 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1178                                          int SPAdj, RegScavenger *RS) const {
1179   unsigned i = 0;
1180   MachineInstr &MI = *II;
1181   MachineBasicBlock &MBB = *MI.getParent();
1182   MachineFunction &MF = *MBB.getParent();
1183   const ARMFrameLowering *TFI =
1184     static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
1185   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1186   assert(!AFI->isThumb1OnlyFunction() &&
1187          "This eliminateFrameIndex does not support Thumb1!");
1188 
1189   while (!MI.getOperand(i).isFI()) {
1190     ++i;
1191     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1192   }
1193 
1194   int FrameIndex = MI.getOperand(i).getIndex();
1195   unsigned FrameReg;
1196 
1197   int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1198 
1199   // Special handling of dbg_value instructions.
1200   if (MI.isDebugValue()) {
1201     MI.getOperand(i).  ChangeToRegister(FrameReg, false /*isDef*/);
1202     MI.getOperand(i+1).ChangeToImmediate(Offset);
1203     return;
1204   }
1205 
1206   // Modify MI as necessary to handle as much of 'Offset' as possible
1207   bool Done = false;
1208   if (!AFI->isThumbFunction())
1209     Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1210   else {
1211     assert(AFI->isThumb2Function());
1212     Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1213   }
1214   if (Done)
1215     return;
1216 
1217   // If we get here, the immediate doesn't fit into the instruction.  We folded
1218   // as much as possible above, handle the rest, providing a register that is
1219   // SP+LargeImm.
1220   assert((Offset ||
1221           (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1222           (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1223          "This code isn't needed if offset already handled!");
1224 
1225   unsigned ScratchReg = 0;
1226   int PIdx = MI.findFirstPredOperandIdx();
1227   ARMCC::CondCodes Pred = (PIdx == -1)
1228     ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1229   unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1230   if (Offset == 0)
1231     // Must be addrmode4/6.
1232     MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1233   else {
1234     ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1235     if (!AFI->isThumbFunction())
1236       emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1237                               Offset, Pred, PredReg, TII);
1238     else {
1239       assert(AFI->isThumb2Function());
1240       emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1241                              Offset, Pred, PredReg, TII);
1242     }
1243     // Update the original instruction to use the scratch register.
1244     MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1245     if (MI.getOpcode() == ARM::t2ADDrSPi)
1246       MI.setDesc(TII.get(ARM::t2ADDri));
1247     else if (MI.getOpcode() == ARM::t2SUBrSPi)
1248       MI.setDesc(TII.get(ARM::t2SUBri));
1249   }
1250 }
1251 
1252 #include "ARMGenRegisterInfo.inc"
1253