1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Base ARM implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "ARMBaseInstrInfo.h" 15 #include "ARM.h" 16 #include "ARMConstantPoolValue.h" 17 #include "ARMHazardRecognizer.h" 18 #include "ARMMachineFunctionInfo.h" 19 #include "ARMRegisterInfo.h" 20 #include "MCTargetDesc/ARMAddressingModes.h" 21 #include "llvm/Constants.h" 22 #include "llvm/Function.h" 23 #include "llvm/GlobalValue.h" 24 #include "llvm/CodeGen/LiveVariables.h" 25 #include "llvm/CodeGen/MachineConstantPool.h" 26 #include "llvm/CodeGen/MachineFrameInfo.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineJumpTableInfo.h" 29 #include "llvm/CodeGen/MachineMemOperand.h" 30 #include "llvm/CodeGen/MachineRegisterInfo.h" 31 #include "llvm/CodeGen/PseudoSourceValue.h" 32 #include "llvm/CodeGen/SelectionDAGNodes.h" 33 #include "llvm/MC/MCAsmInfo.h" 34 #include "llvm/Support/BranchProbability.h" 35 #include "llvm/Support/CommandLine.h" 36 #include "llvm/Support/Debug.h" 37 #include "llvm/Support/ErrorHandling.h" 38 #include "llvm/ADT/STLExtras.h" 39 40 #define GET_INSTRINFO_CTOR 41 #include "ARMGenInstrInfo.inc" 42 43 using namespace llvm; 44 45 static cl::opt<bool> 46 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 47 cl::desc("Enable ARM 2-addr to 3-addr conv")); 48 49 static cl::opt<bool> 50 WidenVMOVS("widen-vmovs", cl::Hidden, 51 cl::desc("Widen ARM vmovs to vmovd when possible")); 52 53 /// ARM_MLxEntry - Record information about MLA / MLS instructions. 54 struct ARM_MLxEntry { 55 unsigned MLxOpc; // MLA / MLS opcode 56 unsigned MulOpc; // Expanded multiplication opcode 57 unsigned AddSubOpc; // Expanded add / sub opcode 58 bool NegAcc; // True if the acc is negated before the add / sub. 59 bool HasLane; // True if instruction has an extra "lane" operand. 60 }; 61 62 static const ARM_MLxEntry ARM_MLxTable[] = { 63 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane 64 // fp scalar ops 65 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false }, 66 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false }, 67 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false }, 68 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false }, 69 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false }, 70 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false }, 71 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false }, 72 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false }, 73 74 // fp SIMD ops 75 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false }, 76 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false }, 77 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false }, 78 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false }, 79 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true }, 80 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true }, 81 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true }, 82 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true }, 83 }; 84 85 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 86 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 87 Subtarget(STI) { 88 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) { 89 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second) 90 assert(false && "Duplicated entries?"); 91 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); 92 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc); 93 } 94 } 95 96 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl 97 // currently defaults to no prepass hazard recognizer. 98 ScheduleHazardRecognizer *ARMBaseInstrInfo:: 99 CreateTargetHazardRecognizer(const TargetMachine *TM, 100 const ScheduleDAG *DAG) const { 101 if (usePreRAHazardRecognizer()) { 102 const InstrItineraryData *II = TM->getInstrItineraryData(); 103 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched"); 104 } 105 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG); 106 } 107 108 ScheduleHazardRecognizer *ARMBaseInstrInfo:: 109 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 110 const ScheduleDAG *DAG) const { 111 if (Subtarget.isThumb2() || Subtarget.hasVFP2()) 112 return (ScheduleHazardRecognizer *) 113 new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG); 114 return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG); 115 } 116 117 MachineInstr * 118 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 119 MachineBasicBlock::iterator &MBBI, 120 LiveVariables *LV) const { 121 // FIXME: Thumb2 support. 122 123 if (!EnableARM3Addr) 124 return NULL; 125 126 MachineInstr *MI = MBBI; 127 MachineFunction &MF = *MI->getParent()->getParent(); 128 uint64_t TSFlags = MI->getDesc().TSFlags; 129 bool isPre = false; 130 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 131 default: return NULL; 132 case ARMII::IndexModePre: 133 isPre = true; 134 break; 135 case ARMII::IndexModePost: 136 break; 137 } 138 139 // Try splitting an indexed load/store to an un-indexed one plus an add/sub 140 // operation. 141 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 142 if (MemOpc == 0) 143 return NULL; 144 145 MachineInstr *UpdateMI = NULL; 146 MachineInstr *MemMI = NULL; 147 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 148 const MCInstrDesc &MCID = MI->getDesc(); 149 unsigned NumOps = MCID.getNumOperands(); 150 bool isLoad = !MCID.mayStore(); 151 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 152 const MachineOperand &Base = MI->getOperand(2); 153 const MachineOperand &Offset = MI->getOperand(NumOps-3); 154 unsigned WBReg = WB.getReg(); 155 unsigned BaseReg = Base.getReg(); 156 unsigned OffReg = Offset.getReg(); 157 unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 158 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 159 switch (AddrMode) { 160 default: 161 assert(false && "Unknown indexed op!"); 162 return NULL; 163 case ARMII::AddrMode2: { 164 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 165 unsigned Amt = ARM_AM::getAM2Offset(OffImm); 166 if (OffReg == 0) { 167 if (ARM_AM::getSOImmVal(Amt) == -1) 168 // Can't encode it in a so_imm operand. This transformation will 169 // add more than 1 instruction. Abandon! 170 return NULL; 171 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 172 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 173 .addReg(BaseReg).addImm(Amt) 174 .addImm(Pred).addReg(0).addReg(0); 175 } else if (Amt != 0) { 176 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 177 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 178 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 179 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) 180 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 181 .addImm(Pred).addReg(0).addReg(0); 182 } else 183 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 184 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 185 .addReg(BaseReg).addReg(OffReg) 186 .addImm(Pred).addReg(0).addReg(0); 187 break; 188 } 189 case ARMII::AddrMode3 : { 190 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 191 unsigned Amt = ARM_AM::getAM3Offset(OffImm); 192 if (OffReg == 0) 193 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 194 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 195 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 196 .addReg(BaseReg).addImm(Amt) 197 .addImm(Pred).addReg(0).addReg(0); 198 else 199 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 200 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 201 .addReg(BaseReg).addReg(OffReg) 202 .addImm(Pred).addReg(0).addReg(0); 203 break; 204 } 205 } 206 207 std::vector<MachineInstr*> NewMIs; 208 if (isPre) { 209 if (isLoad) 210 MemMI = BuildMI(MF, MI->getDebugLoc(), 211 get(MemOpc), MI->getOperand(0).getReg()) 212 .addReg(WBReg).addImm(0).addImm(Pred); 213 else 214 MemMI = BuildMI(MF, MI->getDebugLoc(), 215 get(MemOpc)).addReg(MI->getOperand(1).getReg()) 216 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 217 NewMIs.push_back(MemMI); 218 NewMIs.push_back(UpdateMI); 219 } else { 220 if (isLoad) 221 MemMI = BuildMI(MF, MI->getDebugLoc(), 222 get(MemOpc), MI->getOperand(0).getReg()) 223 .addReg(BaseReg).addImm(0).addImm(Pred); 224 else 225 MemMI = BuildMI(MF, MI->getDebugLoc(), 226 get(MemOpc)).addReg(MI->getOperand(1).getReg()) 227 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 228 if (WB.isDead()) 229 UpdateMI->getOperand(0).setIsDead(); 230 NewMIs.push_back(UpdateMI); 231 NewMIs.push_back(MemMI); 232 } 233 234 // Transfer LiveVariables states, kill / dead info. 235 if (LV) { 236 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 237 MachineOperand &MO = MI->getOperand(i); 238 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 239 unsigned Reg = MO.getReg(); 240 241 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 242 if (MO.isDef()) { 243 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 244 if (MO.isDead()) 245 LV->addVirtualRegisterDead(Reg, NewMI); 246 } 247 if (MO.isUse() && MO.isKill()) { 248 for (unsigned j = 0; j < 2; ++j) { 249 // Look at the two new MI's in reverse order. 250 MachineInstr *NewMI = NewMIs[j]; 251 if (!NewMI->readsRegister(Reg)) 252 continue; 253 LV->addVirtualRegisterKilled(Reg, NewMI); 254 if (VI.removeKill(MI)) 255 VI.Kills.push_back(NewMI); 256 break; 257 } 258 } 259 } 260 } 261 } 262 263 MFI->insert(MBBI, NewMIs[1]); 264 MFI->insert(MBBI, NewMIs[0]); 265 return NewMIs[0]; 266 } 267 268 // Branch analysis. 269 bool 270 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 271 MachineBasicBlock *&FBB, 272 SmallVectorImpl<MachineOperand> &Cond, 273 bool AllowModify) const { 274 // If the block has no terminators, it just falls into the block after it. 275 MachineBasicBlock::iterator I = MBB.end(); 276 if (I == MBB.begin()) 277 return false; 278 --I; 279 while (I->isDebugValue()) { 280 if (I == MBB.begin()) 281 return false; 282 --I; 283 } 284 if (!isUnpredicatedTerminator(I)) 285 return false; 286 287 // Get the last instruction in the block. 288 MachineInstr *LastInst = I; 289 290 // If there is only one terminator instruction, process it. 291 unsigned LastOpc = LastInst->getOpcode(); 292 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 293 if (isUncondBranchOpcode(LastOpc)) { 294 TBB = LastInst->getOperand(0).getMBB(); 295 return false; 296 } 297 if (isCondBranchOpcode(LastOpc)) { 298 // Block ends with fall-through condbranch. 299 TBB = LastInst->getOperand(0).getMBB(); 300 Cond.push_back(LastInst->getOperand(1)); 301 Cond.push_back(LastInst->getOperand(2)); 302 return false; 303 } 304 return true; // Can't handle indirect branch. 305 } 306 307 // Get the instruction before it if it is a terminator. 308 MachineInstr *SecondLastInst = I; 309 unsigned SecondLastOpc = SecondLastInst->getOpcode(); 310 311 // If AllowModify is true and the block ends with two or more unconditional 312 // branches, delete all but the first unconditional branch. 313 if (AllowModify && isUncondBranchOpcode(LastOpc)) { 314 while (isUncondBranchOpcode(SecondLastOpc)) { 315 LastInst->eraseFromParent(); 316 LastInst = SecondLastInst; 317 LastOpc = LastInst->getOpcode(); 318 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 319 // Return now the only terminator is an unconditional branch. 320 TBB = LastInst->getOperand(0).getMBB(); 321 return false; 322 } else { 323 SecondLastInst = I; 324 SecondLastOpc = SecondLastInst->getOpcode(); 325 } 326 } 327 } 328 329 // If there are three terminators, we don't know what sort of block this is. 330 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 331 return true; 332 333 // If the block ends with a B and a Bcc, handle it. 334 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 335 TBB = SecondLastInst->getOperand(0).getMBB(); 336 Cond.push_back(SecondLastInst->getOperand(1)); 337 Cond.push_back(SecondLastInst->getOperand(2)); 338 FBB = LastInst->getOperand(0).getMBB(); 339 return false; 340 } 341 342 // If the block ends with two unconditional branches, handle it. The second 343 // one is not executed, so remove it. 344 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 345 TBB = SecondLastInst->getOperand(0).getMBB(); 346 I = LastInst; 347 if (AllowModify) 348 I->eraseFromParent(); 349 return false; 350 } 351 352 // ...likewise if it ends with a branch table followed by an unconditional 353 // branch. The branch folder can create these, and we must get rid of them for 354 // correctness of Thumb constant islands. 355 if ((isJumpTableBranchOpcode(SecondLastOpc) || 356 isIndirectBranchOpcode(SecondLastOpc)) && 357 isUncondBranchOpcode(LastOpc)) { 358 I = LastInst; 359 if (AllowModify) 360 I->eraseFromParent(); 361 return true; 362 } 363 364 // Otherwise, can't handle this. 365 return true; 366 } 367 368 369 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 370 MachineBasicBlock::iterator I = MBB.end(); 371 if (I == MBB.begin()) return 0; 372 --I; 373 while (I->isDebugValue()) { 374 if (I == MBB.begin()) 375 return 0; 376 --I; 377 } 378 if (!isUncondBranchOpcode(I->getOpcode()) && 379 !isCondBranchOpcode(I->getOpcode())) 380 return 0; 381 382 // Remove the branch. 383 I->eraseFromParent(); 384 385 I = MBB.end(); 386 387 if (I == MBB.begin()) return 1; 388 --I; 389 if (!isCondBranchOpcode(I->getOpcode())) 390 return 1; 391 392 // Remove the branch. 393 I->eraseFromParent(); 394 return 2; 395 } 396 397 unsigned 398 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 399 MachineBasicBlock *FBB, 400 const SmallVectorImpl<MachineOperand> &Cond, 401 DebugLoc DL) const { 402 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 403 int BOpc = !AFI->isThumbFunction() 404 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 405 int BccOpc = !AFI->isThumbFunction() 406 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 407 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function(); 408 409 // Shouldn't be a fall through. 410 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 411 assert((Cond.size() == 2 || Cond.size() == 0) && 412 "ARM branch conditions have two components!"); 413 414 if (FBB == 0) { 415 if (Cond.empty()) { // Unconditional branch? 416 if (isThumb) 417 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0); 418 else 419 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 420 } else 421 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 422 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 423 return 1; 424 } 425 426 // Two-way conditional branch. 427 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 428 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 429 if (isThumb) 430 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0); 431 else 432 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 433 return 2; 434 } 435 436 bool ARMBaseInstrInfo:: 437 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 438 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 439 Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 440 return false; 441 } 442 443 bool ARMBaseInstrInfo:: 444 PredicateInstruction(MachineInstr *MI, 445 const SmallVectorImpl<MachineOperand> &Pred) const { 446 unsigned Opc = MI->getOpcode(); 447 if (isUncondBranchOpcode(Opc)) { 448 MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 449 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 450 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 451 return true; 452 } 453 454 int PIdx = MI->findFirstPredOperandIdx(); 455 if (PIdx != -1) { 456 MachineOperand &PMO = MI->getOperand(PIdx); 457 PMO.setImm(Pred[0].getImm()); 458 MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 459 return true; 460 } 461 return false; 462 } 463 464 bool ARMBaseInstrInfo:: 465 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 466 const SmallVectorImpl<MachineOperand> &Pred2) const { 467 if (Pred1.size() > 2 || Pred2.size() > 2) 468 return false; 469 470 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 471 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 472 if (CC1 == CC2) 473 return true; 474 475 switch (CC1) { 476 default: 477 return false; 478 case ARMCC::AL: 479 return true; 480 case ARMCC::HS: 481 return CC2 == ARMCC::HI; 482 case ARMCC::LS: 483 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 484 case ARMCC::GE: 485 return CC2 == ARMCC::GT; 486 case ARMCC::LE: 487 return CC2 == ARMCC::LT; 488 } 489 } 490 491 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 492 std::vector<MachineOperand> &Pred) const { 493 // FIXME: This confuses implicit_def with optional CPSR def. 494 const MCInstrDesc &MCID = MI->getDesc(); 495 if (!MCID.getImplicitDefs() && !MCID.hasOptionalDef()) 496 return false; 497 498 bool Found = false; 499 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 500 const MachineOperand &MO = MI->getOperand(i); 501 if (MO.isReg() && MO.getReg() == ARM::CPSR) { 502 Pred.push_back(MO); 503 Found = true; 504 } 505 } 506 507 return Found; 508 } 509 510 /// isPredicable - Return true if the specified instruction can be predicated. 511 /// By default, this returns true for every instruction with a 512 /// PredicateOperand. 513 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 514 const MCInstrDesc &MCID = MI->getDesc(); 515 if (!MCID.isPredicable()) 516 return false; 517 518 if ((MCID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { 519 ARMFunctionInfo *AFI = 520 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 521 return AFI->isThumb2Function(); 522 } 523 return true; 524 } 525 526 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 527 LLVM_ATTRIBUTE_NOINLINE 528 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 529 unsigned JTI); 530 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 531 unsigned JTI) { 532 assert(JTI < JT.size()); 533 return JT[JTI].MBBs.size(); 534 } 535 536 /// GetInstSize - Return the size of the specified MachineInstr. 537 /// 538 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 539 const MachineBasicBlock &MBB = *MI->getParent(); 540 const MachineFunction *MF = MBB.getParent(); 541 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 542 543 const MCInstrDesc &MCID = MI->getDesc(); 544 if (MCID.getSize()) 545 return MCID.getSize(); 546 547 // If this machine instr is an inline asm, measure it. 548 if (MI->getOpcode() == ARM::INLINEASM) 549 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 550 if (MI->isLabel()) 551 return 0; 552 unsigned Opc = MI->getOpcode(); 553 switch (Opc) { 554 case TargetOpcode::IMPLICIT_DEF: 555 case TargetOpcode::KILL: 556 case TargetOpcode::PROLOG_LABEL: 557 case TargetOpcode::EH_LABEL: 558 case TargetOpcode::DBG_VALUE: 559 return 0; 560 case ARM::MOVi16_ga_pcrel: 561 case ARM::MOVTi16_ga_pcrel: 562 case ARM::t2MOVi16_ga_pcrel: 563 case ARM::t2MOVTi16_ga_pcrel: 564 return 4; 565 case ARM::MOVi32imm: 566 case ARM::t2MOVi32imm: 567 return 8; 568 case ARM::CONSTPOOL_ENTRY: 569 // If this machine instr is a constant pool entry, its size is recorded as 570 // operand #2. 571 return MI->getOperand(2).getImm(); 572 case ARM::Int_eh_sjlj_longjmp: 573 return 16; 574 case ARM::tInt_eh_sjlj_longjmp: 575 return 10; 576 case ARM::Int_eh_sjlj_setjmp: 577 case ARM::Int_eh_sjlj_setjmp_nofp: 578 return 20; 579 case ARM::tInt_eh_sjlj_setjmp: 580 case ARM::t2Int_eh_sjlj_setjmp: 581 case ARM::t2Int_eh_sjlj_setjmp_nofp: 582 return 12; 583 case ARM::BR_JTr: 584 case ARM::BR_JTm: 585 case ARM::BR_JTadd: 586 case ARM::tBR_JTr: 587 case ARM::t2BR_JT: 588 case ARM::t2TBB_JT: 589 case ARM::t2TBH_JT: { 590 // These are jumptable branches, i.e. a branch followed by an inlined 591 // jumptable. The size is 4 + 4 * number of entries. For TBB, each 592 // entry is one byte; TBH two byte each. 593 unsigned EntrySize = (Opc == ARM::t2TBB_JT) 594 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4); 595 unsigned NumOps = MCID.getNumOperands(); 596 MachineOperand JTOP = 597 MI->getOperand(NumOps - (MCID.isPredicable() ? 3 : 2)); 598 unsigned JTI = JTOP.getIndex(); 599 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 600 assert(MJTI != 0); 601 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 602 assert(JTI < JT.size()); 603 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 604 // 4 aligned. The assembler / linker may add 2 byte padding just before 605 // the JT entries. The size does not include this padding; the 606 // constant islands pass does separate bookkeeping for it. 607 // FIXME: If we know the size of the function is less than (1 << 16) *2 608 // bytes, we can use 16-bit entries instead. Then there won't be an 609 // alignment issue. 610 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 611 unsigned NumEntries = getNumJTEntries(JT, JTI); 612 if (Opc == ARM::t2TBB_JT && (NumEntries & 1)) 613 // Make sure the instruction that follows TBB is 2-byte aligned. 614 // FIXME: Constant island pass should insert an "ALIGN" instruction 615 // instead. 616 ++NumEntries; 617 return NumEntries * EntrySize + InstSize; 618 } 619 default: 620 // Otherwise, pseudo-instruction sizes are zero. 621 return 0; 622 } 623 return 0; // Not reached 624 } 625 626 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 627 MachineBasicBlock::iterator I, DebugLoc DL, 628 unsigned DestReg, unsigned SrcReg, 629 bool KillSrc) const { 630 bool GPRDest = ARM::GPRRegClass.contains(DestReg); 631 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); 632 633 if (GPRDest && GPRSrc) { 634 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) 635 .addReg(SrcReg, getKillRegState(KillSrc)))); 636 return; 637 } 638 639 bool SPRDest = ARM::SPRRegClass.contains(DestReg); 640 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); 641 642 unsigned Opc = 0; 643 if (SPRDest && SPRSrc) { 644 Opc = ARM::VMOVS; 645 646 // An even S-S copy may be feeding a NEON v2f32 instruction being used for 647 // f32 operations. In that case, it is better to copy the full D-regs with 648 // a VMOVD since that can be converted to a NEON-domain move by 649 // NEONMoveFix.cpp. Check that MI is the original COPY instruction, and 650 // that it really defines the whole D-register. 651 if (WidenVMOVS && 652 (DestReg - ARM::S0) % 2 == 0 && (SrcReg - ARM::S0) % 2 == 0 && 653 I != MBB.end() && I->isCopy() && 654 I->getOperand(0).getReg() == DestReg && 655 I->getOperand(1).getReg() == SrcReg) { 656 // I is pointing to the ortiginal COPY instruction. 657 // Find the parent D-registers. 658 const TargetRegisterInfo *TRI = &getRegisterInfo(); 659 unsigned SrcD = TRI->getMatchingSuperReg(SrcReg, ARM::ssub_0, 660 &ARM::DPRRegClass); 661 unsigned DestD = TRI->getMatchingSuperReg(DestReg, ARM::ssub_0, 662 &ARM::DPRRegClass); 663 // Be careful to not clobber an INSERT_SUBREG that reads and redefines a 664 // D-register. There must be an <imp-def> of destD, and no <imp-use>. 665 if (I->definesRegister(DestD, TRI) && !I->readsRegister(DestD, TRI)) { 666 Opc = ARM::VMOVD; 667 SrcReg = SrcD; 668 DestReg = DestD; 669 if (KillSrc) 670 KillSrc = I->killsRegister(SrcReg, TRI); 671 } 672 } 673 } else if (GPRDest && SPRSrc) 674 Opc = ARM::VMOVRS; 675 else if (SPRDest && GPRSrc) 676 Opc = ARM::VMOVSR; 677 else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) 678 Opc = ARM::VMOVD; 679 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) 680 Opc = ARM::VORRq; 681 682 if (Opc) { 683 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); 684 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 685 if (Opc == ARM::VORRq) 686 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 687 AddDefaultPred(MIB); 688 return; 689 } 690 691 // Generate instructions for VMOVQQ and VMOVQQQQ pseudos in place. 692 if (ARM::QQPRRegClass.contains(DestReg, SrcReg) || 693 ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) { 694 const TargetRegisterInfo *TRI = &getRegisterInfo(); 695 assert(ARM::qsub_0 + 3 == ARM::qsub_3 && "Expected contiguous enum."); 696 unsigned EndSubReg = ARM::QQPRRegClass.contains(DestReg, SrcReg) ? 697 ARM::qsub_1 : ARM::qsub_3; 698 for (unsigned i = ARM::qsub_0, e = EndSubReg + 1; i != e; ++i) { 699 unsigned Dst = TRI->getSubReg(DestReg, i); 700 unsigned Src = TRI->getSubReg(SrcReg, i); 701 MachineInstrBuilder Mov = 702 AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VORRq)) 703 .addReg(Dst, RegState::Define) 704 .addReg(Src, getKillRegState(KillSrc)) 705 .addReg(Src, getKillRegState(KillSrc))); 706 if (i == EndSubReg) { 707 Mov->addRegisterDefined(DestReg, TRI); 708 if (KillSrc) 709 Mov->addRegisterKilled(SrcReg, TRI); 710 } 711 } 712 return; 713 } 714 llvm_unreachable("Impossible reg-to-reg copy"); 715 } 716 717 static const 718 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, 719 unsigned Reg, unsigned SubIdx, unsigned State, 720 const TargetRegisterInfo *TRI) { 721 if (!SubIdx) 722 return MIB.addReg(Reg, State); 723 724 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 725 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 726 return MIB.addReg(Reg, State, SubIdx); 727 } 728 729 void ARMBaseInstrInfo:: 730 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 731 unsigned SrcReg, bool isKill, int FI, 732 const TargetRegisterClass *RC, 733 const TargetRegisterInfo *TRI) const { 734 DebugLoc DL; 735 if (I != MBB.end()) DL = I->getDebugLoc(); 736 MachineFunction &MF = *MBB.getParent(); 737 MachineFrameInfo &MFI = *MF.getFrameInfo(); 738 unsigned Align = MFI.getObjectAlignment(FI); 739 740 MachineMemOperand *MMO = 741 MF.getMachineMemOperand(MachinePointerInfo( 742 PseudoSourceValue::getFixedStack(FI)), 743 MachineMemOperand::MOStore, 744 MFI.getObjectSize(FI), 745 Align); 746 747 switch (RC->getSize()) { 748 case 4: 749 if (ARM::GPRRegClass.hasSubClassEq(RC)) { 750 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12)) 751 .addReg(SrcReg, getKillRegState(isKill)) 752 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 753 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 754 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 755 .addReg(SrcReg, getKillRegState(isKill)) 756 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 757 } else 758 llvm_unreachable("Unknown reg class!"); 759 break; 760 case 8: 761 if (ARM::DPRRegClass.hasSubClassEq(RC)) { 762 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 763 .addReg(SrcReg, getKillRegState(isKill)) 764 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 765 } else 766 llvm_unreachable("Unknown reg class!"); 767 break; 768 case 16: 769 if (ARM::QPRRegClass.hasSubClassEq(RC)) { 770 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { 771 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo)) 772 .addFrameIndex(FI).addImm(16) 773 .addReg(SrcReg, getKillRegState(isKill)) 774 .addMemOperand(MMO)); 775 } else { 776 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA)) 777 .addReg(SrcReg, getKillRegState(isKill)) 778 .addFrameIndex(FI) 779 .addMemOperand(MMO)); 780 } 781 } else 782 llvm_unreachable("Unknown reg class!"); 783 break; 784 case 32: 785 if (ARM::QQPRRegClass.hasSubClassEq(RC)) { 786 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 787 // FIXME: It's possible to only store part of the QQ register if the 788 // spilled def has a sub-register index. 789 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) 790 .addFrameIndex(FI).addImm(16) 791 .addReg(SrcReg, getKillRegState(isKill)) 792 .addMemOperand(MMO)); 793 } else { 794 MachineInstrBuilder MIB = 795 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 796 .addFrameIndex(FI)) 797 .addMemOperand(MMO); 798 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 799 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 800 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 801 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 802 } 803 } else 804 llvm_unreachable("Unknown reg class!"); 805 break; 806 case 64: 807 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 808 MachineInstrBuilder MIB = 809 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 810 .addFrameIndex(FI)) 811 .addMemOperand(MMO); 812 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 813 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 814 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 815 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 816 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); 817 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); 818 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); 819 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); 820 } else 821 llvm_unreachable("Unknown reg class!"); 822 break; 823 default: 824 llvm_unreachable("Unknown reg class!"); 825 } 826 } 827 828 unsigned 829 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 830 int &FrameIndex) const { 831 switch (MI->getOpcode()) { 832 default: break; 833 case ARM::STRrs: 834 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 835 if (MI->getOperand(1).isFI() && 836 MI->getOperand(2).isReg() && 837 MI->getOperand(3).isImm() && 838 MI->getOperand(2).getReg() == 0 && 839 MI->getOperand(3).getImm() == 0) { 840 FrameIndex = MI->getOperand(1).getIndex(); 841 return MI->getOperand(0).getReg(); 842 } 843 break; 844 case ARM::STRi12: 845 case ARM::t2STRi12: 846 case ARM::tSTRspi: 847 case ARM::VSTRD: 848 case ARM::VSTRS: 849 if (MI->getOperand(1).isFI() && 850 MI->getOperand(2).isImm() && 851 MI->getOperand(2).getImm() == 0) { 852 FrameIndex = MI->getOperand(1).getIndex(); 853 return MI->getOperand(0).getReg(); 854 } 855 break; 856 case ARM::VST1q64Pseudo: 857 if (MI->getOperand(0).isFI() && 858 MI->getOperand(2).getSubReg() == 0) { 859 FrameIndex = MI->getOperand(0).getIndex(); 860 return MI->getOperand(2).getReg(); 861 } 862 break; 863 case ARM::VSTMQIA: 864 if (MI->getOperand(1).isFI() && 865 MI->getOperand(0).getSubReg() == 0) { 866 FrameIndex = MI->getOperand(1).getIndex(); 867 return MI->getOperand(0).getReg(); 868 } 869 break; 870 } 871 872 return 0; 873 } 874 875 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 876 int &FrameIndex) const { 877 const MachineMemOperand *Dummy; 878 return MI->getDesc().mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex); 879 } 880 881 void ARMBaseInstrInfo:: 882 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 883 unsigned DestReg, int FI, 884 const TargetRegisterClass *RC, 885 const TargetRegisterInfo *TRI) const { 886 DebugLoc DL; 887 if (I != MBB.end()) DL = I->getDebugLoc(); 888 MachineFunction &MF = *MBB.getParent(); 889 MachineFrameInfo &MFI = *MF.getFrameInfo(); 890 unsigned Align = MFI.getObjectAlignment(FI); 891 MachineMemOperand *MMO = 892 MF.getMachineMemOperand( 893 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 894 MachineMemOperand::MOLoad, 895 MFI.getObjectSize(FI), 896 Align); 897 898 switch (RC->getSize()) { 899 case 4: 900 if (ARM::GPRRegClass.hasSubClassEq(RC)) { 901 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) 902 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 903 904 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 905 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 906 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 907 } else 908 llvm_unreachable("Unknown reg class!"); 909 break; 910 case 8: 911 if (ARM::DPRRegClass.hasSubClassEq(RC)) { 912 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 913 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 914 } else 915 llvm_unreachable("Unknown reg class!"); 916 break; 917 case 16: 918 if (ARM::QPRRegClass.hasSubClassEq(RC)) { 919 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { 920 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg) 921 .addFrameIndex(FI).addImm(16) 922 .addMemOperand(MMO)); 923 } else { 924 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) 925 .addFrameIndex(FI) 926 .addMemOperand(MMO)); 927 } 928 } else 929 llvm_unreachable("Unknown reg class!"); 930 break; 931 case 32: 932 if (ARM::QQPRRegClass.hasSubClassEq(RC)) { 933 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 934 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) 935 .addFrameIndex(FI).addImm(16) 936 .addMemOperand(MMO)); 937 } else { 938 MachineInstrBuilder MIB = 939 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 940 .addFrameIndex(FI)) 941 .addMemOperand(MMO); 942 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 943 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 944 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 945 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 946 MIB.addReg(DestReg, RegState::Define | RegState::Implicit); 947 } 948 } else 949 llvm_unreachable("Unknown reg class!"); 950 break; 951 case 64: 952 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 953 MachineInstrBuilder MIB = 954 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 955 .addFrameIndex(FI)) 956 .addMemOperand(MMO); 957 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 958 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 959 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 960 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 961 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI); 962 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI); 963 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI); 964 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI); 965 MIB.addReg(DestReg, RegState::Define | RegState::Implicit); 966 } else 967 llvm_unreachable("Unknown reg class!"); 968 break; 969 default: 970 llvm_unreachable("Unknown regclass!"); 971 } 972 } 973 974 unsigned 975 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 976 int &FrameIndex) const { 977 switch (MI->getOpcode()) { 978 default: break; 979 case ARM::LDRrs: 980 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 981 if (MI->getOperand(1).isFI() && 982 MI->getOperand(2).isReg() && 983 MI->getOperand(3).isImm() && 984 MI->getOperand(2).getReg() == 0 && 985 MI->getOperand(3).getImm() == 0) { 986 FrameIndex = MI->getOperand(1).getIndex(); 987 return MI->getOperand(0).getReg(); 988 } 989 break; 990 case ARM::LDRi12: 991 case ARM::t2LDRi12: 992 case ARM::tLDRspi: 993 case ARM::VLDRD: 994 case ARM::VLDRS: 995 if (MI->getOperand(1).isFI() && 996 MI->getOperand(2).isImm() && 997 MI->getOperand(2).getImm() == 0) { 998 FrameIndex = MI->getOperand(1).getIndex(); 999 return MI->getOperand(0).getReg(); 1000 } 1001 break; 1002 case ARM::VLD1q64Pseudo: 1003 if (MI->getOperand(1).isFI() && 1004 MI->getOperand(0).getSubReg() == 0) { 1005 FrameIndex = MI->getOperand(1).getIndex(); 1006 return MI->getOperand(0).getReg(); 1007 } 1008 break; 1009 case ARM::VLDMQIA: 1010 if (MI->getOperand(1).isFI() && 1011 MI->getOperand(0).getSubReg() == 0) { 1012 FrameIndex = MI->getOperand(1).getIndex(); 1013 return MI->getOperand(0).getReg(); 1014 } 1015 break; 1016 } 1017 1018 return 0; 1019 } 1020 1021 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 1022 int &FrameIndex) const { 1023 const MachineMemOperand *Dummy; 1024 return MI->getDesc().mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex); 1025 } 1026 1027 MachineInstr* 1028 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 1029 int FrameIx, uint64_t Offset, 1030 const MDNode *MDPtr, 1031 DebugLoc DL) const { 1032 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) 1033 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); 1034 return &*MIB; 1035 } 1036 1037 /// Create a copy of a const pool value. Update CPI to the new index and return 1038 /// the label UID. 1039 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 1040 MachineConstantPool *MCP = MF.getConstantPool(); 1041 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1042 1043 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 1044 assert(MCPE.isMachineConstantPoolEntry() && 1045 "Expecting a machine constantpool entry!"); 1046 ARMConstantPoolValue *ACPV = 1047 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 1048 1049 unsigned PCLabelId = AFI->createPICLabelUId(); 1050 ARMConstantPoolValue *NewCPV = 0; 1051 // FIXME: The below assumes PIC relocation model and that the function 1052 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and 1053 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR 1054 // instructions, so that's probably OK, but is PIC always correct when 1055 // we get here? 1056 if (ACPV->isGlobalValue()) 1057 NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId, 1058 ARMCP::CPValue, 4); 1059 else if (ACPV->isExtSymbol()) 1060 NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(), 1061 ACPV->getSymbol(), PCLabelId, 4); 1062 else if (ACPV->isBlockAddress()) 1063 NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId, 1064 ARMCP::CPBlockAddress, 4); 1065 else if (ACPV->isLSDA()) 1066 NewCPV = new ARMConstantPoolValue(MF.getFunction(), PCLabelId, 1067 ARMCP::CPLSDA, 4); 1068 else 1069 llvm_unreachable("Unexpected ARM constantpool value type!!"); 1070 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 1071 return PCLabelId; 1072 } 1073 1074 void ARMBaseInstrInfo:: 1075 reMaterialize(MachineBasicBlock &MBB, 1076 MachineBasicBlock::iterator I, 1077 unsigned DestReg, unsigned SubIdx, 1078 const MachineInstr *Orig, 1079 const TargetRegisterInfo &TRI) const { 1080 unsigned Opcode = Orig->getOpcode(); 1081 switch (Opcode) { 1082 default: { 1083 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1084 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1085 MBB.insert(I, MI); 1086 break; 1087 } 1088 case ARM::tLDRpci_pic: 1089 case ARM::t2LDRpci_pic: { 1090 MachineFunction &MF = *MBB.getParent(); 1091 unsigned CPI = Orig->getOperand(1).getIndex(); 1092 unsigned PCLabelId = duplicateCPV(MF, CPI); 1093 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1094 DestReg) 1095 .addConstantPoolIndex(CPI).addImm(PCLabelId); 1096 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 1097 break; 1098 } 1099 } 1100 } 1101 1102 MachineInstr * 1103 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 1104 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF); 1105 switch(Orig->getOpcode()) { 1106 case ARM::tLDRpci_pic: 1107 case ARM::t2LDRpci_pic: { 1108 unsigned CPI = Orig->getOperand(1).getIndex(); 1109 unsigned PCLabelId = duplicateCPV(MF, CPI); 1110 Orig->getOperand(1).setIndex(CPI); 1111 Orig->getOperand(2).setImm(PCLabelId); 1112 break; 1113 } 1114 } 1115 return MI; 1116 } 1117 1118 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 1119 const MachineInstr *MI1, 1120 const MachineRegisterInfo *MRI) const { 1121 int Opcode = MI0->getOpcode(); 1122 if (Opcode == ARM::t2LDRpci || 1123 Opcode == ARM::t2LDRpci_pic || 1124 Opcode == ARM::tLDRpci || 1125 Opcode == ARM::tLDRpci_pic || 1126 Opcode == ARM::MOV_ga_dyn || 1127 Opcode == ARM::MOV_ga_pcrel || 1128 Opcode == ARM::MOV_ga_pcrel_ldr || 1129 Opcode == ARM::t2MOV_ga_dyn || 1130 Opcode == ARM::t2MOV_ga_pcrel) { 1131 if (MI1->getOpcode() != Opcode) 1132 return false; 1133 if (MI0->getNumOperands() != MI1->getNumOperands()) 1134 return false; 1135 1136 const MachineOperand &MO0 = MI0->getOperand(1); 1137 const MachineOperand &MO1 = MI1->getOperand(1); 1138 if (MO0.getOffset() != MO1.getOffset()) 1139 return false; 1140 1141 if (Opcode == ARM::MOV_ga_dyn || 1142 Opcode == ARM::MOV_ga_pcrel || 1143 Opcode == ARM::MOV_ga_pcrel_ldr || 1144 Opcode == ARM::t2MOV_ga_dyn || 1145 Opcode == ARM::t2MOV_ga_pcrel) 1146 // Ignore the PC labels. 1147 return MO0.getGlobal() == MO1.getGlobal(); 1148 1149 const MachineFunction *MF = MI0->getParent()->getParent(); 1150 const MachineConstantPool *MCP = MF->getConstantPool(); 1151 int CPI0 = MO0.getIndex(); 1152 int CPI1 = MO1.getIndex(); 1153 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1154 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1155 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry(); 1156 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry(); 1157 if (isARMCP0 && isARMCP1) { 1158 ARMConstantPoolValue *ACPV0 = 1159 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1160 ARMConstantPoolValue *ACPV1 = 1161 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1162 return ACPV0->hasSameValue(ACPV1); 1163 } else if (!isARMCP0 && !isARMCP1) { 1164 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal; 1165 } 1166 return false; 1167 } else if (Opcode == ARM::PICLDR) { 1168 if (MI1->getOpcode() != Opcode) 1169 return false; 1170 if (MI0->getNumOperands() != MI1->getNumOperands()) 1171 return false; 1172 1173 unsigned Addr0 = MI0->getOperand(1).getReg(); 1174 unsigned Addr1 = MI1->getOperand(1).getReg(); 1175 if (Addr0 != Addr1) { 1176 if (!MRI || 1177 !TargetRegisterInfo::isVirtualRegister(Addr0) || 1178 !TargetRegisterInfo::isVirtualRegister(Addr1)) 1179 return false; 1180 1181 // This assumes SSA form. 1182 MachineInstr *Def0 = MRI->getVRegDef(Addr0); 1183 MachineInstr *Def1 = MRI->getVRegDef(Addr1); 1184 // Check if the loaded value, e.g. a constantpool of a global address, are 1185 // the same. 1186 if (!produceSameValue(Def0, Def1, MRI)) 1187 return false; 1188 } 1189 1190 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) { 1191 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg 1192 const MachineOperand &MO0 = MI0->getOperand(i); 1193 const MachineOperand &MO1 = MI1->getOperand(i); 1194 if (!MO0.isIdenticalTo(MO1)) 1195 return false; 1196 } 1197 return true; 1198 } 1199 1200 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1201 } 1202 1203 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 1204 /// determine if two loads are loading from the same base address. It should 1205 /// only return true if the base pointers are the same and the only differences 1206 /// between the two addresses is the offset. It also returns the offsets by 1207 /// reference. 1208 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 1209 int64_t &Offset1, 1210 int64_t &Offset2) const { 1211 // Don't worry about Thumb: just ARM and Thumb2. 1212 if (Subtarget.isThumb1Only()) return false; 1213 1214 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 1215 return false; 1216 1217 switch (Load1->getMachineOpcode()) { 1218 default: 1219 return false; 1220 case ARM::LDRi12: 1221 case ARM::LDRBi12: 1222 case ARM::LDRD: 1223 case ARM::LDRH: 1224 case ARM::LDRSB: 1225 case ARM::LDRSH: 1226 case ARM::VLDRD: 1227 case ARM::VLDRS: 1228 case ARM::t2LDRi8: 1229 case ARM::t2LDRDi8: 1230 case ARM::t2LDRSHi8: 1231 case ARM::t2LDRi12: 1232 case ARM::t2LDRSHi12: 1233 break; 1234 } 1235 1236 switch (Load2->getMachineOpcode()) { 1237 default: 1238 return false; 1239 case ARM::LDRi12: 1240 case ARM::LDRBi12: 1241 case ARM::LDRD: 1242 case ARM::LDRH: 1243 case ARM::LDRSB: 1244 case ARM::LDRSH: 1245 case ARM::VLDRD: 1246 case ARM::VLDRS: 1247 case ARM::t2LDRi8: 1248 case ARM::t2LDRDi8: 1249 case ARM::t2LDRSHi8: 1250 case ARM::t2LDRi12: 1251 case ARM::t2LDRSHi12: 1252 break; 1253 } 1254 1255 // Check if base addresses and chain operands match. 1256 if (Load1->getOperand(0) != Load2->getOperand(0) || 1257 Load1->getOperand(4) != Load2->getOperand(4)) 1258 return false; 1259 1260 // Index should be Reg0. 1261 if (Load1->getOperand(3) != Load2->getOperand(3)) 1262 return false; 1263 1264 // Determine the offsets. 1265 if (isa<ConstantSDNode>(Load1->getOperand(1)) && 1266 isa<ConstantSDNode>(Load2->getOperand(1))) { 1267 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); 1268 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); 1269 return true; 1270 } 1271 1272 return false; 1273 } 1274 1275 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 1276 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 1277 /// be scheduled togther. On some targets if two loads are loading from 1278 /// addresses in the same cache line, it's better if they are scheduled 1279 /// together. This function takes two integers that represent the load offsets 1280 /// from the common base address. It returns true if it decides it's desirable 1281 /// to schedule the two loads together. "NumLoads" is the number of loads that 1282 /// have already been scheduled after Load1. 1283 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 1284 int64_t Offset1, int64_t Offset2, 1285 unsigned NumLoads) const { 1286 // Don't worry about Thumb: just ARM and Thumb2. 1287 if (Subtarget.isThumb1Only()) return false; 1288 1289 assert(Offset2 > Offset1); 1290 1291 if ((Offset2 - Offset1) / 8 > 64) 1292 return false; 1293 1294 if (Load1->getMachineOpcode() != Load2->getMachineOpcode()) 1295 return false; // FIXME: overly conservative? 1296 1297 // Four loads in a row should be sufficient. 1298 if (NumLoads >= 3) 1299 return false; 1300 1301 return true; 1302 } 1303 1304 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 1305 const MachineBasicBlock *MBB, 1306 const MachineFunction &MF) const { 1307 // Debug info is never a scheduling boundary. It's necessary to be explicit 1308 // due to the special treatment of IT instructions below, otherwise a 1309 // dbg_value followed by an IT will result in the IT instruction being 1310 // considered a scheduling hazard, which is wrong. It should be the actual 1311 // instruction preceding the dbg_value instruction(s), just like it is 1312 // when debug info is not present. 1313 if (MI->isDebugValue()) 1314 return false; 1315 1316 // Terminators and labels can't be scheduled around. 1317 if (MI->getDesc().isTerminator() || MI->isLabel()) 1318 return true; 1319 1320 // Treat the start of the IT block as a scheduling boundary, but schedule 1321 // t2IT along with all instructions following it. 1322 // FIXME: This is a big hammer. But the alternative is to add all potential 1323 // true and anti dependencies to IT block instructions as implicit operands 1324 // to the t2IT instruction. The added compile time and complexity does not 1325 // seem worth it. 1326 MachineBasicBlock::const_iterator I = MI; 1327 // Make sure to skip any dbg_value instructions 1328 while (++I != MBB->end() && I->isDebugValue()) 1329 ; 1330 if (I != MBB->end() && I->getOpcode() == ARM::t2IT) 1331 return true; 1332 1333 // Don't attempt to schedule around any instruction that defines 1334 // a stack-oriented pointer, as it's unlikely to be profitable. This 1335 // saves compile time, because it doesn't require every single 1336 // stack slot reference to depend on the instruction that does the 1337 // modification. 1338 if (MI->definesRegister(ARM::SP)) 1339 return true; 1340 1341 return false; 1342 } 1343 1344 bool ARMBaseInstrInfo:: 1345 isProfitableToIfCvt(MachineBasicBlock &MBB, 1346 unsigned NumCycles, unsigned ExtraPredCycles, 1347 const BranchProbability &Probability) const { 1348 if (!NumCycles) 1349 return false; 1350 1351 // Attempt to estimate the relative costs of predication versus branching. 1352 unsigned UnpredCost = Probability.getNumerator() * NumCycles; 1353 UnpredCost /= Probability.getDenominator(); 1354 UnpredCost += 1; // The branch itself 1355 UnpredCost += Subtarget.getMispredictionPenalty() / 10; 1356 1357 return (NumCycles + ExtraPredCycles) <= UnpredCost; 1358 } 1359 1360 bool ARMBaseInstrInfo:: 1361 isProfitableToIfCvt(MachineBasicBlock &TMBB, 1362 unsigned TCycles, unsigned TExtra, 1363 MachineBasicBlock &FMBB, 1364 unsigned FCycles, unsigned FExtra, 1365 const BranchProbability &Probability) const { 1366 if (!TCycles || !FCycles) 1367 return false; 1368 1369 // Attempt to estimate the relative costs of predication versus branching. 1370 unsigned TUnpredCost = Probability.getNumerator() * TCycles; 1371 TUnpredCost /= Probability.getDenominator(); 1372 1373 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator(); 1374 unsigned FUnpredCost = Comp * FCycles; 1375 FUnpredCost /= Probability.getDenominator(); 1376 1377 unsigned UnpredCost = TUnpredCost + FUnpredCost; 1378 UnpredCost += 1; // The branch itself 1379 UnpredCost += Subtarget.getMispredictionPenalty() / 10; 1380 1381 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost; 1382 } 1383 1384 /// getInstrPredicate - If instruction is predicated, returns its predicate 1385 /// condition, otherwise returns AL. It also returns the condition code 1386 /// register by reference. 1387 ARMCC::CondCodes 1388 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 1389 int PIdx = MI->findFirstPredOperandIdx(); 1390 if (PIdx == -1) { 1391 PredReg = 0; 1392 return ARMCC::AL; 1393 } 1394 1395 PredReg = MI->getOperand(PIdx+1).getReg(); 1396 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 1397 } 1398 1399 1400 int llvm::getMatchingCondBranchOpcode(int Opc) { 1401 if (Opc == ARM::B) 1402 return ARM::Bcc; 1403 else if (Opc == ARM::tB) 1404 return ARM::tBcc; 1405 else if (Opc == ARM::t2B) 1406 return ARM::t2Bcc; 1407 1408 llvm_unreachable("Unknown unconditional branch opcode!"); 1409 return 0; 1410 } 1411 1412 1413 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 1414 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 1415 unsigned DestReg, unsigned BaseReg, int NumBytes, 1416 ARMCC::CondCodes Pred, unsigned PredReg, 1417 const ARMBaseInstrInfo &TII, unsigned MIFlags) { 1418 bool isSub = NumBytes < 0; 1419 if (isSub) NumBytes = -NumBytes; 1420 1421 while (NumBytes) { 1422 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 1423 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 1424 assert(ThisVal && "Didn't extract field correctly"); 1425 1426 // We will handle these bits from offset, clear them. 1427 NumBytes &= ~ThisVal; 1428 1429 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 1430 1431 // Build the new ADD / SUB. 1432 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 1433 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 1434 .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 1435 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 1436 .setMIFlags(MIFlags); 1437 BaseReg = DestReg; 1438 } 1439 } 1440 1441 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1442 unsigned FrameReg, int &Offset, 1443 const ARMBaseInstrInfo &TII) { 1444 unsigned Opcode = MI.getOpcode(); 1445 const MCInstrDesc &Desc = MI.getDesc(); 1446 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 1447 bool isSub = false; 1448 1449 // Memory operands in inline assembly always use AddrMode2. 1450 if (Opcode == ARM::INLINEASM) 1451 AddrMode = ARMII::AddrMode2; 1452 1453 if (Opcode == ARM::ADDri) { 1454 Offset += MI.getOperand(FrameRegIdx+1).getImm(); 1455 if (Offset == 0) { 1456 // Turn it into a move. 1457 MI.setDesc(TII.get(ARM::MOVr)); 1458 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 1459 MI.RemoveOperand(FrameRegIdx+1); 1460 Offset = 0; 1461 return true; 1462 } else if (Offset < 0) { 1463 Offset = -Offset; 1464 isSub = true; 1465 MI.setDesc(TII.get(ARM::SUBri)); 1466 } 1467 1468 // Common case: small offset, fits into instruction. 1469 if (ARM_AM::getSOImmVal(Offset) != -1) { 1470 // Replace the FrameIndex with sp / fp 1471 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 1472 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 1473 Offset = 0; 1474 return true; 1475 } 1476 1477 // Otherwise, pull as much of the immedidate into this ADDri/SUBri 1478 // as possible. 1479 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 1480 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 1481 1482 // We will handle these bits from offset, clear them. 1483 Offset &= ~ThisImmVal; 1484 1485 // Get the properly encoded SOImmVal field. 1486 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 1487 "Bit extraction didn't work?"); 1488 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 1489 } else { 1490 unsigned ImmIdx = 0; 1491 int InstrOffs = 0; 1492 unsigned NumBits = 0; 1493 unsigned Scale = 1; 1494 switch (AddrMode) { 1495 case ARMII::AddrMode_i12: { 1496 ImmIdx = FrameRegIdx + 1; 1497 InstrOffs = MI.getOperand(ImmIdx).getImm(); 1498 NumBits = 12; 1499 break; 1500 } 1501 case ARMII::AddrMode2: { 1502 ImmIdx = FrameRegIdx+2; 1503 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 1504 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 1505 InstrOffs *= -1; 1506 NumBits = 12; 1507 break; 1508 } 1509 case ARMII::AddrMode3: { 1510 ImmIdx = FrameRegIdx+2; 1511 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 1512 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 1513 InstrOffs *= -1; 1514 NumBits = 8; 1515 break; 1516 } 1517 case ARMII::AddrMode4: 1518 case ARMII::AddrMode6: 1519 // Can't fold any offset even if it's zero. 1520 return false; 1521 case ARMII::AddrMode5: { 1522 ImmIdx = FrameRegIdx+1; 1523 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 1524 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 1525 InstrOffs *= -1; 1526 NumBits = 8; 1527 Scale = 4; 1528 break; 1529 } 1530 default: 1531 llvm_unreachable("Unsupported addressing mode!"); 1532 break; 1533 } 1534 1535 Offset += InstrOffs * Scale; 1536 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 1537 if (Offset < 0) { 1538 Offset = -Offset; 1539 isSub = true; 1540 } 1541 1542 // Attempt to fold address comp. if opcode has offset bits 1543 if (NumBits > 0) { 1544 // Common case: small offset, fits into instruction. 1545 MachineOperand &ImmOp = MI.getOperand(ImmIdx); 1546 int ImmedOffset = Offset / Scale; 1547 unsigned Mask = (1 << NumBits) - 1; 1548 if ((unsigned)Offset <= Mask * Scale) { 1549 // Replace the FrameIndex with sp 1550 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 1551 // FIXME: When addrmode2 goes away, this will simplify (like the 1552 // T2 version), as the LDR.i12 versions don't need the encoding 1553 // tricks for the offset value. 1554 if (isSub) { 1555 if (AddrMode == ARMII::AddrMode_i12) 1556 ImmedOffset = -ImmedOffset; 1557 else 1558 ImmedOffset |= 1 << NumBits; 1559 } 1560 ImmOp.ChangeToImmediate(ImmedOffset); 1561 Offset = 0; 1562 return true; 1563 } 1564 1565 // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 1566 ImmedOffset = ImmedOffset & Mask; 1567 if (isSub) { 1568 if (AddrMode == ARMII::AddrMode_i12) 1569 ImmedOffset = -ImmedOffset; 1570 else 1571 ImmedOffset |= 1 << NumBits; 1572 } 1573 ImmOp.ChangeToImmediate(ImmedOffset); 1574 Offset &= ~(Mask*Scale); 1575 } 1576 } 1577 1578 Offset = (isSub) ? -Offset : Offset; 1579 return Offset == 0; 1580 } 1581 1582 bool ARMBaseInstrInfo:: 1583 AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask, 1584 int &CmpValue) const { 1585 switch (MI->getOpcode()) { 1586 default: break; 1587 case ARM::CMPri: 1588 case ARM::t2CMPri: 1589 SrcReg = MI->getOperand(0).getReg(); 1590 CmpMask = ~0; 1591 CmpValue = MI->getOperand(1).getImm(); 1592 return true; 1593 case ARM::TSTri: 1594 case ARM::t2TSTri: 1595 SrcReg = MI->getOperand(0).getReg(); 1596 CmpMask = MI->getOperand(1).getImm(); 1597 CmpValue = 0; 1598 return true; 1599 } 1600 1601 return false; 1602 } 1603 1604 /// isSuitableForMask - Identify a suitable 'and' instruction that 1605 /// operates on the given source register and applies the same mask 1606 /// as a 'tst' instruction. Provide a limited look-through for copies. 1607 /// When successful, MI will hold the found instruction. 1608 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, 1609 int CmpMask, bool CommonUse) { 1610 switch (MI->getOpcode()) { 1611 case ARM::ANDri: 1612 case ARM::t2ANDri: 1613 if (CmpMask != MI->getOperand(2).getImm()) 1614 return false; 1615 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg()) 1616 return true; 1617 break; 1618 case ARM::COPY: { 1619 // Walk down one instruction which is potentially an 'and'. 1620 const MachineInstr &Copy = *MI; 1621 MachineBasicBlock::iterator AND( 1622 llvm::next(MachineBasicBlock::iterator(MI))); 1623 if (AND == MI->getParent()->end()) return false; 1624 MI = AND; 1625 return isSuitableForMask(MI, Copy.getOperand(0).getReg(), 1626 CmpMask, true); 1627 } 1628 } 1629 1630 return false; 1631 } 1632 1633 /// OptimizeCompareInstr - Convert the instruction supplying the argument to the 1634 /// comparison into one that sets the zero bit in the flags register. 1635 bool ARMBaseInstrInfo:: 1636 OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask, 1637 int CmpValue, const MachineRegisterInfo *MRI) const { 1638 if (CmpValue != 0) 1639 return false; 1640 1641 MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg); 1642 if (llvm::next(DI) != MRI->def_end()) 1643 // Only support one definition. 1644 return false; 1645 1646 MachineInstr *MI = &*DI; 1647 1648 // Masked compares sometimes use the same register as the corresponding 'and'. 1649 if (CmpMask != ~0) { 1650 if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) { 1651 MI = 0; 1652 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg), 1653 UE = MRI->use_end(); UI != UE; ++UI) { 1654 if (UI->getParent() != CmpInstr->getParent()) continue; 1655 MachineInstr *PotentialAND = &*UI; 1656 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true)) 1657 continue; 1658 MI = PotentialAND; 1659 break; 1660 } 1661 if (!MI) return false; 1662 } 1663 } 1664 1665 // Conservatively refuse to convert an instruction which isn't in the same BB 1666 // as the comparison. 1667 if (MI->getParent() != CmpInstr->getParent()) 1668 return false; 1669 1670 // Check that CPSR isn't set between the comparison instruction and the one we 1671 // want to change. 1672 MachineBasicBlock::const_iterator I = CmpInstr, E = MI, 1673 B = MI->getParent()->begin(); 1674 1675 // Early exit if CmpInstr is at the beginning of the BB. 1676 if (I == B) return false; 1677 1678 --I; 1679 for (; I != E; --I) { 1680 const MachineInstr &Instr = *I; 1681 1682 for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) { 1683 const MachineOperand &MO = Instr.getOperand(IO); 1684 if (!MO.isReg()) continue; 1685 1686 // This instruction modifies or uses CPSR after the one we want to 1687 // change. We can't do this transformation. 1688 if (MO.getReg() == ARM::CPSR) 1689 return false; 1690 } 1691 1692 if (I == B) 1693 // The 'and' is below the comparison instruction. 1694 return false; 1695 } 1696 1697 // Set the "zero" bit in CPSR. 1698 switch (MI->getOpcode()) { 1699 default: break; 1700 case ARM::RSBrr: 1701 case ARM::RSBri: 1702 case ARM::RSCrr: 1703 case ARM::RSCri: 1704 case ARM::ADDrr: 1705 case ARM::ADDri: 1706 case ARM::ADCrr: 1707 case ARM::ADCri: 1708 case ARM::SUBrr: 1709 case ARM::SUBri: 1710 case ARM::SBCrr: 1711 case ARM::SBCri: 1712 case ARM::t2RSBri: 1713 case ARM::t2ADDrr: 1714 case ARM::t2ADDri: 1715 case ARM::t2ADCrr: 1716 case ARM::t2ADCri: 1717 case ARM::t2SUBrr: 1718 case ARM::t2SUBri: 1719 case ARM::t2SBCrr: 1720 case ARM::t2SBCri: 1721 case ARM::ANDrr: 1722 case ARM::ANDri: 1723 case ARM::t2ANDrr: 1724 case ARM::t2ANDri: 1725 case ARM::ORRrr: 1726 case ARM::ORRri: 1727 case ARM::t2ORRrr: 1728 case ARM::t2ORRri: 1729 case ARM::EORrr: 1730 case ARM::EORri: 1731 case ARM::t2EORrr: 1732 case ARM::t2EORri: { 1733 // Scan forward for the use of CPSR, if it's a conditional code requires 1734 // checking of V bit, then this is not safe to do. If we can't find the 1735 // CPSR use (i.e. used in another block), then it's not safe to perform 1736 // the optimization. 1737 bool isSafe = false; 1738 I = CmpInstr; 1739 E = MI->getParent()->end(); 1740 while (!isSafe && ++I != E) { 1741 const MachineInstr &Instr = *I; 1742 for (unsigned IO = 0, EO = Instr.getNumOperands(); 1743 !isSafe && IO != EO; ++IO) { 1744 const MachineOperand &MO = Instr.getOperand(IO); 1745 if (!MO.isReg() || MO.getReg() != ARM::CPSR) 1746 continue; 1747 if (MO.isDef()) { 1748 isSafe = true; 1749 break; 1750 } 1751 // Condition code is after the operand before CPSR. 1752 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm(); 1753 switch (CC) { 1754 default: 1755 isSafe = true; 1756 break; 1757 case ARMCC::VS: 1758 case ARMCC::VC: 1759 case ARMCC::GE: 1760 case ARMCC::LT: 1761 case ARMCC::GT: 1762 case ARMCC::LE: 1763 return false; 1764 } 1765 } 1766 } 1767 1768 if (!isSafe) 1769 return false; 1770 1771 // Toggle the optional operand to CPSR. 1772 MI->getOperand(5).setReg(ARM::CPSR); 1773 MI->getOperand(5).setIsDef(true); 1774 CmpInstr->eraseFromParent(); 1775 return true; 1776 } 1777 } 1778 1779 return false; 1780 } 1781 1782 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI, 1783 MachineInstr *DefMI, unsigned Reg, 1784 MachineRegisterInfo *MRI) const { 1785 // Fold large immediates into add, sub, or, xor. 1786 unsigned DefOpc = DefMI->getOpcode(); 1787 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm) 1788 return false; 1789 if (!DefMI->getOperand(1).isImm()) 1790 // Could be t2MOVi32imm <ga:xx> 1791 return false; 1792 1793 if (!MRI->hasOneNonDBGUse(Reg)) 1794 return false; 1795 1796 unsigned UseOpc = UseMI->getOpcode(); 1797 unsigned NewUseOpc = 0; 1798 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm(); 1799 uint32_t SOImmValV1 = 0, SOImmValV2 = 0; 1800 bool Commute = false; 1801 switch (UseOpc) { 1802 default: return false; 1803 case ARM::SUBrr: 1804 case ARM::ADDrr: 1805 case ARM::ORRrr: 1806 case ARM::EORrr: 1807 case ARM::t2SUBrr: 1808 case ARM::t2ADDrr: 1809 case ARM::t2ORRrr: 1810 case ARM::t2EORrr: { 1811 Commute = UseMI->getOperand(2).getReg() != Reg; 1812 switch (UseOpc) { 1813 default: break; 1814 case ARM::SUBrr: { 1815 if (Commute) 1816 return false; 1817 ImmVal = -ImmVal; 1818 NewUseOpc = ARM::SUBri; 1819 // Fallthrough 1820 } 1821 case ARM::ADDrr: 1822 case ARM::ORRrr: 1823 case ARM::EORrr: { 1824 if (!ARM_AM::isSOImmTwoPartVal(ImmVal)) 1825 return false; 1826 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal); 1827 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal); 1828 switch (UseOpc) { 1829 default: break; 1830 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break; 1831 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break; 1832 case ARM::EORrr: NewUseOpc = ARM::EORri; break; 1833 } 1834 break; 1835 } 1836 case ARM::t2SUBrr: { 1837 if (Commute) 1838 return false; 1839 ImmVal = -ImmVal; 1840 NewUseOpc = ARM::t2SUBri; 1841 // Fallthrough 1842 } 1843 case ARM::t2ADDrr: 1844 case ARM::t2ORRrr: 1845 case ARM::t2EORrr: { 1846 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal)) 1847 return false; 1848 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal); 1849 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal); 1850 switch (UseOpc) { 1851 default: break; 1852 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break; 1853 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break; 1854 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break; 1855 } 1856 break; 1857 } 1858 } 1859 } 1860 } 1861 1862 unsigned OpIdx = Commute ? 2 : 1; 1863 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); 1864 bool isKill = UseMI->getOperand(OpIdx).isKill(); 1865 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg)); 1866 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(), 1867 *UseMI, UseMI->getDebugLoc(), 1868 get(NewUseOpc), NewReg) 1869 .addReg(Reg1, getKillRegState(isKill)) 1870 .addImm(SOImmValV1))); 1871 UseMI->setDesc(get(NewUseOpc)); 1872 UseMI->getOperand(1).setReg(NewReg); 1873 UseMI->getOperand(1).setIsKill(); 1874 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2); 1875 DefMI->eraseFromParent(); 1876 return true; 1877 } 1878 1879 unsigned 1880 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, 1881 const MachineInstr *MI) const { 1882 if (!ItinData || ItinData->isEmpty()) 1883 return 1; 1884 1885 const MCInstrDesc &Desc = MI->getDesc(); 1886 unsigned Class = Desc.getSchedClass(); 1887 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; 1888 if (UOps) 1889 return UOps; 1890 1891 unsigned Opc = MI->getOpcode(); 1892 switch (Opc) { 1893 default: 1894 llvm_unreachable("Unexpected multi-uops instruction!"); 1895 break; 1896 case ARM::VLDMQIA: 1897 case ARM::VSTMQIA: 1898 return 2; 1899 1900 // The number of uOps for load / store multiple are determined by the number 1901 // registers. 1902 // 1903 // On Cortex-A8, each pair of register loads / stores can be scheduled on the 1904 // same cycle. The scheduling for the first load / store must be done 1905 // separately by assuming the the address is not 64-bit aligned. 1906 // 1907 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address 1908 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON 1909 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1. 1910 case ARM::VLDMDIA: 1911 case ARM::VLDMDIA_UPD: 1912 case ARM::VLDMDDB_UPD: 1913 case ARM::VLDMSIA: 1914 case ARM::VLDMSIA_UPD: 1915 case ARM::VLDMSDB_UPD: 1916 case ARM::VSTMDIA: 1917 case ARM::VSTMDIA_UPD: 1918 case ARM::VSTMDDB_UPD: 1919 case ARM::VSTMSIA: 1920 case ARM::VSTMSIA_UPD: 1921 case ARM::VSTMSDB_UPD: { 1922 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); 1923 return (NumRegs / 2) + (NumRegs % 2) + 1; 1924 } 1925 1926 case ARM::LDMIA_RET: 1927 case ARM::LDMIA: 1928 case ARM::LDMDA: 1929 case ARM::LDMDB: 1930 case ARM::LDMIB: 1931 case ARM::LDMIA_UPD: 1932 case ARM::LDMDA_UPD: 1933 case ARM::LDMDB_UPD: 1934 case ARM::LDMIB_UPD: 1935 case ARM::STMIA: 1936 case ARM::STMDA: 1937 case ARM::STMDB: 1938 case ARM::STMIB: 1939 case ARM::STMIA_UPD: 1940 case ARM::STMDA_UPD: 1941 case ARM::STMDB_UPD: 1942 case ARM::STMIB_UPD: 1943 case ARM::tLDMIA: 1944 case ARM::tLDMIA_UPD: 1945 case ARM::tSTMIA_UPD: 1946 case ARM::tPOP_RET: 1947 case ARM::tPOP: 1948 case ARM::tPUSH: 1949 case ARM::t2LDMIA_RET: 1950 case ARM::t2LDMIA: 1951 case ARM::t2LDMDB: 1952 case ARM::t2LDMIA_UPD: 1953 case ARM::t2LDMDB_UPD: 1954 case ARM::t2STMIA: 1955 case ARM::t2STMDB: 1956 case ARM::t2STMIA_UPD: 1957 case ARM::t2STMDB_UPD: { 1958 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; 1959 if (Subtarget.isCortexA8()) { 1960 if (NumRegs < 4) 1961 return 2; 1962 // 4 registers would be issued: 2, 2. 1963 // 5 registers would be issued: 2, 2, 1. 1964 UOps = (NumRegs / 2); 1965 if (NumRegs % 2) 1966 ++UOps; 1967 return UOps; 1968 } else if (Subtarget.isCortexA9()) { 1969 UOps = (NumRegs / 2); 1970 // If there are odd number of registers or if it's not 64-bit aligned, 1971 // then it takes an extra AGU (Address Generation Unit) cycle. 1972 if ((NumRegs % 2) || 1973 !MI->hasOneMemOperand() || 1974 (*MI->memoperands_begin())->getAlignment() < 8) 1975 ++UOps; 1976 return UOps; 1977 } else { 1978 // Assume the worst. 1979 return NumRegs; 1980 } 1981 } 1982 } 1983 } 1984 1985 int 1986 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, 1987 const MCInstrDesc &DefMCID, 1988 unsigned DefClass, 1989 unsigned DefIdx, unsigned DefAlign) const { 1990 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 1991 if (RegNo <= 0) 1992 // Def is the address writeback. 1993 return ItinData->getOperandCycle(DefClass, DefIdx); 1994 1995 int DefCycle; 1996 if (Subtarget.isCortexA8()) { 1997 // (regno / 2) + (regno % 2) + 1 1998 DefCycle = RegNo / 2 + 1; 1999 if (RegNo % 2) 2000 ++DefCycle; 2001 } else if (Subtarget.isCortexA9()) { 2002 DefCycle = RegNo; 2003 bool isSLoad = false; 2004 2005 switch (DefMCID.getOpcode()) { 2006 default: break; 2007 case ARM::VLDMSIA: 2008 case ARM::VLDMSIA_UPD: 2009 case ARM::VLDMSDB_UPD: 2010 isSLoad = true; 2011 break; 2012 } 2013 2014 // If there are odd number of 'S' registers or if it's not 64-bit aligned, 2015 // then it takes an extra cycle. 2016 if ((isSLoad && (RegNo % 2)) || DefAlign < 8) 2017 ++DefCycle; 2018 } else { 2019 // Assume the worst. 2020 DefCycle = RegNo + 2; 2021 } 2022 2023 return DefCycle; 2024 } 2025 2026 int 2027 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, 2028 const MCInstrDesc &DefMCID, 2029 unsigned DefClass, 2030 unsigned DefIdx, unsigned DefAlign) const { 2031 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 2032 if (RegNo <= 0) 2033 // Def is the address writeback. 2034 return ItinData->getOperandCycle(DefClass, DefIdx); 2035 2036 int DefCycle; 2037 if (Subtarget.isCortexA8()) { 2038 // 4 registers would be issued: 1, 2, 1. 2039 // 5 registers would be issued: 1, 2, 2. 2040 DefCycle = RegNo / 2; 2041 if (DefCycle < 1) 2042 DefCycle = 1; 2043 // Result latency is issue cycle + 2: E2. 2044 DefCycle += 2; 2045 } else if (Subtarget.isCortexA9()) { 2046 DefCycle = (RegNo / 2); 2047 // If there are odd number of registers or if it's not 64-bit aligned, 2048 // then it takes an extra AGU (Address Generation Unit) cycle. 2049 if ((RegNo % 2) || DefAlign < 8) 2050 ++DefCycle; 2051 // Result latency is AGU cycles + 2. 2052 DefCycle += 2; 2053 } else { 2054 // Assume the worst. 2055 DefCycle = RegNo + 2; 2056 } 2057 2058 return DefCycle; 2059 } 2060 2061 int 2062 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, 2063 const MCInstrDesc &UseMCID, 2064 unsigned UseClass, 2065 unsigned UseIdx, unsigned UseAlign) const { 2066 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 2067 if (RegNo <= 0) 2068 return ItinData->getOperandCycle(UseClass, UseIdx); 2069 2070 int UseCycle; 2071 if (Subtarget.isCortexA8()) { 2072 // (regno / 2) + (regno % 2) + 1 2073 UseCycle = RegNo / 2 + 1; 2074 if (RegNo % 2) 2075 ++UseCycle; 2076 } else if (Subtarget.isCortexA9()) { 2077 UseCycle = RegNo; 2078 bool isSStore = false; 2079 2080 switch (UseMCID.getOpcode()) { 2081 default: break; 2082 case ARM::VSTMSIA: 2083 case ARM::VSTMSIA_UPD: 2084 case ARM::VSTMSDB_UPD: 2085 isSStore = true; 2086 break; 2087 } 2088 2089 // If there are odd number of 'S' registers or if it's not 64-bit aligned, 2090 // then it takes an extra cycle. 2091 if ((isSStore && (RegNo % 2)) || UseAlign < 8) 2092 ++UseCycle; 2093 } else { 2094 // Assume the worst. 2095 UseCycle = RegNo + 2; 2096 } 2097 2098 return UseCycle; 2099 } 2100 2101 int 2102 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, 2103 const MCInstrDesc &UseMCID, 2104 unsigned UseClass, 2105 unsigned UseIdx, unsigned UseAlign) const { 2106 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 2107 if (RegNo <= 0) 2108 return ItinData->getOperandCycle(UseClass, UseIdx); 2109 2110 int UseCycle; 2111 if (Subtarget.isCortexA8()) { 2112 UseCycle = RegNo / 2; 2113 if (UseCycle < 2) 2114 UseCycle = 2; 2115 // Read in E3. 2116 UseCycle += 2; 2117 } else if (Subtarget.isCortexA9()) { 2118 UseCycle = (RegNo / 2); 2119 // If there are odd number of registers or if it's not 64-bit aligned, 2120 // then it takes an extra AGU (Address Generation Unit) cycle. 2121 if ((RegNo % 2) || UseAlign < 8) 2122 ++UseCycle; 2123 } else { 2124 // Assume the worst. 2125 UseCycle = 1; 2126 } 2127 return UseCycle; 2128 } 2129 2130 int 2131 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2132 const MCInstrDesc &DefMCID, 2133 unsigned DefIdx, unsigned DefAlign, 2134 const MCInstrDesc &UseMCID, 2135 unsigned UseIdx, unsigned UseAlign) const { 2136 unsigned DefClass = DefMCID.getSchedClass(); 2137 unsigned UseClass = UseMCID.getSchedClass(); 2138 2139 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) 2140 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 2141 2142 // This may be a def / use of a variable_ops instruction, the operand 2143 // latency might be determinable dynamically. Let the target try to 2144 // figure it out. 2145 int DefCycle = -1; 2146 bool LdmBypass = false; 2147 switch (DefMCID.getOpcode()) { 2148 default: 2149 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 2150 break; 2151 2152 case ARM::VLDMDIA: 2153 case ARM::VLDMDIA_UPD: 2154 case ARM::VLDMDDB_UPD: 2155 case ARM::VLDMSIA: 2156 case ARM::VLDMSIA_UPD: 2157 case ARM::VLDMSDB_UPD: 2158 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 2159 break; 2160 2161 case ARM::LDMIA_RET: 2162 case ARM::LDMIA: 2163 case ARM::LDMDA: 2164 case ARM::LDMDB: 2165 case ARM::LDMIB: 2166 case ARM::LDMIA_UPD: 2167 case ARM::LDMDA_UPD: 2168 case ARM::LDMDB_UPD: 2169 case ARM::LDMIB_UPD: 2170 case ARM::tLDMIA: 2171 case ARM::tLDMIA_UPD: 2172 case ARM::tPUSH: 2173 case ARM::t2LDMIA_RET: 2174 case ARM::t2LDMIA: 2175 case ARM::t2LDMDB: 2176 case ARM::t2LDMIA_UPD: 2177 case ARM::t2LDMDB_UPD: 2178 LdmBypass = 1; 2179 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 2180 break; 2181 } 2182 2183 if (DefCycle == -1) 2184 // We can't seem to determine the result latency of the def, assume it's 2. 2185 DefCycle = 2; 2186 2187 int UseCycle = -1; 2188 switch (UseMCID.getOpcode()) { 2189 default: 2190 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); 2191 break; 2192 2193 case ARM::VSTMDIA: 2194 case ARM::VSTMDIA_UPD: 2195 case ARM::VSTMDDB_UPD: 2196 case ARM::VSTMSIA: 2197 case ARM::VSTMSIA_UPD: 2198 case ARM::VSTMSDB_UPD: 2199 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 2200 break; 2201 2202 case ARM::STMIA: 2203 case ARM::STMDA: 2204 case ARM::STMDB: 2205 case ARM::STMIB: 2206 case ARM::STMIA_UPD: 2207 case ARM::STMDA_UPD: 2208 case ARM::STMDB_UPD: 2209 case ARM::STMIB_UPD: 2210 case ARM::tSTMIA_UPD: 2211 case ARM::tPOP_RET: 2212 case ARM::tPOP: 2213 case ARM::t2STMIA: 2214 case ARM::t2STMDB: 2215 case ARM::t2STMIA_UPD: 2216 case ARM::t2STMDB_UPD: 2217 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 2218 break; 2219 } 2220 2221 if (UseCycle == -1) 2222 // Assume it's read in the first stage. 2223 UseCycle = 1; 2224 2225 UseCycle = DefCycle - UseCycle + 1; 2226 if (UseCycle > 0) { 2227 if (LdmBypass) { 2228 // It's a variable_ops instruction so we can't use DefIdx here. Just use 2229 // first def operand. 2230 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1, 2231 UseClass, UseIdx)) 2232 --UseCycle; 2233 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx, 2234 UseClass, UseIdx)) { 2235 --UseCycle; 2236 } 2237 } 2238 2239 return UseCycle; 2240 } 2241 2242 int 2243 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2244 const MachineInstr *DefMI, unsigned DefIdx, 2245 const MachineInstr *UseMI, unsigned UseIdx) const { 2246 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() || 2247 DefMI->isRegSequence() || DefMI->isImplicitDef()) 2248 return 1; 2249 2250 const MCInstrDesc &DefMCID = DefMI->getDesc(); 2251 if (!ItinData || ItinData->isEmpty()) 2252 return DefMCID.mayLoad() ? 3 : 1; 2253 2254 const MCInstrDesc &UseMCID = UseMI->getDesc(); 2255 const MachineOperand &DefMO = DefMI->getOperand(DefIdx); 2256 if (DefMO.getReg() == ARM::CPSR) { 2257 if (DefMI->getOpcode() == ARM::FMSTAT) { 2258 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?) 2259 return Subtarget.isCortexA9() ? 1 : 20; 2260 } 2261 2262 // CPSR set and branch can be paired in the same cycle. 2263 if (UseMCID.isBranch()) 2264 return 0; 2265 } 2266 2267 unsigned DefAlign = DefMI->hasOneMemOperand() 2268 ? (*DefMI->memoperands_begin())->getAlignment() : 0; 2269 unsigned UseAlign = UseMI->hasOneMemOperand() 2270 ? (*UseMI->memoperands_begin())->getAlignment() : 0; 2271 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, 2272 UseMCID, UseIdx, UseAlign); 2273 2274 if (Latency > 1 && 2275 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) { 2276 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 2277 // variants are one cycle cheaper. 2278 switch (DefMCID.getOpcode()) { 2279 default: break; 2280 case ARM::LDRrs: 2281 case ARM::LDRBrs: { 2282 unsigned ShOpVal = DefMI->getOperand(3).getImm(); 2283 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2284 if (ShImm == 0 || 2285 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 2286 --Latency; 2287 break; 2288 } 2289 case ARM::t2LDRs: 2290 case ARM::t2LDRBs: 2291 case ARM::t2LDRHs: 2292 case ARM::t2LDRSHs: { 2293 // Thumb2 mode: lsl only. 2294 unsigned ShAmt = DefMI->getOperand(3).getImm(); 2295 if (ShAmt == 0 || ShAmt == 2) 2296 --Latency; 2297 break; 2298 } 2299 } 2300 } 2301 2302 if (DefAlign < 8 && Subtarget.isCortexA9()) 2303 switch (DefMCID.getOpcode()) { 2304 default: break; 2305 case ARM::VLD1q8: 2306 case ARM::VLD1q16: 2307 case ARM::VLD1q32: 2308 case ARM::VLD1q64: 2309 case ARM::VLD1q8_UPD: 2310 case ARM::VLD1q16_UPD: 2311 case ARM::VLD1q32_UPD: 2312 case ARM::VLD1q64_UPD: 2313 case ARM::VLD2d8: 2314 case ARM::VLD2d16: 2315 case ARM::VLD2d32: 2316 case ARM::VLD2q8: 2317 case ARM::VLD2q16: 2318 case ARM::VLD2q32: 2319 case ARM::VLD2d8_UPD: 2320 case ARM::VLD2d16_UPD: 2321 case ARM::VLD2d32_UPD: 2322 case ARM::VLD2q8_UPD: 2323 case ARM::VLD2q16_UPD: 2324 case ARM::VLD2q32_UPD: 2325 case ARM::VLD3d8: 2326 case ARM::VLD3d16: 2327 case ARM::VLD3d32: 2328 case ARM::VLD1d64T: 2329 case ARM::VLD3d8_UPD: 2330 case ARM::VLD3d16_UPD: 2331 case ARM::VLD3d32_UPD: 2332 case ARM::VLD1d64T_UPD: 2333 case ARM::VLD3q8_UPD: 2334 case ARM::VLD3q16_UPD: 2335 case ARM::VLD3q32_UPD: 2336 case ARM::VLD4d8: 2337 case ARM::VLD4d16: 2338 case ARM::VLD4d32: 2339 case ARM::VLD1d64Q: 2340 case ARM::VLD4d8_UPD: 2341 case ARM::VLD4d16_UPD: 2342 case ARM::VLD4d32_UPD: 2343 case ARM::VLD1d64Q_UPD: 2344 case ARM::VLD4q8_UPD: 2345 case ARM::VLD4q16_UPD: 2346 case ARM::VLD4q32_UPD: 2347 case ARM::VLD1DUPq8: 2348 case ARM::VLD1DUPq16: 2349 case ARM::VLD1DUPq32: 2350 case ARM::VLD1DUPq8_UPD: 2351 case ARM::VLD1DUPq16_UPD: 2352 case ARM::VLD1DUPq32_UPD: 2353 case ARM::VLD2DUPd8: 2354 case ARM::VLD2DUPd16: 2355 case ARM::VLD2DUPd32: 2356 case ARM::VLD2DUPd8_UPD: 2357 case ARM::VLD2DUPd16_UPD: 2358 case ARM::VLD2DUPd32_UPD: 2359 case ARM::VLD4DUPd8: 2360 case ARM::VLD4DUPd16: 2361 case ARM::VLD4DUPd32: 2362 case ARM::VLD4DUPd8_UPD: 2363 case ARM::VLD4DUPd16_UPD: 2364 case ARM::VLD4DUPd32_UPD: 2365 case ARM::VLD1LNd8: 2366 case ARM::VLD1LNd16: 2367 case ARM::VLD1LNd32: 2368 case ARM::VLD1LNd8_UPD: 2369 case ARM::VLD1LNd16_UPD: 2370 case ARM::VLD1LNd32_UPD: 2371 case ARM::VLD2LNd8: 2372 case ARM::VLD2LNd16: 2373 case ARM::VLD2LNd32: 2374 case ARM::VLD2LNq16: 2375 case ARM::VLD2LNq32: 2376 case ARM::VLD2LNd8_UPD: 2377 case ARM::VLD2LNd16_UPD: 2378 case ARM::VLD2LNd32_UPD: 2379 case ARM::VLD2LNq16_UPD: 2380 case ARM::VLD2LNq32_UPD: 2381 case ARM::VLD4LNd8: 2382 case ARM::VLD4LNd16: 2383 case ARM::VLD4LNd32: 2384 case ARM::VLD4LNq16: 2385 case ARM::VLD4LNq32: 2386 case ARM::VLD4LNd8_UPD: 2387 case ARM::VLD4LNd16_UPD: 2388 case ARM::VLD4LNd32_UPD: 2389 case ARM::VLD4LNq16_UPD: 2390 case ARM::VLD4LNq32_UPD: 2391 // If the address is not 64-bit aligned, the latencies of these 2392 // instructions increases by one. 2393 ++Latency; 2394 break; 2395 } 2396 2397 return Latency; 2398 } 2399 2400 int 2401 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2402 SDNode *DefNode, unsigned DefIdx, 2403 SDNode *UseNode, unsigned UseIdx) const { 2404 if (!DefNode->isMachineOpcode()) 2405 return 1; 2406 2407 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode()); 2408 2409 if (isZeroCost(DefMCID.Opcode)) 2410 return 0; 2411 2412 if (!ItinData || ItinData->isEmpty()) 2413 return DefMCID.mayLoad() ? 3 : 1; 2414 2415 if (!UseNode->isMachineOpcode()) { 2416 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); 2417 if (Subtarget.isCortexA9()) 2418 return Latency <= 2 ? 1 : Latency - 1; 2419 else 2420 return Latency <= 3 ? 1 : Latency - 2; 2421 } 2422 2423 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode()); 2424 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode); 2425 unsigned DefAlign = !DefMN->memoperands_empty() 2426 ? (*DefMN->memoperands_begin())->getAlignment() : 0; 2427 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode); 2428 unsigned UseAlign = !UseMN->memoperands_empty() 2429 ? (*UseMN->memoperands_begin())->getAlignment() : 0; 2430 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, 2431 UseMCID, UseIdx, UseAlign); 2432 2433 if (Latency > 1 && 2434 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) { 2435 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 2436 // variants are one cycle cheaper. 2437 switch (DefMCID.getOpcode()) { 2438 default: break; 2439 case ARM::LDRrs: 2440 case ARM::LDRBrs: { 2441 unsigned ShOpVal = 2442 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 2443 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2444 if (ShImm == 0 || 2445 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 2446 --Latency; 2447 break; 2448 } 2449 case ARM::t2LDRs: 2450 case ARM::t2LDRBs: 2451 case ARM::t2LDRHs: 2452 case ARM::t2LDRSHs: { 2453 // Thumb2 mode: lsl only. 2454 unsigned ShAmt = 2455 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 2456 if (ShAmt == 0 || ShAmt == 2) 2457 --Latency; 2458 break; 2459 } 2460 } 2461 } 2462 2463 if (DefAlign < 8 && Subtarget.isCortexA9()) 2464 switch (DefMCID.getOpcode()) { 2465 default: break; 2466 case ARM::VLD1q8Pseudo: 2467 case ARM::VLD1q16Pseudo: 2468 case ARM::VLD1q32Pseudo: 2469 case ARM::VLD1q64Pseudo: 2470 case ARM::VLD1q8Pseudo_UPD: 2471 case ARM::VLD1q16Pseudo_UPD: 2472 case ARM::VLD1q32Pseudo_UPD: 2473 case ARM::VLD1q64Pseudo_UPD: 2474 case ARM::VLD2d8Pseudo: 2475 case ARM::VLD2d16Pseudo: 2476 case ARM::VLD2d32Pseudo: 2477 case ARM::VLD2q8Pseudo: 2478 case ARM::VLD2q16Pseudo: 2479 case ARM::VLD2q32Pseudo: 2480 case ARM::VLD2d8Pseudo_UPD: 2481 case ARM::VLD2d16Pseudo_UPD: 2482 case ARM::VLD2d32Pseudo_UPD: 2483 case ARM::VLD2q8Pseudo_UPD: 2484 case ARM::VLD2q16Pseudo_UPD: 2485 case ARM::VLD2q32Pseudo_UPD: 2486 case ARM::VLD3d8Pseudo: 2487 case ARM::VLD3d16Pseudo: 2488 case ARM::VLD3d32Pseudo: 2489 case ARM::VLD1d64TPseudo: 2490 case ARM::VLD3d8Pseudo_UPD: 2491 case ARM::VLD3d16Pseudo_UPD: 2492 case ARM::VLD3d32Pseudo_UPD: 2493 case ARM::VLD1d64TPseudo_UPD: 2494 case ARM::VLD3q8Pseudo_UPD: 2495 case ARM::VLD3q16Pseudo_UPD: 2496 case ARM::VLD3q32Pseudo_UPD: 2497 case ARM::VLD3q8oddPseudo: 2498 case ARM::VLD3q16oddPseudo: 2499 case ARM::VLD3q32oddPseudo: 2500 case ARM::VLD3q8oddPseudo_UPD: 2501 case ARM::VLD3q16oddPseudo_UPD: 2502 case ARM::VLD3q32oddPseudo_UPD: 2503 case ARM::VLD4d8Pseudo: 2504 case ARM::VLD4d16Pseudo: 2505 case ARM::VLD4d32Pseudo: 2506 case ARM::VLD1d64QPseudo: 2507 case ARM::VLD4d8Pseudo_UPD: 2508 case ARM::VLD4d16Pseudo_UPD: 2509 case ARM::VLD4d32Pseudo_UPD: 2510 case ARM::VLD1d64QPseudo_UPD: 2511 case ARM::VLD4q8Pseudo_UPD: 2512 case ARM::VLD4q16Pseudo_UPD: 2513 case ARM::VLD4q32Pseudo_UPD: 2514 case ARM::VLD4q8oddPseudo: 2515 case ARM::VLD4q16oddPseudo: 2516 case ARM::VLD4q32oddPseudo: 2517 case ARM::VLD4q8oddPseudo_UPD: 2518 case ARM::VLD4q16oddPseudo_UPD: 2519 case ARM::VLD4q32oddPseudo_UPD: 2520 case ARM::VLD1DUPq8Pseudo: 2521 case ARM::VLD1DUPq16Pseudo: 2522 case ARM::VLD1DUPq32Pseudo: 2523 case ARM::VLD1DUPq8Pseudo_UPD: 2524 case ARM::VLD1DUPq16Pseudo_UPD: 2525 case ARM::VLD1DUPq32Pseudo_UPD: 2526 case ARM::VLD2DUPd8Pseudo: 2527 case ARM::VLD2DUPd16Pseudo: 2528 case ARM::VLD2DUPd32Pseudo: 2529 case ARM::VLD2DUPd8Pseudo_UPD: 2530 case ARM::VLD2DUPd16Pseudo_UPD: 2531 case ARM::VLD2DUPd32Pseudo_UPD: 2532 case ARM::VLD4DUPd8Pseudo: 2533 case ARM::VLD4DUPd16Pseudo: 2534 case ARM::VLD4DUPd32Pseudo: 2535 case ARM::VLD4DUPd8Pseudo_UPD: 2536 case ARM::VLD4DUPd16Pseudo_UPD: 2537 case ARM::VLD4DUPd32Pseudo_UPD: 2538 case ARM::VLD1LNq8Pseudo: 2539 case ARM::VLD1LNq16Pseudo: 2540 case ARM::VLD1LNq32Pseudo: 2541 case ARM::VLD1LNq8Pseudo_UPD: 2542 case ARM::VLD1LNq16Pseudo_UPD: 2543 case ARM::VLD1LNq32Pseudo_UPD: 2544 case ARM::VLD2LNd8Pseudo: 2545 case ARM::VLD2LNd16Pseudo: 2546 case ARM::VLD2LNd32Pseudo: 2547 case ARM::VLD2LNq16Pseudo: 2548 case ARM::VLD2LNq32Pseudo: 2549 case ARM::VLD2LNd8Pseudo_UPD: 2550 case ARM::VLD2LNd16Pseudo_UPD: 2551 case ARM::VLD2LNd32Pseudo_UPD: 2552 case ARM::VLD2LNq16Pseudo_UPD: 2553 case ARM::VLD2LNq32Pseudo_UPD: 2554 case ARM::VLD4LNd8Pseudo: 2555 case ARM::VLD4LNd16Pseudo: 2556 case ARM::VLD4LNd32Pseudo: 2557 case ARM::VLD4LNq16Pseudo: 2558 case ARM::VLD4LNq32Pseudo: 2559 case ARM::VLD4LNd8Pseudo_UPD: 2560 case ARM::VLD4LNd16Pseudo_UPD: 2561 case ARM::VLD4LNd32Pseudo_UPD: 2562 case ARM::VLD4LNq16Pseudo_UPD: 2563 case ARM::VLD4LNq32Pseudo_UPD: 2564 // If the address is not 64-bit aligned, the latencies of these 2565 // instructions increases by one. 2566 ++Latency; 2567 break; 2568 } 2569 2570 return Latency; 2571 } 2572 2573 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 2574 const MachineInstr *MI, 2575 unsigned *PredCost) const { 2576 if (MI->isCopyLike() || MI->isInsertSubreg() || 2577 MI->isRegSequence() || MI->isImplicitDef()) 2578 return 1; 2579 2580 if (!ItinData || ItinData->isEmpty()) 2581 return 1; 2582 2583 const MCInstrDesc &MCID = MI->getDesc(); 2584 unsigned Class = MCID.getSchedClass(); 2585 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; 2586 if (PredCost && MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) 2587 // When predicated, CPSR is an additional source operand for CPSR updating 2588 // instructions, this apparently increases their latencies. 2589 *PredCost = 1; 2590 if (UOps) 2591 return ItinData->getStageLatency(Class); 2592 return getNumMicroOps(ItinData, MI); 2593 } 2594 2595 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 2596 SDNode *Node) const { 2597 if (!Node->isMachineOpcode()) 2598 return 1; 2599 2600 if (!ItinData || ItinData->isEmpty()) 2601 return 1; 2602 2603 unsigned Opcode = Node->getMachineOpcode(); 2604 switch (Opcode) { 2605 default: 2606 return ItinData->getStageLatency(get(Opcode).getSchedClass()); 2607 case ARM::VLDMQIA: 2608 case ARM::VSTMQIA: 2609 return 2; 2610 } 2611 } 2612 2613 bool ARMBaseInstrInfo:: 2614 hasHighOperandLatency(const InstrItineraryData *ItinData, 2615 const MachineRegisterInfo *MRI, 2616 const MachineInstr *DefMI, unsigned DefIdx, 2617 const MachineInstr *UseMI, unsigned UseIdx) const { 2618 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 2619 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask; 2620 if (Subtarget.isCortexA8() && 2621 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP)) 2622 // CortexA8 VFP instructions are not pipelined. 2623 return true; 2624 2625 // Hoist VFP / NEON instructions with 4 or higher latency. 2626 int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx); 2627 if (Latency <= 3) 2628 return false; 2629 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON || 2630 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON; 2631 } 2632 2633 bool ARMBaseInstrInfo:: 2634 hasLowDefLatency(const InstrItineraryData *ItinData, 2635 const MachineInstr *DefMI, unsigned DefIdx) const { 2636 if (!ItinData || ItinData->isEmpty()) 2637 return false; 2638 2639 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 2640 if (DDomain == ARMII::DomainGeneral) { 2641 unsigned DefClass = DefMI->getDesc().getSchedClass(); 2642 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 2643 return (DefCycle != -1 && DefCycle <= 2); 2644 } 2645 return false; 2646 } 2647 2648 bool 2649 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 2650 unsigned &AddSubOpc, 2651 bool &NegAcc, bool &HasLane) const { 2652 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode); 2653 if (I == MLxEntryMap.end()) 2654 return false; 2655 2656 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second]; 2657 MulOpc = Entry.MulOpc; 2658 AddSubOpc = Entry.AddSubOpc; 2659 NegAcc = Entry.NegAcc; 2660 HasLane = Entry.HasLane; 2661 return true; 2662 } 2663