1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARM.h"
17 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMBaseRegisterInfo.h"
20 #include "ARMConstantPoolValue.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMTargetMachine.h"
23 #include "ARMTargetObjectFile.h"
24 #include "InstPrinter/ARMInstPrinter.h"
25 #include "MCTargetDesc/ARMAddressingModes.h"
26 #include "MCTargetDesc/ARMMCExpr.h"
27 #include "llvm/Analysis/DebugInfo.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Module.h"
30 #include "llvm/Type.h"
31 #include "llvm/Assembly/Writer.h"
32 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCExpr.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCSectionMachO.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/Target/Mangler.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include "llvm/ADT/SmallPtrSet.h"
49 #include "llvm/ADT/SmallString.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/TargetRegistry.h"
54 #include "llvm/Support/raw_ostream.h"
55 #include <cctype>
56 using namespace llvm;
57 
58 namespace {
59 
60   // Per section and per symbol attributes are not supported.
61   // To implement them we would need the ability to delay this emission
62   // until the assembly file is fully parsed/generated as only then do we
63   // know the symbol and section numbers.
64   class AttributeEmitter {
65   public:
66     virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
67     virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
68     virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
69     virtual void Finish() = 0;
70     virtual ~AttributeEmitter() {}
71   };
72 
73   class AsmAttributeEmitter : public AttributeEmitter {
74     MCStreamer &Streamer;
75 
76   public:
77     AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
78     void MaybeSwitchVendor(StringRef Vendor) { }
79 
80     void EmitAttribute(unsigned Attribute, unsigned Value) {
81       Streamer.EmitRawText("\t.eabi_attribute " +
82                            Twine(Attribute) + ", " + Twine(Value));
83     }
84 
85     void EmitTextAttribute(unsigned Attribute, StringRef String) {
86       switch (Attribute) {
87       case ARMBuildAttrs::CPU_name:
88         Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower());
89         break;
90       /* GAS requires .fpu to be emitted regardless of EABI attribute */
91       case ARMBuildAttrs::Advanced_SIMD_arch:
92       case ARMBuildAttrs::VFP_arch:
93         Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower());
94         break;
95       default: assert(0 && "Unsupported Text attribute in ASM Mode"); break;
96       }
97     }
98     void Finish() { }
99   };
100 
101   class ObjectAttributeEmitter : public AttributeEmitter {
102     // This structure holds all attributes, accounting for
103     // their string/numeric value, so we can later emmit them
104     // in declaration order, keeping all in the same vector
105     struct AttributeItemType {
106       enum {
107         HiddenAttribute = 0,
108         NumericAttribute,
109         TextAttribute
110       } Type;
111       unsigned Tag;
112       unsigned IntValue;
113       StringRef StringValue;
114     } AttributeItem;
115 
116     MCObjectStreamer &Streamer;
117     StringRef CurrentVendor;
118     SmallVector<AttributeItemType, 64> Contents;
119 
120     // Account for the ULEB/String size of each item,
121     // not just the number of items
122     size_t ContentsSize;
123     // FIXME: this should be in a more generic place, but
124     // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
125     size_t getULEBSize(int Value) {
126       size_t Size = 0;
127       do {
128         Value >>= 7;
129         Size += sizeof(int8_t); // Is this really necessary?
130       } while (Value);
131       return Size;
132     }
133 
134   public:
135     ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
136       Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
137 
138     void MaybeSwitchVendor(StringRef Vendor) {
139       assert(!Vendor.empty() && "Vendor cannot be empty.");
140 
141       if (CurrentVendor.empty())
142         CurrentVendor = Vendor;
143       else if (CurrentVendor == Vendor)
144         return;
145       else
146         Finish();
147 
148       CurrentVendor = Vendor;
149 
150       assert(Contents.size() == 0);
151     }
152 
153     void EmitAttribute(unsigned Attribute, unsigned Value) {
154       AttributeItemType attr = {
155         AttributeItemType::NumericAttribute,
156         Attribute,
157         Value,
158         StringRef("")
159       };
160       ContentsSize += getULEBSize(Attribute);
161       ContentsSize += getULEBSize(Value);
162       Contents.push_back(attr);
163     }
164 
165     void EmitTextAttribute(unsigned Attribute, StringRef String) {
166       AttributeItemType attr = {
167         AttributeItemType::TextAttribute,
168         Attribute,
169         0,
170         String
171       };
172       ContentsSize += getULEBSize(Attribute);
173       // String + \0
174       ContentsSize += String.size()+1;
175 
176       Contents.push_back(attr);
177     }
178 
179     void Finish() {
180       // Vendor size + Vendor name + '\0'
181       const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
182 
183       // Tag + Tag Size
184       const size_t TagHeaderSize = 1 + 4;
185 
186       Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
187       Streamer.EmitBytes(CurrentVendor, 0);
188       Streamer.EmitIntValue(0, 1); // '\0'
189 
190       Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
191       Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
192 
193       // Size should have been accounted for already, now
194       // emit each field as its type (ULEB or String)
195       for (unsigned int i=0; i<Contents.size(); ++i) {
196         AttributeItemType item = Contents[i];
197         Streamer.EmitULEB128IntValue(item.Tag, 0);
198         switch (item.Type) {
199         case AttributeItemType::NumericAttribute:
200           Streamer.EmitULEB128IntValue(item.IntValue, 0);
201           break;
202         case AttributeItemType::TextAttribute:
203           Streamer.EmitBytes(item.StringValue.upper(), 0);
204           Streamer.EmitIntValue(0, 1); // '\0'
205           break;
206         default:
207           assert(0 && "Invalid attribute type");
208         }
209       }
210 
211       Contents.clear();
212     }
213   };
214 
215 } // end of anonymous namespace
216 
217 MachineLocation ARMAsmPrinter::
218 getDebugValueLocation(const MachineInstr *MI) const {
219   MachineLocation Location;
220   assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
221   // Frame address.  Currently handles register +- offset only.
222   if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
223     Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
224   else {
225     DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
226   }
227   return Location;
228 }
229 
230 /// EmitDwarfRegOp - Emit dwarf register operation.
231 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
232   const TargetRegisterInfo *RI = TM.getRegisterInfo();
233   if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
234     AsmPrinter::EmitDwarfRegOp(MLoc);
235   else {
236     unsigned Reg = MLoc.getReg();
237     if (Reg >= ARM::S0 && Reg <= ARM::S31) {
238       assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
239       // S registers are described as bit-pieces of a register
240       // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
241       // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
242 
243       unsigned SReg = Reg - ARM::S0;
244       bool odd = SReg & 0x1;
245       unsigned Rx = 256 + (SReg >> 1);
246 
247       OutStreamer.AddComment("DW_OP_regx for S register");
248       EmitInt8(dwarf::DW_OP_regx);
249 
250       OutStreamer.AddComment(Twine(SReg));
251       EmitULEB128(Rx);
252 
253       if (odd) {
254         OutStreamer.AddComment("DW_OP_bit_piece 32 32");
255         EmitInt8(dwarf::DW_OP_bit_piece);
256         EmitULEB128(32);
257         EmitULEB128(32);
258       } else {
259         OutStreamer.AddComment("DW_OP_bit_piece 32 0");
260         EmitInt8(dwarf::DW_OP_bit_piece);
261         EmitULEB128(32);
262         EmitULEB128(0);
263       }
264     } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
265       assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
266       // Q registers Q0-Q15 are described by composing two D registers together.
267       // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
268       // DW_OP_piece(8)
269 
270       unsigned QReg = Reg - ARM::Q0;
271       unsigned D1 = 256 + 2 * QReg;
272       unsigned D2 = D1 + 1;
273 
274       OutStreamer.AddComment("DW_OP_regx for Q register: D1");
275       EmitInt8(dwarf::DW_OP_regx);
276       EmitULEB128(D1);
277       OutStreamer.AddComment("DW_OP_piece 8");
278       EmitInt8(dwarf::DW_OP_piece);
279       EmitULEB128(8);
280 
281       OutStreamer.AddComment("DW_OP_regx for Q register: D2");
282       EmitInt8(dwarf::DW_OP_regx);
283       EmitULEB128(D2);
284       OutStreamer.AddComment("DW_OP_piece 8");
285       EmitInt8(dwarf::DW_OP_piece);
286       EmitULEB128(8);
287     }
288   }
289 }
290 
291 void ARMAsmPrinter::EmitFunctionEntryLabel() {
292   OutStreamer.ForceCodeRegion();
293 
294   if (AFI->isThumbFunction()) {
295     OutStreamer.EmitAssemblerFlag(MCAF_Code16);
296     OutStreamer.EmitThumbFunc(CurrentFnSym);
297   }
298 
299   OutStreamer.EmitLabel(CurrentFnSym);
300 }
301 
302 /// runOnMachineFunction - This uses the EmitInstruction()
303 /// method to print assembly for each instruction.
304 ///
305 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
306   AFI = MF.getInfo<ARMFunctionInfo>();
307   MCP = MF.getConstantPool();
308 
309   return AsmPrinter::runOnMachineFunction(MF);
310 }
311 
312 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
313                                  raw_ostream &O, const char *Modifier) {
314   const MachineOperand &MO = MI->getOperand(OpNum);
315   unsigned TF = MO.getTargetFlags();
316 
317   switch (MO.getType()) {
318   default:
319     assert(0 && "<unknown operand type>");
320   case MachineOperand::MO_Register: {
321     unsigned Reg = MO.getReg();
322     assert(TargetRegisterInfo::isPhysicalRegister(Reg));
323     assert(!MO.getSubReg() && "Subregs should be eliminated!");
324     O << ARMInstPrinter::getRegisterName(Reg);
325     break;
326   }
327   case MachineOperand::MO_Immediate: {
328     int64_t Imm = MO.getImm();
329     O << '#';
330     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
331         (TF == ARMII::MO_LO16))
332       O << ":lower16:";
333     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
334              (TF == ARMII::MO_HI16))
335       O << ":upper16:";
336     O << Imm;
337     break;
338   }
339   case MachineOperand::MO_MachineBasicBlock:
340     O << *MO.getMBB()->getSymbol();
341     return;
342   case MachineOperand::MO_GlobalAddress: {
343     const GlobalValue *GV = MO.getGlobal();
344     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
345         (TF & ARMII::MO_LO16))
346       O << ":lower16:";
347     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
348              (TF & ARMII::MO_HI16))
349       O << ":upper16:";
350     O << *Mang->getSymbol(GV);
351 
352     printOffset(MO.getOffset(), O);
353     if (TF == ARMII::MO_PLT)
354       O << "(PLT)";
355     break;
356   }
357   case MachineOperand::MO_ExternalSymbol: {
358     O << *GetExternalSymbolSymbol(MO.getSymbolName());
359     if (TF == ARMII::MO_PLT)
360       O << "(PLT)";
361     break;
362   }
363   case MachineOperand::MO_ConstantPoolIndex:
364     O << *GetCPISymbol(MO.getIndex());
365     break;
366   case MachineOperand::MO_JumpTableIndex:
367     O << *GetJTISymbol(MO.getIndex());
368     break;
369   }
370 }
371 
372 //===--------------------------------------------------------------------===//
373 
374 MCSymbol *ARMAsmPrinter::
375 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
376                             const MachineBasicBlock *MBB) const {
377   SmallString<60> Name;
378   raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
379     << getFunctionNumber() << '_' << uid << '_' << uid2
380     << "_set_" << MBB->getNumber();
381   return OutContext.GetOrCreateSymbol(Name.str());
382 }
383 
384 MCSymbol *ARMAsmPrinter::
385 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
386   SmallString<60> Name;
387   raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
388     << getFunctionNumber() << '_' << uid << '_' << uid2;
389   return OutContext.GetOrCreateSymbol(Name.str());
390 }
391 
392 
393 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
394   SmallString<60> Name;
395   raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
396     << getFunctionNumber();
397   return OutContext.GetOrCreateSymbol(Name.str());
398 }
399 
400 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
401                                     unsigned AsmVariant, const char *ExtraCode,
402                                     raw_ostream &O) {
403   // Does this asm operand have a single letter operand modifier?
404   if (ExtraCode && ExtraCode[0]) {
405     if (ExtraCode[1] != 0) return true; // Unknown modifier.
406 
407     switch (ExtraCode[0]) {
408     default: return true;  // Unknown modifier.
409     case 'a': // Print as a memory address.
410       if (MI->getOperand(OpNum).isReg()) {
411         O << "["
412           << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
413           << "]";
414         return false;
415       }
416       // Fallthrough
417     case 'c': // Don't print "#" before an immediate operand.
418       if (!MI->getOperand(OpNum).isImm())
419         return true;
420       O << MI->getOperand(OpNum).getImm();
421       return false;
422     case 'P': // Print a VFP double precision register.
423     case 'q': // Print a NEON quad precision register.
424       printOperand(MI, OpNum, O);
425       return false;
426     case 'y': // Print a VFP single precision register as indexed double.
427       // This uses the ordering of the alias table to get the first 'd' register
428       // that overlaps the 's' register. Also, s0 is an odd register, hence the
429       // odd modulus check below.
430       if (MI->getOperand(OpNum).isReg()) {
431         unsigned Reg = MI->getOperand(OpNum).getReg();
432         const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
433         O << ARMInstPrinter::getRegisterName(TRI->getAliasSet(Reg)[0]) <<
434         (((Reg % 2) == 1) ? "[0]" : "[1]");
435         return false;
436       }
437       return true;
438     case 'B': // Bitwise inverse of integer or symbol without a preceding #.
439       if (!MI->getOperand(OpNum).isImm())
440         return true;
441       O << ~(MI->getOperand(OpNum).getImm());
442       return false;
443     case 'L': // The low 16 bits of an immediate constant.
444       if (!MI->getOperand(OpNum).isImm())
445         return true;
446       O << (MI->getOperand(OpNum).getImm() & 0xffff);
447       return false;
448     case 'M': { // A register range suitable for LDM/STM.
449       if (!MI->getOperand(OpNum).isReg())
450         return true;
451       const MachineOperand &MO = MI->getOperand(OpNum);
452       unsigned RegBegin = MO.getReg();
453       // This takes advantage of the 2 operand-ness of ldm/stm and that we've
454       // already got the operands in registers that are operands to the
455       // inline asm statement.
456 
457       O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
458 
459       // FIXME: The register allocator not only may not have given us the
460       // registers in sequence, but may not be in ascending registers. This
461       // will require changes in the register allocator that'll need to be
462       // propagated down here if the operands change.
463       unsigned RegOps = OpNum + 1;
464       while (MI->getOperand(RegOps).isReg()) {
465         O << ", "
466           << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
467         RegOps++;
468       }
469 
470       O << "}";
471 
472       return false;
473     }
474     case 'R': // The most significant register of a pair.
475     case 'Q': { // The least significant register of a pair.
476       if (OpNum == 0)
477         return true;
478       const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
479       if (!FlagsOP.isImm())
480         return true;
481       unsigned Flags = FlagsOP.getImm();
482       unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
483       if (NumVals != 2)
484         return true;
485       unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
486       if (RegOp >= MI->getNumOperands())
487         return true;
488       const MachineOperand &MO = MI->getOperand(RegOp);
489       if (!MO.isReg())
490         return true;
491       unsigned Reg = MO.getReg();
492       O << ARMInstPrinter::getRegisterName(Reg);
493       return false;
494     }
495 
496     // These modifiers are not yet supported.
497     case 'p': // The high single-precision register of a VFP double-precision
498               // register.
499     case 'e': // The low doubleword register of a NEON quad register.
500     case 'f': // The high doubleword register of a NEON quad register.
501     case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
502     case 'H': // The highest-numbered register of a pair.
503       return true;
504     }
505   }
506 
507   printOperand(MI, OpNum, O);
508   return false;
509 }
510 
511 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
512                                           unsigned OpNum, unsigned AsmVariant,
513                                           const char *ExtraCode,
514                                           raw_ostream &O) {
515   // Does this asm operand have a single letter operand modifier?
516   if (ExtraCode && ExtraCode[0]) {
517     if (ExtraCode[1] != 0) return true; // Unknown modifier.
518 
519     switch (ExtraCode[0]) {
520       case 'A': // A memory operand for a VLD1/VST1 instruction.
521       default: return true;  // Unknown modifier.
522       case 'm': // The base register of a memory operand.
523         if (!MI->getOperand(OpNum).isReg())
524           return true;
525         O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
526         return false;
527     }
528   }
529 
530   const MachineOperand &MO = MI->getOperand(OpNum);
531   assert(MO.isReg() && "unexpected inline asm memory operand");
532   O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
533   return false;
534 }
535 
536 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
537   if (Subtarget->isTargetDarwin()) {
538     Reloc::Model RelocM = TM.getRelocationModel();
539     if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
540       // Declare all the text sections up front (before the DWARF sections
541       // emitted by AsmPrinter::doInitialization) so the assembler will keep
542       // them together at the beginning of the object file.  This helps
543       // avoid out-of-range branches that are due a fundamental limitation of
544       // the way symbol offsets are encoded with the current Darwin ARM
545       // relocations.
546       const TargetLoweringObjectFileMachO &TLOFMacho =
547         static_cast<const TargetLoweringObjectFileMachO &>(
548           getObjFileLowering());
549       OutStreamer.SwitchSection(TLOFMacho.getTextSection());
550       OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
551       OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
552       if (RelocM == Reloc::DynamicNoPIC) {
553         const MCSection *sect =
554           OutContext.getMachOSection("__TEXT", "__symbol_stub4",
555                                      MCSectionMachO::S_SYMBOL_STUBS,
556                                      12, SectionKind::getText());
557         OutStreamer.SwitchSection(sect);
558       } else {
559         const MCSection *sect =
560           OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
561                                      MCSectionMachO::S_SYMBOL_STUBS,
562                                      16, SectionKind::getText());
563         OutStreamer.SwitchSection(sect);
564       }
565       const MCSection *StaticInitSect =
566         OutContext.getMachOSection("__TEXT", "__StaticInit",
567                                    MCSectionMachO::S_REGULAR |
568                                    MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
569                                    SectionKind::getText());
570       OutStreamer.SwitchSection(StaticInitSect);
571     }
572   }
573 
574   // Use unified assembler syntax.
575   OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
576 
577   // Emit ARM Build Attributes
578   if (Subtarget->isTargetELF()) {
579 
580     emitAttributes();
581   }
582 }
583 
584 
585 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
586   if (Subtarget->isTargetDarwin()) {
587     // All darwin targets use mach-o.
588     const TargetLoweringObjectFileMachO &TLOFMacho =
589       static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
590     MachineModuleInfoMachO &MMIMacho =
591       MMI->getObjFileInfo<MachineModuleInfoMachO>();
592 
593     // Output non-lazy-pointers for external and common global variables.
594     MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
595 
596     if (!Stubs.empty()) {
597       // Switch with ".non_lazy_symbol_pointer" directive.
598       OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
599       EmitAlignment(2);
600       for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
601         // L_foo$stub:
602         OutStreamer.EmitLabel(Stubs[i].first);
603         //   .indirect_symbol _foo
604         MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
605         OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
606 
607         if (MCSym.getInt())
608           // External to current translation unit.
609           OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
610         else
611           // Internal to current translation unit.
612           //
613           // When we place the LSDA into the TEXT section, the type info
614           // pointers need to be indirect and pc-rel. We accomplish this by
615           // using NLPs; however, sometimes the types are local to the file.
616           // We need to fill in the value for the NLP in those cases.
617           OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
618                                                         OutContext),
619                                 4/*size*/, 0/*addrspace*/);
620       }
621 
622       Stubs.clear();
623       OutStreamer.AddBlankLine();
624     }
625 
626     Stubs = MMIMacho.GetHiddenGVStubList();
627     if (!Stubs.empty()) {
628       OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
629       EmitAlignment(2);
630       for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
631         // L_foo$stub:
632         OutStreamer.EmitLabel(Stubs[i].first);
633         //   .long _foo
634         OutStreamer.EmitValue(MCSymbolRefExpr::
635                               Create(Stubs[i].second.getPointer(),
636                                      OutContext),
637                               4/*size*/, 0/*addrspace*/);
638       }
639 
640       Stubs.clear();
641       OutStreamer.AddBlankLine();
642     }
643 
644     // Funny Darwin hack: This flag tells the linker that no global symbols
645     // contain code that falls through to other global symbols (e.g. the obvious
646     // implementation of multiple entry points).  If this doesn't occur, the
647     // linker can safely perform dead code stripping.  Since LLVM never
648     // generates code that does this, it is always safe to set.
649     OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
650   }
651 }
652 
653 //===----------------------------------------------------------------------===//
654 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
655 // FIXME:
656 // The following seem like one-off assembler flags, but they actually need
657 // to appear in the .ARM.attributes section in ELF.
658 // Instead of subclassing the MCELFStreamer, we do the work here.
659 
660 void ARMAsmPrinter::emitAttributes() {
661 
662   emitARMAttributeSection();
663 
664   /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
665   bool emitFPU = false;
666   AttributeEmitter *AttrEmitter;
667   if (OutStreamer.hasRawTextSupport()) {
668     AttrEmitter = new AsmAttributeEmitter(OutStreamer);
669     emitFPU = true;
670   } else {
671     MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
672     AttrEmitter = new ObjectAttributeEmitter(O);
673   }
674 
675   AttrEmitter->MaybeSwitchVendor("aeabi");
676 
677   std::string CPUString = Subtarget->getCPUString();
678 
679   if (CPUString == "cortex-a8" ||
680       Subtarget->isCortexA8()) {
681     AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
682     AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
683     AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
684                                ARMBuildAttrs::ApplicationProfile);
685     AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
686                                ARMBuildAttrs::Allowed);
687     AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
688                                ARMBuildAttrs::AllowThumb32);
689     // Fixme: figure out when this is emitted.
690     //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
691     //                           ARMBuildAttrs::AllowWMMXv1);
692     //
693 
694     /// ADD additional Else-cases here!
695   } else if (CPUString == "xscale") {
696     AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
697     AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
698                                ARMBuildAttrs::Allowed);
699     AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
700                                ARMBuildAttrs::Allowed);
701   } else if (CPUString == "generic") {
702     // FIXME: Why these defaults?
703     AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
704     AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
705                                ARMBuildAttrs::Allowed);
706     AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
707                                ARMBuildAttrs::Allowed);
708   }
709 
710   if (Subtarget->hasNEON() && emitFPU) {
711     /* NEON is not exactly a VFP architecture, but GAS emit one of
712      * neon/vfpv3/vfpv2 for .fpu parameters */
713     AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
714     /* If emitted for NEON, omit from VFP below, since you can have both
715      * NEON and VFP in build attributes but only one .fpu */
716     emitFPU = false;
717   }
718 
719   /* VFPv3 + .fpu */
720   if (Subtarget->hasVFP3()) {
721     AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
722                                ARMBuildAttrs::AllowFPv3A);
723     if (emitFPU)
724       AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
725 
726   /* VFPv2 + .fpu */
727   } else if (Subtarget->hasVFP2()) {
728     AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
729                                ARMBuildAttrs::AllowFPv2);
730     if (emitFPU)
731       AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
732   }
733 
734   /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
735    * since NEON can have 1 (allowed) or 2 (MAC operations) */
736   if (Subtarget->hasNEON()) {
737     AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
738                                ARMBuildAttrs::Allowed);
739   }
740 
741   // Signal various FP modes.
742   if (!TM.Options.UnsafeFPMath) {
743     AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
744                                ARMBuildAttrs::Allowed);
745     AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
746                                ARMBuildAttrs::Allowed);
747   }
748 
749   if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
750     AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
751                                ARMBuildAttrs::Allowed);
752   else
753     AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
754                                ARMBuildAttrs::AllowIEE754);
755 
756   // FIXME: add more flags to ARMBuildAttrs.h
757   // 8-bytes alignment stuff.
758   AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
759   AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
760 
761   // Hard float.  Use both S and D registers and conform to AAPCS-VFP.
762   if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
763     AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
764     AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
765   }
766   // FIXME: Should we signal R9 usage?
767 
768   if (Subtarget->hasDivide())
769     AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
770 
771   AttrEmitter->Finish();
772   delete AttrEmitter;
773 }
774 
775 void ARMAsmPrinter::emitARMAttributeSection() {
776   // <format-version>
777   // [ <section-length> "vendor-name"
778   // [ <file-tag> <size> <attribute>*
779   //   | <section-tag> <size> <section-number>* 0 <attribute>*
780   //   | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
781   //   ]+
782   // ]*
783 
784   if (OutStreamer.hasRawTextSupport())
785     return;
786 
787   const ARMElfTargetObjectFile &TLOFELF =
788     static_cast<const ARMElfTargetObjectFile &>
789     (getObjFileLowering());
790 
791   OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
792 
793   // Format version
794   OutStreamer.EmitIntValue(0x41, 1);
795 }
796 
797 //===----------------------------------------------------------------------===//
798 
799 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
800                              unsigned LabelId, MCContext &Ctx) {
801 
802   MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
803                        + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
804   return Label;
805 }
806 
807 static MCSymbolRefExpr::VariantKind
808 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
809   switch (Modifier) {
810   default: llvm_unreachable("Unknown modifier!");
811   case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
812   case ARMCP::TLSGD:       return MCSymbolRefExpr::VK_ARM_TLSGD;
813   case ARMCP::TPOFF:       return MCSymbolRefExpr::VK_ARM_TPOFF;
814   case ARMCP::GOTTPOFF:    return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
815   case ARMCP::GOT:         return MCSymbolRefExpr::VK_ARM_GOT;
816   case ARMCP::GOTOFF:      return MCSymbolRefExpr::VK_ARM_GOTOFF;
817   }
818   return MCSymbolRefExpr::VK_None;
819 }
820 
821 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
822   bool isIndirect = Subtarget->isTargetDarwin() &&
823     Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
824   if (!isIndirect)
825     return Mang->getSymbol(GV);
826 
827   // FIXME: Remove this when Darwin transition to @GOT like syntax.
828   MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
829   MachineModuleInfoMachO &MMIMachO =
830     MMI->getObjFileInfo<MachineModuleInfoMachO>();
831   MachineModuleInfoImpl::StubValueTy &StubSym =
832     GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
833     MMIMachO.getGVStubEntry(MCSym);
834   if (StubSym.getPointer() == 0)
835     StubSym = MachineModuleInfoImpl::
836       StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
837   return MCSym;
838 }
839 
840 void ARMAsmPrinter::
841 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
842   int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
843 
844   ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
845 
846   MCSymbol *MCSym;
847   if (ACPV->isLSDA()) {
848     SmallString<128> Str;
849     raw_svector_ostream OS(Str);
850     OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
851     MCSym = OutContext.GetOrCreateSymbol(OS.str());
852   } else if (ACPV->isBlockAddress()) {
853     const BlockAddress *BA =
854       cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
855     MCSym = GetBlockAddressSymbol(BA);
856   } else if (ACPV->isGlobalValue()) {
857     const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
858     MCSym = GetARMGVSymbol(GV);
859   } else if (ACPV->isMachineBasicBlock()) {
860     const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
861     MCSym = MBB->getSymbol();
862   } else {
863     assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
864     const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
865     MCSym = GetExternalSymbolSymbol(Sym);
866   }
867 
868   // Create an MCSymbol for the reference.
869   const MCExpr *Expr =
870     MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
871                             OutContext);
872 
873   if (ACPV->getPCAdjustment()) {
874     MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
875                                     getFunctionNumber(),
876                                     ACPV->getLabelId(),
877                                     OutContext);
878     const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
879     PCRelExpr =
880       MCBinaryExpr::CreateAdd(PCRelExpr,
881                               MCConstantExpr::Create(ACPV->getPCAdjustment(),
882                                                      OutContext),
883                               OutContext);
884     if (ACPV->mustAddCurrentAddress()) {
885       // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
886       // label, so just emit a local label end reference that instead.
887       MCSymbol *DotSym = OutContext.CreateTempSymbol();
888       OutStreamer.EmitLabel(DotSym);
889       const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
890       PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
891     }
892     Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
893   }
894   OutStreamer.EmitValue(Expr, Size);
895 }
896 
897 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
898   unsigned Opcode = MI->getOpcode();
899   int OpNum = 1;
900   if (Opcode == ARM::BR_JTadd)
901     OpNum = 2;
902   else if (Opcode == ARM::BR_JTm)
903     OpNum = 3;
904 
905   const MachineOperand &MO1 = MI->getOperand(OpNum);
906   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
907   unsigned JTI = MO1.getIndex();
908 
909   // Tag the jump table appropriately for precise disassembly.
910   OutStreamer.EmitJumpTable32Region();
911 
912   // Emit a label for the jump table.
913   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
914   OutStreamer.EmitLabel(JTISymbol);
915 
916   // Emit each entry of the table.
917   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
918   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
919   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
920 
921   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
922     MachineBasicBlock *MBB = JTBBs[i];
923     // Construct an MCExpr for the entry. We want a value of the form:
924     // (BasicBlockAddr - TableBeginAddr)
925     //
926     // For example, a table with entries jumping to basic blocks BB0 and BB1
927     // would look like:
928     // LJTI_0_0:
929     //    .word (LBB0 - LJTI_0_0)
930     //    .word (LBB1 - LJTI_0_0)
931     const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
932 
933     if (TM.getRelocationModel() == Reloc::PIC_)
934       Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
935                                                                    OutContext),
936                                      OutContext);
937     // If we're generating a table of Thumb addresses in static relocation
938     // model, we need to add one to keep interworking correctly.
939     else if (AFI->isThumbFunction())
940       Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
941                                      OutContext);
942     OutStreamer.EmitValue(Expr, 4);
943   }
944 }
945 
946 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
947   unsigned Opcode = MI->getOpcode();
948   int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
949   const MachineOperand &MO1 = MI->getOperand(OpNum);
950   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
951   unsigned JTI = MO1.getIndex();
952 
953   // Emit a label for the jump table.
954   if (MI->getOpcode() == ARM::t2TBB_JT) {
955     OutStreamer.EmitJumpTable8Region();
956   } else if (MI->getOpcode() == ARM::t2TBH_JT) {
957     OutStreamer.EmitJumpTable16Region();
958   } else {
959     OutStreamer.EmitJumpTable32Region();
960   }
961 
962   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
963   OutStreamer.EmitLabel(JTISymbol);
964 
965   // Emit each entry of the table.
966   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
967   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
968   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
969   unsigned OffsetWidth = 4;
970   if (MI->getOpcode() == ARM::t2TBB_JT)
971     OffsetWidth = 1;
972   else if (MI->getOpcode() == ARM::t2TBH_JT)
973     OffsetWidth = 2;
974 
975   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
976     MachineBasicBlock *MBB = JTBBs[i];
977     const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
978                                                       OutContext);
979     // If this isn't a TBB or TBH, the entries are direct branch instructions.
980     if (OffsetWidth == 4) {
981       MCInst BrInst;
982       BrInst.setOpcode(ARM::t2B);
983       BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
984       BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
985       BrInst.addOperand(MCOperand::CreateReg(0));
986       OutStreamer.EmitInstruction(BrInst);
987       continue;
988     }
989     // Otherwise it's an offset from the dispatch instruction. Construct an
990     // MCExpr for the entry. We want a value of the form:
991     // (BasicBlockAddr - TableBeginAddr) / 2
992     //
993     // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
994     // would look like:
995     // LJTI_0_0:
996     //    .byte (LBB0 - LJTI_0_0) / 2
997     //    .byte (LBB1 - LJTI_0_0) / 2
998     const MCExpr *Expr =
999       MCBinaryExpr::CreateSub(MBBSymbolExpr,
1000                               MCSymbolRefExpr::Create(JTISymbol, OutContext),
1001                               OutContext);
1002     Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1003                                    OutContext);
1004     OutStreamer.EmitValue(Expr, OffsetWidth);
1005   }
1006 }
1007 
1008 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1009                                            raw_ostream &OS) {
1010   unsigned NOps = MI->getNumOperands();
1011   assert(NOps==4);
1012   OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1013   // cast away const; DIetc do not take const operands for some reason.
1014   DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1015   OS << V.getName();
1016   OS << " <- ";
1017   // Frame address.  Currently handles register +- offset only.
1018   assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1019   OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1020   OS << ']';
1021   OS << "+";
1022   printOperand(MI, NOps-2, OS);
1023 }
1024 
1025 static void populateADROperands(MCInst &Inst, unsigned Dest,
1026                                 const MCSymbol *Label,
1027                                 unsigned pred, unsigned ccreg,
1028                                 MCContext &Ctx) {
1029   const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
1030   Inst.addOperand(MCOperand::CreateReg(Dest));
1031   Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1032   // Add predicate operands.
1033   Inst.addOperand(MCOperand::CreateImm(pred));
1034   Inst.addOperand(MCOperand::CreateReg(ccreg));
1035 }
1036 
1037 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
1038                                            unsigned Opcode) {
1039   MCInst TmpInst;
1040 
1041   // Emit the instruction as usual, just patch the opcode.
1042   LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1043   TmpInst.setOpcode(Opcode);
1044   OutStreamer.EmitInstruction(TmpInst);
1045 }
1046 
1047 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1048   assert(MI->getFlag(MachineInstr::FrameSetup) &&
1049       "Only instruction which are involved into frame setup code are allowed");
1050 
1051   const MachineFunction &MF = *MI->getParent()->getParent();
1052   const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1053   const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1054 
1055   unsigned FramePtr = RegInfo->getFrameRegister(MF);
1056   unsigned Opc = MI->getOpcode();
1057   unsigned SrcReg, DstReg;
1058 
1059   if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1060     // Two special cases:
1061     // 1) tPUSH does not have src/dst regs.
1062     // 2) for Thumb1 code we sometimes materialize the constant via constpool
1063     // load. Yes, this is pretty fragile, but for now I don't see better
1064     // way... :(
1065     SrcReg = DstReg = ARM::SP;
1066   } else {
1067     SrcReg = MI->getOperand(1).getReg();
1068     DstReg = MI->getOperand(0).getReg();
1069   }
1070 
1071   // Try to figure out the unwinding opcode out of src / dst regs.
1072   if (MI->getDesc().mayStore()) {
1073     // Register saves.
1074     assert(DstReg == ARM::SP &&
1075            "Only stack pointer as a destination reg is supported");
1076 
1077     SmallVector<unsigned, 4> RegList;
1078     // Skip src & dst reg, and pred ops.
1079     unsigned StartOp = 2 + 2;
1080     // Use all the operands.
1081     unsigned NumOffset = 0;
1082 
1083     switch (Opc) {
1084     default:
1085       MI->dump();
1086       assert(0 && "Unsupported opcode for unwinding information");
1087     case ARM::tPUSH:
1088       // Special case here: no src & dst reg, but two extra imp ops.
1089       StartOp = 2; NumOffset = 2;
1090     case ARM::STMDB_UPD:
1091     case ARM::t2STMDB_UPD:
1092     case ARM::VSTMDDB_UPD:
1093       assert(SrcReg == ARM::SP &&
1094              "Only stack pointer as a source reg is supported");
1095       for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1096            i != NumOps; ++i)
1097         RegList.push_back(MI->getOperand(i).getReg());
1098       break;
1099     case ARM::STR_PRE_IMM:
1100     case ARM::STR_PRE_REG:
1101       assert(MI->getOperand(2).getReg() == ARM::SP &&
1102              "Only stack pointer as a source reg is supported");
1103       RegList.push_back(SrcReg);
1104       break;
1105     }
1106     OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1107   } else {
1108     // Changes of stack / frame pointer.
1109     if (SrcReg == ARM::SP) {
1110       int64_t Offset = 0;
1111       switch (Opc) {
1112       default:
1113         MI->dump();
1114         assert(0 && "Unsupported opcode for unwinding information");
1115       case ARM::MOVr:
1116         Offset = 0;
1117         break;
1118       case ARM::ADDri:
1119         Offset = -MI->getOperand(2).getImm();
1120         break;
1121       case ARM::SUBri:
1122         Offset = MI->getOperand(2).getImm();
1123         break;
1124       case ARM::tSUBspi:
1125         Offset = MI->getOperand(2).getImm()*4;
1126         break;
1127       case ARM::tADDspi:
1128       case ARM::tADDrSPi:
1129         Offset = -MI->getOperand(2).getImm()*4;
1130         break;
1131       case ARM::tLDRpci: {
1132         // Grab the constpool index and check, whether it corresponds to
1133         // original or cloned constpool entry.
1134         unsigned CPI = MI->getOperand(1).getIndex();
1135         const MachineConstantPool *MCP = MF.getConstantPool();
1136         if (CPI >= MCP->getConstants().size())
1137           CPI = AFI.getOriginalCPIdx(CPI);
1138         assert(CPI != -1U && "Invalid constpool index");
1139 
1140         // Derive the actual offset.
1141         const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1142         assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1143         // FIXME: Check for user, it should be "add" instruction!
1144         Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1145         break;
1146       }
1147       }
1148 
1149       if (DstReg == FramePtr && FramePtr != ARM::SP)
1150         // Set-up of the frame pointer. Positive values correspond to "add"
1151         // instruction.
1152         OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1153       else if (DstReg == ARM::SP) {
1154         // Change of SP by an offset. Positive values correspond to "sub"
1155         // instruction.
1156         OutStreamer.EmitPad(Offset);
1157       } else {
1158         MI->dump();
1159         assert(0 && "Unsupported opcode for unwinding information");
1160       }
1161     } else if (DstReg == ARM::SP) {
1162       // FIXME: .movsp goes here
1163       MI->dump();
1164       assert(0 && "Unsupported opcode for unwinding information");
1165     }
1166     else {
1167       MI->dump();
1168       assert(0 && "Unsupported opcode for unwinding information");
1169     }
1170   }
1171 }
1172 
1173 extern cl::opt<bool> EnableARMEHABI;
1174 
1175 // Simple pseudo-instructions have their lowering (with expansion to real
1176 // instructions) auto-generated.
1177 #include "ARMGenMCPseudoLowering.inc"
1178 
1179 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1180   if (MI->getOpcode() != ARM::CONSTPOOL_ENTRY)
1181     OutStreamer.EmitCodeRegion();
1182 
1183   // Emit unwinding stuff for frame-related instructions
1184   if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1185     EmitUnwindingInstruction(MI);
1186 
1187   // Do any auto-generated pseudo lowerings.
1188   if (emitPseudoExpansionLowering(OutStreamer, MI))
1189     return;
1190 
1191   assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1192          "Pseudo flag setting opcode should be expanded early");
1193 
1194   // Check for manual lowerings.
1195   unsigned Opc = MI->getOpcode();
1196   switch (Opc) {
1197   case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
1198   case ARM::DBG_VALUE: {
1199     if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1200       SmallString<128> TmpStr;
1201       raw_svector_ostream OS(TmpStr);
1202       PrintDebugValueComment(MI, OS);
1203       OutStreamer.EmitRawText(StringRef(OS.str()));
1204     }
1205     return;
1206   }
1207   case ARM::LEApcrel:
1208   case ARM::tLEApcrel:
1209   case ARM::t2LEApcrel: {
1210     // FIXME: Need to also handle globals and externals
1211     MCInst TmpInst;
1212     TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1213                       : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1214                          : ARM::ADR));
1215     populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1216                         GetCPISymbol(MI->getOperand(1).getIndex()),
1217                         MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1218                         OutContext);
1219     OutStreamer.EmitInstruction(TmpInst);
1220     return;
1221   }
1222   case ARM::LEApcrelJT:
1223   case ARM::tLEApcrelJT:
1224   case ARM::t2LEApcrelJT: {
1225     MCInst TmpInst;
1226     TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1227                       : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1228                          : ARM::ADR));
1229     populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1230                       GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1231                                                   MI->getOperand(2).getImm()),
1232                       MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1233                       OutContext);
1234     OutStreamer.EmitInstruction(TmpInst);
1235     return;
1236   }
1237   // Darwin call instructions are just normal call instructions with different
1238   // clobber semantics (they clobber R9).
1239   case ARM::BXr9_CALL:
1240   case ARM::BX_CALL: {
1241     {
1242       MCInst TmpInst;
1243       TmpInst.setOpcode(ARM::MOVr);
1244       TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1245       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1246       // Add predicate operands.
1247       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1248       TmpInst.addOperand(MCOperand::CreateReg(0));
1249       // Add 's' bit operand (always reg0 for this)
1250       TmpInst.addOperand(MCOperand::CreateReg(0));
1251       OutStreamer.EmitInstruction(TmpInst);
1252     }
1253     {
1254       MCInst TmpInst;
1255       TmpInst.setOpcode(ARM::BX);
1256       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1257       OutStreamer.EmitInstruction(TmpInst);
1258     }
1259     return;
1260   }
1261   case ARM::tBXr9_CALL:
1262   case ARM::tBX_CALL: {
1263     {
1264       MCInst TmpInst;
1265       TmpInst.setOpcode(ARM::tMOVr);
1266       TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1267       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1268       // Add predicate operands.
1269       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1270       TmpInst.addOperand(MCOperand::CreateReg(0));
1271       OutStreamer.EmitInstruction(TmpInst);
1272     }
1273     {
1274       MCInst TmpInst;
1275       TmpInst.setOpcode(ARM::tBX);
1276       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1277       // Add predicate operands.
1278       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1279       TmpInst.addOperand(MCOperand::CreateReg(0));
1280       OutStreamer.EmitInstruction(TmpInst);
1281     }
1282     return;
1283   }
1284   case ARM::BMOVPCRXr9_CALL:
1285   case ARM::BMOVPCRX_CALL: {
1286     {
1287       MCInst TmpInst;
1288       TmpInst.setOpcode(ARM::MOVr);
1289       TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1290       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1291       // Add predicate operands.
1292       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1293       TmpInst.addOperand(MCOperand::CreateReg(0));
1294       // Add 's' bit operand (always reg0 for this)
1295       TmpInst.addOperand(MCOperand::CreateReg(0));
1296       OutStreamer.EmitInstruction(TmpInst);
1297     }
1298     {
1299       MCInst TmpInst;
1300       TmpInst.setOpcode(ARM::MOVr);
1301       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1302       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1303       // Add predicate operands.
1304       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1305       TmpInst.addOperand(MCOperand::CreateReg(0));
1306       // Add 's' bit operand (always reg0 for this)
1307       TmpInst.addOperand(MCOperand::CreateReg(0));
1308       OutStreamer.EmitInstruction(TmpInst);
1309     }
1310     return;
1311   }
1312   case ARM::MOVi16_ga_pcrel:
1313   case ARM::t2MOVi16_ga_pcrel: {
1314     MCInst TmpInst;
1315     TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1316     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1317 
1318     unsigned TF = MI->getOperand(1).getTargetFlags();
1319     bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1320     const GlobalValue *GV = MI->getOperand(1).getGlobal();
1321     MCSymbol *GVSym = GetARMGVSymbol(GV);
1322     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1323     if (isPIC) {
1324       MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1325                                        getFunctionNumber(),
1326                                        MI->getOperand(2).getImm(), OutContext);
1327       const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1328       unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1329       const MCExpr *PCRelExpr =
1330         ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1331                                   MCBinaryExpr::CreateAdd(LabelSymExpr,
1332                                       MCConstantExpr::Create(PCAdj, OutContext),
1333                                           OutContext), OutContext), OutContext);
1334       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1335     } else {
1336       const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1337       TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1338     }
1339 
1340     // Add predicate operands.
1341     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1342     TmpInst.addOperand(MCOperand::CreateReg(0));
1343     // Add 's' bit operand (always reg0 for this)
1344     TmpInst.addOperand(MCOperand::CreateReg(0));
1345     OutStreamer.EmitInstruction(TmpInst);
1346     return;
1347   }
1348   case ARM::MOVTi16_ga_pcrel:
1349   case ARM::t2MOVTi16_ga_pcrel: {
1350     MCInst TmpInst;
1351     TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1352                       ? ARM::MOVTi16 : ARM::t2MOVTi16);
1353     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1354     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1355 
1356     unsigned TF = MI->getOperand(2).getTargetFlags();
1357     bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1358     const GlobalValue *GV = MI->getOperand(2).getGlobal();
1359     MCSymbol *GVSym = GetARMGVSymbol(GV);
1360     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1361     if (isPIC) {
1362       MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1363                                        getFunctionNumber(),
1364                                        MI->getOperand(3).getImm(), OutContext);
1365       const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1366       unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1367       const MCExpr *PCRelExpr =
1368         ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1369                                    MCBinaryExpr::CreateAdd(LabelSymExpr,
1370                                       MCConstantExpr::Create(PCAdj, OutContext),
1371                                           OutContext), OutContext), OutContext);
1372       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1373     } else {
1374       const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1375       TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1376     }
1377     // Add predicate operands.
1378     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1379     TmpInst.addOperand(MCOperand::CreateReg(0));
1380     // Add 's' bit operand (always reg0 for this)
1381     TmpInst.addOperand(MCOperand::CreateReg(0));
1382     OutStreamer.EmitInstruction(TmpInst);
1383     return;
1384   }
1385   case ARM::tPICADD: {
1386     // This is a pseudo op for a label + instruction sequence, which looks like:
1387     // LPC0:
1388     //     add r0, pc
1389     // This adds the address of LPC0 to r0.
1390 
1391     // Emit the label.
1392     OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1393                           getFunctionNumber(), MI->getOperand(2).getImm(),
1394                           OutContext));
1395 
1396     // Form and emit the add.
1397     MCInst AddInst;
1398     AddInst.setOpcode(ARM::tADDhirr);
1399     AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1400     AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1401     AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1402     // Add predicate operands.
1403     AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1404     AddInst.addOperand(MCOperand::CreateReg(0));
1405     OutStreamer.EmitInstruction(AddInst);
1406     return;
1407   }
1408   case ARM::PICADD: {
1409     // This is a pseudo op for a label + instruction sequence, which looks like:
1410     // LPC0:
1411     //     add r0, pc, r0
1412     // This adds the address of LPC0 to r0.
1413 
1414     // Emit the label.
1415     OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1416                           getFunctionNumber(), MI->getOperand(2).getImm(),
1417                           OutContext));
1418 
1419     // Form and emit the add.
1420     MCInst AddInst;
1421     AddInst.setOpcode(ARM::ADDrr);
1422     AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1423     AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1424     AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1425     // Add predicate operands.
1426     AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1427     AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1428     // Add 's' bit operand (always reg0 for this)
1429     AddInst.addOperand(MCOperand::CreateReg(0));
1430     OutStreamer.EmitInstruction(AddInst);
1431     return;
1432   }
1433   case ARM::PICSTR:
1434   case ARM::PICSTRB:
1435   case ARM::PICSTRH:
1436   case ARM::PICLDR:
1437   case ARM::PICLDRB:
1438   case ARM::PICLDRH:
1439   case ARM::PICLDRSB:
1440   case ARM::PICLDRSH: {
1441     // This is a pseudo op for a label + instruction sequence, which looks like:
1442     // LPC0:
1443     //     OP r0, [pc, r0]
1444     // The LCP0 label is referenced by a constant pool entry in order to get
1445     // a PC-relative address at the ldr instruction.
1446 
1447     // Emit the label.
1448     OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1449                           getFunctionNumber(), MI->getOperand(2).getImm(),
1450                           OutContext));
1451 
1452     // Form and emit the load
1453     unsigned Opcode;
1454     switch (MI->getOpcode()) {
1455     default:
1456       llvm_unreachable("Unexpected opcode!");
1457     case ARM::PICSTR:   Opcode = ARM::STRrs; break;
1458     case ARM::PICSTRB:  Opcode = ARM::STRBrs; break;
1459     case ARM::PICSTRH:  Opcode = ARM::STRH; break;
1460     case ARM::PICLDR:   Opcode = ARM::LDRrs; break;
1461     case ARM::PICLDRB:  Opcode = ARM::LDRBrs; break;
1462     case ARM::PICLDRH:  Opcode = ARM::LDRH; break;
1463     case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1464     case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1465     }
1466     MCInst LdStInst;
1467     LdStInst.setOpcode(Opcode);
1468     LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1469     LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1470     LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1471     LdStInst.addOperand(MCOperand::CreateImm(0));
1472     // Add predicate operands.
1473     LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1474     LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1475     OutStreamer.EmitInstruction(LdStInst);
1476 
1477     return;
1478   }
1479   case ARM::CONSTPOOL_ENTRY: {
1480     /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1481     /// in the function.  The first operand is the ID# for this instruction, the
1482     /// second is the index into the MachineConstantPool that this is, the third
1483     /// is the size in bytes of this constant pool entry.
1484     unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1485     unsigned CPIdx   = (unsigned)MI->getOperand(1).getIndex();
1486 
1487     EmitAlignment(2);
1488 
1489     // Mark the constant pool entry as data if we're not already in a data
1490     // region.
1491     OutStreamer.EmitDataRegion();
1492     OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1493 
1494     const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1495     if (MCPE.isMachineConstantPoolEntry())
1496       EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1497     else
1498       EmitGlobalConstant(MCPE.Val.ConstVal);
1499     return;
1500   }
1501   case ARM::t2BR_JT: {
1502     // Lower and emit the instruction itself, then the jump table following it.
1503     MCInst TmpInst;
1504     TmpInst.setOpcode(ARM::tMOVr);
1505     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1506     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1507     // Add predicate operands.
1508     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1509     TmpInst.addOperand(MCOperand::CreateReg(0));
1510     OutStreamer.EmitInstruction(TmpInst);
1511     // Output the data for the jump table itself
1512     EmitJump2Table(MI);
1513     return;
1514   }
1515   case ARM::t2TBB_JT: {
1516     // Lower and emit the instruction itself, then the jump table following it.
1517     MCInst TmpInst;
1518 
1519     TmpInst.setOpcode(ARM::t2TBB);
1520     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1521     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1522     // Add predicate operands.
1523     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1524     TmpInst.addOperand(MCOperand::CreateReg(0));
1525     OutStreamer.EmitInstruction(TmpInst);
1526     // Output the data for the jump table itself
1527     EmitJump2Table(MI);
1528     // Make sure the next instruction is 2-byte aligned.
1529     EmitAlignment(1);
1530     return;
1531   }
1532   case ARM::t2TBH_JT: {
1533     // Lower and emit the instruction itself, then the jump table following it.
1534     MCInst TmpInst;
1535 
1536     TmpInst.setOpcode(ARM::t2TBH);
1537     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1538     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1539     // Add predicate operands.
1540     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1541     TmpInst.addOperand(MCOperand::CreateReg(0));
1542     OutStreamer.EmitInstruction(TmpInst);
1543     // Output the data for the jump table itself
1544     EmitJump2Table(MI);
1545     return;
1546   }
1547   case ARM::tBR_JTr:
1548   case ARM::BR_JTr: {
1549     // Lower and emit the instruction itself, then the jump table following it.
1550     // mov pc, target
1551     MCInst TmpInst;
1552     unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1553       ARM::MOVr : ARM::tMOVr;
1554     TmpInst.setOpcode(Opc);
1555     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1556     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1557     // Add predicate operands.
1558     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1559     TmpInst.addOperand(MCOperand::CreateReg(0));
1560     // Add 's' bit operand (always reg0 for this)
1561     if (Opc == ARM::MOVr)
1562       TmpInst.addOperand(MCOperand::CreateReg(0));
1563     OutStreamer.EmitInstruction(TmpInst);
1564 
1565     // Make sure the Thumb jump table is 4-byte aligned.
1566     if (Opc == ARM::tMOVr)
1567       EmitAlignment(2);
1568 
1569     // Output the data for the jump table itself
1570     EmitJumpTable(MI);
1571     return;
1572   }
1573   case ARM::BR_JTm: {
1574     // Lower and emit the instruction itself, then the jump table following it.
1575     // ldr pc, target
1576     MCInst TmpInst;
1577     if (MI->getOperand(1).getReg() == 0) {
1578       // literal offset
1579       TmpInst.setOpcode(ARM::LDRi12);
1580       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1581       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1582       TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1583     } else {
1584       TmpInst.setOpcode(ARM::LDRrs);
1585       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1586       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1587       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1588       TmpInst.addOperand(MCOperand::CreateImm(0));
1589     }
1590     // Add predicate operands.
1591     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1592     TmpInst.addOperand(MCOperand::CreateReg(0));
1593     OutStreamer.EmitInstruction(TmpInst);
1594 
1595     // Output the data for the jump table itself
1596     EmitJumpTable(MI);
1597     return;
1598   }
1599   case ARM::BR_JTadd: {
1600     // Lower and emit the instruction itself, then the jump table following it.
1601     // add pc, target, idx
1602     MCInst TmpInst;
1603     TmpInst.setOpcode(ARM::ADDrr);
1604     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1605     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1606     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1607     // Add predicate operands.
1608     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1609     TmpInst.addOperand(MCOperand::CreateReg(0));
1610     // Add 's' bit operand (always reg0 for this)
1611     TmpInst.addOperand(MCOperand::CreateReg(0));
1612     OutStreamer.EmitInstruction(TmpInst);
1613 
1614     // Output the data for the jump table itself
1615     EmitJumpTable(MI);
1616     return;
1617   }
1618   case ARM::TRAP: {
1619     // Non-Darwin binutils don't yet support the "trap" mnemonic.
1620     // FIXME: Remove this special case when they do.
1621     if (!Subtarget->isTargetDarwin()) {
1622       //.long 0xe7ffdefe @ trap
1623       uint32_t Val = 0xe7ffdefeUL;
1624       OutStreamer.AddComment("trap");
1625       OutStreamer.EmitIntValue(Val, 4);
1626       return;
1627     }
1628     break;
1629   }
1630   case ARM::tTRAP: {
1631     // Non-Darwin binutils don't yet support the "trap" mnemonic.
1632     // FIXME: Remove this special case when they do.
1633     if (!Subtarget->isTargetDarwin()) {
1634       //.short 57086 @ trap
1635       uint16_t Val = 0xdefe;
1636       OutStreamer.AddComment("trap");
1637       OutStreamer.EmitIntValue(Val, 2);
1638       return;
1639     }
1640     break;
1641   }
1642   case ARM::t2Int_eh_sjlj_setjmp:
1643   case ARM::t2Int_eh_sjlj_setjmp_nofp:
1644   case ARM::tInt_eh_sjlj_setjmp: {
1645     // Two incoming args: GPR:$src, GPR:$val
1646     // mov $val, pc
1647     // adds $val, #7
1648     // str $val, [$src, #4]
1649     // movs r0, #0
1650     // b 1f
1651     // movs r0, #1
1652     // 1:
1653     unsigned SrcReg = MI->getOperand(0).getReg();
1654     unsigned ValReg = MI->getOperand(1).getReg();
1655     MCSymbol *Label = GetARMSJLJEHLabel();
1656     {
1657       MCInst TmpInst;
1658       TmpInst.setOpcode(ARM::tMOVr);
1659       TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1660       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1661       // Predicate.
1662       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1663       TmpInst.addOperand(MCOperand::CreateReg(0));
1664       OutStreamer.AddComment("eh_setjmp begin");
1665       OutStreamer.EmitInstruction(TmpInst);
1666     }
1667     {
1668       MCInst TmpInst;
1669       TmpInst.setOpcode(ARM::tADDi3);
1670       TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1671       // 's' bit operand
1672       TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1673       TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1674       TmpInst.addOperand(MCOperand::CreateImm(7));
1675       // Predicate.
1676       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1677       TmpInst.addOperand(MCOperand::CreateReg(0));
1678       OutStreamer.EmitInstruction(TmpInst);
1679     }
1680     {
1681       MCInst TmpInst;
1682       TmpInst.setOpcode(ARM::tSTRi);
1683       TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1684       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1685       // The offset immediate is #4. The operand value is scaled by 4 for the
1686       // tSTR instruction.
1687       TmpInst.addOperand(MCOperand::CreateImm(1));
1688       // Predicate.
1689       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1690       TmpInst.addOperand(MCOperand::CreateReg(0));
1691       OutStreamer.EmitInstruction(TmpInst);
1692     }
1693     {
1694       MCInst TmpInst;
1695       TmpInst.setOpcode(ARM::tMOVi8);
1696       TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1697       TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1698       TmpInst.addOperand(MCOperand::CreateImm(0));
1699       // Predicate.
1700       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1701       TmpInst.addOperand(MCOperand::CreateReg(0));
1702       OutStreamer.EmitInstruction(TmpInst);
1703     }
1704     {
1705       const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1706       MCInst TmpInst;
1707       TmpInst.setOpcode(ARM::tB);
1708       TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1709       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1710       TmpInst.addOperand(MCOperand::CreateReg(0));
1711       OutStreamer.EmitInstruction(TmpInst);
1712     }
1713     {
1714       MCInst TmpInst;
1715       TmpInst.setOpcode(ARM::tMOVi8);
1716       TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1717       TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1718       TmpInst.addOperand(MCOperand::CreateImm(1));
1719       // Predicate.
1720       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1721       TmpInst.addOperand(MCOperand::CreateReg(0));
1722       OutStreamer.AddComment("eh_setjmp end");
1723       OutStreamer.EmitInstruction(TmpInst);
1724     }
1725     OutStreamer.EmitLabel(Label);
1726     return;
1727   }
1728 
1729   case ARM::Int_eh_sjlj_setjmp_nofp:
1730   case ARM::Int_eh_sjlj_setjmp: {
1731     // Two incoming args: GPR:$src, GPR:$val
1732     // add $val, pc, #8
1733     // str $val, [$src, #+4]
1734     // mov r0, #0
1735     // add pc, pc, #0
1736     // mov r0, #1
1737     unsigned SrcReg = MI->getOperand(0).getReg();
1738     unsigned ValReg = MI->getOperand(1).getReg();
1739 
1740     {
1741       MCInst TmpInst;
1742       TmpInst.setOpcode(ARM::ADDri);
1743       TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1744       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1745       TmpInst.addOperand(MCOperand::CreateImm(8));
1746       // Predicate.
1747       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1748       TmpInst.addOperand(MCOperand::CreateReg(0));
1749       // 's' bit operand (always reg0 for this).
1750       TmpInst.addOperand(MCOperand::CreateReg(0));
1751       OutStreamer.AddComment("eh_setjmp begin");
1752       OutStreamer.EmitInstruction(TmpInst);
1753     }
1754     {
1755       MCInst TmpInst;
1756       TmpInst.setOpcode(ARM::STRi12);
1757       TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1758       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1759       TmpInst.addOperand(MCOperand::CreateImm(4));
1760       // Predicate.
1761       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1762       TmpInst.addOperand(MCOperand::CreateReg(0));
1763       OutStreamer.EmitInstruction(TmpInst);
1764     }
1765     {
1766       MCInst TmpInst;
1767       TmpInst.setOpcode(ARM::MOVi);
1768       TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1769       TmpInst.addOperand(MCOperand::CreateImm(0));
1770       // Predicate.
1771       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1772       TmpInst.addOperand(MCOperand::CreateReg(0));
1773       // 's' bit operand (always reg0 for this).
1774       TmpInst.addOperand(MCOperand::CreateReg(0));
1775       OutStreamer.EmitInstruction(TmpInst);
1776     }
1777     {
1778       MCInst TmpInst;
1779       TmpInst.setOpcode(ARM::ADDri);
1780       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1781       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1782       TmpInst.addOperand(MCOperand::CreateImm(0));
1783       // Predicate.
1784       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1785       TmpInst.addOperand(MCOperand::CreateReg(0));
1786       // 's' bit operand (always reg0 for this).
1787       TmpInst.addOperand(MCOperand::CreateReg(0));
1788       OutStreamer.EmitInstruction(TmpInst);
1789     }
1790     {
1791       MCInst TmpInst;
1792       TmpInst.setOpcode(ARM::MOVi);
1793       TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1794       TmpInst.addOperand(MCOperand::CreateImm(1));
1795       // Predicate.
1796       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1797       TmpInst.addOperand(MCOperand::CreateReg(0));
1798       // 's' bit operand (always reg0 for this).
1799       TmpInst.addOperand(MCOperand::CreateReg(0));
1800       OutStreamer.AddComment("eh_setjmp end");
1801       OutStreamer.EmitInstruction(TmpInst);
1802     }
1803     return;
1804   }
1805   case ARM::Int_eh_sjlj_longjmp: {
1806     // ldr sp, [$src, #8]
1807     // ldr $scratch, [$src, #4]
1808     // ldr r7, [$src]
1809     // bx $scratch
1810     unsigned SrcReg = MI->getOperand(0).getReg();
1811     unsigned ScratchReg = MI->getOperand(1).getReg();
1812     {
1813       MCInst TmpInst;
1814       TmpInst.setOpcode(ARM::LDRi12);
1815       TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1816       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1817       TmpInst.addOperand(MCOperand::CreateImm(8));
1818       // Predicate.
1819       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1820       TmpInst.addOperand(MCOperand::CreateReg(0));
1821       OutStreamer.EmitInstruction(TmpInst);
1822     }
1823     {
1824       MCInst TmpInst;
1825       TmpInst.setOpcode(ARM::LDRi12);
1826       TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1827       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1828       TmpInst.addOperand(MCOperand::CreateImm(4));
1829       // Predicate.
1830       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1831       TmpInst.addOperand(MCOperand::CreateReg(0));
1832       OutStreamer.EmitInstruction(TmpInst);
1833     }
1834     {
1835       MCInst TmpInst;
1836       TmpInst.setOpcode(ARM::LDRi12);
1837       TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1838       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1839       TmpInst.addOperand(MCOperand::CreateImm(0));
1840       // Predicate.
1841       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1842       TmpInst.addOperand(MCOperand::CreateReg(0));
1843       OutStreamer.EmitInstruction(TmpInst);
1844     }
1845     {
1846       MCInst TmpInst;
1847       TmpInst.setOpcode(ARM::BX);
1848       TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1849       // Predicate.
1850       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1851       TmpInst.addOperand(MCOperand::CreateReg(0));
1852       OutStreamer.EmitInstruction(TmpInst);
1853     }
1854     return;
1855   }
1856   case ARM::tInt_eh_sjlj_longjmp: {
1857     // ldr $scratch, [$src, #8]
1858     // mov sp, $scratch
1859     // ldr $scratch, [$src, #4]
1860     // ldr r7, [$src]
1861     // bx $scratch
1862     unsigned SrcReg = MI->getOperand(0).getReg();
1863     unsigned ScratchReg = MI->getOperand(1).getReg();
1864     {
1865       MCInst TmpInst;
1866       TmpInst.setOpcode(ARM::tLDRi);
1867       TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1868       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1869       // The offset immediate is #8. The operand value is scaled by 4 for the
1870       // tLDR instruction.
1871       TmpInst.addOperand(MCOperand::CreateImm(2));
1872       // Predicate.
1873       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1874       TmpInst.addOperand(MCOperand::CreateReg(0));
1875       OutStreamer.EmitInstruction(TmpInst);
1876     }
1877     {
1878       MCInst TmpInst;
1879       TmpInst.setOpcode(ARM::tMOVr);
1880       TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1881       TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1882       // Predicate.
1883       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1884       TmpInst.addOperand(MCOperand::CreateReg(0));
1885       OutStreamer.EmitInstruction(TmpInst);
1886     }
1887     {
1888       MCInst TmpInst;
1889       TmpInst.setOpcode(ARM::tLDRi);
1890       TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1891       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1892       TmpInst.addOperand(MCOperand::CreateImm(1));
1893       // Predicate.
1894       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1895       TmpInst.addOperand(MCOperand::CreateReg(0));
1896       OutStreamer.EmitInstruction(TmpInst);
1897     }
1898     {
1899       MCInst TmpInst;
1900       TmpInst.setOpcode(ARM::tLDRr);
1901       TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1902       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1903       TmpInst.addOperand(MCOperand::CreateReg(0));
1904       // Predicate.
1905       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1906       TmpInst.addOperand(MCOperand::CreateReg(0));
1907       OutStreamer.EmitInstruction(TmpInst);
1908     }
1909     {
1910       MCInst TmpInst;
1911       TmpInst.setOpcode(ARM::tBX);
1912       TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1913       // Predicate.
1914       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1915       TmpInst.addOperand(MCOperand::CreateReg(0));
1916       OutStreamer.EmitInstruction(TmpInst);
1917     }
1918     return;
1919   }
1920   }
1921 
1922   MCInst TmpInst;
1923   LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1924 
1925   OutStreamer.EmitInstruction(TmpInst);
1926 }
1927 
1928 //===----------------------------------------------------------------------===//
1929 // Target Registry Stuff
1930 //===----------------------------------------------------------------------===//
1931 
1932 // Force static initialization.
1933 extern "C" void LLVMInitializeARMAsmPrinter() {
1934   RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1935   RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1936 }
1937